gem5  v21.1.0.2
gic_v3_redistributor.hh
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40 
41 #ifndef __DEV_ARM_GICV3_REDISTRIBUTOR_H__
42 #define __DEV_ARM_GICV3_REDISTRIBUTOR_H__
43 
44 #include "base/addr_range.hh"
45 #include "dev/arm/gic_v3.hh"
46 #include "sim/serialize.hh"
47 
48 namespace gem5
49 {
50 
51 class Gicv3CPUInterface;
52 class Gicv3Distributor;
53 class Gicv3Its;
54 
56 {
57  private:
58 
59  friend class Gicv3CPUInterface;
60  friend class Gicv3Distributor;
61  friend class Gicv3Its;
62 
63  protected:
64 
68  uint32_t cpuId;
70 
71  /*
72  * GICv3 defines 2 contiguous 64KB frames for each redistributor.
73  * Order of frames must be RD_base, SGI_base.
74  */
75  static const uint32_t RD_base = 0x0;
76  static const uint32_t SGI_base = 0x10000;
77 
78  enum
79  {
80  // Control Register
81  GICR_CTLR = RD_base + 0x0000,
82  // Implementer Identification Register
83  GICR_IIDR = RD_base + 0x0004,
84  // Type Register
85  GICR_TYPER = RD_base + 0x0008,
86  // Wake Register
87  GICR_WAKER = RD_base + 0x0014,
88  // Peripheral ID0 Register
89  GICR_PIDR0 = RD_base + 0xffe0,
90  // Peripheral ID1 Register
91  GICR_PIDR1 = RD_base + 0xffe4,
92  // Peripheral ID2 Register
93  GICR_PIDR2 = RD_base + 0xffe8,
94  // Peripheral ID3 Register
95  GICR_PIDR3 = RD_base + 0xffec,
96  // Peripheral ID4 Register
97  GICR_PIDR4 = RD_base + 0xffd0,
98  // Peripheral ID5 Register
99  GICR_PIDR5 = RD_base + 0xffd4,
100  // Peripheral ID6 Register
101  GICR_PIDR6 = RD_base + 0xffd8,
102  // Peripheral ID7 Register
103  GICR_PIDR7 = RD_base + 0xffdc,
104  };
105 
106  static const uint32_t GICR_WAKER_ProcessorSleep = 1 << 1;
107  static const uint32_t GICR_WAKER_ChildrenAsleep = 1 << 2;
108 
110 
111  enum
112  {
113  // Interrupt Group Register 0
115  // Interrupt Set-Enable Register 0
117  // Interrupt Clear-Enable Register 0
119  // Interrupt Set-Pending Register 0
121  // Interrupt Clear-Pending Register 0
123  // Interrupt Set-Active Register 0
125  // Interrupt Clear-Active Register 0
127  // SGI Configuration Register
128  GICR_ICFGR0 = SGI_base + 0x0c00,
129  // PPI Configuration Register
130  GICR_ICFGR1 = SGI_base + 0x0c04,
131  // Interrupt Group Modifier Register 0
133  // Non-secure Access Control Register
134  GICR_NSACR = SGI_base + 0x0e00,
135  };
136 
137  // Interrupt Priority Registers
139 
140  // GIC physical LPI Redistributor register
141  enum
142  {
143  // Set LPI Pending Register
144  GICR_SETLPIR = RD_base + 0x0040,
145  // Clear LPI Pending Register
146  GICR_CLRLPIR = RD_base + 0x0048,
147  //Redistributor Properties Base Address Register
149  // Redistributor LPI Pending Table Base Address Register
151  // Redistributor Invalidate LPI Register
152  GICR_INVLPIR = RD_base + 0x00A0,
153  // Redistributor Invalidate All Register
154  GICR_INVALLR = RD_base + 0x00B0,
155  // Redistributor Synchronize Register
156  GICR_SYNCR = RD_base + 0x00C0,
157  };
158 
168 
169  bool DPG1S;
170  bool DPG1NS;
171  bool DPG0;
173 
175  uint8_t lpiIDBits;
177 
178  BitUnion8(LPIConfigurationTableEntry)
179  Bitfield<7, 2> priority;
180  Bitfield<1> res1;
181  Bitfield<0> enable;
182  EndBitUnion(LPIConfigurationTableEntry)
183 
184  static const uint32_t GICR_CTLR_ENABLE_LPIS = 1 << 0;
185  static const uint32_t GICR_CTLR_DPG0 = 1 << 24;
186  static const uint32_t GICR_CTLR_DPG1NS = 1 << 25;
187  static const uint32_t GICR_CTLR_DPG1S = 1 << 26;
188 
189  public:
190 
191  /*
192  * GICv3 defines only 2 64K consecutive frames for the redistributor
193  * (RD_base and SGI_base) but we are using 2 extra 64K stride frames
194  * to match GICv4 that defines 4 64K consecutive frames for them.
195  * Note this must match with DTB/DTS GIC node definition and boot
196  * loader code.
197  */
198  const uint32_t addrRangeSize;
199 
200  static const uint32_t SMALLEST_LPI_ID = 8192;
201 
202 
203  void activateIRQ(uint32_t int_id);
204  bool canBeSelectedFor1toNInterrupt(Gicv3::GroupId group) const;
205  void deactivateIRQ(uint32_t int_id);
206 
207  inline Gicv3CPUInterface *
209  {
210  return cpuInterface;
211  }
212 
213  uint32_t
215  {
216  return cpuId;
217  }
218 
219  Gicv3::GroupId getIntGroup(int int_id) const;
220  Gicv3::IntStatus intStatus(uint32_t int_id) const;
221  uint8_t readEntryLPI(uint32_t intid);
222  void writeEntryLPI(uint32_t intid, uint8_t lpi_entry);
223  bool isPendingLPI(uint32_t intid);
224  void setClrLPI(uint64_t data, bool set);
225  void sendSGI(uint32_t int_id, Gicv3::GroupId group, bool ns);
226  void serialize(CheckpointOut & cp) const override;
227  void unserialize(CheckpointIn & cp) override;
228  void update();
229  void updateDistributor();
230 
231  protected:
232 
233  bool isLevelSensitive(uint32_t int_id) const
234  {
235  return irqConfig[int_id] == Gicv3::INT_LEVEL_SENSITIVE;
236  }
237 
249  bool treatAsEdgeTriggered(uint32_t int_id) const
250  {
251  return !isLevelSensitive(int_id) || irqPendingIspendr[int_id];
252  }
253 
254  public:
255 
256  Gicv3Redistributor(Gicv3 * gic, uint32_t cpu_id);
257  uint32_t getAffinity() const;
258  void init();
259  uint64_t read(Addr addr, size_t size, bool is_secure_access);
260  void sendPPInt(uint32_t int_id);
261  void clearPPInt(uint32_t int_id);
262  void write(Addr addr, uint64_t data, size_t size, bool is_secure_access);
263 };
264 
265 } // namespace gem5
266 
267 #endif //__DEV_ARM_GICV3_REDISTRIBUTOR_H__
gem5::Gicv3::GroupId
GroupId
Definition: gic_v3.hh:93
gem5::Gicv3Redistributor::GICR_ICACTIVER0
@ GICR_ICACTIVER0
Definition: gic_v3_redistributor.hh:126
gem5::Gicv3Redistributor::irqGrpmod
std::vector< uint8_t > irqGrpmod
Definition: gic_v3_redistributor.hh:166
gem5::Gicv3Redistributor::priority
priority
Definition: gic_v3_redistributor.hh:179
gem5::Gicv3Redistributor::GICR_CTLR
@ GICR_CTLR
Definition: gic_v3_redistributor.hh:81
gem5::Gicv3Redistributor::GICR_CTLR_DPG1S
static const uint32_t GICR_CTLR_DPG1S
Definition: gic_v3_redistributor.hh:187
gem5::Gicv3Redistributor::DPG1NS
bool DPG1NS
Definition: gic_v3_redistributor.hh:170
data
const char data[]
Definition: circlebuf.test.cc:48
serialize.hh
gem5::Gicv3Redistributor::GICR_IGRPMODR0
@ GICR_IGRPMODR0
Definition: gic_v3_redistributor.hh:132
gem5::Gicv3Redistributor::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: gic_v3_redistributor.cc:1079
gem5::Gicv3Redistributor::GICR_CLRLPIR
@ GICR_CLRLPIR
Definition: gic_v3_redistributor.hh:146
gem5::Gicv3Redistributor::GICR_ISENABLER0
@ GICR_ISENABLER0
Definition: gic_v3_redistributor.hh:116
gem5::Gicv3Redistributor::update
void update()
Definition: gic_v3_redistributor.cc:805
gem5::Gicv3Redistributor::GICR_ICPENDR0
@ GICR_ICPENDR0
Definition: gic_v3_redistributor.hh:122
gem5::Gicv3Redistributor::read
uint64_t read(Addr addr, size_t size, bool is_secure_access)
Definition: gic_v3_redistributor.cc:94
gem5::Gicv3Redistributor
Definition: gic_v3_redistributor.hh:55
gem5::Gicv3Redistributor::GICR_INVLPIR
@ GICR_INVLPIR
Definition: gic_v3_redistributor.hh:152
gem5::Gicv3Redistributor::irqConfig
std::vector< Gicv3::IntTriggerType > irqConfig
Definition: gic_v3_redistributor.hh:165
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::Gicv3Redistributor::updateDistributor
void updateDistributor()
Definition: gic_v3_redistributor.cc:795
gem5::Gicv3Redistributor::GICR_PROPBASER
@ GICR_PROPBASER
Definition: gic_v3_redistributor.hh:148
gem5::Gicv3Redistributor::gic
Gicv3 * gic
Definition: gic_v3_redistributor.hh:65
gem5::Gicv3Redistributor::GICR_ICFGR1
@ GICR_ICFGR1
Definition: gic_v3_redistributor.hh:130
gem5::Gicv3Redistributor::GICR_WAKER_ProcessorSleep
static const uint32_t GICR_WAKER_ProcessorSleep
Definition: gic_v3_redistributor.hh:106
gem5::Gicv3Redistributor::init
void init()
Definition: gic_v3_redistributor.cc:85
gem5::Gicv3Redistributor::GICR_CTLR_DPG0
static const uint32_t GICR_CTLR_DPG0
Definition: gic_v3_redistributor.hh:185
gem5::Gicv3Redistributor::GICR_TYPER
@ GICR_TYPER
Definition: gic_v3_redistributor.hh:85
gem5::Gicv3Redistributor::isPendingLPI
bool isPendingLPI(uint32_t intid)
Definition: gic_v3_redistributor.cc:911
gem5::ArmISA::ns
Bitfield< 0 > ns
Definition: misc_types.hh:331
gem5::Gicv3Redistributor::GICR_IGROUPR0
@ GICR_IGROUPR0
Definition: gic_v3_redistributor.hh:114
std::vector< uint8_t >
gem5::Gicv3Redistributor::irqPending
std::vector< bool > irqPending
Definition: gic_v3_redistributor.hh:161
gem5::Gicv3Redistributor::GICR_PIDR4
@ GICR_PIDR4
Definition: gic_v3_redistributor.hh:97
gem5::Gicv3Redistributor::write
void write(Addr addr, uint64_t data, size_t size, bool is_secure_access)
Definition: gic_v3_redistributor.cc:389
gem5::Gicv3Redistributor::EnableLPIs
bool EnableLPIs
Definition: gic_v3_redistributor.hh:172
gem5::Gicv3Redistributor::lpiPendingTablePtr
Addr lpiPendingTablePtr
Definition: gic_v3_redistributor.hh:176
gem5::Gicv3Redistributor::cpuId
uint32_t cpuId
Definition: gic_v3_redistributor.hh:68
gem5::Gicv3Redistributor::getIntGroup
Gicv3::GroupId getIntGroup(int int_id) const
Definition: gic_v3_redistributor.cc:973
gem5::Gicv3Redistributor::DPG1S
bool DPG1S
Definition: gic_v3_redistributor.hh:169
gem5::Gicv3Redistributor::memProxy
PortProxy * memProxy
Definition: gic_v3_redistributor.hh:69
gem5::Gicv3Redistributor::GICR_PIDR0
@ GICR_PIDR0
Definition: gic_v3_redistributor.hh:89
gem5::Gicv3Redistributor::RD_base
static const uint32_t RD_base
Definition: gic_v3_redistributor.hh:75
gem5::Gicv3Redistributor::clearPPInt
void clearPPInt(uint32_t int_id)
Definition: gic_v3_redistributor.cc:728
gem5::Gicv3Redistributor::GICR_PIDR3
@ GICR_PIDR3
Definition: gic_v3_redistributor.hh:95
gem5::Gicv3Redistributor::distributor
Gicv3Distributor * distributor
Definition: gic_v3_redistributor.hh:66
gem5::Gicv3Redistributor::SGI_base
static const uint32_t SGI_base
Definition: gic_v3_redistributor.hh:76
gem5::Gicv3Redistributor::getCPUInterface
Gicv3CPUInterface * getCPUInterface() const
Definition: gic_v3_redistributor.hh:208
gem5::Serializable
Basic support for object serialization.
Definition: serialize.hh:169
gem5::Gicv3Redistributor::GICR_ICENABLER0
@ GICR_ICENABLER0
Definition: gic_v3_redistributor.hh:118
gem5::Gicv3::INT_LEVEL_SENSITIVE
@ INT_LEVEL_SENSITIVE
Definition: gic_v3.hh:102
gem5::Gicv3Redistributor::cpuInterface
Gicv3CPUInterface * cpuInterface
Definition: gic_v3_redistributor.hh:67
gem5::Gicv3Redistributor::GICR_WAKER
@ GICR_WAKER
Definition: gic_v3_redistributor.hh:87
gem5::Gicv3Redistributor::writeEntryLPI
void writeEntryLPI(uint32_t intid, uint8_t lpi_entry)
Definition: gic_v3_redistributor.cc:901
gem5::Gicv3Redistributor::GICR_IIDR
@ GICR_IIDR
Definition: gic_v3_redistributor.hh:83
gem5::Gicv3Redistributor::irqPriority
std::vector< uint8_t > irqPriority
Definition: gic_v3_redistributor.hh:164
gem5::Gicv3Redistributor::treatAsEdgeTriggered
bool treatAsEdgeTriggered(uint32_t int_id) const
This helper is used to check if an interrupt should be treated as edge triggered in the following sce...
Definition: gic_v3_redistributor.hh:249
gem5::Gicv3Redistributor::irqActive
std::vector< bool > irqActive
Definition: gic_v3_redistributor.hh:163
gem5::Gicv3Redistributor::peInLowPowerState
bool peInLowPowerState
Definition: gic_v3_redistributor.hh:109
gem5::Gicv3Redistributor::irqNsacr
std::vector< uint8_t > irqNsacr
Definition: gic_v3_redistributor.hh:167
gem5::PortProxy
This object is a proxy for a port or other object which implements the functional response protocol,...
Definition: port_proxy.hh:86
gem5::Gicv3Redistributor::processorNumber
uint32_t processorNumber() const
Definition: gic_v3_redistributor.hh:214
gem5::Gicv3Redistributor::sendPPInt
void sendPPInt(uint32_t int_id)
Definition: gic_v3_redistributor.cc:716
gem5::Gicv3Redistributor::GICR_ICFGR0
@ GICR_ICFGR0
Definition: gic_v3_redistributor.hh:128
gem5::Gicv3Redistributor::BitUnion8
BitUnion8(LPIConfigurationTableEntry) Bitfield< 7
gem5::Gicv3Redistributor::EndBitUnion
EndBitUnion(LPIConfigurationTableEntry) static const uint32_t GICR_CTLR_ENABLE_LPIS
gem5::Gicv3Redistributor::enable
Bitfield< 0 > enable
Definition: gic_v3_redistributor.hh:181
gem5::Gicv3Redistributor::GICR_NSACR
@ GICR_NSACR
Definition: gic_v3_redistributor.hh:134
gem5::Gicv3Redistributor::isLevelSensitive
bool isLevelSensitive(uint32_t int_id) const
Definition: gic_v3_redistributor.hh:233
gem5::Gicv3Redistributor::GICR_ISACTIVER0
@ GICR_ISACTIVER0
Definition: gic_v3_redistributor.hh:124
gem5::Gicv3Redistributor::DPG0
bool DPG0
Definition: gic_v3_redistributor.hh:171
gem5::Gicv3Redistributor::GICR_PENDBASER
@ GICR_PENDBASER
Definition: gic_v3_redistributor.hh:150
gem5::Gicv3Redistributor::irqGroup
std::vector< uint8_t > irqGroup
Definition: gic_v3_redistributor.hh:159
gem5::Gicv3Redistributor::GICR_SETLPIR
@ GICR_SETLPIR
Definition: gic_v3_redistributor.hh:144
gem5::Gicv3Redistributor::res1
Bitfield< 1 > res1
Definition: gic_v3_redistributor.hh:180
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::Gicv3Redistributor::GICR_PIDR1
@ GICR_PIDR1
Definition: gic_v3_redistributor.hh:91
gem5::Gicv3Redistributor::irqPendingIspendr
std::vector< bool > irqPendingIspendr
Definition: gic_v3_redistributor.hh:162
gem5::Gicv3Redistributor::GICR_PIDR2
@ GICR_PIDR2
Definition: gic_v3_redistributor.hh:93
addr_range.hh
gem5::Gicv3
Definition: gic_v3.hh:56
gem5::Gicv3Distributor
Definition: gic_v3_distributor.hh:51
gem5::Gicv3Redistributor::lpiIDBits
uint8_t lpiIDBits
Definition: gic_v3_redistributor.hh:175
gem5::Gicv3Redistributor::GICR_PIDR7
@ GICR_PIDR7
Definition: gic_v3_redistributor.hh:103
gem5::Gicv3CPUInterface
Definition: gic_v3_cpu_interface.hh:53
gem5::Gicv3Redistributor::lpiConfigurationTablePtr
Addr lpiConfigurationTablePtr
Definition: gic_v3_redistributor.hh:174
gem5::Gicv3Redistributor::deactivateIRQ
void deactivateIRQ(uint32_t int_id)
Definition: gic_v3_redistributor.cc:1008
gem5::Gicv3Its
GICv3 ITS module.
Definition: gic_v3_its.hh:83
gem5::Gicv3Redistributor::SMALLEST_LPI_ID
static const uint32_t SMALLEST_LPI_ID
Definition: gic_v3_redistributor.hh:200
gem5::Gicv3Redistributor::irqEnabled
std::vector< bool > irqEnabled
Definition: gic_v3_redistributor.hh:160
gem5::Gicv3::IntStatus
IntStatus
Definition: gic_v3.hh:84
gem5::Gicv3Redistributor::Gicv3Redistributor
Gicv3Redistributor(Gicv3 *gic, uint32_t cpu_id)
Definition: gic_v3_redistributor.cc:57
gem5::Gicv3Redistributor::intStatus
Gicv3::IntStatus intStatus(uint32_t int_id) const
Definition: gic_v3_redistributor.cc:777
gem5::Gicv3Redistributor::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: gic_v3_redistributor.cc:1057
gem5::Gicv3Redistributor::GICR_CTLR_DPG1NS
static const uint32_t GICR_CTLR_DPG1NS
Definition: gic_v3_redistributor.hh:186
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::Gicv3Redistributor::GICR_PIDR6
@ GICR_PIDR6
Definition: gic_v3_redistributor.hh:101
gem5::Gicv3Redistributor::setClrLPI
void setClrLPI(uint64_t data, bool set)
Definition: gic_v3_redistributor.cc:923
gem5::Gicv3Redistributor::GICR_PIDR5
@ GICR_PIDR5
Definition: gic_v3_redistributor.hh:99
gem5::AddrRange
The AddrRange class encapsulates an address range, and supports a number of tests to check if two ran...
Definition: addr_range.hh:71
gem5::Gicv3Redistributor::canBeSelectedFor1toNInterrupt
bool canBeSelectedFor1toNInterrupt(Gicv3::GroupId group) const
Definition: gic_v3_redistributor.cc:1031
gem5::Gicv3Redistributor::readEntryLPI
uint8_t readEntryLPI(uint32_t intid)
Definition: gic_v3_redistributor.cc:888
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::Gicv3Redistributor::addrRangeSize
const uint32_t addrRangeSize
Definition: gic_v3_redistributor.hh:198
gem5::Gicv3Redistributor::GICR_WAKER_ChildrenAsleep
static const uint32_t GICR_WAKER_ChildrenAsleep
Definition: gic_v3_redistributor.hh:107
gem5::Gicv3Redistributor::sendSGI
void sendSGI(uint32_t int_id, Gicv3::GroupId group, bool ns)
Definition: gic_v3_redistributor.cc:739
gic_v3.hh
gem5::Gicv3Redistributor::activateIRQ
void activateIRQ(uint32_t int_id)
Definition: gic_v3_redistributor.cc:999
gem5::Gicv3Redistributor::GICR_IPRIORITYR
static const AddrRange GICR_IPRIORITYR
Definition: gic_v3_redistributor.hh:138
gem5::Gicv3Redistributor::GICR_SYNCR
@ GICR_SYNCR
Definition: gic_v3_redistributor.hh:156
gem5::Gicv3Redistributor::GICR_INVALLR
@ GICR_INVALLR
Definition: gic_v3_redistributor.hh:154
gem5::Gicv3Redistributor::GICR_ISPENDR0
@ GICR_ISPENDR0
Definition: gic_v3_redistributor.hh:120
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::Gicv3Redistributor::getAffinity
uint32_t getAffinity() const
Definition: gic_v3_redistributor.cc:1014

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