#include <gic_v3_distributor.hh>

Inheritance diagram for gem5::Gicv3Distributor:

Public Member Functions
	Gicv3Distributor (Gicv3 *gic, uint32_t it_lines)

void	sendInt (uint32_t int_id)

void	clearInt (uint32_t int_id)

void	deassertSPI (uint32_t int_id)

void	clearIrqCpuInterface (uint32_t int_id)

void	init ()

uint64_t	read (Addr addr, size_t size, bool is_secure_access)

void	write (Addr addr, uint64_t data, size_t size, bool is_secure_access)

void	copy (Gicv3Registers from, Gicv3Registers to)

void	update ()

Public Member Functions inherited from gem5::Serializable
	Serializable ()

virtual	~Serializable ()

void	serializeSection (CheckpointOut &cp, const char *name) const
	Serialize an object into a new section.

void	serializeSection (CheckpointOut &cp, const std::string &name) const

void	unserializeSection (CheckpointIn &cp, const char *name)
	Unserialize an a child object.

void	unserializeSection (CheckpointIn &cp, const std::string &name)

Static Public Attributes
static const uint32_t	ADDR_RANGE_SIZE = 0x10000

static const uint32_t	IDBITS = 0xf

Protected Types
enum	{ GICD_CTLR = 0x0000 , GICD_TYPER = 0x0004 , GICD_IIDR = 0x0008 , GICD_TYPER2 = 0x000C , GICD_STATUSR = 0x0010 , GICD_SETSPI_NSR = 0x0040 , GICD_CLRSPI_NSR = 0x0048 , GICD_SETSPI_SR = 0x0050 , GICD_CLRSPI_SR = 0x0058 , GICD_SGIR = 0x0f00 , GICD_PIDR0 = 0xffe0 , GICD_PIDR1 = 0xffe4 , GICD_PIDR2 = 0xffe8 , GICD_PIDR3 = 0xffec , GICD_PIDR4 = 0xffd0 , GICD_PIDR5 = 0xffd4 , GICD_PIDR6 = 0xffd8 , GICD_PIDR7 = 0xffdc }

Protected Member Functions
	BitUnion64 (IROUTER) Bitfield< 63

	EndBitUnion (IROUTER) static const uint32_t GICD_CTLR_ENABLEGRP0

void	activateIRQ (uint32_t int_id)

void	deactivateIRQ (uint32_t int_id)

void	fullUpdate ()

Gicv3::GroupId	getIntGroup (int int_id) const

bool	groupEnabled (Gicv3::GroupId group) const

Gicv3::IntStatus	intStatus (uint32_t int_id) const

bool	isNotSPI (uint32_t int_id) const

bool	isLevelSensitive (uint32_t int_id) const

bool	treatAsEdgeTriggered (uint32_t int_id) const
	This helper is used to check if an interrupt should be treated as edge triggered in the following scenarios:

bool	nsAccessToSecInt (uint32_t int_id, bool is_secure_access) const

void	serialize (CheckpointOut &cp) const override
	Serialize an object.

void	unserialize (CheckpointIn &cp) override
	Unserialize an object.

Gicv3CPUInterface *	route (uint32_t int_id)

Protected Attributes
Gicv3 *	gic

const uint32_t	itLines

	res0_1

Bitfield< 39, 32 >	Aff3

Bitfield< 31 >	IRM

Bitfield< 30, 24 >	res0_2

Bitfield< 23, 16 >	Aff2

Bitfield< 15, 8 >	Aff1

Bitfield< 7, 0 >	Aff0

bool	ARE

bool	DS

bool	EnableGrp1S

bool	EnableGrp1NS

bool	EnableGrp0

std::vector< uint8_t >	irqGroup

std::vector< bool >	irqEnabled

std::vector< bool >	irqPending

std::vector< bool >	irqPendingIspendr

std::vector< bool >	irqActive

std::vector< uint8_t >	irqPriority

std::vector< Gicv3::IntTriggerType >	irqConfig

std::vector< uint8_t >	irqGrpmod

std::vector< uint8_t >	irqNsacr

std::vector< IROUTER >	irqAffinityRouting

uint32_t	gicdTyper

uint32_t	gicdPidr0

uint32_t	gicdPidr1

uint32_t	gicdPidr2

uint32_t	gicdPidr3

uint32_t	gicdPidr4

Static Protected Attributes
static const AddrRange	GICD_IGROUPR

static const AddrRange	GICD_ISENABLER

static const AddrRange	GICD_ICENABLER

static const AddrRange	GICD_ISPENDR

static const AddrRange	GICD_ICPENDR

static const AddrRange	GICD_ISACTIVER

static const AddrRange	GICD_ICACTIVER

static const AddrRange	GICD_IPRIORITYR

static const AddrRange	GICD_ITARGETSR

static const AddrRange	GICD_ICFGR

static const AddrRange	GICD_IGRPMODR

static const AddrRange	GICD_NSACR

static const AddrRange	GICD_CPENDSGIR

static const AddrRange	GICD_SPENDSGIR

static const AddrRange	GICD_IROUTER

static const uint32_t	GICD_CTLR_ENABLEGRP1 = 1 << 0

static const uint32_t	GICD_CTLR_ENABLEGRP1NS = 1 << 1

static const uint32_t	GICD_CTLR_ENABLEGRP1A = 1 << 1

static const uint32_t	GICD_CTLR_ENABLEGRP1S = 1 << 2

static const uint32_t	GICD_CTLR_DS = 1 << 6

Friends
class	Gicv3Redistributor

class	Gicv3CPUInterface

class	Gicv3Its

Additional Inherited Members
Static Public Member Functions inherited from gem5::Serializable
static const std::string &	currentSection ()
	Gets the fully-qualified name of the active section.

static void	generateCheckpointOut (const std::string &cpt_dir, std::ofstream &outstream)
	Generate a checkpoint file so that the serialization can be routed to it.

Detailed Description

Definition at line 51 of file gic_v3_distributor.hh.

Member Enumeration Documentation

◆ anonymous enum

anonymous enum

protected

Enumerator
GICD_CTLR
GICD_TYPER
GICD_IIDR
GICD_TYPER2
GICD_STATUSR
GICD_SETSPI_NSR
GICD_CLRSPI_NSR
GICD_SETSPI_SR
GICD_CLRSPI_SR
GICD_SGIR
GICD_PIDR0
GICD_PIDR1
GICD_PIDR2
GICD_PIDR3
GICD_PIDR4
GICD_PIDR5
GICD_PIDR6
GICD_PIDR7

Definition at line 64 of file gic_v3_distributor.hh.

Constructor & Destructor Documentation

◆ Gicv3Distributor()

gem5::Gicv3Distributor::Gicv3Distributor	(	Gicv3 *	gic,
		uint32_t	it_lines )

Definition at line 71 of file gic_v3_distributor.cc.

References gem5::divCeil(), DS, gem5::BaseGic::getSystem(), gic, gicdTyper, gem5::ArmSystem::has(), IDBITS, gem5::Gicv3::INTID_SECURE, itLines, and panic_if.

Member Function Documentation

◆ activateIRQ()

void gem5::Gicv3Distributor::activateIRQ ( uint32_t int_id )

protected

Definition at line 1170 of file gic_v3_distributor.cc.

References irqActive, irqPending, and treatAsEdgeTriggered().

◆ BitUnion64()

gem5::Gicv3Distributor::BitUnion64 ( IROUTER )

protected

◆ clearInt()

void gem5::Gicv3Distributor::clearInt ( uint32_t int_id )

Definition at line 1020 of file gic_v3_distributor.cc.

References deassertSPI(), and isLevelSensitive().

Referenced by gem5::Gicv3::clearInt().

◆ clearIrqCpuInterface()

void gem5::Gicv3Distributor::clearIrqCpuInterface ( uint32_t int_id )

Definition at line 1078 of file gic_v3_distributor.cc.

References route().

Referenced by deassertSPI(), and write().

◆ copy()

void gem5::Gicv3Distributor::copy	(	Gicv3Registers *	from,
		Gicv3Registers *	to )

Definition at line 1185 of file gic_v3_distributor.cc.

References gem5::Gicv3Registers::clearDistRange(), gem5::Gicv3Registers::copyDistRange(), gem5::Gicv3Registers::copyDistRegister(), gic, GICD_CTLR, GICD_ICACTIVER, GICD_ICENABLER, GICD_ICFGR, GICD_ICPENDR, GICD_IGROUPR, GICD_IGRPMODR, GICD_IPRIORITYR, GICD_IROUTER, GICD_ISACTIVER, GICD_ISENABLER, GICD_ISPENDR, GICD_ITARGETSR, GICD_NSACR, itLines, gem5::AddrRange::start(), and gem5::PowerISA::to.

Referenced by gem5::Gicv3::copyGicState().

◆ deactivateIRQ()

void gem5::Gicv3Distributor::deactivateIRQ ( uint32_t int_id )

protected

Definition at line 1179 of file gic_v3_distributor.cc.

References irqActive.

Referenced by gem5::Gicv3CPUInterface::deactivateIRQ().

◆ deassertSPI()

void gem5::Gicv3Distributor::deassertSPI ( uint32_t int_id )

Definition at line 1030 of file gic_v3_distributor.cc.

References clearIrqCpuInterface(), irqPending, itLines, panic_if, gem5::Gicv3::PPI_MAX, gem5::Gicv3::SGI_MAX, and update().

Referenced by clearInt(), and write().

◆ EndBitUnion()

gem5::Gicv3Distributor::EndBitUnion ( IROUTER ) const

protected

◆ fullUpdate()

void gem5::Gicv3Distributor::fullUpdate ( )

protected

◆ getIntGroup()

Gicv3::GroupId gem5::Gicv3Distributor::getIntGroup ( int int_id ) const

protected

Definition at line 1143 of file gic_v3_distributor.cc.

References DS, gem5::Gicv3::G0S, gem5::Gicv3::G1NS, gem5::Gicv3::G1S, irqGroup, irqGrpmod, itLines, panic_if, gem5::Gicv3::PPI_MAX, and gem5::Gicv3::SGI_MAX.

Referenced by nsAccessToSecInt(), read(), route(), gem5::Gicv3CPUInterface::setMiscReg(), update(), gem5::Gicv3CPUInterface::virtualDeactivateIRQ(), and write().

◆ groupEnabled()

bool gem5::Gicv3Distributor::groupEnabled ( Gicv3::GroupId group ) const

inlineprotected

Definition at line 188 of file gic_v3_distributor.hh.

References DS, EnableGrp0, EnableGrp1NS, EnableGrp1S, gem5::Gicv3::G0S, gem5::Gicv3::G1NS, gem5::Gicv3::G1S, and panic.

Referenced by gem5::Gicv3Redistributor::canBeSelectedFor1toNInterrupt(), update(), and gem5::Gicv3Redistributor::update().

◆ init()

void gem5::Gicv3Distributor::init ( )

Definition at line 137 of file gic_v3_distributor.cc.

Referenced by gem5::Gicv3::init().

◆ intStatus()

Gicv3::IntStatus gem5::Gicv3Distributor::intStatus ( uint32_t int_id ) const

protected

Definition at line 1124 of file gic_v3_distributor.cc.

References gem5::Gicv3::INT_ACTIVE, gem5::Gicv3::INT_ACTIVE_PENDING, gem5::Gicv3::INT_INACTIVE, gem5::Gicv3::INT_PENDING, irqActive, irqPending, itLines, panic_if, gem5::Gicv3::PPI_MAX, and gem5::Gicv3::SGI_MAX.

◆ isLevelSensitive()

bool gem5::Gicv3Distributor::isLevelSensitive ( uint32_t int_id ) const

inlineprotected

Definition at line 232 of file gic_v3_distributor.hh.

References gem5::Gicv3::INT_LEVEL_SENSITIVE, and irqConfig.

Referenced by clearInt(), and treatAsEdgeTriggered().

◆ isNotSPI()

bool gem5::Gicv3Distributor::isNotSPI ( uint32_t int_id ) const

inlineprotected

Definition at line 223 of file gic_v3_distributor.hh.

References itLines, gem5::Gicv3::PPI_MAX, and gem5::Gicv3::SGI_MAX.

Referenced by read(), and write().

◆ nsAccessToSecInt()

bool gem5::Gicv3Distributor::nsAccessToSecInt	(	uint32_t	int_id,
		bool	is_secure_access ) const

inlineprotected

Definition at line 253 of file gic_v3_distributor.hh.

References DS, gem5::Gicv3::G1NS, and getIntGroup().

Referenced by read(), and write().

◆ read()

uint64_t gem5::Gicv3Distributor::read	(	Addr	addr,
		size_t	size,
		bool	is_secure_access )

Definition at line 142 of file gic_v3_distributor.cc.

References gem5::X86ISA::addr, ARE, gem5::AddrRange::contains(), DS, EnableGrp0, EnableGrp1NS, EnableGrp1S, gem5::Gicv3::G1NS, getIntGroup(), gic, GICD_CPENDSGIR, GICD_CTLR, GICD_ICACTIVER, GICD_ICENABLER, GICD_ICFGR, GICD_ICPENDR, GICD_IGROUPR, GICD_IGRPMODR, GICD_IIDR, GICD_IPRIORITYR, GICD_IROUTER, GICD_ISACTIVER, GICD_ISENABLER, GICD_ISPENDR, GICD_ITARGETSR, GICD_NSACR, GICD_PIDR0, GICD_PIDR1, GICD_PIDR2, GICD_PIDR3, GICD_PIDR4, GICD_PIDR5, GICD_PIDR6, GICD_PIDR7, GICD_SPENDSGIR, GICD_STATUSR, GICD_TYPER, GICD_TYPER2, gicdPidr0, gicdPidr1, gicdPidr2, gicdPidr3, gicdPidr4, gicdTyper, gem5::ArmISA::i, gem5::Gicv3::INT_EDGE_TRIGGERED, irqActive, irqAffinityRouting, irqConfig, irqEnabled, irqGroup, irqGrpmod, irqNsacr, irqPending, irqPriority, isNotSPI(), itLines, nsAccessToSecInt(), gem5::Gicv3::reserved(), gem5::AddrRange::start(), gem5::X86ISA::val, and warn.

Referenced by gem5::Gicv3::read(), and gem5::Gicv3::readDistributor().

◆ route()

Gicv3CPUInterface * gem5::Gicv3Distributor::route ( uint32_t int_id )

protected

Definition at line 1041 of file gic_v3_distributor.cc.

References gem5::ArmISA::affinity, gem5::Gicv3Redistributor::getCPUInterface(), getIntGroup(), gem5::Gicv3::getRedistributor(), gem5::Gicv3::getRedistributorByAffinity(), gem5::BaseGic::getSystem(), gic, gem5::ArmISA::i, and irqAffinityRouting.

Referenced by clearIrqCpuInterface(), and update().

◆ sendInt()

void gem5::Gicv3Distributor::sendInt ( uint32_t int_id )

Definition at line 1008 of file gic_v3_distributor.cc.

References DPRINTF, irqPending, irqPendingIspendr, itLines, panic_if, gem5::Gicv3::PPI_MAX, gem5::Gicv3::SGI_MAX, and update().

Referenced by gem5::Gicv3::sendInt(), and write().

◆ serialize()

void gem5::Gicv3Distributor::serialize ( CheckpointOut & cp ) const

overrideprotectedvirtual

Serialize an object.

Output an object's state into the current checkpoint section.

Parameters

cp	Checkpoint state

Implements gem5::Serializable.

Definition at line 1208 of file gic_v3_distributor.cc.

References ARE, DS, EnableGrp0, EnableGrp1NS, EnableGrp1S, irqActive, irqAffinityRouting, irqConfig, irqEnabled, irqGroup, irqGrpmod, irqNsacr, irqPending, irqPendingIspendr, irqPriority, SERIALIZE_CONTAINER, and SERIALIZE_SCALAR.

◆ treatAsEdgeTriggered()

bool gem5::Gicv3Distributor::treatAsEdgeTriggered ( uint32_t int_id ) const

inlineprotected

This helper is used to check if an interrupt should be treated as edge triggered in the following scenarios:

a) While activating the interrupt b) While clearing an interrupt via ICPENDR

In fact, in these two situations, a level sensitive interrupt which had been made pending via a write to ISPENDR, will be treated as it if was edge triggered.

Definition at line 248 of file gic_v3_distributor.hh.

References irqPendingIspendr, and isLevelSensitive().

Referenced by activateIRQ(), and write().

◆ unserialize()

void gem5::Gicv3Distributor::unserialize ( CheckpointIn & cp )

overrideprotectedvirtual

Unserialize an object.

Read an object's state from the current checkpoint section.

Parameters

cp	Checkpoint state

Implements gem5::Serializable.

Definition at line 1228 of file gic_v3_distributor.cc.

References ARE, DS, EnableGrp0, EnableGrp1NS, EnableGrp1S, irqActive, irqAffinityRouting, irqConfig, irqEnabled, irqGroup, irqGrpmod, irqNsacr, irqPending, irqPendingIspendr, irqPriority, UNSERIALIZE_CONTAINER, and UNSERIALIZE_SCALAR.

◆ update()

void gem5::Gicv3Distributor::update ( )

◆ write()

void gem5::Gicv3Distributor::write	(	Addr	addr,
		uint64_t	data,
		size_t	size,
		bool	is_secure_access )

Definition at line 514 of file gic_v3_distributor.cc.

References gem5::X86ISA::addr, gem5::bits(), clearIrqCpuInterface(), gem5::AddrRange::contains(), data, deassertSPI(), DPRINTF, DS, gem5::X86ISA::enable, EnableGrp0, EnableGrp1NS, EnableGrp1S, gem5::Gicv3::G1NS, getIntGroup(), gic, GICD_CLRSPI_NSR, GICD_CLRSPI_SR, GICD_CTLR, GICD_CTLR_DS, GICD_CTLR_ENABLEGRP1A, GICD_CTLR_ENABLEGRP1NS, GICD_CTLR_ENABLEGRP1S, GICD_ICACTIVER, GICD_ICENABLER, GICD_ICFGR, GICD_ICPENDR, GICD_IGROUPR, GICD_IGRPMODR, GICD_IPRIORITYR, GICD_IROUTER, GICD_ISACTIVER, GICD_ISENABLER, GICD_ISPENDR, GICD_ITARGETSR, GICD_NSACR, GICD_SETSPI_NSR, GICD_SETSPI_SR, GICD_SGIR, gem5::ArmISA::i, gem5::Gicv3::INT_EDGE_TRIGGERED, gem5::Gicv3::INT_LEVEL_SENSITIVE, irqActive, irqAffinityRouting, irqConfig, irqEnabled, irqGroup, irqGrpmod, irqNsacr, irqPending, irqPendingIspendr, irqPriority, isNotSPI(), itLines, nsAccessToSecInt(), gem5::Gicv3::reserved(), sendInt(), gem5::AddrRange::start(), treatAsEdgeTriggered(), update(), and warn.

Referenced by gem5::Gicv3::write(), and gem5::Gicv3::writeDistributor().

Friends And Related Symbol Documentation

◆ Gicv3CPUInterface

friend class Gicv3CPUInterface

friend

Definition at line 56 of file gic_v3_distributor.hh.

◆ Gicv3Its

friend class Gicv3Its

friend

Definition at line 57 of file gic_v3_distributor.hh.

◆ Gicv3Redistributor

friend class Gicv3Redistributor

friend

Definition at line 55 of file gic_v3_distributor.hh.

Member Data Documentation

◆ ADDR_RANGE_SIZE

const uint32_t gem5::Gicv3Distributor::ADDR_RANGE_SIZE = 0x10000

static

Definition at line 177 of file gic_v3_distributor.hh.

Referenced by gem5::Gicv3::init().

◆ Aff0

Bitfield<7, 0> gem5::Gicv3Distributor::Aff0

protected

Definition at line 142 of file gic_v3_distributor.hh.

◆ Aff1

Bitfield<15, 8> gem5::Gicv3Distributor::Aff1

protected

Definition at line 141 of file gic_v3_distributor.hh.

◆ Aff2

Bitfield<23, 16> gem5::Gicv3Distributor::Aff2

protected

Definition at line 140 of file gic_v3_distributor.hh.

◆ Aff3

Bitfield<39, 32> gem5::Gicv3Distributor::Aff3

protected

Definition at line 137 of file gic_v3_distributor.hh.

◆ ARE

bool gem5::Gicv3Distributor::ARE

protected

Definition at line 152 of file gic_v3_distributor.hh.

Referenced by read(), serialize(), and unserialize().

◆ DS

bool gem5::Gicv3Distributor::DS

protected

Definition at line 153 of file gic_v3_distributor.hh.

Referenced by gem5::Gicv3CPUInterface::getHPPIR0(), gem5::Gicv3CPUInterface::getHPPIR1(), getIntGroup(), gem5::Gicv3Redistributor::getIntGroup(), Gicv3Distributor(), groupEnabled(), gem5::Gicv3CPUInterface::intSignalType(), nsAccessToSecInt(), read(), gem5::Gicv3Redistributor::read(), gem5::Gicv3Redistributor::sendSGI(), serialize(), gem5::Gicv3CPUInterface::setMiscReg(), unserialize(), write(), and gem5::Gicv3Redistributor::write().

◆ EnableGrp0

bool gem5::Gicv3Distributor::EnableGrp0

protected

Definition at line 156 of file gic_v3_distributor.hh.

Referenced by gem5::Gicv3CPUInterface::groupEnabled(), groupEnabled(), read(), serialize(), unserialize(), and write().

◆ EnableGrp1NS

bool gem5::Gicv3Distributor::EnableGrp1NS

protected

Definition at line 155 of file gic_v3_distributor.hh.

Referenced by gem5::Gicv3CPUInterface::groupEnabled(), groupEnabled(), read(), serialize(), unserialize(), and write().

◆ EnableGrp1S

bool gem5::Gicv3Distributor::EnableGrp1S

protected

Definition at line 154 of file gic_v3_distributor.hh.

Referenced by gem5::Gicv3CPUInterface::groupEnabled(), groupEnabled(), read(), serialize(), unserialize(), and write().

◆ gic

Gicv3* gem5::Gicv3Distributor::gic

protected

Definition at line 61 of file gic_v3_distributor.hh.

Referenced by copy(), Gicv3Distributor(), read(), route(), update(), and write().

◆ GICD_CPENDSGIR

const AddrRange gem5::Gicv3Distributor::GICD_CPENDSGIR

staticprotected

Definition at line 129 of file gic_v3_distributor.hh.

Referenced by read().

◆ GICD_CTLR_DS

const uint32_t gem5::Gicv3Distributor::GICD_CTLR_DS = 1 << 6

staticprotected

Definition at line 150 of file gic_v3_distributor.hh.

Referenced by write().

◆ GICD_CTLR_ENABLEGRP1

const uint32_t gem5::Gicv3Distributor::GICD_CTLR_ENABLEGRP1 = 1 << 0

staticprotected

Definition at line 146 of file gic_v3_distributor.hh.

◆ GICD_CTLR_ENABLEGRP1A

const uint32_t gem5::Gicv3Distributor::GICD_CTLR_ENABLEGRP1A = 1 << 1

staticprotected

Definition at line 148 of file gic_v3_distributor.hh.

Referenced by write().

◆ GICD_CTLR_ENABLEGRP1NS

const uint32_t gem5::Gicv3Distributor::GICD_CTLR_ENABLEGRP1NS = 1 << 1

staticprotected

Definition at line 147 of file gic_v3_distributor.hh.

Referenced by write().

◆ GICD_CTLR_ENABLEGRP1S

const uint32_t gem5::Gicv3Distributor::GICD_CTLR_ENABLEGRP1S = 1 << 2

staticprotected

Definition at line 149 of file gic_v3_distributor.hh.

Referenced by write().

◆ GICD_ICACTIVER

const AddrRange gem5::Gicv3Distributor::GICD_ICACTIVER

staticprotected

Definition at line 117 of file gic_v3_distributor.hh.

Referenced by copy(), read(), and write().

◆ GICD_ICENABLER

const AddrRange gem5::Gicv3Distributor::GICD_ICENABLER

staticprotected

Definition at line 109 of file gic_v3_distributor.hh.

Referenced by copy(), read(), and write().

◆ GICD_ICFGR

const AddrRange gem5::Gicv3Distributor::GICD_ICFGR

staticprotected

Definition at line 123 of file gic_v3_distributor.hh.

Referenced by copy(), read(), and write().

◆ GICD_ICPENDR

const AddrRange gem5::Gicv3Distributor::GICD_ICPENDR

staticprotected

Definition at line 113 of file gic_v3_distributor.hh.

Referenced by copy(), read(), and write().

◆ GICD_IGROUPR

const AddrRange gem5::Gicv3Distributor::GICD_IGROUPR

staticprotected

Definition at line 105 of file gic_v3_distributor.hh.

Referenced by copy(), read(), and write().

◆ GICD_IGRPMODR

const AddrRange gem5::Gicv3Distributor::GICD_IGRPMODR

staticprotected

Definition at line 125 of file gic_v3_distributor.hh.

Referenced by copy(), read(), and write().

◆ GICD_IPRIORITYR

const AddrRange gem5::Gicv3Distributor::GICD_IPRIORITYR

staticprotected

Definition at line 119 of file gic_v3_distributor.hh.

Referenced by copy(), read(), and write().

◆ GICD_IROUTER

const AddrRange gem5::Gicv3Distributor::GICD_IROUTER

staticprotected

Definition at line 133 of file gic_v3_distributor.hh.

Referenced by copy(), read(), and write().

◆ GICD_ISACTIVER

const AddrRange gem5::Gicv3Distributor::GICD_ISACTIVER

staticprotected

Definition at line 115 of file gic_v3_distributor.hh.

Referenced by copy(), read(), and write().

◆ GICD_ISENABLER

const AddrRange gem5::Gicv3Distributor::GICD_ISENABLER

staticprotected

Definition at line 107 of file gic_v3_distributor.hh.

Referenced by copy(), read(), and write().

◆ GICD_ISPENDR

const AddrRange gem5::Gicv3Distributor::GICD_ISPENDR

staticprotected

Definition at line 111 of file gic_v3_distributor.hh.

Referenced by copy(), read(), and write().

◆ GICD_ITARGETSR

const AddrRange gem5::Gicv3Distributor::GICD_ITARGETSR

staticprotected

Definition at line 121 of file gic_v3_distributor.hh.

Referenced by copy(), read(), and write().

◆ GICD_NSACR

const AddrRange gem5::Gicv3Distributor::GICD_NSACR

staticprotected

Definition at line 127 of file gic_v3_distributor.hh.

Referenced by copy(), read(), and write().

◆ GICD_SPENDSGIR

const AddrRange gem5::Gicv3Distributor::GICD_SPENDSGIR

staticprotected

Definition at line 131 of file gic_v3_distributor.hh.

Referenced by read().

◆ gicdPidr0

uint32_t gem5::Gicv3Distributor::gicdPidr0

protected

Definition at line 169 of file gic_v3_distributor.hh.

Referenced by read().

◆ gicdPidr1

uint32_t gem5::Gicv3Distributor::gicdPidr1

protected

Definition at line 170 of file gic_v3_distributor.hh.

Referenced by read().

◆ gicdPidr2

uint32_t gem5::Gicv3Distributor::gicdPidr2

protected

Definition at line 171 of file gic_v3_distributor.hh.

Referenced by read(), gem5::Gicv3Its::read(), and gem5::Gicv3Redistributor::read().

◆ gicdPidr3

uint32_t gem5::Gicv3Distributor::gicdPidr3

protected

Definition at line 172 of file gic_v3_distributor.hh.

Referenced by read().

◆ gicdPidr4

uint32_t gem5::Gicv3Distributor::gicdPidr4

protected

Definition at line 173 of file gic_v3_distributor.hh.

Referenced by read().

◆ gicdTyper

uint32_t gem5::Gicv3Distributor::gicdTyper

protected

Definition at line 168 of file gic_v3_distributor.hh.

Referenced by Gicv3Distributor(), and read().

◆ IDBITS

const uint32_t gem5::Gicv3Distributor::IDBITS = 0xf

static

Definition at line 178 of file gic_v3_distributor.hh.

Referenced by Gicv3Distributor(), and gem5::Gicv3Its::lpiOutOfRange().

◆ IRM

Bitfield<31> gem5::Gicv3Distributor::IRM

protected

Definition at line 138 of file gic_v3_distributor.hh.

◆ irqActive

std::vector<bool> gem5::Gicv3Distributor::irqActive

protected

Definition at line 161 of file gic_v3_distributor.hh.

Referenced by activateIRQ(), deactivateIRQ(), intStatus(), read(), serialize(), unserialize(), update(), and write().

◆ irqAffinityRouting

std::vector<IROUTER> gem5::Gicv3Distributor::irqAffinityRouting

protected

Definition at line 166 of file gic_v3_distributor.hh.

Referenced by read(), route(), serialize(), unserialize(), and write().

◆ irqConfig

std::vector<Gicv3::IntTriggerType> gem5::Gicv3Distributor::irqConfig

protected

Definition at line 163 of file gic_v3_distributor.hh.

Referenced by isLevelSensitive(), read(), serialize(), unserialize(), and write().

◆ irqEnabled

std::vector<bool> gem5::Gicv3Distributor::irqEnabled

protected

Definition at line 158 of file gic_v3_distributor.hh.

Referenced by read(), serialize(), unserialize(), update(), and write().

◆ irqGroup

std::vector<uint8_t> gem5::Gicv3Distributor::irqGroup

protected

Definition at line 157 of file gic_v3_distributor.hh.

Referenced by getIntGroup(), read(), serialize(), unserialize(), and write().

◆ irqGrpmod

std::vector<uint8_t> gem5::Gicv3Distributor::irqGrpmod

protected

Definition at line 164 of file gic_v3_distributor.hh.

Referenced by getIntGroup(), read(), serialize(), unserialize(), and write().

◆ irqNsacr

std::vector<uint8_t> gem5::Gicv3Distributor::irqNsacr

protected

Definition at line 165 of file gic_v3_distributor.hh.

Referenced by read(), serialize(), unserialize(), and write().

◆ irqPending

std::vector<bool> gem5::Gicv3Distributor::irqPending

protected

Definition at line 159 of file gic_v3_distributor.hh.

Referenced by activateIRQ(), deassertSPI(), intStatus(), read(), sendInt(), serialize(), unserialize(), update(), and write().

◆ irqPendingIspendr

std::vector<bool> gem5::Gicv3Distributor::irqPendingIspendr

protected

Definition at line 160 of file gic_v3_distributor.hh.

Referenced by sendInt(), serialize(), treatAsEdgeTriggered(), unserialize(), and write().

◆ irqPriority

std::vector<uint8_t> gem5::Gicv3Distributor::irqPriority

protected

Definition at line 162 of file gic_v3_distributor.hh.

Referenced by read(), serialize(), unserialize(), update(), and write().

◆ itLines

const uint32_t gem5::Gicv3Distributor::itLines

protected

Definition at line 62 of file gic_v3_distributor.hh.

Referenced by copy(), deassertSPI(), getIntGroup(), Gicv3Distributor(), intStatus(), isNotSPI(), read(), sendInt(), update(), and write().

◆ res0_1

gem5::Gicv3Distributor::res0_1

protected

Definition at line 136 of file gic_v3_distributor.hh.

◆ res0_2

Bitfield<30, 24> gem5::Gicv3Distributor::res0_2

protected

Definition at line 139 of file gic_v3_distributor.hh.

The documentation for this class was generated from the following files:

dev/arm/gic_v3_distributor.hh
dev/arm/gic_v3_distributor.cc

Public Member Functions

Static Public Attributes

Protected Types

Protected Member Functions

Protected Attributes

Static Protected Attributes

Friends

Additional Inherited Members

Detailed Description

Member Enumeration Documentation

◆ anonymous enum

Constructor & Destructor Documentation

◆ Gicv3Distributor()

Member Function Documentation

◆ activateIRQ()

◆ BitUnion64()

◆ clearInt()

◆ clearIrqCpuInterface()

◆ copy()

◆ deactivateIRQ()

◆ deassertSPI()

◆ EndBitUnion()

◆ fullUpdate()

◆ getIntGroup()

◆ groupEnabled()

◆ init()

◆ intStatus()

◆ isLevelSensitive()

◆ isNotSPI()

◆ nsAccessToSecInt()

◆ read()

◆ route()

◆ sendInt()

◆ serialize()

◆ treatAsEdgeTriggered()

◆ unserialize()

◆ update()

◆ write()

Friends And Related Symbol Documentation

◆ Gicv3CPUInterface

◆ Gicv3Its

◆ Gicv3Redistributor

Member Data Documentation

◆ ADDR_RANGE_SIZE

◆ Aff0

◆ Aff1

◆ Aff2

◆ Aff3

◆ ARE

◆ DS

◆ EnableGrp0

◆ EnableGrp1NS

◆ EnableGrp1S

◆ gic

◆ GICD_CPENDSGIR

◆ GICD_CTLR_DS

◆ GICD_CTLR_ENABLEGRP1

◆ GICD_CTLR_ENABLEGRP1A

◆ GICD_CTLR_ENABLEGRP1NS

◆ GICD_CTLR_ENABLEGRP1S

◆ GICD_ICACTIVER

◆ GICD_ICENABLER

◆ GICD_ICFGR

◆ GICD_ICPENDR

◆ GICD_IGROUPR

◆ GICD_IGRPMODR

◆ GICD_IPRIORITYR

◆ GICD_IROUTER

◆ GICD_ISACTIVER

◆ GICD_ISENABLER

◆ GICD_ISPENDR

◆ GICD_ITARGETSR

◆ GICD_NSACR

◆ GICD_SPENDSGIR

◆ gicdPidr0

◆ gicdPidr1

◆ gicdPidr2

◆ gicdPidr3

◆ gicdPidr4

◆ gicdTyper