gem5  v21.2.1.1
mem64.hh
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37 
38 #ifndef __ARCH_ARM_MEM64_HH__
39 #define __ARCH_ARM_MEM64_HH__
40 
41 #include "arch/arm/insts/misc64.hh"
43 #include "arch/arm/pcstate.hh"
44 #include "cpu/thread_context.hh"
45 
46 namespace gem5
47 {
48 
49 namespace ArmISA
50 {
51 
52 class SysDC64 : public MiscRegOp64
53 {
54  protected:
55  IntRegIndex base;
57  uint64_t imm;
58 
59  // This is used for fault handling only
60  mutable Addr faultAddr;
61 
62  SysDC64(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
63  IntRegIndex _base, MiscRegIndex _dest, uint64_t _imm)
64  : MiscRegOp64(mnem, _machInst, __opClass, false),
65  base(_base), dest(_dest), imm(_imm), faultAddr(0)
66  {}
67 
68  std::string generateDisassembly(
69  Addr pc, const loader::SymbolTable *symtab) const override;
70 };
71 
73 {
74  protected:
75  MightBeMicro64(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
76  : ArmStaticInst(mnem, _machInst, __opClass)
77  {}
78 
79  void
80  advancePC(PCStateBase &pcState) const override
81  {
82  auto &apc = pcState.as<PCState>();
83  if (flags[IsLastMicroop]) {
84  apc.uEnd();
85  } else if (flags[IsMicroop]) {
86  apc.uAdvance();
87  } else {
88  apc.advance();
89  }
90  }
91 
92  void
93  advancePC(ThreadContext *tc) const override
94  {
95  PCState pc = tc->pcState().as<PCState>();
96  if (flags[IsLastMicroop]) {
97  pc.uEnd();
98  } else if (flags[IsMicroop]) {
99  pc.uAdvance();
100  } else {
101  pc.advance();
102  }
103  tc->pcState(pc);
104  }
105 };
106 
107 class Memory64 : public MightBeMicro64
108 {
109  public:
110  enum AddrMode
111  {
115  };
116 
117  protected:
118 
119  IntRegIndex dest;
120  IntRegIndex base;
122  bool baseIsSP;
123  static const unsigned numMicroops = 3;
124 
126 
127  Memory64(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
128  IntRegIndex _dest, IntRegIndex _base)
129  : MightBeMicro64(mnem, _machInst, __opClass),
130  dest(_dest), base(_base), uops(NULL), memAccessFlags(0)
131  {
132  baseIsSP = isSP(_base);
133  }
134 
135  virtual
137  {
138  delete [] uops;
139  }
140 
142  fetchMicroop(MicroPC microPC) const override
143  {
144  assert(uops != NULL && microPC < numMicroops);
145  return uops[microPC];
146  }
147 
148  void startDisassembly(std::ostream &os) const;
149 
150  unsigned memAccessFlags;
151 
152  void setExcAcRel(bool exclusive, bool acrel);
153 };
154 
155 class MemoryImm64 : public Memory64
156 {
157  protected:
158  int64_t imm;
159 
160  MemoryImm64(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
161  IntRegIndex _dest, IntRegIndex _base, int64_t _imm)
162  : Memory64(mnem, _machInst, __opClass, _dest, _base), imm(_imm)
163  {}
164 
165  std::string generateDisassembly(
166  Addr pc, const loader::SymbolTable *symtab) const override;
167 };
168 
169 class MemoryDImm64 : public MemoryImm64
170 {
171  protected:
172  IntRegIndex dest2;
173 
174  MemoryDImm64(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
175  IntRegIndex _dest, IntRegIndex _dest2, IntRegIndex _base,
176  int64_t _imm)
177  : MemoryImm64(mnem, _machInst, __opClass, _dest, _base, _imm),
178  dest2(_dest2)
179  {}
180 
181  std::string generateDisassembly(
182  Addr pc, const loader::SymbolTable *symtab) const override;
183 };
184 
186 {
187  protected:
188  IntRegIndex result;
189 
190  MemoryDImmEx64(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
191  IntRegIndex _result, IntRegIndex _dest, IntRegIndex _dest2,
192  IntRegIndex _base, int32_t _imm)
193  : MemoryDImm64(mnem, _machInst, __opClass, _dest, _dest2,
194  _base, _imm), result(_result)
195  {}
196 
197  std::string generateDisassembly(
198  Addr pc, const loader::SymbolTable *symtab) const override;
199 };
200 
202 {
203  protected:
204  MemoryPreIndex64(const char *mnem, ExtMachInst _machInst,
205  OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
206  int64_t _imm)
207  : MemoryImm64(mnem, _machInst, __opClass, _dest, _base, _imm)
208  {}
209 
210  std::string generateDisassembly(
211  Addr pc, const loader::SymbolTable *symtab) const override;
212 };
213 
215 {
216  protected:
217  MemoryPostIndex64(const char *mnem, ExtMachInst _machInst,
218  OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
219  int64_t _imm)
220  : MemoryImm64(mnem, _machInst, __opClass, _dest, _base, _imm)
221  {}
222 
223  std::string generateDisassembly(
224  Addr pc, const loader::SymbolTable *symtab) const override;
225 };
226 
227 class MemoryReg64 : public Memory64
228 {
229  protected:
230  IntRegIndex offset;
232  uint64_t shiftAmt;
233 
234  MemoryReg64(const char *mnem, ExtMachInst _machInst,
235  OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
236  IntRegIndex _offset, ArmExtendType _type,
237  uint64_t _shiftAmt)
238  : Memory64(mnem, _machInst, __opClass, _dest, _base),
239  offset(_offset), type(_type), shiftAmt(_shiftAmt)
240  {}
241 
242  std::string generateDisassembly(
243  Addr pc, const loader::SymbolTable *symtab) const override;
244 };
245 
246 class MemoryRaw64 : public Memory64
247 {
248  protected:
249  MemoryRaw64(const char *mnem, ExtMachInst _machInst,
250  OpClass __opClass, IntRegIndex _dest, IntRegIndex _base)
251  : Memory64(mnem, _machInst, __opClass, _dest, _base)
252  {}
253 
254  std::string generateDisassembly(
255  Addr pc, const loader::SymbolTable *symtab) const override;
256 };
257 
258 class MemoryEx64 : public Memory64
259 {
260  protected:
261  IntRegIndex result;
262 
263  MemoryEx64(const char *mnem, ExtMachInst _machInst,
264  OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
265  IntRegIndex _result)
266  : Memory64(mnem, _machInst, __opClass, _dest, _base), result(_result)
267  {}
268 
269  std::string generateDisassembly(
270  Addr pc, const loader::SymbolTable *symtab) const override;
271 };
272 
273 class MemoryLiteral64 : public Memory64
274 {
275  protected:
276  int64_t imm;
277 
278  MemoryLiteral64(const char *mnem, ExtMachInst _machInst,
279  OpClass __opClass, IntRegIndex _dest, int64_t _imm)
280  : Memory64(mnem, _machInst, __opClass, _dest, INTREG_ZERO), imm(_imm)
281  {}
282 
283  std::string generateDisassembly(
284  Addr pc, const loader::SymbolTable *symtab) const override;
285 };
286 
288 {
289  protected:
290  IntRegIndex dest2;
291  IntRegIndex result;
292  IntRegIndex result2;
293 
294  MemoryAtomicPair64(const char *mnem, ExtMachInst _machInst,
295  OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
296  IntRegIndex _result)
297  : Memory64(mnem, _machInst, __opClass, _dest, _base),
298  dest2((IntRegIndex)(_dest + (IntRegIndex)(1))),
299  result(_result),
300  result2((IntRegIndex)(_result + (IntRegIndex)(1)))
301  {}
302 
303  std::string generateDisassembly(
304  Addr pc, const loader::SymbolTable *symtab) const override;
305 };
306 
307 } // namespace ArmISA
308 } // namespace gem5
309 
310 #endif //__ARCH_ARM_INSTS_MEM_HH__
gem5::ArmISA::MemoryDImmEx64
Definition: mem64.hh:185
gem5::ArmISA::SysDC64::dest
MiscRegIndex dest
Definition: mem64.hh:56
gem5::ArmISA::MemoryPostIndex64
Definition: mem64.hh:214
gem5::ArmISA::MemoryDImmEx64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: mem64.cc:118
gem5::ArmISA::MemoryAtomicPair64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: mem64.cc:206
gem5::ArmISA::MemoryDImm64::dest2
IntRegIndex dest2
Definition: mem64.hh:172
gem5::ArmISA::Memory64::setExcAcRel
void setExcAcRel(bool exclusive, bool acrel)
Definition: mem64.cc:76
gem5::ArmISA::isSP
static bool isSP(IntRegIndex reg)
Definition: int.hh:528
gem5::ArmISA::MightBeMicro64::MightBeMicro64
MightBeMicro64(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
Definition: mem64.hh:75
gem5::ArmISA::ArmStaticInst
Definition: static_inst.hh:65
gem5::ArmISA::MemoryReg64::offset
IntRegIndex offset
Definition: mem64.hh:230
gem5::ArmISA::MemoryLiteral64::imm
int64_t imm
Definition: mem64.hh:276
gem5::ArmISA::MemoryAtomicPair64
Definition: mem64.hh:287
gem5::ArmISA::MemoryDImm64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: mem64.cc:101
gem5::PCStateBase::as
Target & as()
Definition: pcstate.hh:72
gem5::ArmISA::Memory64::AddrMd_Offset
@ AddrMd_Offset
Definition: mem64.hh:112
gem5::ArmISA::MemoryAtomicPair64::dest2
IntRegIndex dest2
Definition: mem64.hh:290
gem5::ThreadContext::pcState
virtual const PCStateBase & pcState() const =0
gem5::ArmISA::SysDC64::faultAddr
Addr faultAddr
Definition: mem64.hh:60
gem5::ArmISA::Memory64::dest
IntRegIndex dest
Definition: mem64.hh:119
gem5::ArmISA::MemoryRaw64::MemoryRaw64
MemoryRaw64(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _base)
Definition: mem64.hh:249
gem5::ArmISA::ArmExtendType
ArmExtendType
Definition: types.hh:215
gem5::loader::SymbolTable
Definition: symtab.hh:65
gem5::ArmISA::Memory64::fetchMicroop
StaticInstPtr fetchMicroop(MicroPC microPC) const override
Return the microop that goes with a particular micropc.
Definition: mem64.hh:142
gem5::ArmISA::MemoryRaw64
Definition: mem64.hh:246
gem5::ArmISA::MemoryPostIndex64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: mem64.cc:147
gem5::ArmISA::MightBeMicro64::advancePC
void advancePC(PCStateBase &pcState) const override
Definition: mem64.hh:80
gem5::ArmISA::Memory64::Memory64
Memory64(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _base)
Definition: mem64.hh:127
gem5::PowerISA::PCState
Definition: pcstate.hh:42
gem5::ArmISA::Memory64::AddrMd_PostIndex
@ AddrMd_PostIndex
Definition: mem64.hh:114
gem5::ArmISA::MemoryPostIndex64::MemoryPostIndex64
MemoryPostIndex64(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, int64_t _imm)
Definition: mem64.hh:217
gem5::ArmISA::MightBeMicro64::advancePC
void advancePC(ThreadContext *tc) const override
Definition: mem64.hh:93
gem5::ArmISA::MemoryLiteral64::MemoryLiteral64
MemoryLiteral64(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, int64_t _imm)
Definition: mem64.hh:278
gem5::ArmISA::SysDC64::base
IntRegIndex base
Definition: mem64.hh:55
gem5::ArmISA::SysDC64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: mem64.cc:51
gem5::ArmISA::MightBeMicro64
Definition: mem64.hh:72
gem5::RefCountingPtr< StaticInst >
gem5::ArmISA::MemoryImm64::imm
int64_t imm
Definition: mem64.hh:158
gem5::ArmISA::MemoryReg64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: mem64.cc:159
gem5::ArmISA::MemoryReg64
Definition: mem64.hh:227
gem5::ArmISA::MemoryRaw64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: mem64.cc:170
gem5::ArmISA::MemoryImm64::MemoryImm64
MemoryImm64(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, int64_t _imm)
Definition: mem64.hh:160
gem5::MicroPC
uint16_t MicroPC
Definition: types.hh:149
gem5::ArmISA::MemoryLiteral64
Definition: mem64.hh:273
gem5::ArmISA::Memory64::base
IntRegIndex base
Definition: mem64.hh:120
misc64.hh
gem5::ArmISA::MemoryEx64::MemoryEx64
MemoryEx64(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, IntRegIndex _result)
Definition: mem64.hh:263
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::ArmISA::SysDC64::SysDC64
SysDC64(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _base, MiscRegIndex _dest, uint64_t _imm)
Definition: mem64.hh:62
gem5::ArmISA::Memory64::~Memory64
virtual ~Memory64()
Definition: mem64.hh:136
gem5::StaticInst::flags
std::bitset< Num_Flags > flags
Flag values for this instruction.
Definition: static_inst.hh:102
gem5::ArmISA::MemoryAtomicPair64::MemoryAtomicPair64
MemoryAtomicPair64(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, IntRegIndex _result)
Definition: mem64.hh:294
gem5::ArmISA::Memory64::AddrMode
AddrMode
Definition: mem64.hh:110
gem5::ArmISA::Memory64::startDisassembly
void startDisassembly(std::ostream &os) const
Definition: mem64.cc:63
gem5::ArmISA::MemoryReg64::type
ArmExtendType type
Definition: mem64.hh:231
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::MiscRegOp64
This class is implementing the Base class for a generic AArch64 instruction which is making use of sy...
Definition: misc64.hh:124
gem5::ArmISA::MiscRegIndex
MiscRegIndex
Definition: misc.hh:59
pcstate.hh
gem5::ArmISA::MemoryDImm64
Definition: mem64.hh:169
gem5::ArmISA::MemoryImm64
Definition: mem64.hh:155
gem5::ArmISA::MemoryPreIndex64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: mem64.cc:137
gem5::ArmISA::MemoryEx64::result
IntRegIndex result
Definition: mem64.hh:261
gem5::X86ISA::ExtMachInst
Definition: types.hh:206
gem5::ArmISA::SysDC64
Definition: mem64.hh:52
gem5::ArmISA::MemoryEx64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: mem64.cc:180
gem5::ArmISA::MemoryAtomicPair64::result
IntRegIndex result
Definition: mem64.hh:291
gem5::X86ISA::os
Bitfield< 17 > os
Definition: misc.hh:809
gem5::ArmISA::MemoryAtomicPair64::result2
IntRegIndex result2
Definition: mem64.hh:292
static_inst.hh
gem5::ArmISA::MemoryEx64
Definition: mem64.hh:258
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::ArmISA::Memory64::numMicroops
static const unsigned numMicroops
Definition: mem64.hh:123
gem5::ArmISA::MemoryDImmEx64::result
IntRegIndex result
Definition: mem64.hh:188
gem5::ArmISA::Memory64::AddrMd_PreIndex
@ AddrMd_PreIndex
Definition: mem64.hh:113
gem5::ArmISA::MemoryPreIndex64::MemoryPreIndex64
MemoryPreIndex64(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, int64_t _imm)
Definition: mem64.hh:204
gem5::ArmISA::MemoryDImmEx64::MemoryDImmEx64
MemoryDImmEx64(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _result, IntRegIndex _dest, IntRegIndex _dest2, IntRegIndex _base, int32_t _imm)
Definition: mem64.hh:190
gem5::ArmISA::MemoryReg64::shiftAmt
uint64_t shiftAmt
Definition: mem64.hh:232
gem5::PCStateBase
Definition: pcstate.hh:57
gem5::ArmISA::Memory64::baseIsSP
bool baseIsSP
True if the base register is SP (used for SP alignment checking).
Definition: mem64.hh:122
gem5::ArmISA::Memory64
Definition: mem64.hh:107
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::ArmISA::MemoryPreIndex64
Definition: mem64.hh:201
gem5::ArmISA::MemoryLiteral64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: mem64.cc:195
gem5::ArmISA::MemoryReg64::MemoryReg64
MemoryReg64(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, IntRegIndex _offset, ArmExtendType _type, uint64_t _shiftAmt)
Definition: mem64.hh:234
gem5::ArmISA::SysDC64::imm
uint64_t imm
Definition: mem64.hh:57
gem5::ArmISA::MemoryDImm64::MemoryDImm64
MemoryDImm64(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2, IntRegIndex _base, int64_t _imm)
Definition: mem64.hh:174
thread_context.hh
gem5::GenericISA::SimplePCState::advance
void advance() override
Definition: pcstate.hh:376
gem5::ArmISA::MemoryImm64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: mem64.cc:89
gem5::ArmISA::Memory64::memAccessFlags
unsigned memAccessFlags
Definition: mem64.hh:150
gem5::ArmISA::Memory64::uops
StaticInstPtr * uops
Definition: mem64.hh:125

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