gem5  v21.1.0.2
mem64.hh
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37 
38 #ifndef __ARCH_ARM_MEM64_HH__
39 #define __ARCH_ARM_MEM64_HH__
40 
41 #include "arch/arm/insts/misc64.hh"
43 
44 namespace gem5
45 {
46 
47 namespace ArmISA
48 {
49 
50 class SysDC64 : public MiscRegOp64
51 {
52  protected:
53  IntRegIndex base;
55  uint64_t imm;
56 
57  // This is used for fault handling only
58  mutable Addr faultAddr;
59 
60  SysDC64(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
61  IntRegIndex _base, MiscRegIndex _dest, uint64_t _imm)
62  : MiscRegOp64(mnem, _machInst, __opClass, false),
63  base(_base), dest(_dest), imm(_imm), faultAddr(0)
64  {}
65 
66  std::string generateDisassembly(
67  Addr pc, const loader::SymbolTable *symtab) const override;
68 };
69 
71 {
72  protected:
73  MightBeMicro64(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
74  : ArmStaticInst(mnem, _machInst, __opClass)
75  {}
76 
77  void
78  advancePC(PCState &pcState) const override
79  {
80  if (flags[IsLastMicroop]) {
81  pcState.uEnd();
82  } else if (flags[IsMicroop]) {
83  pcState.uAdvance();
84  } else {
85  pcState.advance();
86  }
87  }
88 };
89 
90 class Memory64 : public MightBeMicro64
91 {
92  public:
93  enum AddrMode
94  {
98  };
99 
100  protected:
101 
102  IntRegIndex dest;
103  IntRegIndex base;
105  bool baseIsSP;
106  static const unsigned numMicroops = 3;
107 
109 
110  Memory64(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
111  IntRegIndex _dest, IntRegIndex _base)
112  : MightBeMicro64(mnem, _machInst, __opClass),
113  dest(_dest), base(_base), uops(NULL), memAccessFlags(0)
114  {
115  baseIsSP = isSP(_base);
116  }
117 
118  virtual
120  {
121  delete [] uops;
122  }
123 
125  fetchMicroop(MicroPC microPC) const override
126  {
127  assert(uops != NULL && microPC < numMicroops);
128  return uops[microPC];
129  }
130 
131  void startDisassembly(std::ostream &os) const;
132 
133  unsigned memAccessFlags;
134 
135  void setExcAcRel(bool exclusive, bool acrel);
136 };
137 
138 class MemoryImm64 : public Memory64
139 {
140  protected:
141  int64_t imm;
142 
143  MemoryImm64(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
144  IntRegIndex _dest, IntRegIndex _base, int64_t _imm)
145  : Memory64(mnem, _machInst, __opClass, _dest, _base), imm(_imm)
146  {}
147 
148  std::string generateDisassembly(
149  Addr pc, const loader::SymbolTable *symtab) const override;
150 };
151 
152 class MemoryDImm64 : public MemoryImm64
153 {
154  protected:
155  IntRegIndex dest2;
156 
157  MemoryDImm64(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
158  IntRegIndex _dest, IntRegIndex _dest2, IntRegIndex _base,
159  int64_t _imm)
160  : MemoryImm64(mnem, _machInst, __opClass, _dest, _base, _imm),
161  dest2(_dest2)
162  {}
163 
164  std::string generateDisassembly(
165  Addr pc, const loader::SymbolTable *symtab) const override;
166 };
167 
169 {
170  protected:
171  IntRegIndex result;
172 
173  MemoryDImmEx64(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
174  IntRegIndex _result, IntRegIndex _dest, IntRegIndex _dest2,
175  IntRegIndex _base, int32_t _imm)
176  : MemoryDImm64(mnem, _machInst, __opClass, _dest, _dest2,
177  _base, _imm), result(_result)
178  {}
179 
180  std::string generateDisassembly(
181  Addr pc, const loader::SymbolTable *symtab) const override;
182 };
183 
185 {
186  protected:
187  MemoryPreIndex64(const char *mnem, ExtMachInst _machInst,
188  OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
189  int64_t _imm)
190  : MemoryImm64(mnem, _machInst, __opClass, _dest, _base, _imm)
191  {}
192 
193  std::string generateDisassembly(
194  Addr pc, const loader::SymbolTable *symtab) const override;
195 };
196 
198 {
199  protected:
200  MemoryPostIndex64(const char *mnem, ExtMachInst _machInst,
201  OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
202  int64_t _imm)
203  : MemoryImm64(mnem, _machInst, __opClass, _dest, _base, _imm)
204  {}
205 
206  std::string generateDisassembly(
207  Addr pc, const loader::SymbolTable *symtab) const override;
208 };
209 
210 class MemoryReg64 : public Memory64
211 {
212  protected:
213  IntRegIndex offset;
215  uint64_t shiftAmt;
216 
217  MemoryReg64(const char *mnem, ExtMachInst _machInst,
218  OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
219  IntRegIndex _offset, ArmExtendType _type,
220  uint64_t _shiftAmt)
221  : Memory64(mnem, _machInst, __opClass, _dest, _base),
222  offset(_offset), type(_type), shiftAmt(_shiftAmt)
223  {}
224 
225  std::string generateDisassembly(
226  Addr pc, const loader::SymbolTable *symtab) const override;
227 };
228 
229 class MemoryRaw64 : public Memory64
230 {
231  protected:
232  MemoryRaw64(const char *mnem, ExtMachInst _machInst,
233  OpClass __opClass, IntRegIndex _dest, IntRegIndex _base)
234  : Memory64(mnem, _machInst, __opClass, _dest, _base)
235  {}
236 
237  std::string generateDisassembly(
238  Addr pc, const loader::SymbolTable *symtab) const override;
239 };
240 
241 class MemoryEx64 : public Memory64
242 {
243  protected:
244  IntRegIndex result;
245 
246  MemoryEx64(const char *mnem, ExtMachInst _machInst,
247  OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
248  IntRegIndex _result)
249  : Memory64(mnem, _machInst, __opClass, _dest, _base), result(_result)
250  {}
251 
252  std::string generateDisassembly(
253  Addr pc, const loader::SymbolTable *symtab) const override;
254 };
255 
256 class MemoryLiteral64 : public Memory64
257 {
258  protected:
259  int64_t imm;
260 
261  MemoryLiteral64(const char *mnem, ExtMachInst _machInst,
262  OpClass __opClass, IntRegIndex _dest, int64_t _imm)
263  : Memory64(mnem, _machInst, __opClass, _dest, INTREG_ZERO), imm(_imm)
264  {}
265 
266  std::string generateDisassembly(
267  Addr pc, const loader::SymbolTable *symtab) const override;
268 };
269 
271 {
272  protected:
273  IntRegIndex dest2;
274  IntRegIndex result;
275  IntRegIndex result2;
276 
277  MemoryAtomicPair64(const char *mnem, ExtMachInst _machInst,
278  OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
279  IntRegIndex _result)
280  : Memory64(mnem, _machInst, __opClass, _dest, _base),
281  dest2((IntRegIndex)(_dest + (IntRegIndex)(1))),
282  result(_result),
283  result2((IntRegIndex)(_result + (IntRegIndex)(1)))
284  {}
285 
286  std::string generateDisassembly(
287  Addr pc, const loader::SymbolTable *symtab) const override;
288 };
289 
290 } // namespace ArmISA
291 } // namespace gem5
292 
293 #endif //__ARCH_ARM_INSTS_MEM_HH__
gem5::ArmISA::MemoryDImmEx64
Definition: mem64.hh:168
gem5::ArmISA::SysDC64::dest
MiscRegIndex dest
Definition: mem64.hh:54
gem5::ArmISA::MemoryPostIndex64
Definition: mem64.hh:197
gem5::ArmISA::MemoryDImmEx64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: mem64.cc:118
gem5::ArmISA::MemoryAtomicPair64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: mem64.cc:206
gem5::ArmISA::MemoryDImm64::dest2
IntRegIndex dest2
Definition: mem64.hh:155
gem5::ArmISA::Memory64::setExcAcRel
void setExcAcRel(bool exclusive, bool acrel)
Definition: mem64.cc:76
gem5::ArmISA::isSP
static bool isSP(IntRegIndex reg)
Definition: int.hh:529
gem5::ArmISA::MightBeMicro64::MightBeMicro64
MightBeMicro64(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
Definition: mem64.hh:73
gem5::ArmISA::ArmStaticInst
Definition: static_inst.hh:63
gem5::ArmISA::MemoryReg64::offset
IntRegIndex offset
Definition: mem64.hh:213
gem5::ArmISA::MemoryLiteral64::imm
int64_t imm
Definition: mem64.hh:259
gem5::ArmISA::MemoryAtomicPair64
Definition: mem64.hh:270
gem5::ArmISA::MemoryDImm64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: mem64.cc:101
gem5::ArmISA::Memory64::AddrMd_Offset
@ AddrMd_Offset
Definition: mem64.hh:95
gem5::ArmISA::MemoryAtomicPair64::dest2
IntRegIndex dest2
Definition: mem64.hh:273
gem5::ArmISA::SysDC64::faultAddr
Addr faultAddr
Definition: mem64.hh:58
gem5::ArmISA::Memory64::dest
IntRegIndex dest
Definition: mem64.hh:102
gem5::ArmISA::MemoryRaw64::MemoryRaw64
MemoryRaw64(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _base)
Definition: mem64.hh:232
gem5::ArmISA::ArmExtendType
ArmExtendType
Definition: types.hh:215
gem5::loader::SymbolTable
Definition: symtab.hh:65
gem5::ArmISA::Memory64::fetchMicroop
StaticInstPtr fetchMicroop(MicroPC microPC) const override
Return the microop that goes with a particular micropc.
Definition: mem64.hh:125
gem5::ArmISA::MemoryRaw64
Definition: mem64.hh:229
gem5::ArmISA::MemoryPostIndex64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: mem64.cc:147
gem5::ArmISA::Memory64::Memory64
Memory64(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _base)
Definition: mem64.hh:110
gem5::PowerISA::PCState
Definition: pcstate.hh:42
gem5::ArmISA::Memory64::AddrMd_PostIndex
@ AddrMd_PostIndex
Definition: mem64.hh:97
gem5::ArmISA::MemoryPostIndex64::MemoryPostIndex64
MemoryPostIndex64(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, int64_t _imm)
Definition: mem64.hh:200
gem5::ArmISA::MemoryLiteral64::MemoryLiteral64
MemoryLiteral64(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, int64_t _imm)
Definition: mem64.hh:261
gem5::ArmISA::SysDC64::base
IntRegIndex base
Definition: mem64.hh:53
gem5::ArmISA::SysDC64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: mem64.cc:51
gem5::ArmISA::MightBeMicro64
Definition: mem64.hh:70
gem5::RefCountingPtr< StaticInst >
gem5::ArmISA::MemoryImm64::imm
int64_t imm
Definition: mem64.hh:141
gem5::ArmISA::MemoryReg64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: mem64.cc:159
gem5::ArmISA::MemoryReg64
Definition: mem64.hh:210
gem5::ArmISA::MemoryRaw64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: mem64.cc:170
gem5::ArmISA::MemoryImm64::MemoryImm64
MemoryImm64(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, int64_t _imm)
Definition: mem64.hh:143
gem5::MicroPC
uint16_t MicroPC
Definition: types.hh:149
gem5::ArmISA::MemoryLiteral64
Definition: mem64.hh:256
gem5::ArmISA::Memory64::base
IntRegIndex base
Definition: mem64.hh:103
misc64.hh
gem5::ArmISA::MemoryEx64::MemoryEx64
MemoryEx64(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, IntRegIndex _result)
Definition: mem64.hh:246
gem5::ArmISA::MightBeMicro64::advancePC
void advancePC(PCState &pcState) const override
Definition: mem64.hh:78
gem5::ArmISA::SysDC64::SysDC64
SysDC64(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _base, MiscRegIndex _dest, uint64_t _imm)
Definition: mem64.hh:60
gem5::ArmISA::Memory64::~Memory64
virtual ~Memory64()
Definition: mem64.hh:119
gem5::StaticInst::flags
std::bitset< Num_Flags > flags
Flag values for this instruction.
Definition: static_inst.hh:103
gem5::ArmISA::MemoryAtomicPair64::MemoryAtomicPair64
MemoryAtomicPair64(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, IntRegIndex _result)
Definition: mem64.hh:277
gem5::ArmISA::Memory64::AddrMode
AddrMode
Definition: mem64.hh:93
gem5::ArmISA::Memory64::startDisassembly
void startDisassembly(std::ostream &os) const
Definition: mem64.cc:63
gem5::ArmISA::MemoryReg64::type
ArmExtendType type
Definition: mem64.hh:214
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::MiscRegOp64
This class is implementing the Base class for a generic AArch64 instruction which is making use of sy...
Definition: misc64.hh:124
gem5::ArmISA::MiscRegIndex
MiscRegIndex
Definition: misc.hh:59
gem5::ArmISA::MemoryDImm64
Definition: mem64.hh:152
gem5::ArmISA::MemoryImm64
Definition: mem64.hh:138
gem5::ArmISA::MemoryPreIndex64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: mem64.cc:137
gem5::ArmISA::MemoryEx64::result
IntRegIndex result
Definition: mem64.hh:244
gem5::GenericISA::SimplePCState::advance
void advance()
Definition: types.hh:181
gem5::X86ISA::ExtMachInst
Definition: types.hh:206
gem5::ArmISA::SysDC64
Definition: mem64.hh:50
gem5::ArmISA::MemoryEx64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: mem64.cc:180
gem5::ArmISA::MemoryAtomicPair64::result
IntRegIndex result
Definition: mem64.hh:274
gem5::X86ISA::os
Bitfield< 17 > os
Definition: misc.hh:809
gem5::ArmISA::MemoryAtomicPair64::result2
IntRegIndex result2
Definition: mem64.hh:275
static_inst.hh
gem5::ArmISA::MemoryEx64
Definition: mem64.hh:241
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::ArmISA::Memory64::numMicroops
static const unsigned numMicroops
Definition: mem64.hh:106
gem5::ArmISA::MemoryDImmEx64::result
IntRegIndex result
Definition: mem64.hh:171
gem5::ArmISA::Memory64::AddrMd_PreIndex
@ AddrMd_PreIndex
Definition: mem64.hh:96
gem5::ArmISA::MemoryPreIndex64::MemoryPreIndex64
MemoryPreIndex64(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, int64_t _imm)
Definition: mem64.hh:187
gem5::ArmISA::MemoryDImmEx64::MemoryDImmEx64
MemoryDImmEx64(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _result, IntRegIndex _dest, IntRegIndex _dest2, IntRegIndex _base, int32_t _imm)
Definition: mem64.hh:173
gem5::ArmISA::MemoryReg64::shiftAmt
uint64_t shiftAmt
Definition: mem64.hh:215
gem5::ArmISA::Memory64::baseIsSP
bool baseIsSP
True if the base register is SP (used for SP alignment checking).
Definition: mem64.hh:105
gem5::ArmISA::Memory64
Definition: mem64.hh:90
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::ArmISA::MemoryPreIndex64
Definition: mem64.hh:184
gem5::ArmISA::MemoryLiteral64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: mem64.cc:195
gem5::ArmISA::MemoryReg64::MemoryReg64
MemoryReg64(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, IntRegIndex _offset, ArmExtendType _type, uint64_t _shiftAmt)
Definition: mem64.hh:217
gem5::ArmISA::SysDC64::imm
uint64_t imm
Definition: mem64.hh:55
gem5::ArmISA::MemoryDImm64::MemoryDImm64
MemoryDImm64(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2, IntRegIndex _base, int64_t _imm)
Definition: mem64.hh:157
gem5::ArmISA::MemoryImm64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: mem64.cc:89
gem5::ArmISA::Memory64::memAccessFlags
unsigned memAccessFlags
Definition: mem64.hh:133
gem5::ArmISA::Memory64::uops
StaticInstPtr * uops
Definition: mem64.hh:108

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