gem5  v22.1.0.0
mem64.hh
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37 
38 #ifndef __ARCH_ARM_MEM64_HH__
39 #define __ARCH_ARM_MEM64_HH__
40 
41 #include "arch/arm/insts/misc64.hh"
43 #include "arch/arm/pcstate.hh"
44 #include "cpu/thread_context.hh"
45 
46 namespace gem5
47 {
48 
49 namespace ArmISA
50 {
51 
52 class SysDC64 : public MiscRegOp64
53 {
54  protected:
57 
58  // This is used for fault handling only
59  mutable Addr faultAddr;
60 
61  SysDC64(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
62  RegIndex _base, MiscRegIndex _dest)
63  : MiscRegOp64(mnem, _machInst, __opClass, false),
64  base(_base), dest(_dest), faultAddr(0)
65  {}
66 
67  std::string generateDisassembly(
68  Addr pc, const loader::SymbolTable *symtab) const override;
69 
70  uint32_t iss() const override;
71 };
72 
74 {
75  protected:
76  MightBeMicro64(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
77  : ArmStaticInst(mnem, _machInst, __opClass)
78  {}
79 
80  void
81  advancePC(PCStateBase &pcState) const override
82  {
83  auto &apc = pcState.as<PCState>();
84  if (flags[IsLastMicroop]) {
85  apc.uEnd();
86  } else if (flags[IsMicroop]) {
87  apc.uAdvance();
88  } else {
89  apc.advance();
90  }
91  }
92 
93  void
94  advancePC(ThreadContext *tc) const override
95  {
96  PCState pc = tc->pcState().as<PCState>();
97  if (flags[IsLastMicroop]) {
98  pc.uEnd();
99  } else if (flags[IsMicroop]) {
100  pc.uAdvance();
101  } else {
102  pc.advance();
103  }
104  tc->pcState(pc);
105  }
106 };
107 
108 class Memory64 : public MightBeMicro64
109 {
110  public:
111  enum AddrMode
112  {
116  };
117 
118  protected:
119 
123  bool baseIsSP;
124  static const unsigned numMicroops = 3;
125 
127 
128  Memory64(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
129  RegIndex _dest, RegIndex _base)
130  : MightBeMicro64(mnem, _machInst, __opClass),
131  dest(_dest), base(_base), uops(NULL), memAccessFlags(0)
132  {
133  baseIsSP = isSP(_base);
134  }
135 
136  virtual
138  {
139  delete [] uops;
140  }
141 
143  fetchMicroop(MicroPC microPC) const override
144  {
145  assert(uops != NULL && microPC < numMicroops);
146  return uops[microPC];
147  }
148 
149  void startDisassembly(std::ostream &os) const;
150 
151  unsigned memAccessFlags;
152 
153  void setExcAcRel(bool exclusive, bool acrel);
154 };
155 
156 class MemoryImm64 : public Memory64
157 {
158  protected:
159  int64_t imm;
160 
161  MemoryImm64(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
162  RegIndex _dest, RegIndex _base, int64_t _imm)
163  : Memory64(mnem, _machInst, __opClass, _dest, _base), imm(_imm)
164  {}
165 
166  std::string generateDisassembly(
167  Addr pc, const loader::SymbolTable *symtab) const override;
168 };
169 
170 class MemoryDImm64 : public MemoryImm64
171 {
172  protected:
174 
175  MemoryDImm64(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
176  RegIndex _dest, RegIndex _dest2, RegIndex _base,
177  int64_t _imm)
178  : MemoryImm64(mnem, _machInst, __opClass, _dest, _base, _imm),
179  dest2(_dest2)
180  {}
181 
182  std::string generateDisassembly(
183  Addr pc, const loader::SymbolTable *symtab) const override;
184 };
185 
187 {
188  protected:
190 
191  MemoryDImmEx64(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
192  RegIndex _result, RegIndex _dest, RegIndex _dest2,
193  RegIndex _base, int32_t _imm)
194  : MemoryDImm64(mnem, _machInst, __opClass, _dest, _dest2,
195  _base, _imm), result(_result)
196  {}
197 
198  std::string generateDisassembly(
199  Addr pc, const loader::SymbolTable *symtab) const override;
200 };
201 
203 {
204  protected:
205  MemoryPreIndex64(const char *mnem, ExtMachInst _machInst,
206  OpClass __opClass, RegIndex _dest, RegIndex _base,
207  int64_t _imm)
208  : MemoryImm64(mnem, _machInst, __opClass, _dest, _base, _imm)
209  {}
210 
211  std::string generateDisassembly(
212  Addr pc, const loader::SymbolTable *symtab) const override;
213 };
214 
216 {
217  protected:
218  MemoryPostIndex64(const char *mnem, ExtMachInst _machInst,
219  OpClass __opClass, RegIndex _dest, RegIndex _base,
220  int64_t _imm)
221  : MemoryImm64(mnem, _machInst, __opClass, _dest, _base, _imm)
222  {}
223 
224  std::string generateDisassembly(
225  Addr pc, const loader::SymbolTable *symtab) const override;
226 };
227 
228 class MemoryReg64 : public Memory64
229 {
230  protected:
233  uint64_t shiftAmt;
234 
235  MemoryReg64(const char *mnem, ExtMachInst _machInst,
236  OpClass __opClass, RegIndex _dest, RegIndex _base,
237  RegIndex _offset, ArmExtendType _type,
238  uint64_t _shiftAmt)
239  : Memory64(mnem, _machInst, __opClass, _dest, _base),
240  offset(_offset), type(_type), shiftAmt(_shiftAmt)
241  {}
242 
243  std::string generateDisassembly(
244  Addr pc, const loader::SymbolTable *symtab) const override;
245 };
246 
247 class MemoryRaw64 : public Memory64
248 {
249  protected:
250  MemoryRaw64(const char *mnem, ExtMachInst _machInst,
251  OpClass __opClass, RegIndex _dest, RegIndex _base)
252  : Memory64(mnem, _machInst, __opClass, _dest, _base)
253  {}
254 
255  std::string generateDisassembly(
256  Addr pc, const loader::SymbolTable *symtab) const override;
257 };
258 
259 class MemoryEx64 : public Memory64
260 {
261  protected:
263 
264  MemoryEx64(const char *mnem, ExtMachInst _machInst,
265  OpClass __opClass, RegIndex _dest, RegIndex _base,
266  RegIndex _result)
267  : Memory64(mnem, _machInst, __opClass, _dest, _base), result(_result)
268  {}
269 
270  std::string generateDisassembly(
271  Addr pc, const loader::SymbolTable *symtab) const override;
272 };
273 
274 class MemoryLiteral64 : public Memory64
275 {
276  protected:
277  int64_t imm;
278 
279  MemoryLiteral64(const char *mnem, ExtMachInst _machInst,
280  OpClass __opClass, RegIndex _dest, int64_t _imm)
281  : Memory64(mnem, _machInst, __opClass, _dest, int_reg::Zero), imm(_imm)
282  {}
283 
284  std::string generateDisassembly(
285  Addr pc, const loader::SymbolTable *symtab) const override;
286 };
287 
289 {
290  protected:
294 
295  MemoryAtomicPair64(const char *mnem, ExtMachInst _machInst,
296  OpClass __opClass, RegIndex _dest, RegIndex _base,
297  RegIndex _result)
298  : Memory64(mnem, _machInst, __opClass, _dest, _base),
299  dest2((RegIndex)(_dest + (RegIndex)(1))),
300  result(_result),
301  result2((RegIndex)(_result + (RegIndex)(1)))
302  {}
303 
304  std::string generateDisassembly(
305  Addr pc, const loader::SymbolTable *symtab) const override;
306 };
307 
308 } // namespace ArmISA
309 } // namespace gem5
310 
311 #endif //__ARCH_ARM_INSTS_MEM_HH__
virtual ~Memory64()
Definition: mem64.hh:137
static const unsigned numMicroops
Definition: mem64.hh:124
Memory64(const char *mnem, ExtMachInst _machInst, OpClass __opClass, RegIndex _dest, RegIndex _base)
Definition: mem64.hh:128
bool baseIsSP
True if the base register is SP (used for SP alignment checking).
Definition: mem64.hh:123
void setExcAcRel(bool exclusive, bool acrel)
Definition: mem64.cc:82
unsigned memAccessFlags
Definition: mem64.hh:151
void startDisassembly(std::ostream &os) const
Definition: mem64.cc:69
StaticInstPtr fetchMicroop(MicroPC microPC) const override
Return the microop that goes with a particular micropc.
Definition: mem64.hh:143
StaticInstPtr * uops
Definition: mem64.hh:126
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: mem64.cc:212
MemoryAtomicPair64(const char *mnem, ExtMachInst _machInst, OpClass __opClass, RegIndex _dest, RegIndex _base, RegIndex _result)
Definition: mem64.hh:295
MemoryDImm64(const char *mnem, ExtMachInst _machInst, OpClass __opClass, RegIndex _dest, RegIndex _dest2, RegIndex _base, int64_t _imm)
Definition: mem64.hh:175
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: mem64.cc:107
MemoryDImmEx64(const char *mnem, ExtMachInst _machInst, OpClass __opClass, RegIndex _result, RegIndex _dest, RegIndex _dest2, RegIndex _base, int32_t _imm)
Definition: mem64.hh:191
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: mem64.cc:124
MemoryEx64(const char *mnem, ExtMachInst _machInst, OpClass __opClass, RegIndex _dest, RegIndex _base, RegIndex _result)
Definition: mem64.hh:264
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: mem64.cc:186
MemoryImm64(const char *mnem, ExtMachInst _machInst, OpClass __opClass, RegIndex _dest, RegIndex _base, int64_t _imm)
Definition: mem64.hh:161
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: mem64.cc:95
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: mem64.cc:201
MemoryLiteral64(const char *mnem, ExtMachInst _machInst, OpClass __opClass, RegIndex _dest, int64_t _imm)
Definition: mem64.hh:279
MemoryPostIndex64(const char *mnem, ExtMachInst _machInst, OpClass __opClass, RegIndex _dest, RegIndex _base, int64_t _imm)
Definition: mem64.hh:218
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: mem64.cc:153
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: mem64.cc:143
MemoryPreIndex64(const char *mnem, ExtMachInst _machInst, OpClass __opClass, RegIndex _dest, RegIndex _base, int64_t _imm)
Definition: mem64.hh:205
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: mem64.cc:176
MemoryRaw64(const char *mnem, ExtMachInst _machInst, OpClass __opClass, RegIndex _dest, RegIndex _base)
Definition: mem64.hh:250
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: mem64.cc:165
ArmExtendType type
Definition: mem64.hh:232
MemoryReg64(const char *mnem, ExtMachInst _machInst, OpClass __opClass, RegIndex _dest, RegIndex _base, RegIndex _offset, ArmExtendType _type, uint64_t _shiftAmt)
Definition: mem64.hh:235
void advancePC(PCStateBase &pcState) const override
Definition: mem64.hh:81
void advancePC(ThreadContext *tc) const override
Definition: mem64.hh:94
MightBeMicro64(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
Definition: mem64.hh:76
SysDC64(const char *mnem, ExtMachInst _machInst, OpClass __opClass, RegIndex _base, MiscRegIndex _dest)
Definition: mem64.hh:61
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: mem64.cc:51
MiscRegIndex dest
Definition: mem64.hh:56
uint32_t iss() const override
Definition: mem64.cc:62
This class is implementing the Base class for a generic AArch64 instruction which is making use of sy...
Definition: misc64.hh:125
Target & as()
Definition: pcstate.hh:72
std::bitset< Num_Flags > flags
Flag values for this instruction.
Definition: static_inst.hh:103
ThreadContext is the external interface to all thread state for anything outside of the CPU.
virtual const PCStateBase & pcState() const =0
constexpr RegId Zero
Definition: cc.hh:78
static bool isSP(RegIndex reg)
Definition: int.hh:619
MiscRegIndex
Definition: misc.hh:64
Bitfield< 4 > pc
Bitfield< 17 > os
Definition: misc.hh:810
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
uint16_t RegIndex
Definition: types.hh:176
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
uint16_t MicroPC
Definition: types.hh:149

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