gem5  v21.1.0.2
mem64.cc
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37 
38 #include "arch/arm/insts/mem64.hh"
39 
40 #include "arch/arm/tlb.hh"
41 #include "base/loader/symtab.hh"
42 #include "mem/request.hh"
43 
44 namespace gem5
45 {
46 
47 namespace ArmISA
48 {
49 
50 std::string
52 {
53  std::stringstream ss;
54  printMnemonic(ss, "", false);
55  ccprintf(ss, ", ");
57  return ss.str();
58 }
59 
60 
61 
62 void
63 Memory64::startDisassembly(std::ostream &os) const
64 {
65  printMnemonic(os, "", false);
68  }else{
70  }
71  ccprintf(os, ", [");
73 }
74 
75 void
76 Memory64::setExcAcRel(bool exclusive, bool acrel)
77 {
78  if (exclusive)
80  else
82  if (acrel) {
83  flags[IsWriteBarrier] = true;
84  flags[IsReadBarrier] = true;
85  }
86 }
87 
88 std::string
90  Addr pc, const loader::SymbolTable *symtab) const
91 {
92  std::stringstream ss;
94  if (imm)
95  ccprintf(ss, ", #%d", imm);
96  ccprintf(ss, "]");
97  return ss.str();
98 }
99 
100 std::string
102  Addr pc, const loader::SymbolTable *symtab) const
103 {
104  std::stringstream ss;
105  printMnemonic(ss, "", false);
106  printIntReg(ss, dest);
107  ccprintf(ss, ", ");
108  printIntReg(ss, dest2);
109  ccprintf(ss, ", [");
110  printIntReg(ss, base);
111  if (imm)
112  ccprintf(ss, ", #%d", imm);
113  ccprintf(ss, "]");
114  return ss.str();
115 }
116 
117 std::string
119  Addr pc, const loader::SymbolTable *symtab) const
120 {
121  std::stringstream ss;
122  printMnemonic(ss, "", false);
124  ccprintf(ss, ", ");
125  printIntReg(ss, dest);
126  ccprintf(ss, ", ");
127  printIntReg(ss, dest2);
128  ccprintf(ss, ", [");
129  printIntReg(ss, base);
130  if (imm)
131  ccprintf(ss, ", #%d", imm);
132  ccprintf(ss, "]");
133  return ss.str();
134 }
135 
136 std::string
138  Addr pc, const loader::SymbolTable *symtab) const
139 {
140  std::stringstream ss;
142  ccprintf(ss, ", #%d]!", imm);
143  return ss.str();
144 }
145 
146 std::string
148  Addr pc, const loader::SymbolTable *symtab) const
149 {
150  std::stringstream ss;
152  if (imm)
153  ccprintf(ss, "], #%d", imm);
154  ccprintf(ss, "]");
155  return ss.str();
156 }
157 
158 std::string
160  Addr pc, const loader::SymbolTable *symtab) const
161 {
162  std::stringstream ss;
165  ccprintf(ss, "]");
166  return ss.str();
167 }
168 
169 std::string
171  Addr pc, const loader::SymbolTable *symtab) const
172 {
173  std::stringstream ss;
175  ccprintf(ss, "]");
176  return ss.str();
177 }
178 
179 std::string
181  Addr pc, const loader::SymbolTable *symtab) const
182 {
183  std::stringstream ss;
184  printMnemonic(ss, "", false);
185  printIntReg(ss, dest);
186  ccprintf(ss, ", ");
188  ccprintf(ss, ", [");
189  printIntReg(ss, base);
190  ccprintf(ss, "]");
191  return ss.str();
192 }
193 
194 std::string
196  Addr pc, const loader::SymbolTable *symtab) const
197 {
198  std::stringstream ss;
199  printMnemonic(ss, "", false);
200  printIntReg(ss, dest);
201  ccprintf(ss, ", #%d", pc + imm);
202  return ss.str();
203 }
204 
205 std::string
207  Addr pc, const loader::SymbolTable *symtab) const
208 {
209  std::stringstream ss;
210  printMnemonic(ss, "", false);
212  ccprintf(ss, ", ");
214  ccprintf(ss, ", ");
215  printIntReg(ss, dest);
216  ccprintf(ss, ", ");
217  printIntReg(ss, dest2);
218  ccprintf(ss, ", [");
219  printIntReg(ss, base);
220  ccprintf(ss, "]");
221  return ss.str();
222 }
223 
224 } // namespace ArmISA
225 } // namespace gem5
gem5::ArmISA::MemoryDImmEx64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: mem64.cc:118
gem5::ArmISA::MemoryAtomicPair64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: mem64.cc:206
gem5::ArmISA::MemoryDImm64::dest2
IntRegIndex dest2
Definition: mem64.hh:155
gem5::ArmISA::Memory64::setExcAcRel
void setExcAcRel(bool exclusive, bool acrel)
Definition: mem64.cc:76
gem5::ArmISA::TLB::AllowUnaligned
@ AllowUnaligned
Definition: tlb.hh:123
gem5::ArmISA::MemoryReg64::offset
IntRegIndex offset
Definition: mem64.hh:213
gem5::ArmISA::MemoryLiteral64::imm
int64_t imm
Definition: mem64.hh:259
gem5::ArmISA::MemoryDImm64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: mem64.cc:101
gem5::ArmISA::MemoryAtomicPair64::dest2
IntRegIndex dest2
Definition: mem64.hh:273
gem5::ArmISA::ArmStaticInst::printMnemonic
void printMnemonic(std::ostream &os, const std::string &suffix="", bool withPred=true, bool withCond64=false, ConditionCode cond64=COND_UC) const
Definition: static_inst.cc:377
gem5::ArmISA::Memory64::dest
IntRegIndex dest
Definition: mem64.hh:102
gem5::loader::SymbolTable
Definition: symtab.hh:65
tlb.hh
gem5::ArmISA::MemoryPostIndex64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: mem64.cc:147
request.hh
gem5::ArmISA::SysDC64::base
IntRegIndex base
Definition: mem64.hh:53
gem5::ccprintf
void ccprintf(cp::Print &print)
Definition: cprintf.hh:130
gem5::ArmISA::SysDC64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: mem64.cc:51
gem5::ArmISA::MemoryImm64::imm
int64_t imm
Definition: mem64.hh:141
gem5::ArmISA::MemoryReg64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: mem64.cc:159
gem5::ArmISA::MemoryRaw64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: mem64.cc:170
gem5::ArmISA::ArmStaticInst::printExtendOperand
void printExtendOperand(bool firstOperand, std::ostream &os, IntRegIndex rm, ArmExtendType type, int64_t shiftAmt) const
Definition: static_inst.cc:562
gem5::ArmISA::Memory64::base
IntRegIndex base
Definition: mem64.hh:103
gem5::StaticInst::isDataPrefetch
bool isDataPrefetch() const
Definition: static_inst.hh:174
mem64.hh
gem5::StaticInst::flags
std::bitset< Num_Flags > flags
Flag values for this instruction.
Definition: static_inst.hh:103
gem5::ArmISA::Memory64::startDisassembly
void startDisassembly(std::ostream &os) const
Definition: mem64.cc:63
gem5::ArmISA::MemoryReg64::type
ArmExtendType type
Definition: mem64.hh:214
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ArmISA::MemoryPreIndex64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: mem64.cc:137
gem5::ArmISA::MemoryEx64::result
IntRegIndex result
Definition: mem64.hh:244
gem5::ArmISA::MemoryEx64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: mem64.cc:180
gem5::StaticInst::isInstPrefetch
bool isInstPrefetch() const
Definition: static_inst.hh:173
gem5::ArmISA::MemoryAtomicPair64::result
IntRegIndex result
Definition: mem64.hh:274
gem5::Request::LLSC
@ LLSC
The request is a Load locked/store conditional.
Definition: request.hh:156
gem5::X86ISA::os
Bitfield< 17 > os
Definition: misc.hh:809
gem5::ArmISA::ss
Bitfield< 21 > ss
Definition: misc_types.hh:59
gem5::ArmISA::MemoryAtomicPair64::result2
IntRegIndex result2
Definition: mem64.hh:275
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::ArmISA::MemoryDImmEx64::result
IntRegIndex result
Definition: mem64.hh:171
gem5::ArmISA::MemoryReg64::shiftAmt
uint64_t shiftAmt
Definition: mem64.hh:215
symtab.hh
gem5::ArmISA::ArmStaticInst::printIntReg
void printIntReg(std::ostream &os, RegIndex reg_idx, uint8_t opWidth=0) const
Print a register name for disassembly given the unique dependence tag number (FP or int).
Definition: static_inst.cc:299
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::ArmISA::MemoryLiteral64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: mem64.cc:195
gem5::ArmISA::MemoryImm64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: mem64.cc:89
gem5::ArmISA::Memory64::memAccessFlags
unsigned memAccessFlags
Definition: mem64.hh:133
gem5::ArmISA::ArmStaticInst::printPFflags
void printPFflags(std::ostream &os, int flag) const
Definition: static_inst.cc:334

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