47#include "debug/MemTest.hh"
87 noRequestEvent([
this]{ noRequest(); },
name()),
88 noResponseEvent([
this]{ noResponse(); },
name()),
94 percentReads(
p.percent_reads),
95 percentFunctional(
p.percent_functional),
96 percentUncacheable(
p.percent_uncacheable),
97 percentAtomic(
p.percent_atomic),
98 requestorId(
p.system->getRequestorId(
this)),
99 blockSize(
p.system->cacheLineSize()),
100 blockAddrMask(blockSize - 1),
101 sizeBlocks(size / blockSize),
102 baseAddr1(
p.base_addr_1),
103 baseAddr2(
p.base_addr_2),
104 uncacheAddr(
p.uncacheable_base_addr),
105 progressInterval(
p.progress_interval),
106 progressCheck(
p.progress_check),
107 nextProgressMessage(
p.progress_interval),
108 maxLoads(
p.max_loads),
109 atomic(
p.system->isAtomicMode()),
110 suppressFuncErrors(
p.suppress_func_errors), stats(
this)
113 fatal_if(
id >= blockSize,
"Too many testers, only %d allowed\n",
122 schedule(tickEvent,
curTick());
123 schedule(noRequestEvent, clockEdge(progressCheck));
129 if (if_name ==
"port")
139 assert(req->getSize() == 1);
149 pkt->
isError() ?
"error" :
"success");
151 const uint8_t *pkt_data = pkt->
getConstPtr<uint8_t>();
155 panic(
"%s access failed at %#x\n",
156 pkt->
isWrite() ?
"Write" :
"Read", req->getPaddr());
160 if (pkt_data[0] != ref_data) {
161 panic(
"%s: read of %x (blk %x) @ cycle %d "
162 "returns %x, expected %x\n",
name(),
164 pkt_data[0], ref_data);
167 "Completing atomic at address %x (blk %x) value %x\n",
176 }
else if (pkt->
isRead()) {
178 if (pkt_data[0] != ref_data) {
179 panic(
"%s: read of %x (blk %x) @ cycle %d "
180 "returns %x, expected %x\n",
name(),
182 pkt_data[0], ref_data);
190 "%s: completed %d read, %d write, "
191 "%d atomic accesses @%d\n",
225 : statistics::
Group(parent),
226 ADD_STAT(numReads, statistics::units::Count::get(),
227 "number of read accesses completed"),
228 ADD_STAT(numWrites, statistics::units::Count::get(),
229 "number of write accesses completed"),
230 ADD_STAT(numAtomics, statistics::units::Count::get(),
231 "number of atomic accesses completed")
285 "Tester %s has more than 100 outstanding requests\n",
name());
288 uint8_t *pkt_data =
new uint8_t[1];
293 [[maybe_unused]] uint8_t ref_data = 0;
298 ref_data = ref->second;
302 "Initiating %sread at addr %x (blk %x) expecting %x\n",
303 do_functional ?
"functional " :
"", req->getPaddr(),
307 pkt->dataDynamic(pkt_data);
311 "Initiating atomic at addr %x (blk %x) value %x\n",
317 [](uint8_t*
b, uint8_t
a, uint8_t
c){
322 req->setAtomicOpFunctor(std::move(amo_op));
331 "Initiating %swrite at addr %x (blk %x) value %x\n",
332 do_functional ?
"functional " :
"", req->getPaddr(),
336 pkt->dataDynamic(pkt_data);
342 bool keep_ticking =
true;
The ClockedObject class extends the SimObject with a clock and accessor functions to relate ticks to ...
Tick clockEdge(Cycles cycles=Cycles(0)) const
Determine the tick when a cycle begins, by default the current one, but the argument also enables the...
void recvReqRetry()
Called by the peer if sendTimingReq was called on this peer (causing recvTimingReq to be called on th...
bool recvTimingResp(PacketPtr pkt)
Receive a timing response from the peer.
The MemTest class tests a cache coherent memory system by generating false sharing and verifying the ...
EventFunctionWrapper tickEvent
const bool suppressFuncErrors
std::unordered_set< Addr > outstandingAddrs
gem5::MemTest::MemTestStats stats
std::unordered_map< Addr, uint8_t > atomicPendingData
const Cycles progressCheck
const unsigned percentFunctional
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
Addr blockAlign(Addr addr) const
Get the block aligned address.
const unsigned percentAtomic
const unsigned percentReads
void completeRequest(PacketPtr pkt, bool functional=false)
Complete a request by checking the response.
const unsigned progressInterval
std::unordered_map< Addr, uint8_t > referenceData
const unsigned sizeBlocks
EventFunctionWrapper noRequestEvent
EventFunctionWrapper noResponseEvent
RequestorID requestorId
Request id for all generated traffic.
bool sendPkt(PacketPtr pkt)
const unsigned percentUncacheable
virtual std::string name() const
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
RequestPtr req
A pointer to the original request.
const T * getConstPtr() const
void dataDynamic(T *p)
Set the data pointer to a value that should have delete [] called on it.
bool suppressFuncError() const
void setSuppressFuncError()
Tick sendAtomic(PacketPtr pkt)
Send an atomic request packet, where the data is moved and the state is updated in zero time,...
bool sendTimingReq(PacketPtr pkt)
Attempt to send a timing request to the responder port by calling its corresponding receive function.
void sendFunctional(PacketPtr pkt) const
Send a functional request packet, where the data is instantly updated everywhere in the memory system...
@ ATOMIC_RETURN_OP
The request is an atomic that returns data.
@ UNCACHEABLE
The request is to an uncacheable address.
#define ADD_STAT(n,...)
Convenience macro to add a stat to a statistics group.
std::unique_ptr< AtomicOpFunctor > AtomicOpFunctorPtr
std::enable_if_t< std::is_integral_v< T >, T > random()
Use the SFINAE idiom to choose an implementation based on whether the type is integral or floating po...
void deschedule(Event &event)
bool scheduled() const
Determine if the current event is scheduled.
void schedule(Event &event, Tick when)
void reschedule(Event &event, Tick when, bool always=false)
#define panic(...)
This implements a cprintf based panic() function.
#define fatal_if(cond,...)
Conditional fatal macro that checks the supplied condition and only causes a fatal error if the condi...
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
virtual Port & getPort(const std::string &if_name, PortID idx=InvalidPortID)
Get a port with a given name and index.
Bitfield< 23, 20 > atomic
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
std::shared_ptr< Request > RequestPtr
Tick curTick()
The universal simulation clock.
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
void exitSimLoop(const std::string &message, int exit_code, Tick when, Tick repeat, bool serialize)
Schedule an event to exit the simulation loop (returning to Python) at the end of the current cycle (...
static unsigned int TESTER_ALLOCATOR
void ccprintf(cp::Print &print)
Declaration of Statistics objects.
statistics::Scalar numWrites
statistics::Scalar numReads
statistics::Scalar numAtomics
MemTestStats(statistics::Group *parent)
const std::string & name()