watchdog_generic.hh

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/*
 * Copyright (c) 2020 ARM Limited
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 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
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 * modified or unmodified, in source code or in binary form.
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#ifndef __DEV_ARM_WATCHDOG_GENERIC_HH__
#define __DEV_ARM_WATCHDOG_GENERIC_HH__
 
#include "dev/arm/generic_timer.hh"
#include "dev/io_device.hh"
 
namespace gem5
{
 
class ArmInterruptPin;
struct GenericWatchdogParams;
 
class GenericWatchdog : public PioDevice
{
  public:
    GenericWatchdog(const GenericWatchdogParams &params);
 
    void serialize(CheckpointOut &cp) const override;
    void unserialize(CheckpointIn &cp) override;
 
    bool enabled() const { return controlStatus.enabled; }
 
  protected:
    AddrRangeList getAddrRanges() const override;
 
    Tick read(PacketPtr pkt) override;
    Tick write(PacketPtr pkt) override;
 
    uint32_t readRefresh(Addr addr);
    uint32_t readControl(Addr addr);
 
    void writeRefresh(Addr addr, uint32_t data);
    void writeControl(Addr addr, uint32_t data);
 
  protected:
    class Listener : public SystemCounterListener
    {
      public:
        explicit Listener(GenericWatchdog& _parent)
          : parent(_parent)
        {}
 
        void notify(void) override
        {
            panic_if(parent.enabled(),
                "The Generic Watchdog shall be disabled when "
                "the System Counter is being updated, or "
                "the results are unpredictable");
        }
 
      protected:
        GenericWatchdog &parent;
    };
 
    void explicitRefresh();
    void refresh();
    void timeout();
    EventFunctionWrapper timeoutEvent;
 
  private:
    enum class RefreshOffset : Addr
    {
        WRR = 0x000, // Watchdog Refresh Register
        W_IIDR = 0xfcc, // Watchdog Interface Identification Register
    };
 
    enum class ControlOffset : Addr
    {
        WCS = 0x000, // Watchdog Control and Status Register
        WOR = 0x008, // Watchdog Offset Register
        WCV_LO = 0x010, // Watchdog Compare Register [31:0]
        WCV_HI = 0x014, // Watchdog Compare Register [63:32]
        W_IIDR = 0xfcc, // Watchdog Interface Identification Register
    };
 
    BitUnion32(WCTRLS)
        Bitfield<2> ws1; // Watchdog Signal 1 Status
        Bitfield<1> ws0; // Watchdog Signal 0 Status
        Bitfield<0> enabled; // Watchdog Enable
    EndBitUnion(WCTRLS)
 
    
    WCTRLS controlStatus;
 
    uint32_t offset;
 
    uint64_t compare;
 
    const uint32_t iidr;
 
    const AddrRange refreshFrame;
    const AddrRange controlFrame;
 
    const Tick pioLatency;
 
    SystemCounter &cnt;
    Listener cntListener;
 
    ArmInterruptPin * const ws0;
    ArmInterruptPin * const ws1;
};
 
} // namespace gem5
 
#endif // __DEV_ARM_WATCHDOG_GENERIC_HH__