gem5  v21.1.0.2
watchdog_generic.cc
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37 
39 
40 #include "dev/arm/base_gic.hh"
41 #include "params/GenericWatchdog.hh"
42 
43 namespace gem5
44 {
45 
46 GenericWatchdog::GenericWatchdog(const GenericWatchdogParams &p)
47  : PioDevice(p),
48  timeoutEvent([this]{ timeout(); }, name()),
49  controlStatus(0),
50  offset(0),
51  compare(0),
52  iidr(0),
53  refreshFrame(p.refresh_start, p.refresh_start + 0x10000),
54  controlFrame(p.control_start, p.control_start + 0x10000),
55  pioLatency(p.pio_latency),
56  cnt(*p.system_counter),
57  cntListener(*this),
58  ws0(p.ws0->get()),
59  ws1(p.ws1->get())
60 {
61  cnt.registerListener(&cntListener);
62 }
63 
66 {
67  AddrRangeList ranges;
68  ranges.push_back(refreshFrame);
69  ranges.push_back(controlFrame);
70  return ranges;
71 }
72 
73 Tick
75 {
76  const Addr addr = pkt->getAddr();
77  const size_t size = pkt->getSize();
78  panic_if(size != 4, "GenericWatchdog::read: Invalid size %i\n", size);
79 
80  uint32_t resp = 0;
81 
82  if (refreshFrame.contains(addr)) {
83  resp = readRefresh(addr);
84  } else if (controlFrame.contains(addr)) {
85  resp = readControl(addr);
86  } else {
87  panic("%s unknown address %#x\n", __func__, addr);
88  }
89 
90  pkt->setUintX(resp, ByteOrder::little);
91  pkt->makeResponse();
92  return pioLatency;
93 }
94 
95 uint32_t
97 {
98  const auto daddr = static_cast<RefreshOffset>(
99  addr - refreshFrame.start());
100 
101  switch (daddr) {
102  case RefreshOffset::WRR:
103  // A read of the refresh register has no effect and returns 0
104  return 0;
106  return iidr;
107  default:
108  panic("%s unknown address %#x\n", __func__, addr);
109  }
110 }
111 
112 uint32_t
114 {
115  const auto daddr = static_cast<ControlOffset>(
116  addr - controlFrame.start());
117 
118  switch (daddr) {
119  case ControlOffset::WCS:
120  return controlStatus;
121  case ControlOffset::WOR:
122  return offset;
124  return bits(compare, 31, 0);
126  return bits(compare, 63, 32);
128  return iidr;
129  default:
130  panic("%s unknown address %#x\n", __func__, addr);
131  }
132 }
133 
134 Tick
136 {
137  const Addr addr = pkt->getAddr();
138  const size_t size = pkt->getSize();
139  panic_if(size != 4, "GenericWatchdog::write: Invalid size %i\n", size);
140 
141  uint32_t data = pkt->getUintX(ByteOrder::little);
142 
143  if (refreshFrame.contains(addr)) {
145  } else if (controlFrame.contains(addr)) {
147  } else {
148  panic("%s unknown address %#x\n", __func__, addr);
149  }
150 
151  pkt->makeResponse();
152  return pioLatency;
153 }
154 
155 void
157 {
158  const auto daddr = static_cast<RefreshOffset>(
159  addr - refreshFrame.start());
160 
161  switch (daddr) {
162  case RefreshOffset::WRR:
163  explicitRefresh();
164  break;
165  default:
166  panic("%s unknown address %#x\n", __func__, addr);
167  }
168 }
169 
170 void
172 {
173  const auto daddr = static_cast<ControlOffset>(
174  addr - controlFrame.start());
175 
176  switch (daddr) {
177  case ControlOffset::WCS:
178  controlStatus = data & 0x1;
179  explicitRefresh();
180  break;
181  case ControlOffset::WOR:
182  offset = data;
183  explicitRefresh();
184  break;
186  compare = insertBits(compare, 31, 0, data);
187  break;
189  compare = insertBits(compare, 63, 32, data);
190  break;
191  default:
192  panic("%s unknown address %#x\n", __func__, addr);
193  }
194 }
195 
196 void
198 {
199  // Watchdog signals are cleared in case of an explicit refresh
200  controlStatus.ws0 = 0;
201  controlStatus.ws1 = 0;
202  ws0->clear();
203  ws1->clear();
204 
205  refresh();
206 }
207 
208 void
210 {
211  // Update compare value
212  compare = cnt.value() + offset;
213 
214  // Ask the System Counter how long we have to wait until
215  // it reaches the new compare value
216  Tick timeout_time = cnt.whenValue(compare);
217 
218  reschedule(timeoutEvent, timeout_time, true);
219 }
220 
221 void
223 {
224  if (!controlStatus.enabled)
225  return;
226 
227  if (!controlStatus.ws0) {
228  controlStatus.ws0 = 1;
229  ws0->raise();
230  } else {
231  controlStatus.ws1 = 1;
232  ws1->raise();
233  }
234 
235  refresh();
236 }
237 
238 void
240 {
241  SERIALIZE_SCALAR(controlStatus);
244 
245  bool ev_scheduled = timeoutEvent.scheduled();
246  SERIALIZE_SCALAR(ev_scheduled);
247  if (ev_scheduled)
249 }
250 
251 void
253 {
254  UNSERIALIZE_SCALAR(controlStatus);
257 
258  bool ev_scheduled;
259  UNSERIALIZE_SCALAR(ev_scheduled);
260  if (ev_scheduled) {
261  Tick when;
262  UNSERIALIZE_SCALAR(when);
263  reschedule(timeoutEvent, when, true);
264  }
265 }
266 
267 } // namespace gem5
gem5::Event::when
Tick when() const
Get the time that the event is scheduled.
Definition: eventq.hh:508
gem5::AddrRange::start
Addr start() const
Get the start address of the range.
Definition: addr_range.hh:317
gem5::GenericWatchdog::getAddrRanges
AddrRangeList getAddrRanges() const override
Every PIO device is obliged to provide an implementation that returns the address ranges the device r...
Definition: watchdog_generic.cc:65
gem5::GenericWatchdog::RefreshOffset::WRR
@ WRR
gem5::Packet::getUintX
uint64_t getUintX(ByteOrder endian) const
Get the data in the packet byte swapped from the specified endianness and zero-extended to 64 bits.
Definition: packet.cc:334
data
const char data[]
Definition: circlebuf.test.cc:48
gem5::GenericWatchdog::cnt
SystemCounter & cnt
Definition: watchdog_generic.hh:151
gem5::PioDevice
This device is the base class which all devices senstive to an address range inherit from.
Definition: io_device.hh:102
UNSERIALIZE_SCALAR
#define UNSERIALIZE_SCALAR(scalar)
Definition: serialize.hh:575
gem5::GenericWatchdog::explicitRefresh
void explicitRefresh()
Definition: watchdog_generic.cc:197
gem5::GenericWatchdog::ControlOffset::WCS
@ WCS
gem5::GenericWatchdog::read
Tick read(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: watchdog_generic.cc:74
gem5::AddrRangeList
std::list< AddrRange > AddrRangeList
Convenience typedef for a collection of address ranges.
Definition: addr_range.hh:641
gem5::AddrRange::contains
bool contains(const Addr &a) const
Determine if the range contains an address.
Definition: addr_range.hh:438
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::GenericWatchdog::ControlOffset::W_IIDR
@ W_IIDR
gem5::GenericWatchdog::writeRefresh
void writeRefresh(Addr addr, uint32_t data)
Definition: watchdog_generic.cc:156
base_gic.hh
gem5::GenericWatchdog::readRefresh
uint32_t readRefresh(Addr addr)
Definition: watchdog_generic.cc:96
watchdog_generic.hh
gem5::GenericWatchdog::offset
uint32_t offset
Offset Register.
Definition: watchdog_generic.hh:138
gem5::GenericWatchdog::iidr
const uint32_t iidr
Interface Identification Register.
Definition: watchdog_generic.hh:144
gem5::GenericWatchdog::timeout
void timeout()
Definition: watchdog_generic.cc:222
gem5::GenericWatchdog::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: watchdog_generic.cc:252
gem5::GenericWatchdog::ControlOffset::WOR
@ WOR
gem5::SystemCounter::whenValue
Tick whenValue(uint64_t target_val)
Returns the tick at which a certain counter value is reached.
Definition: generic_timer.cc:156
gem5::GenericWatchdog::ws0
Bitfield< 1 > ws0
Definition: watchdog_generic.hh:130
gem5::GenericWatchdog::refresh
void refresh()
Definition: watchdog_generic.cc:209
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::GenericWatchdog::timeoutEvent
EventFunctionWrapper timeoutEvent
Definition: watchdog_generic.hh:110
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::ArmInterruptPin::clear
virtual void clear()=0
Clear a signalled interrupt.
gem5::ArmISA::offset
Bitfield< 23, 0 > offset
Definition: types.hh:144
gem5::EventManager::reschedule
void reschedule(Event &event, Tick when, bool always=false)
Definition: eventq.hh:1037
gem5::insertBits
constexpr T insertBits(T val, unsigned first, unsigned last, B bit_val)
Returns val with bits first to last set to the LSBs of bit_val.
Definition: bitfield.hh:166
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
gem5::GenericWatchdog::readControl
uint32_t readControl(Addr addr)
Definition: watchdog_generic.cc:113
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
name
const std::string & name()
Definition: trace.cc:49
SERIALIZE_SCALAR
#define SERIALIZE_SCALAR(scalar)
Definition: serialize.hh:568
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:203
gem5::SystemCounter::value
uint64_t value()
Updates and returns the counter value.
Definition: generic_timer.cc:109
gem5::GenericWatchdog::RefreshOffset::W_IIDR
@ W_IIDR
gem5::GenericWatchdog::GenericWatchdog
GenericWatchdog(const GenericWatchdogParams &params)
Definition: watchdog_generic.cc:46
gem5::GenericWatchdog::RefreshOffset
RefreshOffset
Definition: watchdog_generic.hh:113
gem5::Packet::makeResponse
void makeResponse()
Take a request packet and modify it in place to be suitable for returning as a response to that reque...
Definition: packet.hh:1031
gem5::GenericWatchdog::compare
uint64_t compare
Compare Register.
Definition: watchdog_generic.hh:141
gem5::GenericWatchdog::write
Tick write(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: watchdog_generic.cc:135
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::GenericWatchdog::writeControl
void writeControl(Addr addr, uint32_t data)
Definition: watchdog_generic.cc:171
gem5::ArmInterruptPin::raise
virtual void raise()=0
Signal an interrupt.
std::list< AddrRange >
gem5::Packet::getAddr
Addr getAddr() const
Definition: packet.hh:781
gem5::GenericWatchdog::ControlOffset::WCV_HI
@ WCV_HI
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::GenericWatchdog::refreshFrame
const AddrRange refreshFrame
Definition: watchdog_generic.hh:146
gem5::GenericWatchdog::controlFrame
const AddrRange controlFrame
Definition: watchdog_generic.hh:147
gem5::Packet::setUintX
void setUintX(uint64_t w, ByteOrder endian)
Set the value in the word w after truncating it to the length of the packet and then byteswapping it ...
Definition: packet.cc:351
gem5::GenericWatchdog::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: watchdog_generic.cc:239
gem5::GenericWatchdog::ws1
ArmInterruptPin *const ws1
Definition: watchdog_generic.hh:156
gem5::GenericWatchdog::ControlOffset::WCV_LO
@ WCV_LO
gem5::Packet::getSize
unsigned getSize() const
Definition: packet.hh:791
gem5::GenericWatchdog::pioLatency
const Tick pioLatency
Definition: watchdog_generic.hh:149
gem5::Event::scheduled
bool scheduled() const
Determine if the current event is scheduled.
Definition: eventq.hh:465
gem5::GenericWatchdog::ControlOffset
ControlOffset
Definition: watchdog_generic.hh:119
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84

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