gem5  v21.1.0.2
cpu.cc
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37 
38 #include "cpu/minor/cpu.hh"
39 
40 #include "cpu/minor/dyn_inst.hh"
41 #include "cpu/minor/fetch1.hh"
42 #include "cpu/minor/pipeline.hh"
43 #include "debug/Drain.hh"
44 #include "debug/MinorCPU.hh"
45 #include "debug/Quiesce.hh"
46 
47 namespace gem5
48 {
49 
50 MinorCPU::MinorCPU(const MinorCPUParams &params) :
51  BaseCPU(params),
52  threadPolicy(params.threadPolicy),
53  stats(this)
54 {
55  /* This is only written for one thread at the moment */
56  minor::MinorThread *thread;
57 
58  for (ThreadID i = 0; i < numThreads; i++) {
59  if (FullSystem) {
60  thread = new minor::MinorThread(this, i, params.system,
61  params.mmu, params.isa[i]);
63  } else {
64  thread = new minor::MinorThread(this, i, params.system,
65  params.workload[i], params.mmu,
66  params.isa[i]);
67  }
68 
69  threads.push_back(thread);
70  ThreadContext *tc = thread->getTC();
71  threadContexts.push_back(tc);
72  }
73 
74 
75  if (params.checker) {
76  fatal("The Minor model doesn't support checking (yet)\n");
77  }
78 
80 
81  pipeline = new minor::Pipeline(*this, params);
82  activityRecorder = pipeline->getActivityRecorder();
83 
84  fetchEventWrapper = NULL;
85 }
86 
88 {
89  delete pipeline;
90 
91  if (fetchEventWrapper != NULL)
92  delete fetchEventWrapper;
93 
94  for (ThreadID thread_id = 0; thread_id < threads.size(); thread_id++) {
95  delete threads[thread_id];
96  }
97 }
98 
99 void
101 {
102  BaseCPU::init();
103 
104  if (!params().switched_out &&
105  system->getMemoryMode() != enums::timing)
106  {
107  fatal("The Minor CPU requires the memory system to be in "
108  "'timing' mode.\n");
109  }
110 
111  /* Initialise the ThreadContext's memory proxies */
112  for (ThreadID thread_id = 0; thread_id < threads.size(); thread_id++) {
113  ThreadContext *tc = getContext(thread_id);
114 
115  tc->initMemProxies(tc);
116  }
117 }
118 
120 void
122 {
124  pipeline->regStats();
125 }
126 
127 void
129 {
130  threads[thread_id]->serialize(cp);
131 }
132 
133 void
135 {
136  threads[thread_id]->unserialize(cp);
137 }
138 
139 void
141 {
142  pipeline->serialize(cp);
143  BaseCPU::serialize(cp);
144 }
145 
146 void
148 {
149  pipeline->unserialize(cp);
151 }
152 
153 void
155 {
156  DPRINTF(Drain, "[tid:%d] MinorCPU wakeup\n", tid);
157  assert(tid < numThreads);
158 
159  if (threads[tid]->status() == ThreadContext::Suspended) {
160  threads[tid]->activate();
161  }
162 }
163 
164 void
166 {
167  DPRINTF(MinorCPU, "MinorCPU startup\n");
168 
170 
171  for (ThreadID tid = 0; tid < numThreads; tid++)
172  pipeline->wakeupFetch(tid);
173 }
174 
177 {
178  // Deschedule any power gating event (if any)
180 
181  if (switchedOut()) {
182  DPRINTF(Drain, "Minor CPU switched out, draining not needed.\n");
183  return DrainState::Drained;
184  }
185 
186  DPRINTF(Drain, "MinorCPU drain\n");
187 
188  /* Need to suspend all threads and wait for Execute to idle.
189  * Tell Fetch1 not to fetch */
190  if (pipeline->drain()) {
191  DPRINTF(Drain, "MinorCPU drained\n");
192  return DrainState::Drained;
193  } else {
194  DPRINTF(Drain, "MinorCPU not finished draining\n");
195  return DrainState::Draining;
196  }
197 }
198 
199 void
201 {
202  DPRINTF(Drain, "MinorCPU drain done\n");
204 }
205 
206 void
208 {
209  /* When taking over from another cpu make sure lastStopped
210  * is reset since it might have not been defined previously
211  * and might lead to a stats corruption */
212  pipeline->resetLastStopped();
213 
214  if (switchedOut()) {
215  DPRINTF(Drain, "drainResume while switched out. Ignoring\n");
216  return;
217  }
218 
219  DPRINTF(Drain, "MinorCPU drainResume\n");
220 
221  if (!system->isTimingMode()) {
222  fatal("The Minor CPU requires the memory system to be in "
223  "'timing' mode.\n");
224  }
225 
226  for (ThreadID tid = 0; tid < numThreads; tid++){
227  wakeup(tid);
228  }
229 
230  pipeline->drainResume();
231 
232  // Reschedule any power gating event (if any)
234 }
235 
236 void
238 {
239  DPRINTF(Drain, "MinorCPU memWriteback\n");
240 }
241 
242 void
244 {
245  DPRINTF(MinorCPU, "MinorCPU switchOut\n");
246 
247  assert(!switchedOut());
249 
250  /* Check that the CPU is drained? */
252 }
253 
254 void
256 {
257  DPRINTF(MinorCPU, "MinorCPU takeOverFrom\n");
258 
259  BaseCPU::takeOverFrom(old_cpu);
260 }
261 
262 void
264 {
265  DPRINTF(MinorCPU, "ActivateContext thread: %d\n", thread_id);
266 
267  /* Do some cycle accounting. lastStopped is reset to stop the
268  * wakeup call on the pipeline from adding the quiesce period
269  * to BaseCPU::numCycles */
270  stats.quiesceCycles += pipeline->cyclesSinceLastStopped();
271  pipeline->resetLastStopped();
272 
273  /* Wake up the thread, wakeup the pipeline tick */
274  threads[thread_id]->activate();
276 
277  if (!threads[thread_id]->getUseForClone())//the thread is not cloned
278  {
279  pipeline->wakeupFetch(thread_id);
280  } else { //the thread from clone
281  if (fetchEventWrapper != NULL)
282  delete fetchEventWrapper;
283  fetchEventWrapper = new EventFunctionWrapper([this, thread_id]
284  { pipeline->wakeupFetch(thread_id); }, "wakeupFetch");
286  }
287 
288  BaseCPU::activateContext(thread_id);
289 }
290 
291 void
293 {
294  DPRINTF(MinorCPU, "SuspendContext %d\n", thread_id);
295 
296  threads[thread_id]->suspend();
297 
298  BaseCPU::suspendContext(thread_id);
299 }
300 
301 void
302 MinorCPU::wakeupOnEvent(unsigned int stage_id)
303 {
304  DPRINTF(Quiesce, "Event wakeup from stage %d\n", stage_id);
305 
306  /* Mark that some activity has taken place and start the pipeline */
307  activityRecorder->activateStage(stage_id);
308  pipeline->start();
309 }
310 
311 Port &
313 {
314  return pipeline->getInstPort();
315 }
316 
317 Port &
319 {
320  return pipeline->getDataPort();
321 }
322 
323 Counter
325 {
326  Counter ret = 0;
327 
328  for (auto i = threads.begin(); i != threads.end(); i ++)
329  ret += (*i)->numInst;
330 
331  return ret;
332 }
333 
334 Counter
336 {
337  Counter ret = 0;
338 
339  for (auto i = threads.begin(); i != threads.end(); i ++)
340  ret += (*i)->numOp;
341 
342  return ret;
343 }
344 
345 } // namespace gem5
gem5::minor::MinorStats::quiesceCycles
statistics::Scalar quiesceCycles
Number of cycles in quiescent state.
Definition: stats.hh:76
fatal
#define fatal(...)
This implements a cprintf based fatal() function.
Definition: logging.hh:189
dyn_inst.hh
gem5::MinorCPU::takeOverFrom
void takeOverFrom(BaseCPU *old_cpu) override
Load the state of a CPU from the previous CPU object, invoked on all new CPUs that are about to be sw...
Definition: cpu.cc:255
gem5::MinorCPU::pipeline
minor::Pipeline * pipeline
pipeline is a container for the clockable pipeline stage objects.
Definition: cpu.hh:90
gem5::BaseCPU::switchedOut
bool switchedOut() const
Determine if the CPU is switched out.
Definition: base.hh:357
gem5::MinorCPU::memWriteback
void memWriteback() override
Write back dirty buffers to memory using functional writes.
Definition: cpu.cc:237
gem5::ThreadContext::Halted
@ Halted
Permanently shut down.
Definition: thread_context.hh:121
gem5::BaseCPU::startup
void startup() override
startup() is the final initialization call before simulation.
Definition: base.cc:315
gem5::BaseCPU::unserialize
void unserialize(CheckpointIn &cp) override
Reconstruct the state of this object from a checkpoint.
Definition: base.cc:651
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::BaseCPU::init
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: base.cc:272
cpu.hh
gem5::MinorCPU
MinorCPU is an in-order CPU model with four fixed pipeline stages:
Definition: cpu.hh:85
gem5::BaseCPU::system
System * system
Definition: base.hh:376
gem5::EventManager::schedule
void schedule(Event &event, Tick when)
Definition: eventq.hh:1019
gem5::MinorCPU::drainResume
void drainResume() override
Resume execution after a successful drain.
Definition: cpu.cc:207
gem5::MinorCPU::unserialize
void unserialize(CheckpointIn &cp) override
Reconstruct the state of this object from a checkpoint.
Definition: cpu.cc:147
gem5::minor::MinorDynInst::init
static void init()
Initialise the class.
Definition: dyn_inst.cc:83
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
gem5::BaseCPU::schedulePowerGatingEvent
void schedulePowerGatingEvent()
Definition: base.cc:460
gem5::SimpleThread
The SimpleThread object provides a combination of the ThreadState object and the ThreadContext interf...
Definition: simple_thread.hh:94
gem5::MinorCPU::totalInsts
Counter totalInsts() const override
Simple inst count interface from BaseCPU.
Definition: cpu.cc:324
gem5::MinorCPU::wakeupOnEvent
void wakeupOnEvent(unsigned int stage_id)
Interface for stages to signal that they have become active after a callback or eventq event where th...
Definition: cpu.cc:302
gem5::MinorCPU::getDataPort
Port & getDataPort() override
Return a reference to the data port.
Definition: cpu.cc:318
gem5::MinorCPU::threads
std::vector< minor::MinorThread * > threads
These are thread state-representing objects for this CPU.
Definition: cpu.hh:101
gem5::Cycles
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:78
gem5::MinorCPU::stats
minor::MinorStats stats
Processor-specific statistics.
Definition: cpu.hh:140
gem5::BaseCPU::numThreads
ThreadID numThreads
Number of threads we're actually simulating (<= SMT_MAX_THREADS).
Definition: base.hh:368
gem5::BaseCPU::regStats
void regStats() override
Callback to set stat parameters.
Definition: base.cc:386
gem5::BaseCPU::deschedulePowerGatingEvent
void deschedulePowerGatingEvent()
Definition: base.cc:452
gem5::DrainState
DrainState
Object drain/handover states.
Definition: drain.hh:74
gem5::BaseCPU::suspendContext
virtual void suspendContext(ThreadID thread_num)
Notify the CPU that the indicated context is now suspended.
Definition: base.cc:502
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::MinorCPU::MinorCPU
MinorCPU(const MinorCPUParams &params)
Definition: cpu.cc:50
gem5::MinorCPU::regStats
void regStats() override
Stats interface from SimObject (by way of BaseCPU)
Definition: cpu.cc:121
gem5::SimObject::params
const Params & params() const
Definition: sim_object.hh:176
gem5::ThreadContext::Suspended
@ Suspended
Temporarily inactive.
Definition: thread_context.hh:112
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
pipeline.hh
gem5::MinorCPU::totalOps
Counter totalOps() const override
Definition: cpu.cc:335
gem5::BaseCPU::serialize
void serialize(CheckpointOut &cp) const override
Serialize this object to the given output stream.
Definition: base.cc:630
gem5::MinorCPU::init
void init() override
Starting, waking and initialisation.
Definition: cpu.cc:100
gem5::minor::Pipeline::CPUStageId
@ CPUStageId
Definition: pipeline.hh:102
gem5::System::getMemoryMode
enums::MemoryMode getMemoryMode() const
Get the memory mode of the system.
Definition: system.hh:299
gem5::BaseCPU
Definition: base.hh:107
gem5::ThreadContext::initMemProxies
virtual void initMemProxies(ThreadContext *tc)=0
Initialise the physical and virtual port proxies and tie them to the data port of the CPU.
gem5::MinorCPU::suspendContext
void suspendContext(ThreadID thread_id) override
Notify the CPU that the indicated context is now suspended.
Definition: cpu.cc:292
gem5::MinorCPU::serialize
void serialize(CheckpointOut &cp) const override
Serialize pipeline data.
Definition: cpu.cc:140
gem5::minor::Pipeline
The constructed pipeline.
Definition: pipeline.hh:73
gem5::MinorCPU::wakeup
void wakeup(ThreadID tid) override
Definition: cpu.cc:154
gem5::DrainState::Drained
@ Drained
Buffers drained, ready for serialization/handover.
gem5::System::isTimingMode
bool isTimingMode() const
Is the system in timing mode?
Definition: system.hh:276
gem5::BaseCPU::getContext
virtual ThreadContext * getContext(int tn)
Given a thread num get tho thread context for it.
Definition: base.hh:290
gem5::MinorCPU::unserializeThread
void unserializeThread(CheckpointIn &cp, ThreadID tid) override
Unserialize one thread.
Definition: cpu.cc:134
gem5::MinorCPU::~MinorCPU
~MinorCPU()
Definition: cpu.cc:87
gem5::MinorCPU::signalDrainDone
void signalDrainDone()
Signal from Pipeline that MinorCPU should signal that a drain is complete and set its drainState.
Definition: cpu.cc:200
gem5::MinorCPU::drain
DrainState drain() override
Drain interface.
Definition: cpu.cc:176
gem5::SimpleThread::setStatus
void setStatus(Status newStatus) override
Definition: simple_thread.hh:232
gem5::Clocked::clockEdge
Tick clockEdge(Cycles cycles=Cycles(0)) const
Determine the tick when a cycle begins, by default the current one, but the argument also enables the...
Definition: clocked_object.hh:177
gem5::MinorCPU::activateContext
void activateContext(ThreadID thread_id) override
Thread activation interface from BaseCPU.
Definition: cpu.cc:263
gem5::EventFunctionWrapper
Definition: eventq.hh:1115
gem5::Drainable::signalDrainDone
void signalDrainDone() const
Signal that an object is drained.
Definition: drain.hh:305
gem5::FullSystem
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:223
gem5::SimpleThread::getTC
ThreadContext * getTC()
Returns the pointer to this SimpleThread's ThreadContext.
Definition: simple_thread.hh:169
gem5::ActivityRecorder::reset
void reset()
Clears the time buffer and the activity count.
Definition: activity.cc:125
gem5::ActivityRecorder::activateStage
void activateStage(const int idx)
Marks a stage as active.
Definition: activity.cc:91
gem5::BaseCPU::threadContexts
std::vector< ThreadContext * > threadContexts
Definition: base.hh:262
gem5::BaseCPU::takeOverFrom
virtual void takeOverFrom(BaseCPU *cpu)
Load the state of a CPU from the previous CPU object, invoked on all new CPUs that are about to be sw...
Definition: base.cc:554
gem5::MinorCPU::serializeThread
void serializeThread(CheckpointOut &cp, ThreadID tid) const override
Serialize a single thread.
Definition: cpu.cc:128
gem5::BaseCPU::activateContext
virtual void activateContext(ThreadID thread_num)
Notify the CPU that the indicated context is now active.
Definition: base.cc:488
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
gem5::minor::MinorThread
SimpleThread MinorThread
Minor will use the SimpleThread state for now.
Definition: cpu.hh:65
gem5::statistics::Counter
double Counter
All counters are of 64-bit values.
Definition: types.hh:47
gem5::MinorCPU::switchOut
void switchOut() override
Switching interface from BaseCPU.
Definition: cpu.cc:243
gem5::BaseCPU::switchOut
virtual void switchOut()
Prepare for another CPU to take over execution.
Definition: base.cc:540
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::MinorCPU::activityRecorder
minor::MinorActivityRecorder * activityRecorder
Activity recording for pipeline.
Definition: cpu.hh:96
gem5::MinorCPU::getInstPort
Port & getInstPort() override
Return a reference to the instruction port.
Definition: cpu.cc:312
pipeline
Definition: pipeline.h:43
gem5::MinorCPU::startup
void startup() override
startup() is the final initialization call before simulation.
Definition: cpu.cc:165
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::MinorCPU::fetchEventWrapper
EventFunctionWrapper * fetchEventWrapper
Definition: cpu.hh:206
fetch1.hh
gem5::DrainState::Draining
@ Draining
Draining buffers pending serialization/handover.
gem5::ThreadID
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:242
gem5::ArmISA::status
Bitfield< 5, 0 > status
Definition: misc_types.hh:422

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