gem5 v24.0.0.0
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cpu.cc
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1/*
2 * Copyright (c) 2012-2014, 2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 */
37
38#include "cpu/minor/cpu.hh"
39
40#include "cpu/minor/dyn_inst.hh"
41#include "cpu/minor/fetch1.hh"
42#include "cpu/minor/pipeline.hh"
43#include "debug/Drain.hh"
44#include "debug/MinorCPU.hh"
45#include "debug/Quiesce.hh"
46
47namespace gem5
48{
49
50MinorCPU::MinorCPU(const BaseMinorCPUParams &params) :
51 BaseCPU(params),
52 threadPolicy(params.threadPolicy),
53 stats(this)
54{
55 /* This is only written for one thread at the moment */
56 minor::MinorThread *thread;
57
58 for (ThreadID i = 0; i < numThreads; i++) {
59 if (FullSystem) {
60 thread = new minor::MinorThread(this, i, params.system,
61 params.mmu, params.isa[i], params.decoder[i]);
63 } else {
64 thread = new minor::MinorThread(this, i, params.system,
65 params.workload[i], params.mmu,
66 params.isa[i], params.decoder[i]);
67 }
68
69 threads.push_back(thread);
70 ThreadContext *tc = thread->getTC();
71 threadContexts.push_back(tc);
72 }
73
74
75 if (params.checker) {
76 fatal("The Minor model doesn't support checking (yet)\n");
77 }
78
79 pipeline = new minor::Pipeline(*this, params);
80 activityRecorder = pipeline->getActivityRecorder();
81
82 fetchEventWrapper = NULL;
83}
84
86{
87 delete pipeline;
88
89 if (fetchEventWrapper != NULL)
90 delete fetchEventWrapper;
91
92 for (ThreadID thread_id = 0; thread_id < threads.size(); thread_id++) {
93 delete threads[thread_id];
94 }
95}
96
97void
99{
101
102 if (!params().switched_out && system->getMemoryMode() != enums::timing) {
103 fatal("The Minor CPU requires the memory system to be in "
104 "'timing' mode.\n");
105 }
106}
107
109void
111{
113 pipeline->regStats();
114}
115
116void
118{
119 threads[thread_id]->serialize(cp);
120}
121
122void
124{
125 threads[thread_id]->unserialize(cp);
126}
127
128void
130{
131 pipeline->serialize(cp);
133}
134
135void
137{
138 pipeline->unserialize(cp);
140}
141
142void
144{
145 DPRINTF(Drain, "[tid:%d] MinorCPU wakeup\n", tid);
146 assert(tid < numThreads);
147
148 if (threads[tid]->status() == ThreadContext::Suspended) {
149 threads[tid]->activate();
150 }
151}
152
153void
155{
156 DPRINTF(MinorCPU, "MinorCPU startup\n");
157
159
160 for (ThreadID tid = 0; tid < numThreads; tid++)
161 pipeline->wakeupFetch(tid);
162}
163
166{
167 // Deschedule any power gating event (if any)
169
170 if (switchedOut()) {
171 DPRINTF(Drain, "Minor CPU switched out, draining not needed.\n");
172 return DrainState::Drained;
173 }
174
175 DPRINTF(Drain, "MinorCPU drain\n");
176
177 /* Need to suspend all threads and wait for Execute to idle.
178 * Tell Fetch1 not to fetch */
179 if (pipeline->drain()) {
180 DPRINTF(Drain, "MinorCPU drained\n");
181 return DrainState::Drained;
182 } else {
183 DPRINTF(Drain, "MinorCPU not finished draining\n");
185 }
186}
187
188void
190{
191 DPRINTF(Drain, "MinorCPU drain done\n");
193}
194
195void
197{
198 /* When taking over from another cpu make sure lastStopped
199 * is reset since it might have not been defined previously
200 * and might lead to a stats corruption */
201 pipeline->resetLastStopped();
202
203 if (switchedOut()) {
204 DPRINTF(Drain, "drainResume while switched out. Ignoring\n");
205 return;
206 }
207
208 DPRINTF(Drain, "MinorCPU drainResume\n");
209
210 if (!system->isTimingMode()) {
211 fatal("The Minor CPU requires the memory system to be in "
212 "'timing' mode.\n");
213 }
214
215 for (ThreadID tid = 0; tid < numThreads; tid++){
216 wakeup(tid);
217 }
218
219 pipeline->drainResume();
220
221 // Reschedule any power gating event (if any)
223}
224
225void
227{
228 DPRINTF(Drain, "MinorCPU memWriteback\n");
229}
230
231void
233{
234 DPRINTF(MinorCPU, "MinorCPU switchOut\n");
235
236 assert(!switchedOut());
238
239 /* Check that the CPU is drained? */
241}
242
243void
245{
246 DPRINTF(MinorCPU, "MinorCPU takeOverFrom\n");
247
248 BaseCPU::takeOverFrom(old_cpu);
249}
250
251void
253{
254 DPRINTF(MinorCPU, "ActivateContext thread: %d\n", thread_id);
255
256 /* Do some cycle accounting. lastStopped is reset to stop the
257 * wakeup call on the pipeline from adding the quiesce period
258 * to BaseCPU::numCycles */
259 stats.quiesceCycles += pipeline->cyclesSinceLastStopped();
260 pipeline->resetLastStopped();
261
262 /* Wake up the thread, wakeup the pipeline tick */
263 threads[thread_id]->activate();
265
266 if (!threads[thread_id]->getUseForClone())//the thread is not cloned
267 {
268 pipeline->wakeupFetch(thread_id);
269 } else { //the thread from clone
270 if (fetchEventWrapper != NULL)
271 delete fetchEventWrapper;
272 fetchEventWrapper = new EventFunctionWrapper([this, thread_id]
273 { pipeline->wakeupFetch(thread_id); }, "wakeupFetch");
275 }
276
277 BaseCPU::activateContext(thread_id);
278}
279
280void
282{
283 DPRINTF(MinorCPU, "SuspendContext %d\n", thread_id);
284
285 threads[thread_id]->suspend();
286
287 BaseCPU::suspendContext(thread_id);
288}
289
290void
291MinorCPU::wakeupOnEvent(unsigned int stage_id)
292{
293 DPRINTF(Quiesce, "Event wakeup from stage %d\n", stage_id);
294
295 /* Mark that some activity has taken place and start the pipeline */
297 pipeline->start();
298}
299
300Port &
302{
303 return pipeline->getInstPort();
304}
305
306Port &
308{
309 return pipeline->getDataPort();
310}
311
314{
315 Counter ret = 0;
316
317 for (auto i = threads.begin(); i != threads.end(); i ++)
318 ret += (*i)->numInst;
319
320 return ret;
321}
322
325{
326 Counter ret = 0;
327
328 for (auto i = threads.begin(); i != threads.end(); i ++)
329 ret += (*i)->numOp;
330
331 return ret;
332}
333
334} // namespace gem5
#define DPRINTF(x,...)
Definition trace.hh:210
void reset()
Clears the time buffer and the activity count.
Definition activity.cc:125
void activateStage(const int idx)
Marks a stage as active.
Definition activity.cc:91
void regStats() override
Callback to set stat parameters.
Definition base.cc:431
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition base.cc:310
System * system
Definition base.hh:392
void unserialize(CheckpointIn &cp) override
Reconstruct the state of this object from a checkpoint.
Definition base.cc:725
void serialize(CheckpointOut &cp) const override
Serialize this object to the given output stream.
Definition base.cc:704
void schedulePowerGatingEvent()
Definition base.cc:502
virtual void suspendContext(ThreadID thread_num)
Notify the CPU that the indicated context is now suspended.
Definition base.cc:550
ThreadID numThreads
Number of threads we're actually simulating (<= SMT_MAX_THREADS).
Definition base.hh:390
void deschedulePowerGatingEvent()
Definition base.cc:494
void startup() override
startup() is the final initialization call before simulation.
Definition base.cc:349
virtual void switchOut()
Prepare for another CPU to take over execution.
Definition base.cc:588
virtual void takeOverFrom(BaseCPU *cpu)
Load the state of a CPU from the previous CPU object, invoked on all new CPUs that are about to be sw...
Definition base.cc:602
std::vector< ThreadContext * > threadContexts
Definition base.hh:260
bool switchedOut() const
Determine if the CPU is switched out.
Definition base.hh:373
virtual void activateContext(ThreadID thread_num)
Notify the CPU that the indicated context is now active.
Definition base.cc:530
Tick clockEdge(Cycles cycles=Cycles(0)) const
Determine the tick when a cycle begins, by default the current one, but the argument also enables the...
Cycles is a wrapper class for representing cycle counts, i.e.
Definition types.hh:79
MinorCPU is an in-order CPU model with four fixed pipeline stages:
Definition cpu.hh:85
Port & getInstPort() override
Return a reference to the instruction port.
Definition cpu.cc:301
MinorCPU(const BaseMinorCPUParams &params)
Definition cpu.cc:50
void serialize(CheckpointOut &cp) const override
Serialize pipeline data.
Definition cpu.cc:129
void wakeup(ThreadID tid) override
Definition cpu.cc:143
void serializeThread(CheckpointOut &cp, ThreadID tid) const override
Serialize a single thread.
Definition cpu.cc:117
DrainState drain() override
Drain interface.
Definition cpu.cc:165
Counter totalInsts() const override
Simple inst count interface from BaseCPU.
Definition cpu.cc:313
void unserialize(CheckpointIn &cp) override
Reconstruct the state of this object from a checkpoint.
Definition cpu.cc:136
minor::Pipeline * pipeline
pipeline is a container for the clockable pipeline stage objects.
Definition cpu.hh:89
minor::MinorStats stats
Processor-specific statistics.
Definition cpu.hh:139
minor::MinorActivityRecorder * activityRecorder
Activity recording for pipeline.
Definition cpu.hh:95
void signalDrainDone()
Signal from Pipeline that MinorCPU should signal that a drain is complete and set its drainState.
Definition cpu.cc:189
void init() override
Starting, waking and initialisation.
Definition cpu.cc:98
void switchOut() override
Switching interface from BaseCPU.
Definition cpu.cc:232
void wakeupOnEvent(unsigned int stage_id)
Interface for stages to signal that they have become active after a callback or eventq event where th...
Definition cpu.cc:291
void memWriteback() override
Write back dirty buffers to memory using functional writes.
Definition cpu.cc:226
Counter totalOps() const override
Definition cpu.cc:324
void regStats() override
Stats interface from SimObject (by way of BaseCPU)
Definition cpu.cc:110
void activateContext(ThreadID thread_id) override
Thread activation interface from BaseCPU.
Definition cpu.cc:252
void unserializeThread(CheckpointIn &cp, ThreadID tid) override
Unserialize one thread.
Definition cpu.cc:123
void takeOverFrom(BaseCPU *old_cpu) override
Load the state of a CPU from the previous CPU object, invoked on all new CPUs that are about to be sw...
Definition cpu.cc:244
void startup() override
startup() is the final initialization call before simulation.
Definition cpu.cc:154
Port & getDataPort() override
Return a reference to the data port.
Definition cpu.cc:307
std::vector< minor::MinorThread * > threads
These are thread state-representing objects for this CPU.
Definition cpu.hh:100
void drainResume() override
Resume execution after a successful drain.
Definition cpu.cc:196
void suspendContext(ThreadID thread_id) override
Notify the CPU that the indicated context is now suspended.
Definition cpu.cc:281
EventFunctionWrapper * fetchEventWrapper
Definition cpu.hh:205
Ports are used to interface objects to each other.
Definition port.hh:62
The SimpleThread object provides a combination of the ThreadState object and the ThreadContext interf...
void setStatus(Status newStatus) override
ThreadContext * getTC()
Returns the pointer to this SimpleThread's ThreadContext.
bool isTimingMode() const
Is the system in timing mode?
Definition system.hh:270
enums::MemoryMode getMemoryMode() const
Get the memory mode of the system.
Definition system.hh:293
ThreadContext is the external interface to all thread state for anything outside of the CPU.
@ Halted
Permanently shut down.
@ Suspended
Temporarily inactive.
The constructed pipeline.
Definition pipeline.hh:73
Top level definition of the Minor in-order CPU model.
Fetch1 is responsible for fetching "lines" from memory and passing them to Fetch2.
void signalDrainDone() const
Signal that an object is drained.
Definition drain.hh:305
DrainState
Object drain/handover states.
Definition drain.hh:75
@ Draining
Draining buffers pending serialization/handover.
@ Drained
Buffers drained, ready for serialization/handover.
void schedule(Event &event, Tick when)
Definition eventq.hh:1012
#define fatal(...)
This implements a cprintf based fatal() function.
Definition logging.hh:200
const Params & params() const
The dynamic instruction and instruction/line id (sequence numbers) definition for Minor.
Bitfield< 7 > i
Definition misc_types.hh:67
Bitfield< 5, 0 > status
SimpleThread MinorThread
Minor will use the SimpleThread state for now.
Definition cpu.hh:67
double Counter
All counters are of 64-bit values.
Definition types.hh:46
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
int16_t ThreadID
Thread index/ID type.
Definition types.hh:235
std::ostream CheckpointOut
Definition serialize.hh:66
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition root.cc:220
The constructed pipeline.
statistics::Scalar quiesceCycles
Number of cycles in quiescent state.
Definition stats.hh:63

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