43#include "debug/Drain.hh"
44#include "debug/MinorCPU.hh"
45#include "debug/Quiesce.hh"
52 threadPolicy(params.threadPolicy),
76 fatal(
"The Minor model doesn't support checking (yet)\n");
103 fatal(
"The Minor CPU requires the memory system to be in "
119 threads[thread_id]->serialize(cp);
125 threads[thread_id]->unserialize(cp);
145 DPRINTF(Drain,
"[tid:%d] MinorCPU wakeup\n", tid);
171 DPRINTF(Drain,
"Minor CPU switched out, draining not needed.\n");
175 DPRINTF(Drain,
"MinorCPU drain\n");
180 DPRINTF(Drain,
"MinorCPU drained\n");
183 DPRINTF(Drain,
"MinorCPU not finished draining\n");
191 DPRINTF(Drain,
"MinorCPU drain done\n");
204 DPRINTF(Drain,
"drainResume while switched out. Ignoring\n");
208 DPRINTF(Drain,
"MinorCPU drainResume\n");
211 fatal(
"The Minor CPU requires the memory system to be in "
228 DPRINTF(Drain,
"MinorCPU memWriteback\n");
263 threads[thread_id]->activate();
266 if (!
threads[thread_id]->getUseForClone())
273 {
pipeline->wakeupFetch(thread_id); },
"wakeupFetch");
293 DPRINTF(Quiesce,
"Event wakeup from stage %d\n", stage_id);
318 ret += (*i)->numInst;
void reset()
Clears the time buffer and the activity count.
void activateStage(const int idx)
Marks a stage as active.
void regStats() override
Callback to set stat parameters.
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
void unserialize(CheckpointIn &cp) override
Reconstruct the state of this object from a checkpoint.
void serialize(CheckpointOut &cp) const override
Serialize this object to the given output stream.
void schedulePowerGatingEvent()
virtual void suspendContext(ThreadID thread_num)
Notify the CPU that the indicated context is now suspended.
ThreadID numThreads
Number of threads we're actually simulating (<= SMT_MAX_THREADS).
void deschedulePowerGatingEvent()
void startup() override
startup() is the final initialization call before simulation.
virtual void switchOut()
Prepare for another CPU to take over execution.
virtual void takeOverFrom(BaseCPU *cpu)
Load the state of a CPU from the previous CPU object, invoked on all new CPUs that are about to be sw...
std::vector< ThreadContext * > threadContexts
bool switchedOut() const
Determine if the CPU is switched out.
virtual void activateContext(ThreadID thread_num)
Notify the CPU that the indicated context is now active.
Tick clockEdge(Cycles cycles=Cycles(0)) const
Determine the tick when a cycle begins, by default the current one, but the argument also enables the...
Cycles is a wrapper class for representing cycle counts, i.e.
MinorCPU is an in-order CPU model with four fixed pipeline stages:
Port & getInstPort() override
Return a reference to the instruction port.
MinorCPU(const BaseMinorCPUParams ¶ms)
void serialize(CheckpointOut &cp) const override
Serialize pipeline data.
void wakeup(ThreadID tid) override
void serializeThread(CheckpointOut &cp, ThreadID tid) const override
Serialize a single thread.
DrainState drain() override
Drain interface.
Counter totalInsts() const override
Simple inst count interface from BaseCPU.
void unserialize(CheckpointIn &cp) override
Reconstruct the state of this object from a checkpoint.
minor::Pipeline * pipeline
pipeline is a container for the clockable pipeline stage objects.
minor::MinorStats stats
Processor-specific statistics.
minor::MinorActivityRecorder * activityRecorder
Activity recording for pipeline.
void signalDrainDone()
Signal from Pipeline that MinorCPU should signal that a drain is complete and set its drainState.
void init() override
Starting, waking and initialisation.
void switchOut() override
Switching interface from BaseCPU.
void wakeupOnEvent(unsigned int stage_id)
Interface for stages to signal that they have become active after a callback or eventq event where th...
void memWriteback() override
Write back dirty buffers to memory using functional writes.
Counter totalOps() const override
void regStats() override
Stats interface from SimObject (by way of BaseCPU)
void activateContext(ThreadID thread_id) override
Thread activation interface from BaseCPU.
void unserializeThread(CheckpointIn &cp, ThreadID tid) override
Unserialize one thread.
void takeOverFrom(BaseCPU *old_cpu) override
Load the state of a CPU from the previous CPU object, invoked on all new CPUs that are about to be sw...
void startup() override
startup() is the final initialization call before simulation.
Port & getDataPort() override
Return a reference to the data port.
std::vector< minor::MinorThread * > threads
These are thread state-representing objects for this CPU.
void drainResume() override
Resume execution after a successful drain.
void suspendContext(ThreadID thread_id) override
Notify the CPU that the indicated context is now suspended.
EventFunctionWrapper * fetchEventWrapper
Ports are used to interface objects to each other.
The SimpleThread object provides a combination of the ThreadState object and the ThreadContext interf...
void setStatus(Status newStatus) override
ThreadContext * getTC()
Returns the pointer to this SimpleThread's ThreadContext.
bool isTimingMode() const
Is the system in timing mode?
enums::MemoryMode getMemoryMode() const
Get the memory mode of the system.
ThreadContext is the external interface to all thread state for anything outside of the CPU.
@ Halted
Permanently shut down.
@ Suspended
Temporarily inactive.
The constructed pipeline.
Top level definition of the Minor in-order CPU model.
Fetch1 is responsible for fetching "lines" from memory and passing them to Fetch2.
void signalDrainDone() const
Signal that an object is drained.
DrainState
Object drain/handover states.
@ Draining
Draining buffers pending serialization/handover.
@ Drained
Buffers drained, ready for serialization/handover.
void schedule(Event &event, Tick when)
#define fatal(...)
This implements a cprintf based fatal() function.
const Params & params() const
The dynamic instruction and instruction/line id (sequence numbers) definition for Minor.
SimpleThread MinorThread
Minor will use the SimpleThread state for now.
double Counter
All counters are of 64-bit values.
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
int16_t ThreadID
Thread index/ID type.
std::ostream CheckpointOut
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
The constructed pipeline.
statistics::Scalar quiesceCycles
Number of cycles in quiescent state.