gem5  v22.0.0.1
cpu.cc
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37 
38 #include "cpu/minor/cpu.hh"
39 
40 #include "cpu/minor/dyn_inst.hh"
41 #include "cpu/minor/fetch1.hh"
42 #include "cpu/minor/pipeline.hh"
43 #include "debug/Drain.hh"
44 #include "debug/MinorCPU.hh"
45 #include "debug/Quiesce.hh"
46 
47 namespace gem5
48 {
49 
50 MinorCPU::MinorCPU(const BaseMinorCPUParams &params) :
51  BaseCPU(params),
52  threadPolicy(params.threadPolicy),
53  stats(this)
54 {
55  /* This is only written for one thread at the moment */
56  minor::MinorThread *thread;
57 
58  for (ThreadID i = 0; i < numThreads; i++) {
59  if (FullSystem) {
60  thread = new minor::MinorThread(this, i, params.system,
61  params.mmu, params.isa[i], params.decoder[i]);
63  } else {
64  thread = new minor::MinorThread(this, i, params.system,
65  params.workload[i], params.mmu,
66  params.isa[i], params.decoder[i]);
67  }
68 
69  threads.push_back(thread);
70  ThreadContext *tc = thread->getTC();
71  threadContexts.push_back(tc);
72  }
73 
74 
75  if (params.checker) {
76  fatal("The Minor model doesn't support checking (yet)\n");
77  }
78 
79  pipeline = new minor::Pipeline(*this, params);
80  activityRecorder = pipeline->getActivityRecorder();
81 
82  fetchEventWrapper = NULL;
83 }
84 
86 {
87  delete pipeline;
88 
89  if (fetchEventWrapper != NULL)
90  delete fetchEventWrapper;
91 
92  for (ThreadID thread_id = 0; thread_id < threads.size(); thread_id++) {
93  delete threads[thread_id];
94  }
95 }
96 
97 void
99 {
100  BaseCPU::init();
101 
102  if (!params().switched_out && system->getMemoryMode() != enums::timing) {
103  fatal("The Minor CPU requires the memory system to be in "
104  "'timing' mode.\n");
105  }
106 }
107 
109 void
111 {
112  BaseCPU::regStats();
113  pipeline->regStats();
114 }
115 
116 void
118 {
119  threads[thread_id]->serialize(cp);
120 }
121 
122 void
124 {
125  threads[thread_id]->unserialize(cp);
126 }
127 
128 void
130 {
131  pipeline->serialize(cp);
132  BaseCPU::serialize(cp);
133 }
134 
135 void
137 {
138  pipeline->unserialize(cp);
140 }
141 
142 void
144 {
145  DPRINTF(Drain, "[tid:%d] MinorCPU wakeup\n", tid);
146  assert(tid < numThreads);
147 
148  if (threads[tid]->status() == ThreadContext::Suspended) {
149  threads[tid]->activate();
150  }
151 }
152 
153 void
155 {
156  DPRINTF(MinorCPU, "MinorCPU startup\n");
157 
158  BaseCPU::startup();
159 
160  for (ThreadID tid = 0; tid < numThreads; tid++)
161  pipeline->wakeupFetch(tid);
162 }
163 
166 {
167  // Deschedule any power gating event (if any)
168  deschedulePowerGatingEvent();
169 
170  if (switchedOut()) {
171  DPRINTF(Drain, "Minor CPU switched out, draining not needed.\n");
172  return DrainState::Drained;
173  }
174 
175  DPRINTF(Drain, "MinorCPU drain\n");
176 
177  /* Need to suspend all threads and wait for Execute to idle.
178  * Tell Fetch1 not to fetch */
179  if (pipeline->drain()) {
180  DPRINTF(Drain, "MinorCPU drained\n");
181  return DrainState::Drained;
182  } else {
183  DPRINTF(Drain, "MinorCPU not finished draining\n");
184  return DrainState::Draining;
185  }
186 }
187 
188 void
190 {
191  DPRINTF(Drain, "MinorCPU drain done\n");
193 }
194 
195 void
197 {
198  /* When taking over from another cpu make sure lastStopped
199  * is reset since it might have not been defined previously
200  * and might lead to a stats corruption */
201  pipeline->resetLastStopped();
202 
203  if (switchedOut()) {
204  DPRINTF(Drain, "drainResume while switched out. Ignoring\n");
205  return;
206  }
207 
208  DPRINTF(Drain, "MinorCPU drainResume\n");
209 
210  if (!system->isTimingMode()) {
211  fatal("The Minor CPU requires the memory system to be in "
212  "'timing' mode.\n");
213  }
214 
215  for (ThreadID tid = 0; tid < numThreads; tid++){
216  wakeup(tid);
217  }
218 
219  pipeline->drainResume();
220 
221  // Reschedule any power gating event (if any)
222  schedulePowerGatingEvent();
223 }
224 
225 void
227 {
228  DPRINTF(Drain, "MinorCPU memWriteback\n");
229 }
230 
231 void
233 {
234  DPRINTF(MinorCPU, "MinorCPU switchOut\n");
235 
236  assert(!switchedOut());
237  BaseCPU::switchOut();
238 
239  /* Check that the CPU is drained? */
241 }
242 
243 void
244 MinorCPU::takeOverFrom(BaseCPU *old_cpu)
245 {
246  DPRINTF(MinorCPU, "MinorCPU takeOverFrom\n");
247 
248  BaseCPU::takeOverFrom(old_cpu);
249 }
250 
251 void
253 {
254  DPRINTF(MinorCPU, "ActivateContext thread: %d\n", thread_id);
255 
256  /* Do some cycle accounting. lastStopped is reset to stop the
257  * wakeup call on the pipeline from adding the quiesce period
258  * to BaseCPU::numCycles */
259  stats.quiesceCycles += pipeline->cyclesSinceLastStopped();
260  pipeline->resetLastStopped();
261 
262  /* Wake up the thread, wakeup the pipeline tick */
263  threads[thread_id]->activate();
265 
266  if (!threads[thread_id]->getUseForClone())//the thread is not cloned
267  {
268  pipeline->wakeupFetch(thread_id);
269  } else { //the thread from clone
270  if (fetchEventWrapper != NULL)
271  delete fetchEventWrapper;
272  fetchEventWrapper = new EventFunctionWrapper([this, thread_id]
273  { pipeline->wakeupFetch(thread_id); }, "wakeupFetch");
274  schedule(*fetchEventWrapper, clockEdge(Cycles(0)));
275  }
276 
277  BaseCPU::activateContext(thread_id);
278 }
279 
280 void
282 {
283  DPRINTF(MinorCPU, "SuspendContext %d\n", thread_id);
284 
285  threads[thread_id]->suspend();
286 
287  BaseCPU::suspendContext(thread_id);
288 }
289 
290 void
291 MinorCPU::wakeupOnEvent(unsigned int stage_id)
292 {
293  DPRINTF(Quiesce, "Event wakeup from stage %d\n", stage_id);
294 
295  /* Mark that some activity has taken place and start the pipeline */
296  activityRecorder->activateStage(stage_id);
297  pipeline->start();
298 }
299 
300 Port &
302 {
303  return pipeline->getInstPort();
304 }
305 
306 Port &
308 {
309  return pipeline->getDataPort();
310 }
311 
312 Counter
314 {
315  Counter ret = 0;
316 
317  for (auto i = threads.begin(); i != threads.end(); i ++)
318  ret += (*i)->numInst;
319 
320  return ret;
321 }
322 
323 Counter
325 {
326  Counter ret = 0;
327 
328  for (auto i = threads.begin(); i != threads.end(); i ++)
329  ret += (*i)->numOp;
330 
331  return ret;
332 }
333 
334 } // namespace gem5
gem5::minor::MinorStats::quiesceCycles
statistics::Scalar quiesceCycles
Number of cycles in quiescent state.
Definition: stats.hh:76
fatal
#define fatal(...)
This implements a cprintf based fatal() function.
Definition: logging.hh:190
dyn_inst.hh
gem5::MinorCPU::takeOverFrom
void takeOverFrom(BaseCPU *old_cpu) override
Definition: cpu.cc:244
gem5::unserialize
void unserialize(ThreadContext &tc, CheckpointIn &cp)
Definition: thread_context.cc:264
gem5::MinorCPU::pipeline
minor::Pipeline * pipeline
pipeline is a container for the clockable pipeline stage objects.
Definition: cpu.hh:90
gem5::MinorCPU::memWriteback
void memWriteback() override
Definition: cpu.cc:226
gem5::ThreadContext::Halted
@ Halted
Permanently shut down.
Definition: thread_context.hh:122
gem5::CheckpointIn
Definition: serialize.hh:68
cpu.hh
gem5::MinorCPU
MinorCPU is an in-order CPU model with four fixed pipeline stages:
Definition: cpu.hh:85
gem5::X86ISA::system
Bitfield< 15 > system
Definition: misc.hh:997
gem5::MinorCPU::drainResume
void drainResume() override
Definition: cpu.cc:196
gem5::MinorCPU::unserialize
void unserialize(CheckpointIn &cp) override
Definition: cpu.cc:136
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:67
gem5::SimpleThread
The SimpleThread object provides a combination of the ThreadState object and the ThreadContext interf...
Definition: simple_thread.hh:95
gem5::MinorCPU::totalInsts
Counter totalInsts() const override
Simple inst count interface from BaseCPU.
Definition: cpu.cc:313
gem5::MinorCPU::wakeupOnEvent
void wakeupOnEvent(unsigned int stage_id)
Interface for stages to signal that they have become active after a callback or eventq event where th...
Definition: cpu.cc:291
gem5::MinorCPU::getDataPort
Port & getDataPort() override
Return a reference to the data port.
Definition: cpu.cc:307
gem5::takeOverFrom
void takeOverFrom(ThreadContext &ntc, ThreadContext &otc)
Copy state between thread contexts in preparation for CPU handover.
Definition: thread_context.cc:312
gem5::MinorCPU::threads
std::vector< minor::MinorThread * > threads
These are thread state-representing objects for this CPU.
Definition: cpu.hh:101
gem5::Cycles
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:78
gem5::MinorCPU::stats
minor::MinorStats stats
Processor-specific statistics.
Definition: cpu.hh:140
gem5::DrainState
DrainState
Object drain/handover states.
Definition: drain.hh:74
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::MinorCPU::MinorCPU
MinorCPU(const BaseMinorCPUParams &params)
Definition: cpu.cc:50
gem5::MinorCPU::regStats
void regStats() override
Stats interface from SimObject (by way of BaseCPU)
Definition: cpu.cc:110
gem5::ThreadContext::Suspended
@ Suspended
Temporarily inactive.
Definition: thread_context.hh:113
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
pipeline.hh
gem5::MinorCPU::totalOps
Counter totalOps() const override
Definition: cpu.cc:324
gem5::MinorCPU::init
void init() override
Starting, waking and initialisation.
Definition: cpu.cc:98
gem5::minor::Pipeline::CPUStageId
@ CPUStageId
Definition: pipeline.hh:102
gem5::MinorCPU::suspendContext
void suspendContext(ThreadID thread_id) override
Definition: cpu.cc:281
gem5::MinorCPU::serialize
void serialize(CheckpointOut &cp) const override
Serialize pipeline data.
Definition: cpu.cc:129
gem5::minor::Pipeline
The constructed pipeline.
Definition: pipeline.hh:73
gem5::MinorCPU::wakeup
void wakeup(ThreadID tid) override
Definition: cpu.cc:143
gem5::DrainState::Drained
@ Drained
Buffers drained, ready for serialization/handover.
gem5::serialize
void serialize(const ThreadContext &tc, CheckpointOut &cp)
Thread context serialization helpers.
Definition: thread_context.cc:215
gem5::MinorCPU::unserializeThread
void unserializeThread(CheckpointIn &cp, ThreadID tid) override
Definition: cpu.cc:123
gem5::MinorCPU::~MinorCPU
~MinorCPU()
Definition: cpu.cc:85
gem5::MinorCPU::signalDrainDone
void signalDrainDone()
Signal from Pipeline that MinorCPU should signal that a drain is complete and set its drainState.
Definition: cpu.cc:189
gem5::MinorCPU::drain
DrainState drain() override
Drain interface.
Definition: cpu.cc:165
gem5::SimpleThread::setStatus
void setStatus(Status newStatus) override
Definition: simple_thread.hh:222
gem5::MinorCPU::activateContext
void activateContext(ThreadID thread_id) override
Thread activation interface from BaseCPU.
Definition: cpu.cc:252
gem5::EventFunctionWrapper
Definition: eventq.hh:1115
gem5::Drainable::signalDrainDone
void signalDrainDone() const
Signal that an object is drained.
Definition: drain.hh:305
gem5::FullSystem
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:220
gem5::SimpleThread::getTC
ThreadContext * getTC()
Returns the pointer to this SimpleThread's ThreadContext.
Definition: simple_thread.hh:167
gem5::ActivityRecorder::reset
void reset()
Clears the time buffer and the activity count.
Definition: activity.cc:125
gem5::ActivityRecorder::activateStage
void activateStage(const int idx)
Marks a stage as active.
Definition: activity.cc:91
gem5::MinorCPU::serializeThread
void serializeThread(CheckpointOut &cp, ThreadID tid) const override
Definition: cpu.cc:117
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
gem5::minor::MinorThread
SimpleThread MinorThread
Minor will use the SimpleThread state for now.
Definition: cpu.hh:65
gem5::statistics::Counter
double Counter
All counters are of 64-bit values.
Definition: types.hh:47
gem5::MinorCPU::switchOut
void switchOut() override
Switching interface from BaseCPU.
Definition: cpu.cc:232
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::statistics::init
const FlagsType init
This Stat is Initialized.
Definition: info.hh:56
gem5::MinorCPU::activityRecorder
minor::MinorActivityRecorder * activityRecorder
Activity recording for pipeline.
Definition: cpu.hh:96
gem5::MinorCPU::getInstPort
Port & getInstPort() override
Return a reference to the instruction port.
Definition: cpu.cc:301
pipeline
Definition: pipeline.h:43
gem5::MinorCPU::startup
void startup() override
Definition: cpu.cc:154
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::MinorCPU::fetchEventWrapper
EventFunctionWrapper * fetchEventWrapper
Definition: cpu.hh:206
fetch1.hh
gem5::DrainState::Draining
@ Draining
Draining buffers pending serialization/handover.
gem5::ThreadID
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:235
gem5::ArmISA::status
Bitfield< 5, 0 > status
Definition: misc_types.hh:423

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