gem5  v21.1.0.2
Public Types | Public Member Functions | Public Attributes | Protected Attributes | List of all members
gem5::SimpleThread Class Reference

The SimpleThread object provides a combination of the ThreadState object and the ThreadContext interface. More...

#include <simple_thread.hh>

Inheritance diagram for gem5::SimpleThread:
gem5::ThreadState gem5::ThreadContext gem5::Serializable gem5::PCEventScope

Public Types

typedef ThreadContext::Status Status
 
- Public Types inherited from gem5::ThreadState
typedef ThreadContext::Status Status
 
- Public Types inherited from gem5::ThreadContext
enum  Status { Active, Suspended, Halting, Halted }
 

Public Member Functions

std::string name () const
 
 SimpleThread (BaseCPU *_cpu, int _thread_num, System *_system, BaseMMU *_mmu, BaseISA *_isa)
 
 SimpleThread (BaseCPU *_cpu, int _thread_num, System *_system, Process *_process, BaseMMU *_mmu, BaseISA *_isa)
 
virtual ~SimpleThread ()
 
void takeOverFrom (ThreadContext *oldContext) override
 
void copyState (ThreadContext *oldContext)
 
void serialize (CheckpointOut &cp) const override
 Serialize an object. More...
 
void unserialize (CheckpointIn &cp) override
 Unserialize an object. More...
 
ThreadContextgetTC ()
 Returns the pointer to this SimpleThread's ThreadContext. More...
 
void demapPage (Addr vaddr, uint64_t asn)
 
bool schedule (PCEvent *e) override
 
bool remove (PCEvent *e) override
 
void scheduleInstCountEvent (Event *event, Tick count) override
 
void descheduleInstCountEvent (Event *event) override
 
Tick getCurrentInstCount () override
 
BaseCPUgetCpuPtr () override
 
int cpuId () const override
 
uint32_t socketId () const override
 
int threadId () const override
 
void setThreadId (int id) override
 
ContextID contextId () const override
 
void setContextId (ContextID id) override
 
BaseMMUgetMMUPtr () override
 
CheckerCPUgetCheckerCpuPtr () override
 
BaseISAgetIsaPtr () override
 
TheISA::Decoder * getDecoderPtr () override
 
SystemgetSystemPtr () override
 
PortProxygetVirtProxy () override
 
void initMemProxies (ThreadContext *tc) override
 Initialise the physical and virtual port proxies and tie them to the data port of the CPU. More...
 
ProcessgetProcessPtr () override
 
void setProcessPtr (Process *p) override
 
Status status () const override
 
void setStatus (Status newStatus) override
 
void activate () override
 Set the status to Active. More...
 
void suspend () override
 Set the status to Suspended. More...
 
void halt () override
 Set the status to Halted. More...
 
Tick readLastActivate () override
 
Tick readLastSuspend () override
 
void copyArchRegs (ThreadContext *tc) override
 
void clearArchRegs () override
 
RegVal readIntReg (RegIndex reg_idx) const override
 
RegVal readFloatReg (RegIndex reg_idx) const override
 
const TheISA::VecRegContainer & readVecReg (const RegId &reg) const override
 
TheISA::VecRegContainer & getWritableVecReg (const RegId &reg) override
 
const TheISA::VecElem & readVecElem (const RegId &reg) const override
 
const TheISA::VecPredRegContainer & readVecPredReg (const RegId &reg) const override
 
TheISA::VecPredRegContainer & getWritableVecPredReg (const RegId &reg) override
 
RegVal readCCReg (RegIndex reg_idx) const override
 
void setIntReg (RegIndex reg_idx, RegVal val) override
 
void setFloatReg (RegIndex reg_idx, RegVal val) override
 
void setVecReg (const RegId &reg, const TheISA::VecRegContainer &val) override
 
void setVecElem (const RegId &reg, const TheISA::VecElem &val) override
 
void setVecPredReg (const RegId &reg, const TheISA::VecPredRegContainer &val) override
 
void setCCReg (RegIndex reg_idx, RegVal val) override
 
TheISA::PCState pcState () const override
 
void pcState (const TheISA::PCState &val) override
 
void pcStateNoRecord (const TheISA::PCState &val) override
 
Addr instAddr () const override
 
Addr nextInstAddr () const override
 
MicroPC microPC () const override
 
bool readPredicate () const
 
void setPredicate (bool val)
 
RegVal readMiscRegNoEffect (RegIndex misc_reg) const override
 
RegVal readMiscReg (RegIndex misc_reg) override
 
void setMiscRegNoEffect (RegIndex misc_reg, RegVal val) override
 
void setMiscReg (RegIndex misc_reg, RegVal val) override
 
RegId flattenRegId (const RegId &regId) const override
 
unsigned readStCondFailures () const override
 
bool readMemAccPredicate ()
 
void setMemAccPredicate (bool val)
 
void setStCondFailures (unsigned sc_failures) override
 
RegVal readIntRegFlat (RegIndex idx) const override
 Flat register interfaces. More...
 
void setIntRegFlat (RegIndex idx, RegVal val) override
 
RegVal readFloatRegFlat (RegIndex idx) const override
 
void setFloatRegFlat (RegIndex idx, RegVal val) override
 
const TheISA::VecRegContainer & readVecRegFlat (RegIndex reg) const override
 
TheISA::VecRegContainer & getWritableVecRegFlat (RegIndex reg) override
 
void setVecRegFlat (RegIndex reg, const TheISA::VecRegContainer &val) override
 
const TheISA::VecElem & readVecElemFlat (RegIndex reg, const ElemIndex &elemIndex) const override
 
void setVecElemFlat (RegIndex reg, const ElemIndex &elemIndex, const TheISA::VecElem &val) override
 
const TheISA::VecPredRegContainer & readVecPredRegFlat (RegIndex reg) const override
 
TheISA::VecPredRegContainer & getWritableVecPredRegFlat (RegIndex reg) override
 
void setVecPredRegFlat (RegIndex reg, const TheISA::VecPredRegContainer &val) override
 
RegVal readCCRegFlat (RegIndex idx) const override
 
void setCCRegFlat (RegIndex idx, RegVal val) override
 
void htmAbortTransaction (uint64_t htm_uid, HtmFailureFaultCause cause) override
 
BaseHTMCheckpointPtrgetHtmCheckpointPtr () override
 
void setHtmCheckpointPtr (BaseHTMCheckpointPtr new_cpt) override
 
- Public Member Functions inherited from gem5::ThreadState
 ThreadState (BaseCPU *cpu, ThreadID _tid, Process *_process)
 
virtual ~ThreadState ()
 
void serialize (CheckpointOut &cp) const override
 Serialize an object. More...
 
void unserialize (CheckpointIn &cp) override
 Unserialize an object. More...
 
int cpuId () const
 
uint32_t socketId () const
 
ContextID contextId () const
 
void setContextId (ContextID id)
 
void setThreadId (ThreadID id)
 
ThreadID threadId () const
 
Tick readLastActivate () const
 
Tick readLastSuspend () const
 
void initMemProxies (ThreadContext *tc)
 Initialise the physical and virtual port proxies and tie them to the data port of the CPU. More...
 
PortProxygetVirtProxy ()
 
ProcessgetProcessPtr ()
 
void setProcessPtr (Process *p)
 
Status status () const
 Returns the status of this thread. More...
 
void setStatus (Status new_status)
 Sets the status of this thread. More...
 
- Public Member Functions inherited from gem5::Serializable
 Serializable ()
 
virtual ~Serializable ()
 
void serializeSection (CheckpointOut &cp, const char *name) const
 Serialize an object into a new section. More...
 
void serializeSection (CheckpointOut &cp, const std::string &name) const
 
void unserializeSection (CheckpointIn &cp, const char *name)
 Unserialize an a child object. More...
 
void unserializeSection (CheckpointIn &cp, const std::string &name)
 
- Public Member Functions inherited from gem5::ThreadContext
bool getUseForClone ()
 
void setUseForClone (bool new_val)
 
virtual ~ThreadContext ()
 
virtual void sendFunctional (PacketPtr pkt)
 
void quiesce ()
 Quiesce thread context. More...
 
void quiesceTick (Tick resume)
 Quiesce, suspend, and schedule activate at resume. More...
 
virtual void regStats (const std::string &name)
 
void setNPC (Addr val)
 
virtual int exit ()
 

Public Attributes

PCEventQueue pcEventQueue
 
EventQueue comInstEventQueue
 An instruction-based event queue. More...
 
Systemsystem
 
BaseMMUmmu
 
TheISA::Decoder decoder
 
int64_t htmTransactionStarts
 
int64_t htmTransactionStops
 
- Public Attributes inherited from gem5::ThreadState
Counter numInst
 Number of instructions committed. More...
 
Counter numOp
 Number of ops (including micro ops) committed. More...
 
gem5::ThreadState::ThreadStateStats threadStats
 
Counter numLoad
 Number of simulated loads, used for tracking events based on the number of loads committed. More...
 
Counter startNumLoad
 The number of simulated loads committed prior to this run. More...
 
Tick lastActivate
 Last time activate was called on this thread. More...
 
Tick lastSuspend
 Last time suspend was called on this thread. More...
 
unsigned storeCondFailures
 
- Public Attributes inherited from gem5::ThreadContext
int intResult = DefaultIntResult
 
double floatResult = DefaultFloatResult
 
int intOffset = 0
 

Protected Attributes

std::vector< RegValfloatRegs
 
std::vector< RegValintRegs
 
std::vector< TheISA::VecRegContainer > vecRegs
 
std::vector< TheISA::VecPredRegContainer > vecPredRegs
 
std::vector< RegValccRegs
 
TheISA::ISA *const isa
 
TheISA::PCState _pcState
 
std::unique_ptr< BaseHTMCheckpoint_htmCheckpoint
 
bool predicate
 Did this instruction execute or is it predicated false. More...
 
bool memAccPredicate
 True if the memory access should be skipped for this instruction. More...
 
- Protected Attributes inherited from gem5::ThreadState
ThreadContext::Status _status
 
BaseCPUbaseCpu
 
ContextID _contextId
 
ThreadID _threadId
 
Processprocess
 
PortProxyvirtProxy
 A translating port proxy, outgoing only, for functional accesse to virtual addresses. More...
 
- Protected Attributes inherited from gem5::ThreadContext
bool useForClone = false
 

Additional Inherited Members

- Static Public Member Functions inherited from gem5::Serializable
static const std::string & currentSection ()
 Gets the fully-qualified name of the active section. More...
 
static void generateCheckpointOut (const std::string &cpt_dir, std::ofstream &outstream)
 Generate a checkpoint file so that the serialization can be routed to it. More...
 
- Static Public Member Functions inherited from gem5::ThreadContext
static void compare (ThreadContext *one, ThreadContext *two)
 function to compare two thread contexts (for debugging) More...
 
- Static Public Attributes inherited from gem5::ThreadContext
static const int ints []
 
static const double floats []
 
static const int DefaultIntResult = 0
 
static const double DefaultFloatResult = 0.0
 

Detailed Description

The SimpleThread object provides a combination of the ThreadState object and the ThreadContext interface.

It implements the ThreadContext interface and adds to the ThreadState object by adding all the objects needed for simple functional execution, including a simple architectural register file, and pointers to the ITB and DTB in full system mode. For CPU models that do not need more advanced ways to hold state (i.e. a separate physical register file, or separate fetch and commit PC's), this SimpleThread class provides all the necessary state for full architecture-level functional simulation. See the AtomicSimpleCPU or TimingSimpleCPU for examples.

Definition at line 94 of file simple_thread.hh.

Member Typedef Documentation

◆ Status

Definition at line 97 of file simple_thread.hh.

Constructor & Destructor Documentation

◆ SimpleThread() [1/2]

gem5::SimpleThread::SimpleThread ( BaseCPU _cpu,
int  _thread_num,
System _system,
BaseMMU _mmu,
BaseISA _isa 
)

Definition at line 88 of file simple_thread.cc.

◆ SimpleThread() [2/2]

gem5::SimpleThread::SimpleThread ( BaseCPU _cpu,
int  _thread_num,
System _system,
Process _process,
BaseMMU _mmu,
BaseISA _isa 
)

◆ ~SimpleThread()

virtual gem5::SimpleThread::~SimpleThread ( )
inlinevirtual

Definition at line 151 of file simple_thread.hh.

Member Function Documentation

◆ activate()

void gem5::SimpleThread::activate ( )
overridevirtual

◆ clearArchRegs()

void gem5::SimpleThread::clearArchRegs ( )
inlineoverridevirtual

◆ contextId()

ContextID gem5::SimpleThread::contextId ( ) const
inlineoverridevirtual

◆ copyArchRegs()

void gem5::SimpleThread::copyArchRegs ( ThreadContext tc)
overridevirtual

◆ copyState()

void gem5::SimpleThread::copyState ( ThreadContext oldContext)

◆ cpuId()

int gem5::SimpleThread::cpuId ( ) const
inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 202 of file simple_thread.hh.

References gem5::ThreadState::cpuId().

◆ demapPage()

void gem5::SimpleThread::demapPage ( Addr  vaddr,
uint64_t  asn 
)
inline

◆ descheduleInstCountEvent()

void gem5::SimpleThread::descheduleInstCountEvent ( Event event)
inlineoverridevirtual

◆ flattenRegId()

RegId gem5::SimpleThread::flattenRegId ( const RegId regId) const
inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 470 of file simple_thread.hh.

References isa.

◆ getCheckerCpuPtr()

CheckerCPU* gem5::SimpleThread::getCheckerCpuPtr ( )
inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 211 of file simple_thread.hh.

◆ getCpuPtr()

BaseCPU* gem5::SimpleThread::getCpuPtr ( )
inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 200 of file simple_thread.hh.

References gem5::ThreadState::baseCpu.

◆ getCurrentInstCount()

Tick gem5::SimpleThread::getCurrentInstCount ( )
inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 195 of file simple_thread.hh.

References comInstEventQueue, and gem5::EventQueue::getCurTick().

◆ getDecoderPtr()

TheISA::Decoder* gem5::SimpleThread::getDecoderPtr ( )
inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 215 of file simple_thread.hh.

References decoder.

◆ getHtmCheckpointPtr()

BaseHTMCheckpointPtr & gem5::SimpleThread::getHtmCheckpointPtr ( )
overridevirtual

Implements gem5::ThreadContext.

Definition at line 185 of file simple_thread.cc.

References _htmCheckpoint.

◆ getIsaPtr()

BaseISA* gem5::SimpleThread::getIsaPtr ( )
inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 213 of file simple_thread.hh.

References isa.

Referenced by copyArchRegs().

◆ getMMUPtr()

BaseMMU* gem5::SimpleThread::getMMUPtr ( )
inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 209 of file simple_thread.hh.

References mmu.

Referenced by gem5::minor::ExecContext::demapPage().

◆ getProcessPtr()

Process* gem5::SimpleThread::getProcessPtr ( )
inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 227 of file simple_thread.hh.

References gem5::ThreadState::getProcessPtr().

◆ getSystemPtr()

System* gem5::SimpleThread::getSystemPtr ( )
inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 217 of file simple_thread.hh.

References system.

◆ getTC()

ThreadContext* gem5::SimpleThread::getTC ( )
inline

◆ getVirtProxy()

PortProxy& gem5::SimpleThread::getVirtProxy ( )
inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 219 of file simple_thread.hh.

References gem5::ThreadState::getVirtProxy().

◆ getWritableVecPredReg()

TheISA::VecPredRegContainer& gem5::SimpleThread::getWritableVecPredReg ( const RegId reg)
inlineoverridevirtual

◆ getWritableVecPredRegFlat()

TheISA::VecPredRegContainer& gem5::SimpleThread::getWritableVecPredRegFlat ( RegIndex  reg)
inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 551 of file simple_thread.hh.

References gem5::X86ISA::reg, and vecPredRegs.

Referenced by getWritableVecPredReg().

◆ getWritableVecReg()

TheISA::VecRegContainer& gem5::SimpleThread::getWritableVecReg ( const RegId reg)
inlineoverridevirtual

◆ getWritableVecRegFlat()

TheISA::VecRegContainer& gem5::SimpleThread::getWritableVecRegFlat ( RegIndex  reg)
inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 520 of file simple_thread.hh.

References gem5::X86ISA::reg, and vecRegs.

Referenced by getWritableVecReg().

◆ halt()

void gem5::SimpleThread::halt ( )
overridevirtual

◆ htmAbortTransaction()

void gem5::SimpleThread::htmAbortTransaction ( uint64_t  htm_uid,
HtmFailureFaultCause  cause 
)
overridevirtual

◆ initMemProxies()

void gem5::SimpleThread::initMemProxies ( ThreadContext tc)
inlineoverridevirtual

Initialise the physical and virtual port proxies and tie them to the data port of the CPU.

tc ThreadContext for the virtual-to-physical translation

Implements gem5::ThreadContext.

Definition at line 222 of file simple_thread.hh.

References gem5::ThreadState::initMemProxies().

◆ instAddr()

Addr gem5::SimpleThread::instAddr ( ) const
inlineoverridevirtual

◆ microPC()

MicroPC gem5::SimpleThread::microPC ( ) const
inlineoverridevirtual

◆ name()

std::string gem5::SimpleThread::name ( ) const
inline

◆ nextInstAddr()

Addr gem5::SimpleThread::nextInstAddr ( ) const
inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 440 of file simple_thread.hh.

References _pcState.

Referenced by gem5::CheckerCPU::nextInstAddr().

◆ pcState() [1/2]

TheISA::PCState gem5::SimpleThread::pcState ( ) const
inlineoverridevirtual

◆ pcState() [2/2]

void gem5::SimpleThread::pcState ( const TheISA::PCState &  val)
inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 431 of file simple_thread.hh.

References _pcState, and gem5::X86ISA::val.

◆ pcStateNoRecord()

void gem5::SimpleThread::pcStateNoRecord ( const TheISA::PCState &  val)
inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 434 of file simple_thread.hh.

References _pcState, and gem5::X86ISA::val.

◆ readCCReg()

RegVal gem5::SimpleThread::readCCReg ( RegIndex  reg_idx) const
inlineoverridevirtual

◆ readCCRegFlat()

RegVal gem5::SimpleThread::readCCRegFlat ( RegIndex  idx) const
inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 563 of file simple_thread.hh.

References ccRegs.

Referenced by readCCReg().

◆ readFloatReg()

RegVal gem5::SimpleThread::readFloatReg ( RegIndex  reg_idx) const
inlineoverridevirtual

◆ readFloatRegFlat()

RegVal gem5::SimpleThread::readFloatRegFlat ( RegIndex  idx) const
inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 503 of file simple_thread.hh.

References floatRegs.

Referenced by readFloatReg().

◆ readIntReg()

RegVal gem5::SimpleThread::readIntReg ( RegIndex  reg_idx) const
inlineoverridevirtual

◆ readIntRegFlat()

RegVal gem5::SimpleThread::readIntRegFlat ( RegIndex  idx) const
inlineoverridevirtual

Flat register interfaces.

Some architectures have different registers visible in different modes. Such architectures "flatten" a register (see flattenRegId()) to map it into the gem5 register file. This interface provides a flat interface to the underlying register file, which allows for example serialization code to access all registers.

Implements gem5::ThreadContext.

Definition at line 495 of file simple_thread.hh.

References intRegs.

Referenced by readIntReg().

◆ readLastActivate()

Tick gem5::SimpleThread::readLastActivate ( )
inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 244 of file simple_thread.hh.

References gem5::ThreadState::readLastActivate().

◆ readLastSuspend()

Tick gem5::SimpleThread::readLastSuspend ( )
inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 249 of file simple_thread.hh.

References gem5::ThreadState::readLastSuspend().

◆ readMemAccPredicate()

bool gem5::SimpleThread::readMemAccPredicate ( )
inline

◆ readMiscReg()

RegVal gem5::SimpleThread::readMiscReg ( RegIndex  misc_reg)
inlineoverridevirtual

◆ readMiscRegNoEffect()

RegVal gem5::SimpleThread::readMiscRegNoEffect ( RegIndex  misc_reg) const
inlineoverridevirtual

◆ readPredicate()

bool gem5::SimpleThread::readPredicate ( ) const
inline

◆ readStCondFailures()

unsigned gem5::SimpleThread::readStCondFailures ( ) const
inlineoverridevirtual

◆ readVecElem()

const TheISA::VecElem& gem5::SimpleThread::readVecElem ( const RegId reg) const
inlineoverridevirtual

◆ readVecElemFlat()

const TheISA::VecElem& gem5::SimpleThread::readVecElemFlat ( RegIndex  reg,
const ElemIndex elemIndex 
) const
inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 532 of file simple_thread.hh.

References gem5::X86ISA::reg, and vecRegs.

Referenced by readVecElem().

◆ readVecPredReg()

const TheISA::VecPredRegContainer& gem5::SimpleThread::readVecPredReg ( const RegId reg) const
inlineoverridevirtual

◆ readVecPredRegFlat()

const TheISA::VecPredRegContainer& gem5::SimpleThread::readVecPredRegFlat ( RegIndex  reg) const
inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 545 of file simple_thread.hh.

References gem5::X86ISA::reg, and vecPredRegs.

Referenced by readVecPredReg().

◆ readVecReg()

const TheISA::VecRegContainer& gem5::SimpleThread::readVecReg ( const RegId reg) const
inlineoverridevirtual

◆ readVecRegFlat()

const TheISA::VecRegContainer& gem5::SimpleThread::readVecRegFlat ( RegIndex  reg) const
inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 514 of file simple_thread.hh.

References gem5::X86ISA::reg, and vecRegs.

Referenced by readVecReg().

◆ remove()

bool gem5::SimpleThread::remove ( PCEvent e)
inlineoverridevirtual

◆ schedule()

bool gem5::SimpleThread::schedule ( PCEvent e)
inlineoverridevirtual

◆ scheduleInstCountEvent()

void gem5::SimpleThread::scheduleInstCountEvent ( Event event,
Tick  count 
)
inlineoverridevirtual

◆ serialize()

void gem5::SimpleThread::serialize ( CheckpointOut cp) const
overridevirtual

Serialize an object.

Output an object's state into the current checkpoint section.

Parameters
cpCheckpoint state

Implements gem5::Serializable.

Definition at line 116 of file simple_thread.cc.

References gem5::ThreadState::serialize(), and gem5::serialize().

Referenced by gem5::BaseKvmCPU::serializeThread().

◆ setCCReg()

void gem5::SimpleThread::setCCReg ( RegIndex  reg_idx,
RegVal  val 
)
inlineoverridevirtual

◆ setCCRegFlat()

void gem5::SimpleThread::setCCRegFlat ( RegIndex  idx,
RegVal  val 
)
inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 564 of file simple_thread.hh.

References ccRegs, and gem5::X86ISA::val.

Referenced by setCCReg().

◆ setContextId()

void gem5::SimpleThread::setContextId ( ContextID  id)
inlineoverridevirtual

◆ setFloatReg()

void gem5::SimpleThread::setFloatReg ( RegIndex  reg_idx,
RegVal  val 
)
inlineoverridevirtual

◆ setFloatRegFlat()

void gem5::SimpleThread::setFloatRegFlat ( RegIndex  idx,
RegVal  val 
)
inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 508 of file simple_thread.hh.

References floatRegs, and gem5::X86ISA::val.

Referenced by setFloatReg().

◆ setHtmCheckpointPtr()

void gem5::SimpleThread::setHtmCheckpointPtr ( BaseHTMCheckpointPtr  new_cpt)
overridevirtual

Implements gem5::ThreadContext.

Definition at line 191 of file simple_thread.cc.

References _htmCheckpoint.

◆ setIntReg()

void gem5::SimpleThread::setIntReg ( RegIndex  reg_idx,
RegVal  val 
)
inlineoverridevirtual

◆ setIntRegFlat()

void gem5::SimpleThread::setIntRegFlat ( RegIndex  idx,
RegVal  val 
)
inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 497 of file simple_thread.hh.

References intRegs, and gem5::X86ISA::val.

Referenced by setIntReg().

◆ setMemAccPredicate()

void gem5::SimpleThread::setMemAccPredicate ( bool  val)
inline

◆ setMiscReg()

void gem5::SimpleThread::setMiscReg ( RegIndex  misc_reg,
RegVal  val 
)
inlineoverridevirtual

◆ setMiscRegNoEffect()

void gem5::SimpleThread::setMiscRegNoEffect ( RegIndex  misc_reg,
RegVal  val 
)
inlineoverridevirtual

◆ setPredicate()

void gem5::SimpleThread::setPredicate ( bool  val)
inline

◆ setProcessPtr()

void gem5::SimpleThread::setProcessPtr ( Process p)
inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 228 of file simple_thread.hh.

References gem5::MipsISA::p, and gem5::ThreadState::setProcessPtr().

◆ setStatus()

void gem5::SimpleThread::setStatus ( Status  newStatus)
inlineoverridevirtual

◆ setStCondFailures()

void gem5::SimpleThread::setStCondFailures ( unsigned  sc_failures)
inlineoverridevirtual

◆ setThreadId()

void gem5::SimpleThread::setThreadId ( int  id)
inlineoverridevirtual

◆ setVecElem()

void gem5::SimpleThread::setVecElem ( const RegId reg,
const TheISA::VecElem &  val 
)
inlineoverridevirtual

◆ setVecElemFlat()

void gem5::SimpleThread::setVecElemFlat ( RegIndex  reg,
const ElemIndex elemIndex,
const TheISA::VecElem &  val 
)
inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 538 of file simple_thread.hh.

References gem5::X86ISA::reg, gem5::X86ISA::val, and vecRegs.

Referenced by setVecElem().

◆ setVecPredReg()

void gem5::SimpleThread::setVecPredReg ( const RegId reg,
const TheISA::VecPredRegContainer &  val 
)
inlineoverridevirtual

◆ setVecPredRegFlat()

void gem5::SimpleThread::setVecPredRegFlat ( RegIndex  reg,
const TheISA::VecPredRegContainer &  val 
)
inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 557 of file simple_thread.hh.

References gem5::X86ISA::reg, gem5::X86ISA::val, and vecPredRegs.

Referenced by setVecPredReg().

◆ setVecReg()

void gem5::SimpleThread::setVecReg ( const RegId reg,
const TheISA::VecRegContainer &  val 
)
inlineoverridevirtual

◆ setVecRegFlat()

void gem5::SimpleThread::setVecRegFlat ( RegIndex  reg,
const TheISA::VecRegContainer &  val 
)
inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 526 of file simple_thread.hh.

References gem5::X86ISA::reg, gem5::X86ISA::val, and vecRegs.

Referenced by setVecReg().

◆ socketId()

uint32_t gem5::SimpleThread::socketId ( ) const
inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 203 of file simple_thread.hh.

References gem5::ThreadState::socketId().

◆ status()

Status gem5::SimpleThread::status ( ) const
inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 230 of file simple_thread.hh.

References gem5::ThreadState::_status.

Referenced by activate(), halt(), suspend(), and gem5::BaseKvmCPU::wakeup().

◆ suspend()

void gem5::SimpleThread::suspend ( )
overridevirtual

◆ takeOverFrom()

void gem5::SimpleThread::takeOverFrom ( ThreadContext oldContext)
overridevirtual

◆ threadId()

int gem5::SimpleThread::threadId ( ) const
inlineoverridevirtual

◆ unserialize()

void gem5::SimpleThread::unserialize ( CheckpointIn cp)
overridevirtual

Unserialize an object.

Read an object's state from the current checkpoint section.

Parameters
cpCheckpoint state

Implements gem5::Serializable.

Definition at line 124 of file simple_thread.cc.

References gem5::ThreadState::unserialize(), and gem5::unserialize().

Referenced by gem5::BaseKvmCPU::unserializeThread().

Member Data Documentation

◆ _htmCheckpoint

std::unique_ptr<BaseHTMCheckpoint> gem5::SimpleThread::_htmCheckpoint
protected

Definition at line 110 of file simple_thread.hh.

Referenced by getHtmCheckpointPtr(), and setHtmCheckpointPtr().

◆ _pcState

TheISA::PCState gem5::SimpleThread::_pcState
protected

◆ ccRegs

std::vector<RegVal> gem5::SimpleThread::ccRegs
protected

◆ comInstEventQueue

EventQueue gem5::SimpleThread::comInstEventQueue

An instruction-based event queue.

Used for scheduling events based on number of instructions committed.

Definition at line 130 of file simple_thread.hh.

Referenced by descheduleInstCountEvent(), gem5::minor::Execute::doInstCommitAccounting(), getCurrentInstCount(), scheduleInstCountEvent(), gem5::BaseSimpleCPU::serviceInstCountEvents(), gem5::BaseKvmCPU::setupInstStop(), and gem5::BaseKvmCPU::tick().

◆ decoder

TheISA::Decoder gem5::SimpleThread::decoder

◆ floatRegs

std::vector<RegVal> gem5::SimpleThread::floatRegs
protected

◆ htmTransactionStarts

int64_t gem5::SimpleThread::htmTransactionStarts

◆ htmTransactionStops

int64_t gem5::SimpleThread::htmTransactionStops

◆ intRegs

std::vector<RegVal> gem5::SimpleThread::intRegs
protected

◆ isa

TheISA::ISA* const gem5::SimpleThread::isa
protected

◆ memAccPredicate

bool gem5::SimpleThread::memAccPredicate
protected

True if the memory access should be skipped for this instruction.

Definition at line 116 of file simple_thread.hh.

Referenced by readMemAccPredicate(), and setMemAccPredicate().

◆ mmu

BaseMMU* gem5::SimpleThread::mmu

◆ pcEventQueue

PCEventQueue gem5::SimpleThread::pcEventQueue

Definition at line 125 of file simple_thread.hh.

Referenced by remove(), and schedule().

◆ predicate

bool gem5::SimpleThread::predicate
protected

Did this instruction execute or is it predicated false.

Definition at line 113 of file simple_thread.hh.

Referenced by readPredicate(), and setPredicate().

◆ system

System* gem5::SimpleThread::system

Definition at line 132 of file simple_thread.hh.

Referenced by getSystemPtr().

◆ vecPredRegs

std::vector<TheISA::VecPredRegContainer> gem5::SimpleThread::vecPredRegs
protected

◆ vecRegs

std::vector<TheISA::VecRegContainer> gem5::SimpleThread::vecRegs
protected

The documentation for this class was generated from the following files:

Generated on Tue Sep 21 2021 12:28:10 for gem5 by doxygen 1.8.17