gem5  v21.1.0.2
base.hh
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41 
42 #ifndef __CPU_SIMPLE_BASE_HH__
43 #define __CPU_SIMPLE_BASE_HH__
44 
45 #include "base/statistics.hh"
46 #include "cpu/base.hh"
47 #include "cpu/checker/cpu.hh"
48 #include "cpu/exec_context.hh"
49 #include "cpu/pc_event.hh"
50 #include "cpu/simple_thread.hh"
51 #include "cpu/static_inst.hh"
52 #include "mem/packet.hh"
53 #include "mem/port.hh"
54 #include "mem/request.hh"
55 #include "sim/eventq.hh"
56 #include "sim/full_system.hh"
57 #include "sim/system.hh"
58 
59 namespace gem5
60 {
61 
62 // forward declarations
63 class Checkpoint;
64 class Process;
65 class Processor;
66 class ThreadContext;
67 
68 namespace Trace
69 {
70  class InstRecord;
71 }
72 
73 struct BaseSimpleCPUParams;
74 namespace branch_prediction
75 {
76  class BPredUnit;
77 } // namespace branch_prediction
78 class SimpleExecContext;
79 
80 class BaseSimpleCPU : public BaseCPU
81 {
82  protected:
85 
87 
88  void checkPcEventQueue();
89  void swapActiveThread();
90 
91  public:
92  BaseSimpleCPU(const BaseSimpleCPUParams &params);
93  virtual ~BaseSimpleCPU();
94  void wakeup(ThreadID tid) override;
95  void init() override;
96  public:
99 
102 
106 
107  protected:
108  enum Status
109  {
121  };
122 
124 
131  void traceFault();
132 
133  public:
134  void checkForInterrupts();
135  void setupFetchRequest(const RequestPtr &req);
136  void serviceInstCountEvents();
137  void preExecute();
138  void postExecute();
139  void advancePC(const Fault &fault);
140 
141  void haltContext(ThreadID thread_num) override;
142 
143  // statistics
144  void resetStats() override;
145 
146  virtual Fault
147  readMem(Addr addr, uint8_t* data, unsigned size, Request::Flags flags,
148  const std::vector<bool>& byte_enable=std::vector<bool>())
149  {
150  panic("readMem() is not implemented");
151  }
152 
153  virtual Fault
154  initiateMemRead(Addr addr, unsigned size, Request::Flags flags,
155  const std::vector<bool>& byte_enable=std::vector<bool>())
156  {
157  panic("initiateMemRead() is not implemented\n");
158  }
159 
160  virtual Fault
161  writeMem(uint8_t* data, unsigned size, Addr addr, Request::Flags flags,
162  uint64_t* res,
163  const std::vector<bool>& byte_enable=std::vector<bool>())
164  {
165  panic("writeMem() is not implemented\n");
166  }
167 
168  virtual Fault
169  amoMem(Addr addr, uint8_t* data, unsigned size, Request::Flags flags,
170  AtomicOpFunctorPtr amo_op)
171  {
172  panic("amoMem() is not implemented\n");
173  }
174 
175  virtual Fault
176  initiateMemAMO(Addr addr, unsigned size, Request::Flags flags,
177  AtomicOpFunctorPtr amo_op)
178  {
179  panic("initiateMemAMO() is not implemented\n");
180  }
181 
182  void countInst();
183  Counter totalInsts() const override;
184  Counter totalOps() const override;
185 
186  void serializeThread(CheckpointOut &cp, ThreadID tid) const override;
187  void unserializeThread(CheckpointIn &cp, ThreadID tid) override;
188 
193  virtual Fault initiateHtmCmd(Request::Flags flags) = 0;
194 
203  virtual void htmSendAbortSignal(HtmFailureFaultCause cause) = 0;
204 };
205 
206 } // namespace gem5
207 
208 #endif // __CPU_SIMPLE_BASE_HH__
gem5::BaseSimpleCPU::initiateMemAMO
virtual Fault initiateMemAMO(Addr addr, unsigned size, Request::Flags flags, AtomicOpFunctorPtr amo_op)
Definition: base.hh:176
gem5::BaseSimpleCPU::serializeThread
void serializeThread(CheckpointOut &cp, ThreadID tid) const override
Serialize a single thread.
Definition: base.cc:217
gem5::BaseSimpleCPU::DcacheRetry
@ DcacheRetry
Definition: base.hh:118
gem5::BaseSimpleCPU::totalOps
Counter totalOps() const override
Definition: base.cc:185
gem5::BaseSimpleCPU::threadInfo
std::vector< SimpleExecContext * > threadInfo
Definition: base.hh:100
system.hh
data
const char data[]
Definition: circlebuf.test.cc:48
gem5::BaseSimpleCPU::traceData
Trace::InstRecord * traceData
Definition: base.hh:97
gem5::HtmFailureFaultCause
HtmFailureFaultCause
Definition: htm.hh:47
gem5::BaseSimpleCPU::_status
Status _status
Definition: base.hh:123
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::BaseSimpleCPU::curStaticInst
StaticInstPtr curStaticInst
Current instruction.
Definition: base.hh:104
gem5::BaseSimpleCPU::amoMem
virtual Fault amoMem(Addr addr, uint8_t *data, unsigned size, Request::Flags flags, AtomicOpFunctorPtr amo_op)
Definition: base.hh:169
gem5::BaseSimpleCPU::ITBWaitResponse
@ ITBWaitResponse
Definition: base.hh:113
std::vector
STL vector class.
Definition: stl.hh:37
gem5::BaseSimpleCPU::BaseSimpleCPU
BaseSimpleCPU(const BaseSimpleCPUParams &params)
Definition: base.cc:83
gem5::BaseSimpleCPU::unserializeThread
void unserializeThread(CheckpointIn &cp, ThreadID tid) override
Unserialize one thread.
Definition: base.cc:225
gem5::BaseSimpleCPU::IcacheRetry
@ IcacheRetry
Definition: base.hh:114
gem5::BaseSimpleCPU::~BaseSimpleCPU
virtual ~BaseSimpleCPU()
Definition: base.cc:195
request.hh
gem5::BaseSimpleCPU::checkForInterrupts
void checkForInterrupts()
Definition: base.cc:258
gem5::RefCountingPtr< StaticInst >
packet.hh
gem5::BaseSimpleCPU::htmSendAbortSignal
virtual void htmSendAbortSignal(HtmFailureFaultCause cause)=0
This function is used to instruct the memory subsystem that a transaction should be aborted and the s...
gem5::BaseSimpleCPU::writeMem
virtual Fault writeMem(uint8_t *data, unsigned size, Addr addr, Request::Flags flags, uint64_t *res, const std::vector< bool > &byte_enable=std::vector< bool >())
Definition: base.hh:161
gem5::Flags< FlagsType >
gem5::BaseSimpleCPU::readMem
virtual Fault readMem(Addr addr, uint8_t *data, unsigned size, Request::Flags flags, const std::vector< bool > &byte_enable=std::vector< bool >())
Definition: base.hh:147
gem5::BaseSimpleCPU::checkPcEventQueue
void checkPcEventQueue()
Definition: base.cc:133
gem5::BaseSimpleCPU::Status
Status
Definition: base.hh:108
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::SimObject::params
const Params & params() const
Definition: sim_object.hh:176
gem5::BaseSimpleCPU::preExecute
void preExecute()
Definition: base.cc:313
statistics.hh
gem5::CheckerCPU
CheckerCPU class.
Definition: cpu.hh:84
gem5::BaseSimpleCPU::setupFetchRequest
void setupFetchRequest(const RequestPtr &req)
Definition: base.cc:289
cpu.hh
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::BaseSimpleCPU::DTBWaitResponse
@ DTBWaitResponse
Definition: base.hh:117
port.hh
gem5::BaseSimpleCPU::activeThreads
std::list< ThreadID > activeThreads
Definition: base.hh:101
gem5::BaseCPU
Definition: base.hh:107
gem5::BaseSimpleCPU
Definition: base.hh:80
static_inst.hh
gem5::BaseSimpleCPU::traceFault
void traceFault()
Handler used when encountering a fault; its purpose is to tear down the InstRecord.
Definition: base.cc:247
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::BaseSimpleCPU::IcacheWaitSwitch
@ IcacheWaitSwitch
Definition: base.hh:116
full_system.hh
gem5::BaseSimpleCPU::postExecute
void postExecute()
Definition: base.cc:394
gem5::BaseSimpleCPU::Faulting
@ Faulting
Definition: base.hh:112
gem5::BaseSimpleCPU::branchPred
branch_prediction::BPredUnit * branchPred
Definition: base.hh:84
simple_thread.hh
gem5::BaseSimpleCPU::zeroReg
const RegIndex zeroReg
Definition: base.hh:86
gem5::BaseSimpleCPU::countInst
void countInst()
Definition: base.cc:161
gem5::BaseSimpleCPU::resetStats
void resetStats() override
Callback to reset stats.
Definition: base.cc:208
base.hh
pc_event.hh
gem5::BaseSimpleCPU::Running
@ Running
Definition: base.hh:111
gem5::BaseSimpleCPU::initiateMemRead
virtual Fault initiateMemRead(Addr addr, unsigned size, Request::Flags flags, const std::vector< bool > &byte_enable=std::vector< bool >())
Definition: base.hh:154
gem5::BaseSimpleCPU::swapActiveThread
void swapActiveThread()
Definition: base.cc:145
exec_context.hh
gem5::BaseSimpleCPU::IcacheWaitResponse
@ IcacheWaitResponse
Definition: base.hh:115
gem5::statistics::Counter
double Counter
All counters are of 64-bit values.
Definition: types.hh:47
gem5::BaseSimpleCPU::serviceInstCountEvents
void serviceInstCountEvents()
Definition: base.cc:306
gem5::branch_prediction::BPredUnit
Basically a wrapper class to hold both the branch predictor and the BTB.
Definition: bpred_unit.hh:68
gem5::BaseSimpleCPU::wakeup
void wakeup(ThreadID tid) override
Definition: base.cc:236
gem5::BaseSimpleCPU::advancePC
void advancePC(const Fault &fault)
Definition: base.cc:470
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::BaseSimpleCPU::checker
CheckerCPU * checker
Definition: base.hh:98
gem5::Trace::InstRecord
Definition: insttracer.hh:58
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
std::list< ThreadID >
gem5::BaseSimpleCPU::haltContext
void haltContext(ThreadID thread_num) override
Notify the CPU that the indicated context is now halted.
Definition: base.cc:200
gem5::AtomicOpFunctorPtr
std::unique_ptr< AtomicOpFunctor > AtomicOpFunctorPtr
Definition: amo.hh:242
gem5::BaseSimpleCPU::DcacheWaitResponse
@ DcacheWaitResponse
Definition: base.hh:119
gem5::BaseSimpleCPU::totalInsts
Counter totalInsts() const override
Definition: base.cc:174
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::BaseSimpleCPU::Idle
@ Idle
Definition: base.hh:110
gem5::BaseSimpleCPU::curMacroStaticInst
StaticInstPtr curMacroStaticInst
Definition: base.hh:105
gem5::BaseSimpleCPU::initiateHtmCmd
virtual Fault initiateHtmCmd(Request::Flags flags)=0
Hardware transactional memory commands (HtmCmds), e.g.
gem5::BaseSimpleCPU::curThread
ThreadID curThread
Definition: base.hh:83
gem5::BaseSimpleCPU::DcacheWaitSwitch
@ DcacheWaitSwitch
Definition: base.hh:120
gem5::ThreadID
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:242
gem5::BaseSimpleCPU::init
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: base.cc:122
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
eventq.hh

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