base.hh

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/*
 * Copyright (c) 2011-2012,2015,2018,2020-2021 ARM Limited
 * Copyright (c) 2013 Advanced Micro Devices, Inc.
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 * not be construed as granting a license to any other intellectual
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 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
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 *
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 * All rights reserved.
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 * modification, are permitted provided that the following conditions are
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#ifndef __CPU_SIMPLE_BASE_HH__
#define __CPU_SIMPLE_BASE_HH__
 
#include <memory>
 
#include "arch/generic/pcstate.hh"
#include "base/statistics.hh"
#include "cpu/base.hh"
#include "cpu/checker/cpu.hh"
#include "cpu/exec_context.hh"
#include "cpu/pc_event.hh"
#include "cpu/simple_thread.hh"
#include "cpu/static_inst.hh"
#include "mem/packet.hh"
#include "mem/port.hh"
#include "mem/request.hh"
#include "sim/eventq.hh"
#include "sim/full_system.hh"
#include "sim/system.hh"
 
namespace gem5
{
 
// forward declarations
class Checkpoint;
class Process;
class Processor;
class ThreadContext;
 
namespace trace
{
    class InstRecord;
}
 
struct BaseSimpleCPUParams;
namespace branch_prediction
{
    class BPredUnit;
} // namespace branch_prediction
class SimpleExecContext;
 
class BaseSimpleCPU : public BaseCPU
{
  protected:
    ThreadID curThread;
    branch_prediction::BPredUnit *branchPred;
 
    void checkPcEventQueue();
    void swapActiveThread();
 
  public:
    BaseSimpleCPU(const BaseSimpleCPUParams &params);
    virtual ~BaseSimpleCPU();
    void wakeup(ThreadID tid) override;
  public:
    trace::InstRecord *traceData;
    CheckerCPU *checker;
 
    std::vector<SimpleExecContext*> threadInfo;
    std::list<ThreadID> activeThreads;
 
    StaticInstPtr curStaticInst;
    StaticInstPtr curMacroStaticInst;
 
  protected:
    enum Status
    {
        Idle,
        Running,
        Faulting,
        ITBWaitResponse,
        IcacheRetry,
        IcacheWaitResponse,
        IcacheWaitSwitch,
        DTBWaitResponse,
        DcacheRetry,
        DcacheWaitResponse,
        DcacheWaitSwitch,
    };
 
    Status _status;
 
    void traceFault();
 
    std::unique_ptr<PCStateBase> preExecuteTempPC;
 
  public:
    void checkForInterrupts();
    void setupFetchRequest(const RequestPtr &req);
    void serviceInstCountEvents();
    void preExecute();
    void postExecute();
    void advancePC(const Fault &fault);
 
    void haltContext(ThreadID thread_num) override;
 
    // statistics
    void resetStats() override;
 
    virtual Fault
    readMem(Addr addr, uint8_t* data, unsigned size, Request::Flags flags,
            const std::vector<bool>& byte_enable=std::vector<bool>())
    {
        panic("readMem() is not implemented");
    }
 
    virtual Fault
    initiateMemRead(Addr addr, unsigned size, Request::Flags flags,
            const std::vector<bool>& byte_enable=std::vector<bool>())
    {
        panic("initiateMemRead() is not implemented\n");
    }
 
    virtual Fault
    writeMem(uint8_t* data, unsigned size, Addr addr, Request::Flags flags,
            uint64_t* res,
            const std::vector<bool>& byte_enable=std::vector<bool>())
    {
        panic("writeMem() is not implemented\n");
    }
 
    virtual Fault
    amoMem(Addr addr, uint8_t* data, unsigned size, Request::Flags flags,
            AtomicOpFunctorPtr amo_op)
    {
        panic("amoMem() is not implemented\n");
    }
 
    virtual Fault
    initiateMemAMO(Addr addr, unsigned size, Request::Flags flags,
            AtomicOpFunctorPtr amo_op)
    {
        panic("initiateMemAMO() is not implemented\n");
    }
 
    void countInst();
    Counter totalInsts() const override;
    Counter totalOps() const override;
 
    void serializeThread(CheckpointOut &cp, ThreadID tid) const override;
    void unserializeThread(CheckpointIn &cp, ThreadID tid) override;
 
    virtual Fault initiateMemMgmtCmd(Request::Flags flags) = 0;
 
};
 
} // namespace gem5
 
#endif // __CPU_SIMPLE_BASE_HH__