gem5  v21.2.1.1
base.hh
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41 
42 #ifndef __CPU_SIMPLE_BASE_HH__
43 #define __CPU_SIMPLE_BASE_HH__
44 
45 #include <memory>
46 
47 #include "arch/generic/pcstate.hh"
48 #include "base/statistics.hh"
49 #include "cpu/base.hh"
50 #include "cpu/checker/cpu.hh"
51 #include "cpu/exec_context.hh"
52 #include "cpu/pc_event.hh"
53 #include "cpu/simple_thread.hh"
54 #include "cpu/static_inst.hh"
55 #include "mem/packet.hh"
56 #include "mem/port.hh"
57 #include "mem/request.hh"
58 #include "sim/eventq.hh"
59 #include "sim/full_system.hh"
60 #include "sim/system.hh"
61 
62 namespace gem5
63 {
64 
65 // forward declarations
66 class Checkpoint;
67 class Process;
68 class Processor;
69 class ThreadContext;
70 
71 namespace Trace
72 {
73  class InstRecord;
74 }
75 
76 struct BaseSimpleCPUParams;
77 namespace branch_prediction
78 {
79  class BPredUnit;
80 } // namespace branch_prediction
81 class SimpleExecContext;
82 
83 class BaseSimpleCPU : public BaseCPU
84 {
85  protected:
88 
90 
91  void checkPcEventQueue();
92  void swapActiveThread();
93 
94  public:
95  BaseSimpleCPU(const BaseSimpleCPUParams &params);
96  virtual ~BaseSimpleCPU();
97  void wakeup(ThreadID tid) override;
98  public:
101 
104 
108 
109  protected:
110  enum Status
111  {
123  };
124 
126 
133  void traceFault();
134 
135  std::unique_ptr<PCStateBase> preExecuteTempPC;
136 
137  public:
138  void checkForInterrupts();
139  void setupFetchRequest(const RequestPtr &req);
140  void serviceInstCountEvents();
141  void preExecute();
142  void postExecute();
143  void advancePC(const Fault &fault);
144 
145  void haltContext(ThreadID thread_num) override;
146 
147  // statistics
148  void resetStats() override;
149 
150  virtual Fault
151  readMem(Addr addr, uint8_t* data, unsigned size, Request::Flags flags,
152  const std::vector<bool>& byte_enable=std::vector<bool>())
153  {
154  panic("readMem() is not implemented");
155  }
156 
157  virtual Fault
158  initiateMemRead(Addr addr, unsigned size, Request::Flags flags,
159  const std::vector<bool>& byte_enable=std::vector<bool>())
160  {
161  panic("initiateMemRead() is not implemented\n");
162  }
163 
164  virtual Fault
165  writeMem(uint8_t* data, unsigned size, Addr addr, Request::Flags flags,
166  uint64_t* res,
167  const std::vector<bool>& byte_enable=std::vector<bool>())
168  {
169  panic("writeMem() is not implemented\n");
170  }
171 
172  virtual Fault
173  amoMem(Addr addr, uint8_t* data, unsigned size, Request::Flags flags,
174  AtomicOpFunctorPtr amo_op)
175  {
176  panic("amoMem() is not implemented\n");
177  }
178 
179  virtual Fault
180  initiateMemAMO(Addr addr, unsigned size, Request::Flags flags,
181  AtomicOpFunctorPtr amo_op)
182  {
183  panic("initiateMemAMO() is not implemented\n");
184  }
185 
186  void countInst();
187  Counter totalInsts() const override;
188  Counter totalOps() const override;
189 
190  void serializeThread(CheckpointOut &cp, ThreadID tid) const override;
191  void unserializeThread(CheckpointIn &cp, ThreadID tid) override;
192 
197  virtual Fault initiateHtmCmd(Request::Flags flags) = 0;
198 };
199 
200 } // namespace gem5
201 
202 #endif // __CPU_SIMPLE_BASE_HH__
gem5::BaseSimpleCPU::initiateMemAMO
virtual Fault initiateMemAMO(Addr addr, unsigned size, Request::Flags flags, AtomicOpFunctorPtr amo_op)
Definition: base.hh:180
gem5::BaseSimpleCPU::serializeThread
void serializeThread(CheckpointOut &cp, ThreadID tid) const override
Definition: base.cc:209
gem5::BaseSimpleCPU::DcacheRetry
@ DcacheRetry
Definition: base.hh:120
gem5::BaseSimpleCPU::totalOps
Counter totalOps() const override
Definition: base.cc:177
gem5::BaseSimpleCPU::threadInfo
std::vector< SimpleExecContext * > threadInfo
Definition: base.hh:102
system.hh
data
const char data[]
Definition: circlebuf.test.cc:48
gem5::BaseSimpleCPU::traceData
Trace::InstRecord * traceData
Definition: base.hh:99
gem5::BaseSimpleCPU::_status
Status _status
Definition: base.hh:125
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::BaseSimpleCPU::curStaticInst
StaticInstPtr curStaticInst
Current instruction.
Definition: base.hh:106
gem5::BaseSimpleCPU::amoMem
virtual Fault amoMem(Addr addr, uint8_t *data, unsigned size, Request::Flags flags, AtomicOpFunctorPtr amo_op)
Definition: base.hh:173
gem5::BaseSimpleCPU::ITBWaitResponse
@ ITBWaitResponse
Definition: base.hh:115
std::vector
STL vector class.
Definition: stl.hh:37
gem5::BaseSimpleCPU::BaseSimpleCPU
BaseSimpleCPU(const BaseSimpleCPUParams &params)
Definition: base.cc:84
gem5::BaseSimpleCPU::unserializeThread
void unserializeThread(CheckpointIn &cp, ThreadID tid) override
Definition: base.cc:217
gem5::BaseSimpleCPU::IcacheRetry
@ IcacheRetry
Definition: base.hh:116
gem5::BaseSimpleCPU::~BaseSimpleCPU
virtual ~BaseSimpleCPU()
Definition: base.cc:187
request.hh
gem5::BaseSimpleCPU::checkForInterrupts
void checkForInterrupts()
Definition: base.cc:250
gem5::RefCountingPtr< StaticInst >
packet.hh
gem5::BaseSimpleCPU::writeMem
virtual Fault writeMem(uint8_t *data, unsigned size, Addr addr, Request::Flags flags, uint64_t *res, const std::vector< bool > &byte_enable=std::vector< bool >())
Definition: base.hh:165
gem5::Flags< FlagsType >
gem5::BaseSimpleCPU::readMem
virtual Fault readMem(Addr addr, uint8_t *data, unsigned size, Request::Flags flags, const std::vector< bool > &byte_enable=std::vector< bool >())
Definition: base.hh:151
gem5::BaseSimpleCPU::checkPcEventQueue
void checkPcEventQueue()
Definition: base.cc:125
gem5::BaseSimpleCPU::Status
Status
Definition: base.hh:110
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::BaseSimpleCPU::preExecute
void preExecute()
Definition: base.cc:305
statistics.hh
gem5::CheckerCPU
CheckerCPU class.
Definition: cpu.hh:84
gem5::BaseSimpleCPU::setupFetchRequest
void setupFetchRequest(const RequestPtr &req)
Definition: base.cc:281
cpu.hh
gem5::BaseSimpleCPU::preExecuteTempPC
std::unique_ptr< PCStateBase > preExecuteTempPC
Definition: base.hh:135
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::BaseSimpleCPU::DTBWaitResponse
@ DTBWaitResponse
Definition: base.hh:119
port.hh
gem5::BaseSimpleCPU::activeThreads
std::list< ThreadID > activeThreads
Definition: base.hh:103
gem5::BaseSimpleCPU
Definition: base.hh:83
static_inst.hh
gem5::BaseSimpleCPU::traceFault
void traceFault()
Handler used when encountering a fault; its purpose is to tear down the InstRecord.
Definition: base.cc:239
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::BaseSimpleCPU::IcacheWaitSwitch
@ IcacheWaitSwitch
Definition: base.hh:118
full_system.hh
gem5::BaseSimpleCPU::postExecute
void postExecute()
Definition: base.cc:387
gem5::BaseSimpleCPU::Faulting
@ Faulting
Definition: base.hh:114
pcstate.hh
gem5::BaseSimpleCPU::branchPred
branch_prediction::BPredUnit * branchPred
Definition: base.hh:87
simple_thread.hh
gem5::BaseSimpleCPU::zeroReg
const RegIndex zeroReg
Definition: base.hh:89
gem5::BaseSimpleCPU::countInst
void countInst()
Definition: base.cc:153
gem5::BaseSimpleCPU::resetStats
void resetStats() override
Definition: base.cc:200
base.hh
pc_event.hh
gem5::BaseSimpleCPU::Running
@ Running
Definition: base.hh:113
gem5::BaseSimpleCPU::initiateMemRead
virtual Fault initiateMemRead(Addr addr, unsigned size, Request::Flags flags, const std::vector< bool > &byte_enable=std::vector< bool >())
Definition: base.hh:158
gem5::BaseSimpleCPU::swapActiveThread
void swapActiveThread()
Definition: base.cc:137
exec_context.hh
gem5::BaseSimpleCPU::IcacheWaitResponse
@ IcacheWaitResponse
Definition: base.hh:117
gem5::statistics::Counter
double Counter
All counters are of 64-bit values.
Definition: types.hh:47
gem5::BaseSimpleCPU::serviceInstCountEvents
void serviceInstCountEvents()
Definition: base.cc:298
gem5::branch_prediction::BPredUnit
Basically a wrapper class to hold both the branch predictor and the BTB.
Definition: bpred_unit.hh:68
gem5::BaseSimpleCPU::wakeup
void wakeup(ThreadID tid) override
Definition: base.cc:228
gem5::BaseSimpleCPU::advancePC
void advancePC(const Fault &fault)
Definition: base.cc:462
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::BaseSimpleCPU::checker
CheckerCPU * checker
Definition: base.hh:100
gem5::Trace::InstRecord
Definition: insttracer.hh:61
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
std::list< ThreadID >
gem5::BaseSimpleCPU::haltContext
void haltContext(ThreadID thread_num) override
Definition: base.cc:192
gem5::AtomicOpFunctorPtr
std::unique_ptr< AtomicOpFunctor > AtomicOpFunctorPtr
Definition: amo.hh:242
gem5::BaseSimpleCPU::DcacheWaitResponse
@ DcacheWaitResponse
Definition: base.hh:121
gem5::BaseSimpleCPU::totalInsts
Counter totalInsts() const override
Definition: base.cc:166
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::BaseSimpleCPU::Idle
@ Idle
Definition: base.hh:112
gem5::BaseSimpleCPU::curMacroStaticInst
StaticInstPtr curMacroStaticInst
Definition: base.hh:107
gem5::BaseSimpleCPU::initiateHtmCmd
virtual Fault initiateHtmCmd(Request::Flags flags)=0
Hardware transactional memory commands (HtmCmds), e.g.
gem5::BaseSimpleCPU::curThread
ThreadID curThread
Definition: base.hh:86
gem5::BaseSimpleCPU::DcacheWaitSwitch
@ DcacheWaitSwitch
Definition: base.hh:122
gem5::ThreadID
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:242
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
eventq.hh

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