gem5  v21.1.0.2
base.cc
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41 
42 #include "cpu/simple/base.hh"
43 
44 #include "base/cprintf.hh"
45 #include "base/inifile.hh"
46 #include "base/loader/symtab.hh"
47 #include "base/logging.hh"
48 #include "base/pollevent.hh"
49 #include "base/trace.hh"
50 #include "base/types.hh"
51 #include "config/the_isa.hh"
52 #include "cpu/base.hh"
53 #include "cpu/checker/cpu.hh"
55 #include "cpu/exetrace.hh"
56 #include "cpu/null_static_inst.hh"
57 #include "cpu/pred/bpred_unit.hh"
59 #include "cpu/simple_thread.hh"
60 #include "cpu/smt.hh"
61 #include "cpu/static_inst.hh"
62 #include "cpu/thread_context.hh"
63 #include "debug/Decode.hh"
64 #include "debug/ExecFaulting.hh"
65 #include "debug/Fetch.hh"
66 #include "debug/HtmCpu.hh"
67 #include "debug/Quiesce.hh"
68 #include "mem/packet.hh"
69 #include "mem/request.hh"
70 #include "params/BaseSimpleCPU.hh"
71 #include "sim/byteswap.hh"
72 #include "sim/debug.hh"
73 #include "sim/faults.hh"
74 #include "sim/full_system.hh"
75 #include "sim/sim_events.hh"
76 #include "sim/sim_object.hh"
77 #include "sim/stats.hh"
78 #include "sim/system.hh"
79 
80 namespace gem5
81 {
82 
83 BaseSimpleCPU::BaseSimpleCPU(const BaseSimpleCPUParams &p)
84  : BaseCPU(p),
85  curThread(0),
86  branchPred(p.branchPred),
87  zeroReg(p.isa[0]->regClasses().at(IntRegClass).zeroReg()),
88  traceData(NULL),
89  _status(Idle)
90 {
91  SimpleThread *thread;
92 
93  for (unsigned i = 0; i < numThreads; i++) {
94  if (FullSystem) {
95  thread = new SimpleThread(
96  this, i, p.system, p.mmu, p.isa[i]);
97  } else {
98  thread = new SimpleThread(
99  this, i, p.system, p.workload[i], p.mmu, p.isa[i]);
100  }
101  threadInfo.push_back(new SimpleExecContext(this, thread));
102  ThreadContext *tc = thread->getTC();
103  threadContexts.push_back(tc);
104  }
105 
106  if (p.checker) {
107  if (numThreads != 1)
108  fatal("Checker currently does not support SMT");
109 
110  BaseCPU *temp_checker = p.checker;
111  checker = dynamic_cast<CheckerCPU *>(temp_checker);
112  checker->setSystem(p.system);
113  // Manipulate thread context
114  ThreadContext *cpu_tc = threadContexts[0];
116  } else {
117  checker = NULL;
118  }
119 }
120 
121 void
123 {
124  BaseCPU::init();
125 
126  for (auto tc : threadContexts) {
127  // Initialise the ThreadContext's memory proxies
128  tc->initMemProxies(tc);
129  }
130 }
131 
132 void
134 {
135  Addr oldpc, pc = threadInfo[curThread]->thread->instAddr();
136  do {
137  oldpc = pc;
138  threadInfo[curThread]->thread->pcEventQueue.service(
139  oldpc, threadContexts[curThread]);
140  pc = threadInfo[curThread]->thread->instAddr();
141  } while (oldpc != pc);
142 }
143 
144 void
146 {
147  if (numThreads > 1) {
149  !threadInfo[curThread]->stayAtPC) {
150  // Swap active threads
151  if (!activeThreads.empty()) {
152  curThread = activeThreads.front();
153  activeThreads.pop_front();
154  activeThreads.push_back(curThread);
155  }
156  }
157  }
158 }
159 
160 void
162 {
164 
166  t_info.numInst++;
167  t_info.execContextStats.numInsts++;
168  }
169  t_info.numOp++;
170  t_info.execContextStats.numOps++;
171 }
172 
173 Counter
175 {
176  Counter total_inst = 0;
177  for (auto& t_info : threadInfo) {
178  total_inst += t_info->numInst;
179  }
180 
181  return total_inst;
182 }
183 
184 Counter
186 {
187  Counter total_op = 0;
188  for (auto& t_info : threadInfo) {
189  total_op += t_info->numOp;
190  }
191 
192  return total_op;
193 }
194 
196 {
197 }
198 
199 void
201 {
202  // for now, these are equivalent
203  suspendContext(thread_num);
205 }
206 
207 void
209 {
211  for (auto &thread_info : threadInfo) {
212  thread_info->execContextStats.notIdleFraction = (_status != Idle);
213  }
214 }
215 
216 void
218 {
219  assert(_status == Idle || _status == Running);
220 
221  threadInfo[tid]->thread->serialize(cp);
222 }
223 
224 void
226 {
227  threadInfo[tid]->thread->unserialize(cp);
228 }
229 
230 void
231 change_thread_state(ThreadID tid, int activate, int priority)
232 {
233 }
234 
235 void
237 {
238  getCpuAddrMonitor(tid)->gotWakeup = true;
239 
240  if (threadInfo[tid]->thread->status() == ThreadContext::Suspended) {
241  DPRINTF(Quiesce,"[tid:%d] Suspended Processor awoke\n", tid);
242  threadInfo[tid]->thread->activate();
243  }
244 }
245 
246 void
248 {
249  if (debug::ExecFaulting) {
250  traceData->setFaulting(true);
251  } else {
252  delete traceData;
253  traceData = NULL;
254  }
255 }
256 
257 void
259 {
261  SimpleThread* thread = t_info.thread;
262  ThreadContext* tc = thread->getTC();
263 
264  if (checkInterrupts(curThread)) {
265  Fault interrupt = interrupts[curThread]->getInterrupt();
266 
267  if (interrupt != NoFault) {
268  // hardware transactional memory
269  // Postpone taking interrupts while executing transactions.
270  assert(!std::dynamic_pointer_cast<GenericHtmFailureFault>(
271  interrupt));
272  if (t_info.inHtmTransactionalState()) {
273  DPRINTF(HtmCpu, "Deferring pending interrupt - %s -"
274  "due to transactional state\n",
275  interrupt->name());
276  return;
277  }
278 
279  t_info.fetchOffset = 0;
280  interrupts[curThread]->updateIntrInfo();
281  interrupt->invoke(tc);
282  thread->decoder.reset();
283  }
284  }
285 }
286 
287 
288 void
290 {
292  SimpleThread* thread = t_info.thread;
293 
294  auto &decoder = thread->decoder;
295  Addr instAddr = thread->instAddr();
296  Addr fetchPC = (instAddr & decoder.pcMask()) + t_info.fetchOffset;
297 
298  // set up memory request for instruction fetch
299  DPRINTF(Fetch, "Fetch: Inst PC:%08p, Fetch PC:%08p\n", instAddr, fetchPC);
300 
301  req->setVirt(fetchPC, decoder.moreBytesSize(), Request::INST_FETCH,
302  instRequestorId(), instAddr);
303 }
304 
305 void
307 {
310 }
311 
312 void
314 {
316  SimpleThread* thread = t_info.thread;
317 
318  // maintain $r0 semantics
319  thread->setIntReg(zeroReg, 0);
320 
321  // resets predicates
322  t_info.setPredicate(true);
323  t_info.setMemAccPredicate(true);
324 
325  // decode the instruction
326  TheISA::PCState pcState = thread->pcState();
327 
328  auto &decoder = thread->decoder;
329 
330  if (isRomMicroPC(pcState.microPC())) {
331  t_info.stayAtPC = false;
332  curStaticInst = decoder.fetchRomMicroop(
333  pcState.microPC(), curMacroStaticInst);
334  } else if (!curMacroStaticInst) {
335  //We're not in the middle of a macro instruction
336  StaticInstPtr instPtr = NULL;
337 
338  //Predecode, ie bundle up an ExtMachInst
339  //If more fetch data is needed, pass it in.
340  Addr fetchPC =
341  (pcState.instAddr() & decoder.pcMask()) + t_info.fetchOffset;
342 
343  decoder.moreBytes(pcState, fetchPC);
344 
345  //Decode an instruction if one is ready. Otherwise, we'll have to
346  //fetch beyond the MachInst at the current pc.
347  instPtr = decoder.decode(pcState);
348  if (instPtr) {
349  t_info.stayAtPC = false;
350  thread->pcState(pcState);
351  } else {
352  t_info.stayAtPC = true;
353  t_info.fetchOffset += decoder.moreBytesSize();
354  }
355 
356  //If we decoded an instruction and it's microcoded, start pulling
357  //out micro ops
358  if (instPtr && instPtr->isMacroop()) {
359  curMacroStaticInst = instPtr;
360  curStaticInst =
361  curMacroStaticInst->fetchMicroop(pcState.microPC());
362  } else {
363  curStaticInst = instPtr;
364  }
365  } else {
366  //Read the next micro op from the macro op
367  curStaticInst = curMacroStaticInst->fetchMicroop(pcState.microPC());
368  }
369 
370  //If we decoded an instruction this "tick", record information about it.
371  if (curStaticInst) {
372 #if TRACING_ON
373  traceData = tracer->getInstRecord(curTick(), thread->getTC(),
375 #endif // TRACING_ON
376  }
377 
378  if (branchPred && curStaticInst &&
380  // Use a fake sequence number since we only have one
381  // instruction in flight at the same time.
382  const InstSeqNum cur_sn(0);
383  t_info.predPC = thread->pcState();
384  const bool predict_taken(
385  branchPred->predict(curStaticInst, cur_sn, t_info.predPC,
386  curThread));
387 
388  if (predict_taken)
390  }
391 }
392 
393 void
395 {
397 
398  assert(curStaticInst);
399 
401  Addr instAddr = pc.instAddr();
402 
403  if (curStaticInst->isMemRef()) {
404  t_info.execContextStats.numMemRefs++;
405  }
406 
407  if (curStaticInst->isLoad()) {
408  ++t_info.numLoad;
409  }
410 
411  if (curStaticInst->isControl()) {
412  ++t_info.execContextStats.numBranches;
413  }
414 
415  /* Power model statistics */
416  //integer alu accesses
417  if (curStaticInst->isInteger()){
419  t_info.execContextStats.numIntInsts++;
420  }
421 
422  //float alu accesses
423  if (curStaticInst->isFloating()){
425  t_info.execContextStats.numFpInsts++;
426  }
427 
428  //vector alu accesses
429  if (curStaticInst->isVector()){
431  t_info.execContextStats.numVecInsts++;
432  }
433 
434  //number of function calls/returns to get window accesses
437  }
438 
439  //the number of branch predictions that will be made
440  if (curStaticInst->isCondCtrl()){
442  }
443 
444  //result bus acceses
445  if (curStaticInst->isLoad()){
447  }
448 
451  }
452  /* End power model statistics */
453 
455 
456  if (FullSystem)
457  traceFunctions(instAddr);
458 
459  if (traceData) {
460  traceData->dump();
461  delete traceData;
462  traceData = NULL;
463  }
464 
465  // Call CPU instruction commit probes
466  probeInstCommit(curStaticInst, instAddr);
467 }
468 
469 void
471 {
473  SimpleThread* thread = t_info.thread;
474 
475  const bool branching(thread->pcState().branching());
476 
477  //Since we're moving to a new pc, zero out the offset
478  t_info.fetchOffset = 0;
479  if (fault != NoFault) {
481  fault->invoke(threadContexts[curThread], curStaticInst);
482  thread->decoder.reset();
483  } else {
484  if (curStaticInst) {
487  TheISA::PCState pcState = thread->pcState();
488  curStaticInst->advancePC(pcState);
489  thread->pcState(pcState);
490  }
491  }
492 
494  // Use a fake sequence number since we only have one
495  // instruction in flight at the same time.
496  const InstSeqNum cur_sn(0);
497 
498  if (t_info.predPC == thread->pcState()) {
499  // Correctly predicted branch
500  branchPred->update(cur_sn, curThread);
501  } else {
502  // Mis-predicted branch
503  branchPred->squash(cur_sn, thread->pcState(), branching, curThread);
505  }
506  }
507 }
508 
509 } // namespace gem5
gem5::curTick
Tick curTick()
The universal simulation clock.
Definition: cur_tick.hh:46
fatal
#define fatal(...)
This implements a cprintf based fatal() function.
Definition: logging.hh:189
gem5::branch_prediction::BPredUnit::update
void update(const InstSeqNum &done_sn, ThreadID tid)
Tells the branch predictor to commit any updates until the given sequence number.
Definition: bpred_unit.cc:305
gem5::BaseSimpleCPU::serializeThread
void serializeThread(CheckpointOut &cp, ThreadID tid) const override
Serialize a single thread.
Definition: base.cc:217
gem5::Trace::InstRecord::setFaulting
void setFaulting(bool val)
Definition: insttracer.hh:230
gem5::SimpleExecContext::numOp
Counter numOp
Definition: exec_context.hh:77
gem5::BaseSimpleCPU::totalOps
Counter totalOps() const override
Definition: base.cc:185
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:260
gem5::BaseCPU::tracer
Trace::InstTracer * tracer
Definition: base.hh:264
gem5::StaticInst::isMicroop
bool isMicroop() const
Definition: static_inst.hh:208
gem5::BaseCPU::interrupts
std::vector< BaseInterrupts * > interrupts
Definition: base.hh:225
gem5::BaseSimpleCPU::threadInfo
std::vector< SimpleExecContext * > threadInfo
Definition: base.hh:100
gem5::SimpleThread::setIntReg
void setIntReg(RegIndex reg_idx, RegVal val) override
Definition: simple_thread.hh:367
system.hh
gem5::BaseSimpleCPU::traceData
Trace::InstRecord * traceData
Definition: base.hh:97
sim_events.hh
gem5::SimpleExecContext::numLoad
Counter numLoad
Definition: exec_context.hh:79
gem5::isRomMicroPC
static bool isRomMicroPC(MicroPC upc)
Definition: types.hh:166
gem5::SimpleExecContext::ExecContextStats::numCallsReturns
statistics::Scalar numCallsReturns
Definition: exec_context.hh:206
gem5::BaseSimpleCPU::_status
Status _status
Definition: base.hh:123
gem5::StaticInst::isControl
bool isControl() const
Definition: static_inst.hh:182
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::SimpleThread::instAddr
Addr instAddr() const override
Definition: simple_thread.hh:439
gem5::BaseCPU::updateCycleCounters
void updateCycleCounters(CPUState state)
base method keeping track of cycle progression
Definition: base.hh:523
gem5::BaseCPU::init
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: base.cc:272
gem5::BaseSimpleCPU::curStaticInst
StaticInstPtr curStaticInst
Current instruction.
Definition: base.hh:104
exetrace.hh
gem5::SimpleExecContext::execContextStats
gem5::SimpleExecContext::ExecContextStats execContextStats
gem5::StaticInst::isCondCtrl
bool isCondCtrl() const
Definition: static_inst.hh:187
gem5::linux::thread_info
Definition: thread_info.hh:40
gem5::StaticInst::isDelayedCommit
bool isDelayedCommit() const
Definition: static_inst.hh:209
gem5::BaseSimpleCPU::BaseSimpleCPU
BaseSimpleCPU(const BaseSimpleCPUParams &params)
Definition: base.cc:83
gem5::BaseSimpleCPU::unserializeThread
void unserializeThread(CheckpointIn &cp, ThreadID tid) override
Unserialize one thread.
Definition: base.cc:225
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
gem5::CheckerThreadContext
Derived ThreadContext class for use with the Checker.
Definition: thread_context.hh:69
gem5::statistics::Group::resetStats
virtual void resetStats()
Callback to reset stats.
Definition: group.cc:86
faults.hh
gem5::BaseSimpleCPU::~BaseSimpleCPU
virtual ~BaseSimpleCPU()
Definition: base.cc:195
gem5::SimpleThread
The SimpleThread object provides a combination of the ThreadState object and the ThreadContext interf...
Definition: simple_thread.hh:94
gem5::SimpleExecContext::ExecContextStats::numPredictedBranches
statistics::Scalar numPredictedBranches
Number of branches predicted as taken.
Definition: exec_context.hh:265
request.hh
gem5::EventQueue::serviceEvents
void serviceEvents(Tick when)
process all events up to the given timestamp.
Definition: eventq.hh:876
gem5::SimpleExecContext::ExecContextStats::numVecInsts
statistics::Scalar numVecInsts
Definition: exec_context.hh:218
gem5::SimpleExecContext::setPredicate
void setPredicate(bool val) override
Definition: exec_context.hh:552
gem5::BaseSimpleCPU::checkForInterrupts
void checkForInterrupts()
Definition: base.cc:258
gem5::RefCountingPtr< StaticInst >
packet.hh
gem5::StaticInst::fetchMicroop
virtual StaticInstPtr fetchMicroop(MicroPC upc) const
Return the microop that goes with a particular micropc.
Definition: static_inst.cc:54
gem5::ArmISA::at
Bitfield< 35, 32 > at
Definition: misc_types.hh:154
gem5::StaticInst::opClass
OpClass opClass() const
Operation class. Used to select appropriate function unit in issue.
Definition: static_inst.hh:232
gem5::BaseCPU::numThreads
ThreadID numThreads
Number of threads we're actually simulating (<= SMT_MAX_THREADS).
Definition: base.hh:368
stats.hh
gem5::StaticInst::isFloating
bool isFloating() const
Definition: static_inst.hh:179
gem5::SimpleThread::decoder
TheISA::Decoder decoder
Definition: simple_thread.hh:136
gem5::nullStaticInstPtr
const StaticInstPtr nullStaticInstPtr
Statically allocated null StaticInstPtr.
Definition: null_static_inst.cc:36
gem5::StaticInst::isReturn
bool isReturn() const
Definition: static_inst.hh:184
gem5::BaseCPU::suspendContext
virtual void suspendContext(ThreadID thread_num)
Notify the CPU that the indicated context is now suspended.
Definition: base.cc:502
smt.hh
gem5::BaseSimpleCPU::checkPcEventQueue
void checkPcEventQueue()
Definition: base.cc:133
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::SimpleExecContext::ExecContextStats::numInsts
statistics::Scalar numInsts
Definition: exec_context.hh:193
gem5::SimpleExecContext::fetchOffset
Addr fetchOffset
Definition: exec_context.hh:67
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::SimpleExecContext::inHtmTransactionalState
bool inHtmTransactionalState() const override
Definition: exec_context.hh:586
sim_object.hh
gem5::StaticInst::isAtomic
bool isAtomic() const
Definition: static_inst.hh:171
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::ThreadContext::Suspended
@ Suspended
Temporarily inactive.
Definition: thread_context.hh:112
gem5::BaseSimpleCPU::preExecute
void preExecute()
Definition: base.cc:313
gem5::MipsISA::PCState
GenericISA::DelaySlotPCState< 4 > PCState
Definition: pcstate.hh:40
debug.hh
gem5::SimpleExecContext::ExecContextStats::numCondCtrlInsts
statistics::Scalar numCondCtrlInsts
Definition: exec_context.hh:209
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
pollevent.hh
gem5::CheckerCPU
CheckerCPU class.
Definition: cpu.hh:84
gem5::SimpleExecContext::stayAtPC
bool stayAtPC
Definition: exec_context.hh:70
gem5::BaseSimpleCPU::setupFetchRequest
void setupFetchRequest(const RequestPtr &req)
Definition: base.cc:289
cpu.hh
gem5::BaseCPU::instRequestorId
RequestorID instRequestorId() const
Reads this CPU's unique instruction requestor ID.
Definition: base.hh:196
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::Request::INST_FETCH
@ INST_FETCH
The request was an instruction fetch.
Definition: request.hh:115
gem5::BaseSimpleCPU::activeThreads
std::list< ThreadID > activeThreads
Definition: base.hh:101
gem5::StaticInst::isLoad
bool isLoad() const
Definition: static_inst.hh:169
gem5::SimpleExecContext::ExecContextStats::statExecutedInstType
statistics::Vector statExecutedInstType
Definition: exec_context.hh:271
gem5::StaticInst::isStore
bool isStore() const
Definition: static_inst.hh:170
gem5::BaseCPU
Definition: base.hh:107
cprintf.hh
static_inst.hh
gem5::BaseSimpleCPU::traceFault
void traceFault()
Handler used when encountering a fault; its purpose is to tear down the InstRecord.
Definition: base.cc:247
gem5::SimpleExecContext::numInst
Counter numInst
PER-THREAD STATS.
Definition: exec_context.hh:76
inifile.hh
gem5::SimpleThread::pcState
TheISA::PCState pcState() const override
Definition: simple_thread.hh:430
gem5::StaticInst::isVector
bool isVector() const
Definition: static_inst.hh:180
gem5::Trace::InstTracer::getInstRecord
virtual InstRecord * getInstRecord(Tick when, ThreadContext *tc, const StaticInstPtr staticInst, TheISA::PCState pc, const StaticInstPtr macroStaticInst=NULL)=0
gem5::branch_prediction::BPredUnit::squash
void squash(const InstSeqNum &squashed_sn, ThreadID tid)
Squashes all outstanding updates until a given sequence number.
Definition: bpred_unit.cc:328
null_static_inst.hh
gem5::BaseCPU::getCpuAddrMonitor
AddressMonitor * getCpuAddrMonitor(ThreadID tid)
Definition: base.hh:609
gem5::BaseCPU::probeInstCommit
virtual void probeInstCommit(const StaticInstPtr &inst, Addr pc)
Helper method to trigger PMU probes for a committed instruction.
Definition: base.cc:356
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::AddressMonitor::gotWakeup
bool gotWakeup
Definition: base.hh:83
gem5::StaticInst::isLastMicroop
bool isLastMicroop() const
Definition: static_inst.hh:210
gem5::SimpleExecContext::ExecContextStats::numFpInsts
statistics::Scalar numFpInsts
Definition: exec_context.hh:215
gem5::StaticInst::isMemRef
bool isMemRef() const
Definition: static_inst.hh:165
full_system.hh
gem5::SimpleExecContext::ExecContextStats::numVecAluAccesses
statistics::Scalar numVecAluAccesses
Definition: exec_context.hh:203
gem5::SimpleExecContext::ExecContextStats::numStoreInsts
statistics::Scalar numStoreInsts
Definition: exec_context.hh:243
gem5::BaseSimpleCPU::postExecute
void postExecute()
Definition: base.cc:394
gem5::SimpleExecContext::predPC
TheISA::PCState predPC
Definition: exec_context.hh:73
gem5::Trace::InstRecord::dump
virtual void dump()=0
gem5::BaseCPU::CPU_STATE_SLEEP
@ CPU_STATE_SLEEP
Definition: base.hh:515
gem5::SimpleExecContext::thread
SimpleThread * thread
Definition: exec_context.hh:64
gem5::FullSystem
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:223
gem5::SimpleThread::getTC
ThreadContext * getTC()
Returns the pointer to this SimpleThread's ThreadContext.
Definition: simple_thread.hh:169
base.hh
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Definition: exec_context.hh:242
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Definition: base.hh:84
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Definition: base.hh:262
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Definition: base.hh:86
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Definition: base.cc:161
gem5::BaseSimpleCPU::resetStats
void resetStats() override
Callback to reset stats.
Definition: base.cc:208
gem5::SimpleExecContext::ExecContextStats::numIntInsts
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Definition: exec_context.hh:212
gem5::SimpleExecContext::ExecContextStats::numIntAluAccesses
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Definition: exec_context.hh:197
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Definition: exec_context.hh:568
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Definition: base.hh:563
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Definition: exec_context.hh:60
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Definition: base.hh:111
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Definition: static_inst.hh:207
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Definition: base.hh:256
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Definition: base.cc:145
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Definition: pra_constants.hh:243
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All counters are of 64-bit values.
Definition: types.hh:47
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Definition: base.cc:306
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Definition: exec_context.hh:200
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Definition: base.cc:236
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Definition: static_inst.hh:178
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Definition: base.cc:470
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Definition: static_inst.hh:183
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Definition: inst_seq.hh:40
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Definition: exec_context.hh:263
gem5::SimpleExecContext::ExecContextStats::numOps
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Definition: exec_context.hh:194
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Definition: serialize.hh:66
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Definition: base.hh:98
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Definition: nop.cc:61
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Notify the CPU that the indicated context is now halted.
Definition: base.cc:200
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Number of misprediced branches.
Definition: exec_context.hh:267
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Changes the status and priority of the thread with the given number.
Definition: base.cc:231
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Counter totalInsts() const override
Definition: base.cc:174
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@ IntRegClass
Integer register.
Definition: reg_class.hh:57
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Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
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@ Idle
Definition: base.hh:110
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Definition: base.hh:105
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An instruction-based event queue.
Definition: simple_thread.hh:130
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virtual void advancePC(TheISA::PCState &pc_state) const =0
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Definition: base.hh:83
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Definition: exec_context.hh:241
gem5::branch_prediction::BPredUnit::predict
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Predicts whether or not the instruction is a taken branch, and the target of the branch if it is take...
Definition: bpred_unit.cc:130
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Thread index/ID type.
Definition: types.hh:242
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Definition: base.cc:122
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Definition: cpu.cc:97

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