gem5  v22.0.0.2
base.cc
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41 
42 #include "cpu/simple/base.hh"
43 
44 #include "arch/generic/decoder.hh"
45 #include "base/cprintf.hh"
46 #include "base/inifile.hh"
47 #include "base/loader/symtab.hh"
48 #include "base/logging.hh"
49 #include "base/pollevent.hh"
50 #include "base/trace.hh"
51 #include "base/types.hh"
52 #include "config/the_isa.hh"
53 #include "cpu/base.hh"
54 #include "cpu/checker/cpu.hh"
56 #include "cpu/exetrace.hh"
57 #include "cpu/null_static_inst.hh"
58 #include "cpu/pred/bpred_unit.hh"
60 #include "cpu/simple_thread.hh"
61 #include "cpu/smt.hh"
62 #include "cpu/static_inst.hh"
63 #include "cpu/thread_context.hh"
64 #include "debug/Decode.hh"
65 #include "debug/ExecFaulting.hh"
66 #include "debug/Fetch.hh"
67 #include "debug/HtmCpu.hh"
68 #include "debug/Quiesce.hh"
69 #include "mem/packet.hh"
70 #include "mem/request.hh"
71 #include "params/BaseSimpleCPU.hh"
72 #include "sim/byteswap.hh"
73 #include "sim/debug.hh"
74 #include "sim/faults.hh"
75 #include "sim/full_system.hh"
76 #include "sim/sim_events.hh"
77 #include "sim/sim_object.hh"
78 #include "sim/stats.hh"
79 #include "sim/system.hh"
80 
81 namespace gem5
82 {
83 
84 BaseSimpleCPU::BaseSimpleCPU(const BaseSimpleCPUParams &p)
85  : BaseCPU(p),
86  curThread(0),
87  branchPred(p.branchPred),
88  traceData(NULL),
89  _status(Idle)
90 {
91  SimpleThread *thread;
92 
93  for (unsigned i = 0; i < numThreads; i++) {
94  if (FullSystem) {
95  thread = new SimpleThread(
96  this, i, p.system, p.mmu, p.isa[i], p.decoder[i]);
97  } else {
98  thread = new SimpleThread(
99  this, i, p.system, p.workload[i], p.mmu, p.isa[i],
100  p.decoder[i]);
101  }
102  threadInfo.push_back(new SimpleExecContext(this, thread));
103  ThreadContext *tc = thread->getTC();
104  threadContexts.push_back(tc);
105  }
106 
107  if (p.checker) {
108  if (numThreads != 1)
109  fatal("Checker currently does not support SMT");
110 
111  BaseCPU *temp_checker = p.checker;
112  checker = dynamic_cast<CheckerCPU *>(temp_checker);
113  checker->setSystem(p.system);
114  // Manipulate thread context
115  ThreadContext *cpu_tc = threadContexts[0];
116  threadContexts[0] = new CheckerThreadContext<ThreadContext>(
117  cpu_tc, this->checker);
118  } else {
119  checker = NULL;
120  }
121 }
122 
123 void
125 {
126  Addr oldpc, pc = threadInfo[curThread]->thread->pcState().instAddr();
127  do {
128  oldpc = pc;
129  threadInfo[curThread]->thread->pcEventQueue.service(
130  oldpc, threadContexts[curThread]);
131  pc = threadInfo[curThread]->thread->pcState().instAddr();
132  } while (oldpc != pc);
133 }
134 
135 void
137 {
138  if (numThreads > 1) {
140  !threadInfo[curThread]->stayAtPC) {
141  // Swap active threads
142  if (!activeThreads.empty()) {
143  curThread = activeThreads.front();
144  activeThreads.pop_front();
145  activeThreads.push_back(curThread);
146  }
147  }
148  }
149 }
150 
151 void
153 {
155 
157  t_info.numInst++;
158  t_info.execContextStats.numInsts++;
159  }
160  t_info.numOp++;
161  t_info.execContextStats.numOps++;
162 }
163 
164 Counter
166 {
167  Counter total_inst = 0;
168  for (auto& t_info : threadInfo) {
169  total_inst += t_info->numInst;
170  }
171 
172  return total_inst;
173 }
174 
175 Counter
177 {
178  Counter total_op = 0;
179  for (auto& t_info : threadInfo) {
180  total_op += t_info->numOp;
181  }
182 
183  return total_op;
184 }
185 
187 {
188 }
189 
190 void
192 {
193  // for now, these are equivalent
194  suspendContext(thread_num);
195  updateCycleCounters(BaseCPU::CPU_STATE_SLEEP);
196 }
197 
198 void
200 {
201  BaseCPU::resetStats();
202  for (auto &thread_info : threadInfo) {
203  thread_info->execContextStats.notIdleFraction = (_status != Idle);
204  }
205 }
206 
207 void
209 {
210  assert(_status == Idle || _status == Running);
211 
212  threadInfo[tid]->thread->serialize(cp);
213 }
214 
215 void
217 {
218  threadInfo[tid]->thread->unserialize(cp);
219 }
220 
221 void
222 change_thread_state(ThreadID tid, int activate, int priority)
223 {
224 }
225 
226 void
228 {
229  getCpuAddrMonitor(tid)->gotWakeup = true;
230 
231  if (threadInfo[tid]->thread->status() == ThreadContext::Suspended) {
232  DPRINTF(Quiesce,"[tid:%d] Suspended Processor awoke\n", tid);
233  threadInfo[tid]->thread->activate();
234  }
235 }
236 
237 void
239 {
240  if (debug::ExecFaulting) {
241  traceData->setFaulting(true);
242  } else {
243  delete traceData;
244  traceData = NULL;
245  }
246 }
247 
248 void
250 {
252  SimpleThread* thread = t_info.thread;
253  ThreadContext* tc = thread->getTC();
254 
255  if (checkInterrupts(curThread)) {
256  Fault interrupt = interrupts[curThread]->getInterrupt();
257 
258  if (interrupt != NoFault) {
259  // hardware transactional memory
260  // Postpone taking interrupts while executing transactions.
261  assert(!std::dynamic_pointer_cast<GenericHtmFailureFault>(
262  interrupt));
263  if (t_info.inHtmTransactionalState()) {
264  DPRINTF(HtmCpu, "Deferring pending interrupt - %s -"
265  "due to transactional state\n",
266  interrupt->name());
267  return;
268  }
269 
270  t_info.fetchOffset = 0;
271  interrupts[curThread]->updateIntrInfo();
272  interrupt->invoke(tc);
273  thread->decoder->reset();
274  }
275  }
276 }
277 
278 
279 void
281 {
283  SimpleThread* thread = t_info.thread;
284 
285  auto &decoder = thread->decoder;
286  Addr instAddr = thread->pcState().instAddr();
287  Addr fetchPC = (instAddr & decoder->pcMask()) + t_info.fetchOffset;
288 
289  // set up memory request for instruction fetch
290  DPRINTF(Fetch, "Fetch: Inst PC:%08p, Fetch PC:%08p\n", instAddr, fetchPC);
291 
292  req->setVirt(fetchPC, decoder->moreBytesSize(), Request::INST_FETCH,
293  instRequestorId(), instAddr);
294 }
295 
296 void
298 {
301 }
302 
303 void
305 {
307  SimpleThread* thread = t_info.thread;
308 
309  // resets predicates
310  t_info.setPredicate(true);
311  t_info.setMemAccPredicate(true);
312 
313  // decode the instruction
314  set(preExecuteTempPC, thread->pcState());
315  auto &pc_state = *preExecuteTempPC;
316 
317  auto &decoder = thread->decoder;
318 
319  if (isRomMicroPC(pc_state.microPC())) {
320  t_info.stayAtPC = false;
321  curStaticInst = decoder->fetchRomMicroop(
322  pc_state.microPC(), curMacroStaticInst);
323  } else if (!curMacroStaticInst) {
324  //We're not in the middle of a macro instruction
325  StaticInstPtr instPtr = NULL;
326 
327  //Predecode, ie bundle up an ExtMachInst
328  //If more fetch data is needed, pass it in.
329  Addr fetch_pc =
330  (pc_state.instAddr() & decoder->pcMask()) + t_info.fetchOffset;
331 
332  decoder->moreBytes(pc_state, fetch_pc);
333 
334  //Decode an instruction if one is ready. Otherwise, we'll have to
335  //fetch beyond the MachInst at the current pc.
336  instPtr = decoder->decode(pc_state);
337  if (instPtr) {
338  t_info.stayAtPC = false;
339  thread->pcState(pc_state);
340  } else {
341  t_info.stayAtPC = true;
342  t_info.fetchOffset += decoder->moreBytesSize();
343  }
344 
345  //If we decoded an instruction and it's microcoded, start pulling
346  //out micro ops
347  if (instPtr && instPtr->isMacroop()) {
348  curMacroStaticInst = instPtr;
349  curStaticInst =
350  curMacroStaticInst->fetchMicroop(pc_state.microPC());
351  } else {
352  curStaticInst = instPtr;
353  }
354  } else {
355  //Read the next micro op from the macro op
356  curStaticInst = curMacroStaticInst->fetchMicroop(pc_state.microPC());
357  }
358 
359  //If we decoded an instruction this "tick", record information about it.
360  if (curStaticInst) {
361 #if TRACING_ON
362  traceData = tracer->getInstRecord(curTick(), thread->getTC(),
364 #endif // TRACING_ON
365  }
366 
367  if (branchPred && curStaticInst &&
369  // Use a fake sequence number since we only have one
370  // instruction in flight at the same time.
371  const InstSeqNum cur_sn(0);
372  set(t_info.predPC, thread->pcState());
373  const bool predict_taken(
374  branchPred->predict(curStaticInst, cur_sn, *t_info.predPC,
375  curThread));
376 
377  if (predict_taken)
379  }
380 }
381 
382 void
384 {
386 
387  assert(curStaticInst);
388 
389  Addr instAddr = threadContexts[curThread]->pcState().instAddr();
390 
391  if (curStaticInst->isMemRef()) {
392  t_info.execContextStats.numMemRefs++;
393  }
394 
395  if (curStaticInst->isLoad()) {
396  ++t_info.numLoad;
397  }
398 
399  if (curStaticInst->isControl()) {
400  ++t_info.execContextStats.numBranches;
401  }
402 
403  /* Power model statistics */
404  //integer alu accesses
405  if (curStaticInst->isInteger()){
407  t_info.execContextStats.numIntInsts++;
408  }
409 
410  //float alu accesses
411  if (curStaticInst->isFloating()){
413  t_info.execContextStats.numFpInsts++;
414  }
415 
416  //vector alu accesses
417  if (curStaticInst->isVector()){
419  t_info.execContextStats.numVecInsts++;
420  }
421 
422  //number of function calls/returns to get window accesses
425  }
426 
427  //the number of branch predictions that will be made
428  if (curStaticInst->isCondCtrl()){
430  }
431 
432  //result bus acceses
433  if (curStaticInst->isLoad()){
435  }
436 
439  }
440  /* End power model statistics */
441 
443 
444  if (FullSystem)
445  traceFunctions(instAddr);
446 
447  if (traceData) {
448  traceData->dump();
449  delete traceData;
450  traceData = NULL;
451  }
452 
453  // Call CPU instruction commit probes
454  probeInstCommit(curStaticInst, instAddr);
455 }
456 
457 void
459 {
461  SimpleThread* thread = t_info.thread;
462 
463  const bool branching = thread->pcState().branching();
464 
465  //Since we're moving to a new pc, zero out the offset
466  t_info.fetchOffset = 0;
467  if (fault != NoFault) {
469  fault->invoke(threadContexts[curThread], curStaticInst);
470  thread->decoder->reset();
471  } else {
472  if (curStaticInst) {
475  curStaticInst->advancePC(thread);
476  }
477  }
478 
480  // Use a fake sequence number since we only have one
481  // instruction in flight at the same time.
482  const InstSeqNum cur_sn(0);
483 
484  if (*t_info.predPC == thread->pcState()) {
485  // Correctly predicted branch
486  branchPred->update(cur_sn, curThread);
487  } else {
488  // Mis-predicted branch
489  branchPred->squash(cur_sn, thread->pcState(), branching,
490  curThread);
492  }
493  }
494 }
495 
496 } // namespace gem5
gem5::curTick
Tick curTick()
The universal simulation clock.
Definition: cur_tick.hh:46
fatal
#define fatal(...)
This implements a cprintf based fatal() function.
Definition: logging.hh:190
gem5::branch_prediction::BPredUnit::update
void update(const InstSeqNum &done_sn, ThreadID tid)
Tells the branch predictor to commit any updates until the given sequence number.
Definition: bpred_unit.cc:304
gem5::BaseSimpleCPU::serializeThread
void serializeThread(CheckpointOut &cp, ThreadID tid) const override
Definition: base.cc:208
gem5::Trace::InstRecord::setFaulting
void setFaulting(bool val)
Definition: insttracer.hh:266
gem5::PCStateBase::instAddr
Addr instAddr() const
Returns the memory address of the instruction this PC points to.
Definition: pcstate.hh:107
gem5::SimpleExecContext::numOp
Counter numOp
Definition: exec_context.hh:77
gem5::branch_prediction::BPredUnit::predict
bool predict(const StaticInstPtr &inst, const InstSeqNum &seqNum, PCStateBase &pc, ThreadID tid)
Predicts whether or not the instruction is a taken branch, and the target of the branch if it is take...
Definition: bpred_unit.cc:131
gem5::BaseSimpleCPU::totalOps
Counter totalOps() const override
Definition: base.cc:176
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:253
gem5::StaticInst::isMicroop
bool isMicroop() const
Definition: static_inst.hh:186
gem5::BaseSimpleCPU::threadInfo
std::vector< SimpleExecContext * > threadInfo
Definition: base.hh:100
system.hh
gem5::BaseSimpleCPU::traceData
Trace::InstRecord * traceData
Definition: base.hh:97
sim_events.hh
gem5::SimpleExecContext::numLoad
Counter numLoad
Definition: exec_context.hh:79
gem5::isRomMicroPC
static bool isRomMicroPC(MicroPC upc)
Definition: types.hh:166
gem5::SimpleExecContext::ExecContextStats::numCallsReturns
statistics::Scalar numCallsReturns
Definition: exec_context.hh:226
gem5::BaseSimpleCPU::_status
Status _status
Definition: base.hh:123
gem5::StaticInst::isControl
bool isControl() const
Definition: static_inst.hh:160
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::ArmISA::set
Bitfield< 12, 11 > set
Definition: misc_types.hh:703
gem5::Request::INST_FETCH
@ INST_FETCH
The request was an instruction fetch.
Definition: request.hh:115
gem5::BaseSimpleCPU::curStaticInst
StaticInstPtr curStaticInst
Current instruction.
Definition: base.hh:104
exetrace.hh
gem5::SimpleExecContext::execContextStats
gem5::SimpleExecContext::ExecContextStats execContextStats
gem5::StaticInst::isCondCtrl
bool isCondCtrl() const
Definition: static_inst.hh:165
gem5::linux::thread_info
Definition: thread_info.hh:40
gem5::StaticInst::isDelayedCommit
bool isDelayedCommit() const
Definition: static_inst.hh:187
gem5::BaseSimpleCPU::BaseSimpleCPU
BaseSimpleCPU(const BaseSimpleCPUParams &params)
Definition: base.cc:84
gem5::BaseSimpleCPU::unserializeThread
void unserializeThread(CheckpointIn &cp, ThreadID tid) override
Definition: base.cc:216
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:67
gem5::CheckerThreadContext
Derived ThreadContext class for use with the Checker.
Definition: thread_context.hh:69
faults.hh
gem5::BaseSimpleCPU::~BaseSimpleCPU
virtual ~BaseSimpleCPU()
Definition: base.cc:186
gem5::SimpleThread
The SimpleThread object provides a combination of the ThreadState object and the ThreadContext interf...
Definition: simple_thread.hh:95
gem5::SimpleExecContext::ExecContextStats::numPredictedBranches
statistics::Scalar numPredictedBranches
Number of branches predicted as taken.
Definition: exec_context.hh:289
request.hh
gem5::StaticInst::advancePC
virtual void advancePC(PCStateBase &pc_state) const =0
gem5::EventQueue::serviceEvents
void serviceEvents(Tick when)
process all events up to the given timestamp.
Definition: eventq.hh:876
gem5::SimpleExecContext::ExecContextStats::numVecInsts
statistics::Scalar numVecInsts
Definition: exec_context.hh:238
gem5::SimpleExecContext::setPredicate
void setPredicate(bool val) override
Definition: exec_context.hh:486
gem5::BaseSimpleCPU::checkForInterrupts
void checkForInterrupts()
Definition: base.cc:249
gem5::RefCountingPtr< StaticInst >
packet.hh
gem5::StaticInst::fetchMicroop
virtual StaticInstPtr fetchMicroop(MicroPC upc) const
Return the microop that goes with a particular micropc.
Definition: static_inst.cc:39
gem5::StaticInst::opClass
OpClass opClass() const
Operation class. Used to select appropriate function unit in issue.
Definition: static_inst.hh:210
gem5::PCStateBase::branching
virtual bool branching() const =0
stats.hh
gem5::StaticInst::isFloating
bool isFloating() const
Definition: static_inst.hh:157
gem5::nullStaticInstPtr
const StaticInstPtr nullStaticInstPtr
Statically allocated null StaticInstPtr.
Definition: null_static_inst.cc:36
gem5::StaticInst::isReturn
bool isReturn() const
Definition: static_inst.hh:162
smt.hh
decoder.hh
gem5::BaseSimpleCPU::checkPcEventQueue
void checkPcEventQueue()
Definition: base.cc:124
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::SimpleExecContext::ExecContextStats::numInsts
statistics::Scalar numInsts
Definition: exec_context.hh:213
gem5::SimpleExecContext::fetchOffset
Addr fetchOffset
Definition: exec_context.hh:67
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:248
gem5::VegaISA::p
Bitfield< 54 > p
Definition: pagetable.hh:70
gem5::SimpleExecContext::inHtmTransactionalState
bool inHtmTransactionalState() const override
Definition: exec_context.hh:520
sim_object.hh
gem5::StaticInst::isAtomic
bool isAtomic() const
Definition: static_inst.hh:149
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::ThreadContext::Suspended
@ Suspended
Temporarily inactive.
Definition: thread_context.hh:113
gem5::BaseSimpleCPU::preExecute
void preExecute()
Definition: base.cc:304
debug.hh
gem5::SimpleExecContext::ExecContextStats::numCondCtrlInsts
statistics::Scalar numCondCtrlInsts
Definition: exec_context.hh:229
pollevent.hh
gem5::CheckerCPU
CheckerCPU class.
Definition: cpu.hh:84
gem5::SimpleExecContext::stayAtPC
bool stayAtPC
Definition: exec_context.hh:70
gem5::BaseSimpleCPU::setupFetchRequest
void setupFetchRequest(const RequestPtr &req)
Definition: base.cc:280
cpu.hh
gem5::BaseSimpleCPU::preExecuteTempPC
std::unique_ptr< PCStateBase > preExecuteTempPC
Definition: base.hh:133
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::BaseSimpleCPU::activeThreads
std::list< ThreadID > activeThreads
Definition: base.hh:101
gem5::StaticInst::isLoad
bool isLoad() const
Definition: static_inst.hh:147
gem5::SimpleExecContext::ExecContextStats::statExecutedInstType
statistics::Vector statExecutedInstType
Definition: exec_context.hh:295
gem5::StaticInst::isStore
bool isStore() const
Definition: static_inst.hh:148
cprintf.hh
static_inst.hh
gem5::BaseSimpleCPU::traceFault
void traceFault()
Handler used when encountering a fault; its purpose is to tear down the InstRecord.
Definition: base.cc:238
gem5::SimpleExecContext::numInst
Counter numInst
PER-THREAD STATS.
Definition: exec_context.hh:76
inifile.hh
gem5::StaticInst::isVector
bool isVector() const
Definition: static_inst.hh:158
gem5::InstDecoder::reset
virtual void reset()
Definition: decoder.hh:63
gem5::SimpleThread::decoder
InstDecoder * decoder
Definition: simple_thread.hh:134
gem5::branch_prediction::BPredUnit::squash
void squash(const InstSeqNum &squashed_sn, ThreadID tid)
Squashes all outstanding updates until a given sequence number.
Definition: bpred_unit.cc:327
gem5::SimpleThread::pcState
const PCStateBase & pcState() const override
Definition: simple_thread.hh:258
null_static_inst.hh
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::StaticInst::isLastMicroop
bool isLastMicroop() const
Definition: static_inst.hh:188
gem5::SimpleExecContext::ExecContextStats::numFpInsts
statistics::Scalar numFpInsts
Definition: exec_context.hh:235
gem5::StaticInst::isMemRef
bool isMemRef() const
Definition: static_inst.hh:143
full_system.hh
gem5::SimpleExecContext::ExecContextStats::numVecAluAccesses
statistics::Scalar numVecAluAccesses
Definition: exec_context.hh:223
gem5::SimpleExecContext::ExecContextStats::numStoreInsts
statistics::Scalar numStoreInsts
Definition: exec_context.hh:267
gem5::BaseSimpleCPU::postExecute
void postExecute()
Definition: base.cc:383
gem5::Trace::InstRecord::dump
virtual void dump()=0
gem5::SimpleExecContext::thread
SimpleThread * thread
Definition: exec_context.hh:64
gem5::FullSystem
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:220
gem5::SimpleThread::getTC
ThreadContext * getTC()
Returns the pointer to this SimpleThread's ThreadContext.
Definition: simple_thread.hh:167
base.hh
gem5::SimpleExecContext::ExecContextStats::numLoadInsts
statistics::Scalar numLoadInsts
Definition: exec_context.hh:266
gem5::BaseSimpleCPU::branchPred
branch_prediction::BPredUnit * branchPred
Definition: base.hh:87
simple_thread.hh
gem5::BaseSimpleCPU::countInst
void countInst()
Definition: base.cc:152
gem5::BaseSimpleCPU::resetStats
void resetStats() override
Definition: base.cc:199
gem5::SimpleExecContext::ExecContextStats::numIntInsts
statistics::Scalar numIntInsts
Definition: exec_context.hh:232
gem5::SimpleExecContext::ExecContextStats::numIntAluAccesses
statistics::Scalar numIntAluAccesses
Definition: exec_context.hh:217
gem5::SimpleExecContext::setMemAccPredicate
void setMemAccPredicate(bool val) override
Definition: exec_context.hh:502
base.hh
gem5::SimpleExecContext
Definition: exec_context.hh:60
gem5::BaseSimpleCPU::Running
@ Running
Definition: base.hh:111
types.hh
bpred_unit.hh
gem5::StaticInst::isMacroop
bool isMacroop() const
Definition: static_inst.hh:185
gem5::BaseSimpleCPU::swapActiveThread
void swapActiveThread()
Definition: base.cc:136
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::statistics::Counter
double Counter
All counters are of 64-bit values.
Definition: types.hh:47
gem5::BaseSimpleCPU::serviceInstCountEvents
void serviceInstCountEvents()
Definition: base.cc:297
logging.hh
gem5::SimpleExecContext::ExecContextStats::numFpAluAccesses
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Definition: exec_context.hh:220
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Definition: static_inst.hh:156
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Definition: static_inst.hh:161
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Definition: inst_seq.hh:40
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Definition: exec_context.hh:287
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Definition: exec_context.hh:214
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Definition: serialize.hh:66
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Definition: exec_context.hh:291
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Definition: base.cc:222
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Definition: base.cc:165
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Definition: base.hh:105
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Definition: simple_thread.hh:128
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Definition: base.hh:86
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Definition: exec_context.hh:265
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