gem5  v21.2.0.0
base.cc
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41 
42 #include "cpu/simple/base.hh"
43 
44 #include "arch/generic/decoder.hh"
45 #include "base/cprintf.hh"
46 #include "base/inifile.hh"
47 #include "base/loader/symtab.hh"
48 #include "base/logging.hh"
49 #include "base/pollevent.hh"
50 #include "base/trace.hh"
51 #include "base/types.hh"
52 #include "config/the_isa.hh"
53 #include "cpu/base.hh"
54 #include "cpu/checker/cpu.hh"
56 #include "cpu/exetrace.hh"
57 #include "cpu/null_static_inst.hh"
58 #include "cpu/pred/bpred_unit.hh"
60 #include "cpu/simple_thread.hh"
61 #include "cpu/smt.hh"
62 #include "cpu/static_inst.hh"
63 #include "cpu/thread_context.hh"
64 #include "debug/Decode.hh"
65 #include "debug/ExecFaulting.hh"
66 #include "debug/Fetch.hh"
67 #include "debug/HtmCpu.hh"
68 #include "debug/Quiesce.hh"
69 #include "mem/packet.hh"
70 #include "mem/request.hh"
71 #include "params/BaseSimpleCPU.hh"
72 #include "sim/byteswap.hh"
73 #include "sim/debug.hh"
74 #include "sim/faults.hh"
75 #include "sim/full_system.hh"
76 #include "sim/sim_events.hh"
77 #include "sim/sim_object.hh"
78 #include "sim/stats.hh"
79 #include "sim/system.hh"
80 
81 namespace gem5
82 {
83 
84 BaseSimpleCPU::BaseSimpleCPU(const BaseSimpleCPUParams &p)
85  : BaseCPU(p),
86  curThread(0),
87  branchPred(p.branchPred),
88  zeroReg(p.isa[0]->regClasses().at(IntRegClass).zeroReg()),
89  traceData(NULL),
90  _status(Idle)
91 {
92  SimpleThread *thread;
93 
94  for (unsigned i = 0; i < numThreads; i++) {
95  if (FullSystem) {
96  thread = new SimpleThread(
97  this, i, p.system, p.mmu, p.isa[i], p.decoder[i]);
98  } else {
99  thread = new SimpleThread(
100  this, i, p.system, p.workload[i], p.mmu, p.isa[i],
101  p.decoder[i]);
102  }
103  threadInfo.push_back(new SimpleExecContext(this, thread));
104  ThreadContext *tc = thread->getTC();
105  threadContexts.push_back(tc);
106  }
107 
108  if (p.checker) {
109  if (numThreads != 1)
110  fatal("Checker currently does not support SMT");
111 
112  BaseCPU *temp_checker = p.checker;
113  checker = dynamic_cast<CheckerCPU *>(temp_checker);
114  checker->setSystem(p.system);
115  // Manipulate thread context
116  ThreadContext *cpu_tc = threadContexts[0];
117  threadContexts[0] = new CheckerThreadContext<ThreadContext>(
118  cpu_tc, this->checker);
119  } else {
120  checker = NULL;
121  }
122 }
123 
124 void
126 {
127  Addr oldpc, pc = threadInfo[curThread]->thread->pcState().instAddr();
128  do {
129  oldpc = pc;
130  threadInfo[curThread]->thread->pcEventQueue.service(
131  oldpc, threadContexts[curThread]);
132  pc = threadInfo[curThread]->thread->pcState().instAddr();
133  } while (oldpc != pc);
134 }
135 
136 void
138 {
139  if (numThreads > 1) {
141  !threadInfo[curThread]->stayAtPC) {
142  // Swap active threads
143  if (!activeThreads.empty()) {
144  curThread = activeThreads.front();
145  activeThreads.pop_front();
146  activeThreads.push_back(curThread);
147  }
148  }
149  }
150 }
151 
152 void
154 {
156 
158  t_info.numInst++;
159  t_info.execContextStats.numInsts++;
160  }
161  t_info.numOp++;
162  t_info.execContextStats.numOps++;
163 }
164 
165 Counter
167 {
168  Counter total_inst = 0;
169  for (auto& t_info : threadInfo) {
170  total_inst += t_info->numInst;
171  }
172 
173  return total_inst;
174 }
175 
176 Counter
178 {
179  Counter total_op = 0;
180  for (auto& t_info : threadInfo) {
181  total_op += t_info->numOp;
182  }
183 
184  return total_op;
185 }
186 
188 {
189 }
190 
191 void
193 {
194  // for now, these are equivalent
195  suspendContext(thread_num);
196  updateCycleCounters(BaseCPU::CPU_STATE_SLEEP);
197 }
198 
199 void
201 {
202  BaseCPU::resetStats();
203  for (auto &thread_info : threadInfo) {
204  thread_info->execContextStats.notIdleFraction = (_status != Idle);
205  }
206 }
207 
208 void
210 {
211  assert(_status == Idle || _status == Running);
212 
213  threadInfo[tid]->thread->serialize(cp);
214 }
215 
216 void
218 {
219  threadInfo[tid]->thread->unserialize(cp);
220 }
221 
222 void
223 change_thread_state(ThreadID tid, int activate, int priority)
224 {
225 }
226 
227 void
229 {
230  getCpuAddrMonitor(tid)->gotWakeup = true;
231 
232  if (threadInfo[tid]->thread->status() == ThreadContext::Suspended) {
233  DPRINTF(Quiesce,"[tid:%d] Suspended Processor awoke\n", tid);
234  threadInfo[tid]->thread->activate();
235  }
236 }
237 
238 void
240 {
241  if (debug::ExecFaulting) {
242  traceData->setFaulting(true);
243  } else {
244  delete traceData;
245  traceData = NULL;
246  }
247 }
248 
249 void
251 {
253  SimpleThread* thread = t_info.thread;
254  ThreadContext* tc = thread->getTC();
255 
256  if (checkInterrupts(curThread)) {
257  Fault interrupt = interrupts[curThread]->getInterrupt();
258 
259  if (interrupt != NoFault) {
260  // hardware transactional memory
261  // Postpone taking interrupts while executing transactions.
262  assert(!std::dynamic_pointer_cast<GenericHtmFailureFault>(
263  interrupt));
264  if (t_info.inHtmTransactionalState()) {
265  DPRINTF(HtmCpu, "Deferring pending interrupt - %s -"
266  "due to transactional state\n",
267  interrupt->name());
268  return;
269  }
270 
271  t_info.fetchOffset = 0;
272  interrupts[curThread]->updateIntrInfo();
273  interrupt->invoke(tc);
274  thread->decoder->reset();
275  }
276  }
277 }
278 
279 
280 void
282 {
284  SimpleThread* thread = t_info.thread;
285 
286  auto &decoder = thread->decoder;
287  Addr instAddr = thread->pcState().instAddr();
288  Addr fetchPC = (instAddr & decoder->pcMask()) + t_info.fetchOffset;
289 
290  // set up memory request for instruction fetch
291  DPRINTF(Fetch, "Fetch: Inst PC:%08p, Fetch PC:%08p\n", instAddr, fetchPC);
292 
293  req->setVirt(fetchPC, decoder->moreBytesSize(), Request::INST_FETCH,
294  instRequestorId(), instAddr);
295 }
296 
297 void
299 {
302 }
303 
304 void
306 {
308  SimpleThread* thread = t_info.thread;
309 
310  // maintain $r0 semantics
311  thread->setIntReg(zeroReg, 0);
312 
313  // resets predicates
314  t_info.setPredicate(true);
315  t_info.setMemAccPredicate(true);
316 
317  // decode the instruction
318  set(preExecuteTempPC, thread->pcState());
319  auto &pc_state = *preExecuteTempPC;
320 
321  auto &decoder = thread->decoder;
322 
323  if (isRomMicroPC(pc_state.microPC())) {
324  t_info.stayAtPC = false;
325  curStaticInst = decoder->fetchRomMicroop(
326  pc_state.microPC(), curMacroStaticInst);
327  } else if (!curMacroStaticInst) {
328  //We're not in the middle of a macro instruction
329  StaticInstPtr instPtr = NULL;
330 
331  //Predecode, ie bundle up an ExtMachInst
332  //If more fetch data is needed, pass it in.
333  Addr fetch_pc =
334  (pc_state.instAddr() & decoder->pcMask()) + t_info.fetchOffset;
335 
336  decoder->moreBytes(pc_state, fetch_pc);
337 
338  //Decode an instruction if one is ready. Otherwise, we'll have to
339  //fetch beyond the MachInst at the current pc.
340  instPtr = decoder->decode(pc_state);
341  if (instPtr) {
342  t_info.stayAtPC = false;
343  thread->pcState(pc_state);
344  } else {
345  t_info.stayAtPC = true;
346  t_info.fetchOffset += decoder->moreBytesSize();
347  }
348 
349  //If we decoded an instruction and it's microcoded, start pulling
350  //out micro ops
351  if (instPtr && instPtr->isMacroop()) {
352  curMacroStaticInst = instPtr;
353  curStaticInst =
354  curMacroStaticInst->fetchMicroop(pc_state.microPC());
355  } else {
356  curStaticInst = instPtr;
357  }
358  } else {
359  //Read the next micro op from the macro op
360  curStaticInst = curMacroStaticInst->fetchMicroop(pc_state.microPC());
361  }
362 
363  //If we decoded an instruction this "tick", record information about it.
364  if (curStaticInst) {
365 #if TRACING_ON
366  traceData = tracer->getInstRecord(curTick(), thread->getTC(),
368 #endif // TRACING_ON
369  }
370 
371  if (branchPred && curStaticInst &&
373  // Use a fake sequence number since we only have one
374  // instruction in flight at the same time.
375  const InstSeqNum cur_sn(0);
376  set(t_info.predPC, thread->pcState());
377  const bool predict_taken(
378  branchPred->predict(curStaticInst, cur_sn, *t_info.predPC,
379  curThread));
380 
381  if (predict_taken)
383  }
384 }
385 
386 void
388 {
390 
391  assert(curStaticInst);
392 
393  Addr instAddr = threadContexts[curThread]->pcState().instAddr();
394 
395  if (curStaticInst->isMemRef()) {
396  t_info.execContextStats.numMemRefs++;
397  }
398 
399  if (curStaticInst->isLoad()) {
400  ++t_info.numLoad;
401  }
402 
403  if (curStaticInst->isControl()) {
404  ++t_info.execContextStats.numBranches;
405  }
406 
407  /* Power model statistics */
408  //integer alu accesses
409  if (curStaticInst->isInteger()){
411  t_info.execContextStats.numIntInsts++;
412  }
413 
414  //float alu accesses
415  if (curStaticInst->isFloating()){
417  t_info.execContextStats.numFpInsts++;
418  }
419 
420  //vector alu accesses
421  if (curStaticInst->isVector()){
423  t_info.execContextStats.numVecInsts++;
424  }
425 
426  //number of function calls/returns to get window accesses
429  }
430 
431  //the number of branch predictions that will be made
432  if (curStaticInst->isCondCtrl()){
434  }
435 
436  //result bus acceses
437  if (curStaticInst->isLoad()){
439  }
440 
443  }
444  /* End power model statistics */
445 
447 
448  if (FullSystem)
449  traceFunctions(instAddr);
450 
451  if (traceData) {
452  traceData->dump();
453  delete traceData;
454  traceData = NULL;
455  }
456 
457  // Call CPU instruction commit probes
458  probeInstCommit(curStaticInst, instAddr);
459 }
460 
461 void
463 {
465  SimpleThread* thread = t_info.thread;
466 
467  const bool branching = thread->pcState().branching();
468 
469  //Since we're moving to a new pc, zero out the offset
470  t_info.fetchOffset = 0;
471  if (fault != NoFault) {
473  fault->invoke(threadContexts[curThread], curStaticInst);
474  thread->decoder->reset();
475  } else {
476  if (curStaticInst) {
479  curStaticInst->advancePC(thread);
480  }
481  }
482 
484  // Use a fake sequence number since we only have one
485  // instruction in flight at the same time.
486  const InstSeqNum cur_sn(0);
487 
488  if (*t_info.predPC == thread->pcState()) {
489  // Correctly predicted branch
490  branchPred->update(cur_sn, curThread);
491  } else {
492  // Mis-predicted branch
493  branchPred->squash(cur_sn, thread->pcState(), branching,
494  curThread);
496  }
497  }
498 }
499 
500 } // namespace gem5
gem5::curTick
Tick curTick()
The universal simulation clock.
Definition: cur_tick.hh:46
fatal
#define fatal(...)
This implements a cprintf based fatal() function.
Definition: logging.hh:190
gem5::branch_prediction::BPredUnit::update
void update(const InstSeqNum &done_sn, ThreadID tid)
Tells the branch predictor to commit any updates until the given sequence number.
Definition: bpred_unit.cc:304
gem5::BaseSimpleCPU::serializeThread
void serializeThread(CheckpointOut &cp, ThreadID tid) const override
Definition: base.cc:209
gem5::Trace::InstRecord::setFaulting
void setFaulting(bool val)
Definition: insttracer.hh:232
gem5::PCStateBase::instAddr
Addr instAddr() const
Returns the memory address of the instruction this PC points to.
Definition: pcstate.hh:107
gem5::SimpleExecContext::numOp
Counter numOp
Definition: exec_context.hh:77
gem5::branch_prediction::BPredUnit::predict
bool predict(const StaticInstPtr &inst, const InstSeqNum &seqNum, PCStateBase &pc, ThreadID tid)
Predicts whether or not the instruction is a taken branch, and the target of the branch if it is take...
Definition: bpred_unit.cc:131
gem5::BaseSimpleCPU::totalOps
Counter totalOps() const override
Definition: base.cc:177
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:260
gem5::StaticInst::isMicroop
bool isMicroop() const
Definition: static_inst.hh:207
gem5::BaseSimpleCPU::threadInfo
std::vector< SimpleExecContext * > threadInfo
Definition: base.hh:102
gem5::SimpleThread::setIntReg
void setIntReg(RegIndex reg_idx, RegVal val) override
Definition: simple_thread.hh:359
system.hh
gem5::Request::INST_FETCH
@ INST_FETCH
The request was an instruction fetch.
Definition: request.hh:115
gem5::BaseSimpleCPU::traceData
Trace::InstRecord * traceData
Definition: base.hh:99
sim_events.hh
gem5::SimpleExecContext::numLoad
Counter numLoad
Definition: exec_context.hh:79
gem5::isRomMicroPC
static bool isRomMicroPC(MicroPC upc)
Definition: types.hh:166
gem5::SimpleExecContext::ExecContextStats::numCallsReturns
statistics::Scalar numCallsReturns
Definition: exec_context.hh:210
gem5::BaseSimpleCPU::_status
Status _status
Definition: base.hh:125
gem5::StaticInst::isControl
bool isControl() const
Definition: static_inst.hh:181
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::BaseSimpleCPU::curStaticInst
StaticInstPtr curStaticInst
Current instruction.
Definition: base.hh:106
exetrace.hh
gem5::SimpleExecContext::execContextStats
gem5::SimpleExecContext::ExecContextStats execContextStats
gem5::StaticInst::isCondCtrl
bool isCondCtrl() const
Definition: static_inst.hh:186
gem5::linux::thread_info
Definition: thread_info.hh:40
gem5::StaticInst::isDelayedCommit
bool isDelayedCommit() const
Definition: static_inst.hh:208
gem5::BaseSimpleCPU::BaseSimpleCPU
BaseSimpleCPU(const BaseSimpleCPUParams &params)
Definition: base.cc:84
gem5::BaseSimpleCPU::unserializeThread
void unserializeThread(CheckpointIn &cp, ThreadID tid) override
Definition: base.cc:217
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:67
gem5::CheckerThreadContext
Derived ThreadContext class for use with the Checker.
Definition: thread_context.hh:69
faults.hh
gem5::BaseSimpleCPU::~BaseSimpleCPU
virtual ~BaseSimpleCPU()
Definition: base.cc:187
gem5::SimpleThread
The SimpleThread object provides a combination of the ThreadState object and the ThreadContext interf...
Definition: simple_thread.hh:93
gem5::SimpleExecContext::ExecContextStats::numPredictedBranches
statistics::Scalar numPredictedBranches
Number of branches predicted as taken.
Definition: exec_context.hh:273
request.hh
gem5::StaticInst::advancePC
virtual void advancePC(PCStateBase &pc_state) const =0
gem5::EventQueue::serviceEvents
void serviceEvents(Tick when)
process all events up to the given timestamp.
Definition: eventq.hh:876
gem5::SimpleExecContext::ExecContextStats::numVecInsts
statistics::Scalar numVecInsts
Definition: exec_context.hh:222
gem5::SimpleExecContext::setPredicate
void setPredicate(bool val) override
Definition: exec_context.hh:559
gem5::BaseSimpleCPU::checkForInterrupts
void checkForInterrupts()
Definition: base.cc:250
gem5::RefCountingPtr< StaticInst >
packet.hh
gem5::StaticInst::fetchMicroop
virtual StaticInstPtr fetchMicroop(MicroPC upc) const
Return the microop that goes with a particular micropc.
Definition: static_inst.cc:39
gem5::ArmISA::at
Bitfield< 35, 32 > at
Definition: misc_types.hh:155
gem5::StaticInst::opClass
OpClass opClass() const
Operation class. Used to select appropriate function unit in issue.
Definition: static_inst.hh:231
gem5::PCStateBase::branching
virtual bool branching() const =0
stats.hh
gem5::StaticInst::isFloating
bool isFloating() const
Definition: static_inst.hh:178
gem5::nullStaticInstPtr
const StaticInstPtr nullStaticInstPtr
Statically allocated null StaticInstPtr.
Definition: null_static_inst.cc:36
gem5::StaticInst::isReturn
bool isReturn() const
Definition: static_inst.hh:183
smt.hh
decoder.hh
gem5::BaseSimpleCPU::checkPcEventQueue
void checkPcEventQueue()
Definition: base.cc:125
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::SimpleExecContext::ExecContextStats::numInsts
statistics::Scalar numInsts
Definition: exec_context.hh:197
gem5::SimpleExecContext::fetchOffset
Addr fetchOffset
Definition: exec_context.hh:67
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::SimpleExecContext::inHtmTransactionalState
bool inHtmTransactionalState() const override
Definition: exec_context.hh:593
sim_object.hh
gem5::StaticInst::isAtomic
bool isAtomic() const
Definition: static_inst.hh:170
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::ThreadContext::Suspended
@ Suspended
Temporarily inactive.
Definition: thread_context.hh:113
gem5::BaseSimpleCPU::preExecute
void preExecute()
Definition: base.cc:305
debug.hh
gem5::SimpleExecContext::ExecContextStats::numCondCtrlInsts
statistics::Scalar numCondCtrlInsts
Definition: exec_context.hh:213
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
pollevent.hh
gem5::CheckerCPU
CheckerCPU class.
Definition: cpu.hh:84
gem5::SimpleExecContext::stayAtPC
bool stayAtPC
Definition: exec_context.hh:70
gem5::BaseSimpleCPU::setupFetchRequest
void setupFetchRequest(const RequestPtr &req)
Definition: base.cc:281
cpu.hh
gem5::BaseSimpleCPU::preExecuteTempPC
std::unique_ptr< PCStateBase > preExecuteTempPC
Definition: base.hh:135
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::BaseSimpleCPU::activeThreads
std::list< ThreadID > activeThreads
Definition: base.hh:103
gem5::StaticInst::isLoad
bool isLoad() const
Definition: static_inst.hh:168
gem5::SimpleExecContext::ExecContextStats::statExecutedInstType
statistics::Vector statExecutedInstType
Definition: exec_context.hh:279
gem5::StaticInst::isStore
bool isStore() const
Definition: static_inst.hh:169
cprintf.hh
static_inst.hh
gem5::BaseSimpleCPU::traceFault
void traceFault()
Handler used when encountering a fault; its purpose is to tear down the InstRecord.
Definition: base.cc:239
gem5::SimpleExecContext::numInst
Counter numInst
PER-THREAD STATS.
Definition: exec_context.hh:76
inifile.hh
gem5::StaticInst::isVector
bool isVector() const
Definition: static_inst.hh:179
gem5::InstDecoder::reset
virtual void reset()
Definition: decoder.hh:63
gem5::SimpleThread::decoder
InstDecoder * decoder
Definition: simple_thread.hh:136
gem5::branch_prediction::BPredUnit::squash
void squash(const InstSeqNum &squashed_sn, ThreadID tid)
Squashes all outstanding updates until a given sequence number.
Definition: bpred_unit.cc:327
gem5::SimpleThread::pcState
const PCStateBase & pcState() const override
Definition: simple_thread.hh:422
null_static_inst.hh
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::StaticInst::isLastMicroop
bool isLastMicroop() const
Definition: static_inst.hh:209
gem5::SimpleExecContext::ExecContextStats::numFpInsts
statistics::Scalar numFpInsts
Definition: exec_context.hh:219
gem5::StaticInst::isMemRef
bool isMemRef() const
Definition: static_inst.hh:164
full_system.hh
gem5::SimpleExecContext::ExecContextStats::numVecAluAccesses
statistics::Scalar numVecAluAccesses
Definition: exec_context.hh:207
gem5::SimpleExecContext::ExecContextStats::numStoreInsts
statistics::Scalar numStoreInsts
Definition: exec_context.hh:251
gem5::BaseSimpleCPU::postExecute
void postExecute()
Definition: base.cc:387
gem5::Trace::InstRecord::dump
virtual void dump()=0
gem5::SimpleExecContext::thread
SimpleThread * thread
Definition: exec_context.hh:64
gem5::FullSystem
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:220
gem5::SimpleThread::getTC
ThreadContext * getTC()
Returns the pointer to this SimpleThread's ThreadContext.
Definition: simple_thread.hh:169
base.hh
gem5::SimpleExecContext::ExecContextStats::numLoadInsts
statistics::Scalar numLoadInsts
Definition: exec_context.hh:250
gem5::IntRegClass
@ IntRegClass
Integer register.
Definition: reg_class.hh:58
gem5::BaseSimpleCPU::branchPred
branch_prediction::BPredUnit * branchPred
Definition: base.hh:87
simple_thread.hh
gem5::BaseSimpleCPU::zeroReg
const RegIndex zeroReg
Definition: base.hh:89
gem5::BaseSimpleCPU::countInst
void countInst()
Definition: base.cc:153
gem5::BaseSimpleCPU::resetStats
void resetStats() override
Definition: base.cc:200
gem5::SimpleExecContext::ExecContextStats::numIntInsts
statistics::Scalar numIntInsts
Definition: exec_context.hh:216
gem5::SimpleExecContext::ExecContextStats::numIntAluAccesses
statistics::Scalar numIntAluAccesses
Definition: exec_context.hh:201
gem5::SimpleExecContext::setMemAccPredicate
void setMemAccPredicate(bool val) override
Definition: exec_context.hh:575
base.hh
gem5::SimpleExecContext
Definition: exec_context.hh:60
gem5::BaseSimpleCPU::Running
@ Running
Definition: base.hh:113
types.hh
bpred_unit.hh
gem5::StaticInst::isMacroop
bool isMacroop() const
Definition: static_inst.hh:206
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Definition: types.hh:47
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Definition: inst_seq.hh:40
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Definition: base.cc:223
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Definition: base.cc:166
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Definition: base.hh:112
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Definition: simple_thread.hh:130
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