gem5  v21.2.1.1
cpu.hh
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41 
42 #ifndef __CPU_CHECKER_CPU_HH__
43 #define __CPU_CHECKER_CPU_HH__
44 
45 #include <list>
46 #include <map>
47 #include <queue>
48 
49 #include "arch/generic/pcstate.hh"
50 #include "base/statistics.hh"
51 #include "cpu/base.hh"
52 #include "cpu/exec_context.hh"
53 #include "cpu/inst_res.hh"
54 #include "cpu/pc_event.hh"
55 #include "cpu/simple_thread.hh"
56 #include "cpu/static_inst.hh"
57 #include "debug/Checker.hh"
58 #include "mem/request.hh"
59 #include "params/CheckerCPU.hh"
60 #include "sim/eventq.hh"
61 
62 namespace gem5
63 {
64 
65 class ThreadContext;
66 class Request;
67 
84 class CheckerCPU : public BaseCPU, public ExecContext
85 {
86  protected:
89 
91 
92  public:
93  void init() override;
94 
96  CheckerCPU(const Params &p);
97  virtual ~CheckerCPU();
98 
99  void setSystem(System *system);
100 
101  void setIcachePort(RequestPort *icache_port);
102 
103  void setDcachePort(RequestPort *dcache_port);
104 
105  Port &
106  getDataPort() override
107  {
108  // the checker does not have ports on its own so return the
109  // data port of the actual CPU core
110  assert(dcachePort);
111  return *dcachePort;
112  }
113 
114  Port &
115  getInstPort() override
116  {
117  // the checker does not have ports on its own so return the
118  // data port of the actual CPU core
119  assert(icachePort);
120  return *icachePort;
121  }
122 
123  protected:
124 
126 
128 
131 
133 
135 
136  // ISAs like ARM can have multiple destination registers to check,
137  // keep them all in a std::queue
138  std::queue<InstResult> result;
139 
142 
143  // number of simulated instructions
146 
147  std::queue<int> miscRegIdxs;
148 
149  public:
150 
151  // Primary thread being run.
153 
154  BaseMMU* getMMUPtr() { return mmu; }
155 
156  virtual Counter totalInsts() const override { return 0; }
157 
158  virtual Counter totalOps() const override { return 0; }
159 
160  // number of simulated loads
163 
164  void serialize(CheckpointOut &cp) const override;
165  void unserialize(CheckpointIn &cp) override;
166 
167  // The register accessor methods provide the index of the
168  // instruction's operand (e.g., 0 or 1), not the architectural
169  // register index, to simplify the implementation of register
170  // renaming. We find the architectural register index by indexing
171  // into the instruction's own operand index table. Note that a
172  // raw pointer to the StaticInst is provided instead of a
173  // ref-counted StaticInstPtr to redice overhead. This is fine as
174  // long as these methods don't copy the pointer into any long-term
175  // storage (which is pretty hard to imagine they would have reason
176  // to do).
177 
178  RegVal
179  readIntRegOperand(const StaticInst *si, int idx) override
180  {
181  const RegId& reg = si->srcRegIdx(idx);
182  assert(reg.is(IntRegClass));
183  return thread->readIntReg(reg.index());
184  }
185 
186  RegVal
187  readFloatRegOperandBits(const StaticInst *si, int idx) override
188  {
189  const RegId& reg = si->srcRegIdx(idx);
190  assert(reg.is(FloatRegClass));
191  return thread->readFloatReg(reg.index());
192  }
193 
198  readVecRegOperand(const StaticInst *si, int idx) const override
199  {
200  const RegId& reg = si->srcRegIdx(idx);
201  assert(reg.is(VecRegClass));
202  return thread->readVecReg(reg);
203  }
204 
209  getWritableVecRegOperand(const StaticInst *si, int idx) override
210  {
211  const RegId& reg = si->destRegIdx(idx);
212  assert(reg.is(VecRegClass));
213  return thread->getWritableVecReg(reg);
214  }
215 
216  RegVal
217  readVecElemOperand(const StaticInst *si, int idx) const override
218  {
219  const RegId& reg = si->srcRegIdx(idx);
220  return thread->readVecElem(reg);
221  }
222 
224  readVecPredRegOperand(const StaticInst *si, int idx) const override
225  {
226  const RegId& reg = si->srcRegIdx(idx);
227  assert(reg.is(VecPredRegClass));
228  return thread->readVecPredReg(reg);
229  }
230 
232  getWritableVecPredRegOperand(const StaticInst *si, int idx) override
233  {
234  const RegId& reg = si->destRegIdx(idx);
235  assert(reg.is(VecPredRegClass));
237  }
238 
239  RegVal
240  readCCRegOperand(const StaticInst *si, int idx) override
241  {
242  const RegId& reg = si->srcRegIdx(idx);
243  assert(reg.is(CCRegClass));
244  return thread->readCCReg(reg.index());
245  }
246 
247  void
248  setIntRegOperand(const StaticInst *si, int idx, RegVal val) override
249  {
250  const RegId& reg = si->destRegIdx(idx);
251  assert(reg.is(IntRegClass));
252  thread->setIntReg(reg.index(), val);
253  result.emplace(val);
254  }
255 
256  void
257  setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) override
258  {
259  const RegId& reg = si->destRegIdx(idx);
260  assert(reg.is(FloatRegClass));
261  thread->setFloatReg(reg.index(), val);
262  result.emplace(val);
263  }
264 
265  void
266  setCCRegOperand(const StaticInst *si, int idx, RegVal val) override
267  {
268  const RegId& reg = si->destRegIdx(idx);
269  assert(reg.is(CCRegClass));
270  thread->setCCReg(reg.index(), val);
271  result.emplace(val);
272  }
273 
274  void
275  setVecRegOperand(const StaticInst *si, int idx,
276  const TheISA::VecRegContainer& val) override
277  {
278  const RegId& reg = si->destRegIdx(idx);
279  assert(reg.is(VecRegClass));
280  thread->setVecReg(reg, val);
281  result.emplace(val);
282  }
283 
284  void
285  setVecElemOperand(const StaticInst *si, int idx, RegVal val) override
286  {
287  const RegId& reg = si->destRegIdx(idx);
288  assert(reg.is(VecElemClass));
290  result.emplace(val);
291  }
292 
293  void
295  const TheISA::VecPredRegContainer& val) override
296  {
297  const RegId& reg = si->destRegIdx(idx);
298  assert(reg.is(VecPredRegClass));
300  result.emplace(val);
301  }
302 
303  bool readPredicate() const override { return thread->readPredicate(); }
304 
305  void
306  setPredicate(bool val) override
307  {
309  }
310 
311  bool
312  readMemAccPredicate() const override
313  {
314  return thread->readMemAccPredicate();
315  }
316 
317  void
318  setMemAccPredicate(bool val) override
319  {
321  }
322 
323  uint64_t
324  getHtmTransactionUid() const override
325  {
326  panic("not yet supported!");
327  return 0;
328  };
329 
330  uint64_t
331  newHtmTransactionUid() const override
332  {
333  panic("not yet supported!");
334  return 0;
335  };
336 
337  Fault
339  {
340  panic("not yet supported!");
341  return NoFault;
342  }
343 
344  bool
345  inHtmTransactionalState() const override
346  {
347  return (getHtmTransactionalDepth() > 0);
348  }
349 
350  uint64_t
351  getHtmTransactionalDepth() const override
352  {
355  }
356 
357  const PCStateBase &
358  pcState() const override
359  {
360  return thread->pcState();
361  }
362  void
363  pcState(const PCStateBase &val) override
364  {
365  DPRINTF(Checker, "Changing PC to %s, old PC %s.\n",
366  val, thread->pcState());
367  thread->pcState(val);
368  }
370 
371  RegVal
372  readMiscRegNoEffect(int misc_reg) const
373  {
374  return thread->readMiscRegNoEffect(misc_reg);
375  }
376 
377  RegVal
378  readMiscReg(int misc_reg) override
379  {
380  return thread->readMiscReg(misc_reg);
381  }
382 
383  void
385  {
386  DPRINTF(Checker, "Setting misc reg %d with no effect to check later\n",
387  misc_reg);
388  miscRegIdxs.push(misc_reg);
389  return thread->setMiscRegNoEffect(misc_reg, val);
390  }
391 
392  void
393  setMiscReg(int misc_reg, RegVal val) override
394  {
395  DPRINTF(Checker, "Setting misc reg %d with effect to check later\n",
396  misc_reg);
397  miscRegIdxs.push(misc_reg);
398  return thread->setMiscReg(misc_reg, val);
399  }
400 
401  RegVal
402  readMiscRegOperand(const StaticInst *si, int idx) override
403  {
404  const RegId& reg = si->srcRegIdx(idx);
405  assert(reg.is(MiscRegClass));
406  return thread->readMiscReg(reg.index());
407  }
408 
409  void
410  setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override
411  {
412  const RegId& reg = si->destRegIdx(idx);
413  assert(reg.is(MiscRegClass));
414  return this->setMiscReg(reg.index(), val);
415  }
416 
418 
419  void
421  {
422  changedPC = true;
423  set(newPCState, val);
424  }
425 
426  void
427  demapPage(Addr vaddr, uint64_t asn) override
428  {
429  mmu->demapPage(vaddr, asn);
430  }
431 
432  // monitor/mwait funtions
433  void armMonitor(Addr address) override { BaseCPU::armMonitor(0, address); }
434  bool mwait(PacketPtr pkt) override { return BaseCPU::mwait(0, pkt); }
435 
436  void
438  {
439  return BaseCPU::mwaitAtomic(0, tc, thread->mmu);
440  }
441 
442  AddressMonitor *
443  getAddrMonitor() override
444  {
445  return BaseCPU::getCpuAddrMonitor(0);
446  }
447 
464  RequestPtr genMemFragmentRequest(Addr frag_addr, int size,
465  Request::Flags flags,
466  const std::vector<bool>& byte_enable,
467  int& frag_size, int& size_left) const;
468 
469  Fault readMem(Addr addr, uint8_t *data, unsigned size,
470  Request::Flags flags,
471  const std::vector<bool>& byte_enable) override;
472 
473  Fault writeMem(uint8_t *data, unsigned size, Addr addr,
474  Request::Flags flags, uint64_t *res,
475  const std::vector<bool>& byte_enable) override;
476 
477  Fault
478  amoMem(Addr addr, uint8_t* data, unsigned size,
479  Request::Flags flags, AtomicOpFunctorPtr amo_op) override
480  {
481  panic("AMO is not supported yet in CPU checker\n");
482  }
483 
484  unsigned int
485  readStCondFailures() const override
486  {
487  return thread->readStCondFailures();
488  }
489 
490  void setStCondFailures(unsigned int sc_failures) override {}
492 
493  void wakeup(ThreadID tid) override { }
494 
495  void
497  {
498  if (exitOnError)
499  dumpAndExit();
500  }
501 
502  bool checkFlags(const RequestPtr &unverified_req, Addr vAddr,
503  Addr pAddr, int flags);
504 
505  void dumpAndExit();
506 
507  ThreadContext *tcBase() const override { return tc; }
509 
513 
514  bool changedPC;
516  std::unique_ptr<PCStateBase> newPCState;
520 
522 };
523 
530 template <class DynInstPtr>
531 class Checker : public CheckerCPU
532 {
533  public:
534  Checker(const Params &p)
535  : CheckerCPU(p), updateThisCycle(false), unverifiedInst(NULL)
536  { }
537 
538  void switchOut();
539  void takeOverFrom(BaseCPU *oldCPU);
540 
541  void advancePC(const Fault &fault);
542 
543  void verify(const DynInstPtr &inst);
544 
545  void validateInst(const DynInstPtr &inst);
546  void validateExecution(const DynInstPtr &inst);
547  void validateState();
548 
549  void copyResult(const DynInstPtr &inst, const InstResult& mismatch_val,
550  int start_idx);
551  void handlePendingInt();
552 
553  private:
554  void
555  handleError(const DynInstPtr &inst)
556  {
557  if (exitOnError) {
558  dumpAndExit(inst);
559  } else if (updateOnError) {
560  updateThisCycle = true;
561  }
562  }
563 
564  void dumpAndExit(const DynInstPtr &inst);
565 
567 
569 
572  void dumpInsts();
573 };
574 
575 } // namespace gem5
576 
577 #endif // __CPU_CHECKER_CPU_HH__
gem5::SimpleThread::readMiscReg
RegVal readMiscReg(RegIndex misc_reg) override
Definition: simple_thread.hh:441
gem5::CheckerCPU::pcState
const PCStateBase & pcState() const override
Definition: cpu.hh:358
gem5::CheckerCPU::CheckerCPU
CheckerCPU(const Params &p)
Definition: cpu.cc:65
gem5::SimpleThread::readIntReg
RegVal readIntReg(RegIndex reg_idx) const override
Definition: simple_thread.hh:267
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:260
gem5::Checker::validateInst
void validateInst(const DynInstPtr &inst)
Definition: cpu_impl.hh:445
gem5::CheckerCPU::numInst
Counter numInst
Definition: cpu.hh:144
gem5::CheckerCPU::amoMem
Fault amoMem(Addr addr, uint8_t *data, unsigned size, Request::Flags flags, AtomicOpFunctorPtr amo_op) override
Definition: cpu.hh:478
gem5::CheckerCPU::totalInsts
virtual Counter totalInsts() const override
Definition: cpu.hh:156
gem5::Checker::verify
void verify(const DynInstPtr &inst)
Definition: cpu_impl.hh:120
gem5::SimpleThread::htmTransactionStops
int64_t htmTransactionStops
Definition: simple_thread.hh:140
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::CheckerCPU::readCCRegOperand
RegVal readCCRegOperand(const StaticInst *si, int idx) override
Definition: cpu.hh:240
gem5::SimpleThread::setIntReg
void setIntReg(RegIndex reg_idx, RegVal val) override
Definition: simple_thread.hh:359
gem5::ArmISA::VecPredRegContainer
VecPredReg::Container VecPredRegContainer
Definition: vec.hh:68
gem5::SimpleThread::readVecReg
const TheISA::VecRegContainer & readVecReg(const RegId &reg) const override
Definition: simple_thread.hh:289
gem5::CheckerCPU::serialize
void serialize(CheckpointOut &cp) const override
Definition: cpu.cc:131
data
const char data[]
Definition: circlebuf.test.cc:48
gem5::Checker::updateThisCycle
bool updateThisCycle
Definition: cpu.hh:566
gem5::CheckerCPU::getMMUPtr
BaseMMU * getMMUPtr()
Definition: cpu.hh:154
gem5::CheckerCPU::readPredicate
bool readPredicate() const override
Definition: cpu.hh:303
gem5::VecElemClass
@ VecElemClass
Vector Register Native Elem lane.
Definition: reg_class.hh:63
gem5::CheckerCPU::readFloatRegOperandBits
RegVal readFloatRegOperandBits(const StaticInst *si, int idx) override
Reads a floating point register in its binary format, instead of by value.
Definition: cpu.hh:187
gem5::CheckerCPU::~CheckerCPU
virtual ~CheckerCPU()
Definition: cpu.cc:92
gem5::Checker::advancePC
void advancePC(const Fault &fault)
Definition: cpu_impl.hh:67
gem5::CCRegClass
@ CCRegClass
Condition-code register.
Definition: reg_class.hh:65
gem5::CheckerCPU::readMiscRegNoEffect
RegVal readMiscRegNoEffect(int misc_reg) const
Definition: cpu.hh:372
gem5::CheckerCPU::setStCondFailures
void setStCondFailures(unsigned int sc_failures) override
Sets the number of consecutive store conditional failures.
Definition: cpu.hh:490
gem5::CheckerCPU::initiateHtmCmd
Fault initiateHtmCmd(Request::Flags flags) override
Initiate an HTM command, e.g.
Definition: cpu.hh:338
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::CheckerCPU::unverifiedReq
RequestPtr unverifiedReq
Definition: cpu.hh:511
gem5::CheckerCPU::readStCondFailures
unsigned int readStCondFailures() const override
Returns the number of consecutive store conditional failures.
Definition: cpu.hh:485
gem5::CheckerCPU::setVecElemOperand
void setVecElemOperand(const StaticInst *si, int idx, RegVal val) override
Sets a vector register to a value.
Definition: cpu.hh:285
gem5::o3::DynInstPtr
RefCountingPtr< DynInst > DynInstPtr
Definition: dyn_inst_ptr.hh:55
gem5::CheckerCPU::genMemFragmentRequest
RequestPtr genMemFragmentRequest(Addr frag_addr, int size, Request::Flags flags, const std::vector< bool > &byte_enable, int &frag_size, int &size_left) const
Helper function used to generate the request for a single fragment of a memory access.
Definition: cpu.cc:141
gem5::CheckerCPU::workload
std::vector< Process * > workload
Definition: cpu.hh:125
gem5::Checker::instList
std::list< DynInstPtr > instList
Definition: cpu.hh:570
gem5::CheckerCPU::armMonitor
void armMonitor(Addr address) override
Definition: cpu.hh:433
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
gem5::SimpleThread::setMiscReg
void setMiscReg(RegIndex misc_reg, RegVal val) override
Definition: simple_thread.hh:453
gem5::Checker::handleError
void handleError(const DynInstPtr &inst)
Definition: cpu.hh:555
gem5::CheckerCPU::setCCRegOperand
void setCCRegOperand(const StaticInst *si, int idx, RegVal val) override
Definition: cpu.hh:266
gem5::CheckerCPU::thread
SimpleThread * thread
Definition: cpu.hh:152
gem5::X86ISA::system
Bitfield< 15 > system
Definition: misc.hh:1003
gem5::SimpleThread::setVecReg
void setVecReg(const RegId &reg, const TheISA::VecRegContainer &val) override
Definition: simple_thread.hh:382
gem5::CheckerCPU::getWritableVecRegOperand
TheISA::VecRegContainer & getWritableVecRegOperand(const StaticInst *si, int idx) override
Read destination vector register operand for modification.
Definition: cpu.hh:209
std::vector
STL vector class.
Definition: stl.hh:37
gem5::CheckerCPU::readVecRegOperand
const TheISA::VecRegContainer & readVecRegOperand(const StaticInst *si, int idx) const override
Read source vector register operand.
Definition: cpu.hh:198
gem5::SimpleThread::readCCReg
RegVal readCCReg(RegIndex reg_idx) const override
Definition: simple_thread.hh:347
gem5::CheckerCPU::readMemAccPredicate
bool readMemAccPredicate() const override
Definition: cpu.hh:312
gem5::CheckerCPU::readMiscRegOperand
RegVal readMiscRegOperand(const StaticInst *si, int idx) override
Definition: cpu.hh:402
gem5::CheckerCPU::miscRegIdxs
std::queue< int > miscRegIdxs
Definition: cpu.hh:147
gem5::CheckerCPU::willChangePC
bool willChangePC
Definition: cpu.hh:515
gem5::SimpleThread::htmTransactionStarts
int64_t htmTransactionStarts
Definition: simple_thread.hh:139
inst_res.hh
gem5::Checker::copyResult
void copyResult(const DynInstPtr &inst, const InstResult &mismatch_val, int start_idx)
Definition: cpu_impl.hh:579
gem5::SimpleThread
The SimpleThread object provides a combination of the ThreadState object and the ThreadContext interf...
Definition: simple_thread.hh:93
gem5::RegId::index
RegIndex index() const
Index accessors.
Definition: reg_class.hh:180
gem5::CheckerCPU::writeMem
Fault writeMem(uint8_t *data, unsigned size, Addr addr, Request::Flags flags, uint64_t *res, const std::vector< bool > &byte_enable) override
Definition: cpu.cc:252
request.hh
gem5::SimpleThread::setVecPredReg
void setVecPredReg(const RegId &reg, const TheISA::VecPredRegContainer &val) override
Definition: simple_thread.hh:402
gem5::CheckerCPU::getHtmTransactionUid
uint64_t getHtmTransactionUid() const override
Definition: cpu.hh:324
gem5::CheckerCPU::wakeup
void wakeup(ThreadID tid) override
Definition: cpu.hh:493
gem5::Checker::handlePendingInt
void handlePendingInt()
Definition: cpu_impl.hh:86
gem5::VecPredRegClass
@ VecPredRegClass
Definition: reg_class.hh:64
gem5::RefCountingPtr< StaticInst >
gem5::BaseMMU
Definition: mmu.hh:53
gem5::CheckerCPU::setVecPredRegOperand
void setVecPredRegOperand(const StaticInst *si, int idx, const TheISA::VecPredRegContainer &val) override
Sets a destination predicate register operand to a value.
Definition: cpu.hh:294
gem5::CheckerCPU::youngestSN
InstSeqNum youngestSN
Definition: cpu.hh:521
gem5::CheckerCPU::getWritableVecPredRegOperand
TheISA::VecPredRegContainer & getWritableVecPredRegOperand(const StaticInst *si, int idx) override
Gets destination predicate register operand for modification.
Definition: cpu.hh:232
gem5::RequestPort
A RequestPort is a specialisation of a Port, which implements the default protocol for the three diff...
Definition: port.hh:77
gem5::Checker::Checker
Checker(const Params &p)
Definition: cpu.hh:534
gem5::CheckerCPU::dumpAndExit
void dumpAndExit()
Definition: cpu.cc:374
gem5::Checker::unverifiedInst
DynInstPtr unverifiedInst
Definition: cpu.hh:568
gem5::SimpleThread::readStCondFailures
unsigned readStCondFailures() const override
Definition: simple_thread.hh:464
gem5::SimpleThread::mmu
BaseMMU * mmu
Definition: simple_thread.hh:134
gem5::CheckerCPU::setMiscReg
void setMiscReg(int misc_reg, RegVal val) override
Sets a miscellaneous register, handling any architectural side effects due to writing that register.
Definition: cpu.hh:393
gem5::FloatRegClass
@ FloatRegClass
Floating-point register.
Definition: reg_class.hh:59
gem5::CheckerCPU::tc
ThreadContext * tc
Definition: cpu.hh:132
gem5::SimpleThread::readMemAccPredicate
bool readMemAccPredicate()
Definition: simple_thread.hh:467
gem5::Flags< FlagsType >
gem5::CheckerCPU::readVecPredRegOperand
const TheISA::VecPredRegContainer & readVecPredRegOperand(const StaticInst *si, int idx) const override
Predicate registers interface.
Definition: cpu.hh:224
gem5::CheckerCPU::setMemAccPredicate
void setMemAccPredicate(bool val) override
Definition: cpu.hh:318
gem5::System
Definition: system.hh:75
gem5::StaticInst
Base, ISA-independent static instruction class.
Definition: static_inst.hh:87
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::SimpleThread::readPredicate
bool readPredicate() const
Definition: simple_thread.hh:431
gem5::CheckerCPU::dcachePort
RequestPort * dcachePort
Definition: cpu.hh:130
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::SimpleThread::readMiscRegNoEffect
RegVal readMiscRegNoEffect(RegIndex misc_reg) const override
Definition: simple_thread.hh:435
gem5::CheckerCPU::demapPage
void demapPage(Addr vaddr, uint64_t asn) override
Invalidate a page in the DTLB and ITLB.
Definition: cpu.hh:427
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::CheckerCPU::newHtmTransactionUid
uint64_t newHtmTransactionUid() const override
Definition: cpu.hh:331
gem5::CheckerCPU::zeroReg
const RegIndex zeroReg
Definition: cpu.hh:90
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Bitfield< 0 > p
Definition: pra_constants.hh:326
statistics.hh
gem5::CheckerCPU::newPCState
std::unique_ptr< PCStateBase > newPCState
Definition: cpu.hh:516
gem5::CheckerCPU
CheckerCPU class.
Definition: cpu.hh:84
gem5::SimpleThread::setMiscRegNoEffect
void setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override
Definition: simple_thread.hh:447
gem5::SimpleThread::setMemAccPredicate
void setMemAccPredicate(bool val)
Definition: simple_thread.hh:473
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std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::BaseMMU::demapPage
void demapPage(Addr vaddr, uint64_t asn)
Definition: mmu.cc:97
gem5::CheckerCPU::icachePort
RequestPort * icachePort
Definition: cpu.hh:129
gem5::CheckerCPU::mwaitAtomic
void mwaitAtomic(ThreadContext *tc) override
Definition: cpu.hh:437
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gem5::VecRegContainer< NumVecElemPerVecReg *sizeof(VecElem)> VecRegContainer
Definition: vec.hh:62
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Definition: cpu.hh:127
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gem5::CheckerCPU::tcBase
ThreadContext * tcBase() const override
Returns a pointer to the ThreadContext.
Definition: cpu.hh:507
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Definition: cpu_impl.hh:466
gem5::CheckerCPU::result
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Definition: cpu.hh:138
gem5::CheckerCPU::numLoad
Counter numLoad
Definition: cpu.hh:161
gem5::CheckerCPU::startNumInst
Counter startNumInst
Definition: cpu.hh:145
gem5::CheckerCPU::requestorId
RequestorID requestorId
id attached to all issued requests
Definition: cpu.hh:88
gem5::SimpleThread::pcState
const PCStateBase & pcState() const override
Definition: simple_thread.hh:422
gem5::CheckerCPU::recordPCChange
void recordPCChange(const PCStateBase &val)
Definition: cpu.hh:420
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RegVal readVecElem(const RegId &reg) const override
Definition: simple_thread.hh:311
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bool changedPC
Definition: cpu.hh:514
gem5::CheckerCPU::pcState
void pcState(const PCStateBase &val) override
Definition: cpu.hh:363
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Bitfield< 6 > si
Definition: misc_types.hh:773
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uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::SimpleThread::setFloatReg
void setFloatReg(RegIndex reg_idx, RegVal val) override
Definition: simple_thread.hh:369
gem5::CheckerCPU::setMiscRegOperand
void setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override
Definition: cpu.hh:410
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Definition: cpu.hh:134
gem5::CheckerCPU::readMem
Fault readMem(Addr addr, uint8_t *data, unsigned size, Request::Flags flags, const std::vector< bool > &byte_enable) override
Definition: cpu.cc:168
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RegVal readFloatReg(RegIndex reg_idx) const override
Definition: simple_thread.hh:278
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bool exitOnError
Definition: cpu.hh:517
gem5::CheckerCPU::checkFlags
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Checks if the flags set by the Checker and Checkee match.
Definition: cpu.cc:357
gem5::CheckerCPU::setVecRegOperand
void setVecRegOperand(const StaticInst *si, int idx, const TheISA::VecRegContainer &val) override
Sets a destination vector register operand to a value.
Definition: cpu.hh:275
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Port & getDataPort() override
Definition: cpu.hh:106
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Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::SimpleThread::getWritableVecPredReg
TheISA::VecPredRegContainer & getWritableVecPredReg(const RegId &reg) override
Definition: simple_thread.hh:334
gem5::CheckerCPU::readMiscReg
RegVal readMiscReg(int misc_reg) override
Reads a miscellaneous register, handling any architectural side effects due to reading that register.
Definition: cpu.hh:378
pcstate.hh
gem5::IntRegClass
@ IntRegClass
Integer register.
Definition: reg_class.hh:58
gem5::CheckerCPU::init
void init() override
Definition: cpu.cc:59
gem5::CheckerCPU::threadBase
SimpleThread * threadBase()
Definition: cpu.hh:508
gem5::SimpleThread::getWritableVecReg
TheISA::VecRegContainer & getWritableVecReg(const RegId &reg) override
Definition: simple_thread.hh:300
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Port & getInstPort() override
Definition: cpu.hh:115
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void unserialize(CheckpointIn &cp) override
Definition: cpu.cc:136
gem5::CheckerCPU::handleError
void handleError()
Definition: cpu.hh:496
simple_thread.hh
gem5::SimpleThread::readVecPredReg
const TheISA::VecPredRegContainer & readVecPredReg(const RegId &reg) const override
Definition: simple_thread.hh:322
gem5::Checker::takeOverFrom
void takeOverFrom(BaseCPU *oldCPU)
Definition: cpu_impl.hh:441
gem5::CheckerCPU::curStaticInst
StaticInstPtr curStaticInst
Definition: cpu.hh:140
gem5::CheckerCPU::setDcachePort
void setDcachePort(RequestPort *dcache_port)
Definition: cpu.cc:125
gem5::CheckerCPU::setPredicate
void setPredicate(bool val) override
Definition: cpu.hh:306
gem5::CheckerCPU::readVecElemOperand
RegVal readVecElemOperand(const StaticInst *si, int idx) const override
Vector Elem Interfaces.
Definition: cpu.hh:217
base.hh
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
gem5::MiscRegClass
@ MiscRegClass
Control (misc) register.
Definition: reg_class.hh:66
pc_event.hh
gem5::Checker::InstListIt
std::list< DynInstPtr >::iterator InstListIt
Definition: cpu.hh:571
gem5::SimpleThread::setVecElem
void setVecElem(const RegId &reg, RegVal val) override
Definition: simple_thread.hh:392
gem5::CheckerCPU::PARAMS
PARAMS(CheckerCPU)
gem5::CheckerCPU::mwait
bool mwait(PacketPtr pkt) override
Definition: cpu.hh:434
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gem5::CheckerCPU::readIntRegOperand
RegVal readIntRegOperand(const StaticInst *si, int idx) override
Reads an integer register.
Definition: cpu.hh:179
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double Counter
All counters are of 64-bit values.
Definition: types.hh:47
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Definition: cpu_impl.hh:435
gem5::CheckerCPU::warnOnlyOnLoadError
bool warnOnlyOnLoadError
Definition: cpu.hh:519
gem5::CheckerCPU::setMiscRegNoEffect
void setMiscRegNoEffect(int misc_reg, RegVal val)
Definition: cpu.hh:384
gem5::CheckerCPU::getHtmTransactionalDepth
uint64_t getHtmTransactionalDepth() const override
Definition: cpu.hh:351
gem5::CheckerCPU::inHtmTransactionalState
bool inHtmTransactionalState() const override
Definition: cpu.hh:345
gem5::ExecContext
The ExecContext is an abstract base class the provides the interface used by the ISA to manipulate th...
Definition: exec_context.hh:73
gem5::CheckerCPU::startNumLoad
Counter startNumLoad
Definition: cpu.hh:162
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uint64_t InstSeqNum
Definition: inst_seq.hh:40
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std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::Checker::validateState
void validateState()
Definition: cpu_impl.hh:553
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uint16_t RequestorID
Definition: request.hh:95
gem5::CheckerCPU::getAddrMonitor
AddressMonitor * getAddrMonitor() override
Definition: cpu.hh:443
gem5::VecRegClass
@ VecRegClass
Vector Register.
Definition: reg_class.hh:61
gem5::MipsISA::vaddr
vaddr
Definition: pra_constants.hh:278
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Definition: pcstate.hh:57
gem5::CheckerCPU::setIcachePort
void setIcachePort(RequestPort *icache_port)
Definition: cpu.cc:119
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
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gem5::AtomicOpFunctorPtr
std::unique_ptr< AtomicOpFunctor > AtomicOpFunctorPtr
Definition: amo.hh:242
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::CheckerCPU::setIntRegOperand
void setIntRegOperand(const StaticInst *si, int idx, RegVal val) override
Sets an integer register to a value.
Definition: cpu.hh:248
gem5::CheckerCPU::curMacroStaticInst
StaticInstPtr curMacroStaticInst
Definition: cpu.hh:141
gem5::Checker
Templated Checker class.
Definition: cpu.hh:531
gem5::CheckerCPU::updateOnError
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Definition: cpu.hh:518
gem5::CheckerCPU::setFloatRegOperandBits
void setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) override
Sets the bits of a floating point register of single width to a binary value.
Definition: cpu.hh:257
gem5::CheckerCPU::totalOps
virtual Counter totalOps() const override
Definition: cpu.hh:158
gem5::SimpleThread::setPredicate
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Definition: simple_thread.hh:432
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Definition: cpu_impl.hh:658
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Definition: inst_res.hh:50
gem5::CheckerCPU::unverifiedMemData
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Definition: cpu.hh:512
gem5::SimpleThread::setCCReg
void setCCReg(RegIndex reg_idx, RegVal val) override
Definition: simple_thread.hh:413
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int16_t ThreadID
Thread index/ID type.
Definition: types.hh:242
gem5::CheckerCPU::unverifiedResult
InstResult unverifiedResult
Definition: cpu.hh:510
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:113
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
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void setSystem(System *system)
Definition: cpu.cc:97
eventq.hh

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