gem5  v22.0.0.2
cpu.hh
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41 
42 #ifndef __CPU_CHECKER_CPU_HH__
43 #define __CPU_CHECKER_CPU_HH__
44 
45 #include <list>
46 #include <map>
47 #include <queue>
48 
49 #include "arch/generic/pcstate.hh"
50 #include "base/statistics.hh"
51 #include "cpu/base.hh"
52 #include "cpu/exec_context.hh"
53 #include "cpu/inst_res.hh"
54 #include "cpu/pc_event.hh"
55 #include "cpu/simple_thread.hh"
56 #include "cpu/static_inst.hh"
57 #include "debug/Checker.hh"
58 #include "mem/request.hh"
59 #include "params/CheckerCPU.hh"
60 #include "sim/eventq.hh"
61 
62 namespace gem5
63 {
64 
65 class ThreadContext;
66 class Request;
67 
84 class CheckerCPU : public BaseCPU, public ExecContext
85 {
86  protected:
89 
90  public:
91  void init() override;
92 
94  CheckerCPU(const Params &p);
95  virtual ~CheckerCPU();
96 
97  void setSystem(System *system);
98 
99  void setIcachePort(RequestPort *icache_port);
100 
101  void setDcachePort(RequestPort *dcache_port);
102 
103  Port &
104  getDataPort() override
105  {
106  // the checker does not have ports on its own so return the
107  // data port of the actual CPU core
108  assert(dcachePort);
109  return *dcachePort;
110  }
111 
112  Port &
113  getInstPort() override
114  {
115  // the checker does not have ports on its own so return the
116  // data port of the actual CPU core
117  assert(icachePort);
118  return *icachePort;
119  }
120 
121  protected:
122 
124 
126 
129 
131 
133 
134  // ISAs like ARM can have multiple destination registers to check,
135  // keep them all in a std::queue
136  std::queue<InstResult> result;
137 
140 
141  // number of simulated instructions
144 
145  std::queue<int> miscRegIdxs;
146 
147  public:
148 
149  // Primary thread being run.
151 
152  BaseMMU* getMMUPtr() { return mmu; }
153 
154  virtual Counter totalInsts() const override { return 0; }
155 
156  virtual Counter totalOps() const override { return 0; }
157 
158  // number of simulated loads
161 
162  void serialize(CheckpointOut &cp) const override;
163  void unserialize(CheckpointIn &cp) override;
164 
165  // The register accessor methods provide the index of the
166  // instruction's operand (e.g., 0 or 1), not the architectural
167  // register index, to simplify the implementation of register
168  // renaming. We find the architectural register index by indexing
169  // into the instruction's own operand index table. Note that a
170  // raw pointer to the StaticInst is provided instead of a
171  // ref-counted StaticInstPtr to redice overhead. This is fine as
172  // long as these methods don't copy the pointer into any long-term
173  // storage (which is pretty hard to imagine they would have reason
174  // to do).
175 
176  RegVal
177  getRegOperand(const StaticInst *si, int idx) override
178  {
179  const RegId& id = si->srcRegIdx(idx);
180  if (id.is(InvalidRegClass))
181  return 0;
182  return thread->getReg(id);
183  }
184 
185  void
186  getRegOperand(const StaticInst *si, int idx, void *val) override
187  {
188  thread->getReg(si->srcRegIdx(idx), val);
189  }
190 
191  void *
192  getWritableRegOperand(const StaticInst *si, int idx) override
193  {
194  return thread->getWritableReg(si->destRegIdx(idx));
195  }
196 
197  void
198  setRegOperand(const StaticInst *si, int idx, RegVal val) override
199  {
200  const RegId& id = si->destRegIdx(idx);
201  if (id.is(InvalidRegClass))
202  return;
203  thread->setReg(id, val);
204  result.emplace(val);
205  }
206 
207  void
208  setRegOperand(const StaticInst *si, int idx, const void *val) override
209  {
210  const RegId& id = si->destRegIdx(idx);
211  if (id.is(InvalidRegClass))
212  return;
213  thread->setReg(id, val);
214  //TODO setVecResult, setVecPredResult setVecElemResult?
215  }
216 
217  bool readPredicate() const override { return thread->readPredicate(); }
218 
219  void
220  setPredicate(bool val) override
221  {
223  }
224 
225  bool
226  readMemAccPredicate() const override
227  {
228  return thread->readMemAccPredicate();
229  }
230 
231  void
232  setMemAccPredicate(bool val) override
233  {
235  }
236 
237  uint64_t
238  getHtmTransactionUid() const override
239  {
240  panic("not yet supported!");
241  return 0;
242  };
243 
244  uint64_t
245  newHtmTransactionUid() const override
246  {
247  panic("not yet supported!");
248  return 0;
249  };
250 
251  Fault
253  {
254  panic("not yet supported!");
255  return NoFault;
256  }
257 
258  bool
259  inHtmTransactionalState() const override
260  {
261  return (getHtmTransactionalDepth() > 0);
262  }
263 
264  uint64_t
265  getHtmTransactionalDepth() const override
266  {
269  }
270 
271  const PCStateBase &
272  pcState() const override
273  {
274  return thread->pcState();
275  }
276  void
277  pcState(const PCStateBase &val) override
278  {
279  DPRINTF(Checker, "Changing PC to %s, old PC %s.\n",
280  val, thread->pcState());
281  thread->pcState(val);
282  }
284 
285  RegVal
286  readMiscRegNoEffect(int misc_reg) const
287  {
288  return thread->readMiscRegNoEffect(misc_reg);
289  }
290 
291  RegVal
292  readMiscReg(int misc_reg) override
293  {
294  return thread->readMiscReg(misc_reg);
295  }
296 
297  void
299  {
300  DPRINTF(Checker, "Setting misc reg %d with no effect to check later\n",
301  misc_reg);
302  miscRegIdxs.push(misc_reg);
303  return thread->setMiscRegNoEffect(misc_reg, val);
304  }
305 
306  void
307  setMiscReg(int misc_reg, RegVal val) override
308  {
309  DPRINTF(Checker, "Setting misc reg %d with effect to check later\n",
310  misc_reg);
311  miscRegIdxs.push(misc_reg);
312  return thread->setMiscReg(misc_reg, val);
313  }
314 
315  RegVal
316  readMiscRegOperand(const StaticInst *si, int idx) override
317  {
318  const RegId& reg = si->srcRegIdx(idx);
319  assert(reg.is(MiscRegClass));
320  return thread->readMiscReg(reg.index());
321  }
322 
323  void
324  setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override
325  {
326  const RegId& reg = si->destRegIdx(idx);
327  assert(reg.is(MiscRegClass));
328  return this->setMiscReg(reg.index(), val);
329  }
330 
332 
333  void
335  {
336  changedPC = true;
337  set(newPCState, val);
338  }
339 
340  void
341  demapPage(Addr vaddr, uint64_t asn) override
342  {
343  mmu->demapPage(vaddr, asn);
344  }
345 
346  // monitor/mwait funtions
347  void armMonitor(Addr address) override { BaseCPU::armMonitor(0, address); }
348  bool mwait(PacketPtr pkt) override { return BaseCPU::mwait(0, pkt); }
349 
350  void
352  {
353  return BaseCPU::mwaitAtomic(0, tc, thread->mmu);
354  }
355 
356  AddressMonitor *
357  getAddrMonitor() override
358  {
359  return BaseCPU::getCpuAddrMonitor(0);
360  }
361 
378  RequestPtr genMemFragmentRequest(Addr frag_addr, int size,
380  const std::vector<bool>& byte_enable,
381  int& frag_size, int& size_left) const;
382 
383  Fault readMem(Addr addr, uint8_t *data, unsigned size,
385  const std::vector<bool>& byte_enable) override;
386 
387  Fault writeMem(uint8_t *data, unsigned size, Addr addr,
388  Request::Flags flags, uint64_t *res,
389  const std::vector<bool>& byte_enable) override;
390 
391  Fault
392  amoMem(Addr addr, uint8_t* data, unsigned size,
393  Request::Flags flags, AtomicOpFunctorPtr amo_op) override
394  {
395  panic("AMO is not supported yet in CPU checker\n");
396  }
397 
398  unsigned int
399  readStCondFailures() const override
400  {
401  return thread->readStCondFailures();
402  }
403 
404  void setStCondFailures(unsigned int sc_failures) override {}
406 
407  void wakeup(ThreadID tid) override { }
408 
409  void
411  {
412  if (exitOnError)
413  dumpAndExit();
414  }
415 
416  bool checkFlags(const RequestPtr &unverified_req, Addr vAddr,
417  Addr pAddr, int flags);
418 
419  void dumpAndExit();
420 
421  ThreadContext *tcBase() const override { return tc; }
423 
427 
428  bool changedPC;
430  std::unique_ptr<PCStateBase> newPCState;
434 
436 };
437 
444 template <class DynInstPtr>
445 class Checker : public CheckerCPU
446 {
447  public:
448  Checker(const Params &p)
449  : CheckerCPU(p), updateThisCycle(false), unverifiedInst(NULL)
450  { }
451 
452  void switchOut();
453  void takeOverFrom(BaseCPU *oldCPU);
454 
455  void advancePC(const Fault &fault);
456 
457  void verify(const DynInstPtr &inst);
458 
459  void validateInst(const DynInstPtr &inst);
460  void validateExecution(const DynInstPtr &inst);
461  void validateState();
462 
463  void copyResult(const DynInstPtr &inst, const InstResult& mismatch_val,
464  int start_idx);
465  void handlePendingInt();
466 
467  private:
468  void
469  handleError(const DynInstPtr &inst)
470  {
471  if (exitOnError) {
472  dumpAndExit(inst);
473  } else if (updateOnError) {
474  updateThisCycle = true;
475  }
476  }
477 
478  void dumpAndExit(const DynInstPtr &inst);
479 
481 
483 
486  void dumpInsts();
487 };
488 
489 } // namespace gem5
490 
491 #endif // __CPU_CHECKER_CPU_HH__
gem5::SimpleThread::readMiscReg
RegVal readMiscReg(RegIndex misc_reg) override
Definition: simple_thread.hh:277
gem5::CheckerCPU::pcState
const PCStateBase & pcState() const override
Definition: cpu.hh:272
gem5::CheckerCPU::CheckerCPU
CheckerCPU(const Params &p)
Definition: cpu.cc:65
gem5::SimpleThread::getWritableReg
void * getWritableReg(const RegId &arch_reg) override
Definition: simple_thread.hh:380
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:253
gem5::Checker::validateInst
void validateInst(const DynInstPtr &inst)
Definition: cpu_impl.hh:442
gem5::CheckerCPU::numInst
Counter numInst
Definition: cpu.hh:142
gem5::CheckerCPU::amoMem
Fault amoMem(Addr addr, uint8_t *data, unsigned size, Request::Flags flags, AtomicOpFunctorPtr amo_op) override
Definition: cpu.hh:392
gem5::SimpleThread::getReg
RegVal getReg(const RegId &arch_reg) const override
Definition: simple_thread.hh:321
gem5::CheckerCPU::totalInsts
virtual Counter totalInsts() const override
Definition: cpu.hh:154
gem5::Checker::verify
void verify(const DynInstPtr &inst)
Definition: cpu_impl.hh:120
gem5::SimpleThread::htmTransactionStops
int64_t htmTransactionStops
Definition: simple_thread.hh:138
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::CheckerCPU::serialize
void serialize(CheckpointOut &cp) const override
Definition: cpu.cc:130
data
const char data[]
Definition: circlebuf.test.cc:48
gem5::Checker::updateThisCycle
bool updateThisCycle
Definition: cpu.hh:480
gem5::CheckerCPU::getMMUPtr
BaseMMU * getMMUPtr()
Definition: cpu.hh:152
gem5::CheckerCPU::readPredicate
bool readPredicate() const override
Definition: cpu.hh:217
gem5::InvalidRegClass
@ InvalidRegClass
Definition: reg_class.hh:67
gem5::CheckerCPU::~CheckerCPU
virtual ~CheckerCPU()
Definition: cpu.cc:91
gem5::Checker::advancePC
void advancePC(const Fault &fault)
Definition: cpu_impl.hh:67
gem5::CheckerCPU::readMiscRegNoEffect
RegVal readMiscRegNoEffect(int misc_reg) const
Definition: cpu.hh:286
gem5::CheckerCPU::setStCondFailures
void setStCondFailures(unsigned int sc_failures) override
Sets the number of consecutive store conditional failures.
Definition: cpu.hh:404
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::ArmISA::set
Bitfield< 12, 11 > set
Definition: misc_types.hh:703
gem5::CheckerCPU::unverifiedReq
RequestPtr unverifiedReq
Definition: cpu.hh:425
gem5::CheckerCPU::readStCondFailures
unsigned int readStCondFailures() const override
Returns the number of consecutive store conditional failures.
Definition: cpu.hh:399
gem5::o3::DynInstPtr
RefCountingPtr< DynInst > DynInstPtr
Definition: dyn_inst_ptr.hh:55
gem5::CheckerCPU::genMemFragmentRequest
RequestPtr genMemFragmentRequest(Addr frag_addr, int size, Request::Flags flags, const std::vector< bool > &byte_enable, int &frag_size, int &size_left) const
Helper function used to generate the request for a single fragment of a memory access.
Definition: cpu.cc:140
gem5::CheckerCPU::workload
std::vector< Process * > workload
Definition: cpu.hh:123
gem5::Checker::instList
std::list< DynInstPtr > instList
Definition: cpu.hh:484
gem5::CheckerCPU::setRegOperand
void setRegOperand(const StaticInst *si, int idx, const void *val) override
Definition: cpu.hh:208
gem5::CheckerCPU::armMonitor
void armMonitor(Addr address) override
Definition: cpu.hh:347
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:769
gem5::CheckerCPU::setRegOperand
void setRegOperand(const StaticInst *si, int idx, RegVal val) override
Definition: cpu.hh:198
gem5::SimpleThread::setMiscReg
void setMiscReg(RegIndex misc_reg, RegVal val) override
Definition: simple_thread.hh:289
gem5::Checker::handleError
void handleError(const DynInstPtr &inst)
Definition: cpu.hh:469
gem5::CheckerCPU::thread
SimpleThread * thread
Definition: cpu.hh:150
gem5::X86ISA::system
Bitfield< 15 > system
Definition: misc.hh:997
std::vector
STL vector class.
Definition: stl.hh:37
gem5::CheckerCPU::readMemAccPredicate
bool readMemAccPredicate() const override
Definition: cpu.hh:226
gem5::CheckerCPU::readMiscRegOperand
RegVal readMiscRegOperand(const StaticInst *si, int idx) override
Definition: cpu.hh:316
gem5::CheckerCPU::getRegOperand
RegVal getRegOperand(const StaticInst *si, int idx) override
Definition: cpu.hh:177
gem5::CheckerCPU::miscRegIdxs
std::queue< int > miscRegIdxs
Definition: cpu.hh:145
gem5::SimpleThread::setReg
void setReg(const RegId &arch_reg, RegVal val) override
Definition: simple_thread.hh:399
gem5::CheckerCPU::willChangePC
bool willChangePC
Definition: cpu.hh:429
gem5::SimpleThread::htmTransactionStarts
int64_t htmTransactionStarts
Definition: simple_thread.hh:137
inst_res.hh
gem5::Checker::copyResult
void copyResult(const DynInstPtr &inst, const InstResult &mismatch_val, int start_idx)
Definition: cpu_impl.hh:576
gem5::SimpleThread
The SimpleThread object provides a combination of the ThreadState object and the ThreadContext interf...
Definition: simple_thread.hh:95
gem5::CheckerCPU::writeMem
Fault writeMem(uint8_t *data, unsigned size, Addr addr, Request::Flags flags, uint64_t *res, const std::vector< bool > &byte_enable) override
Definition: cpu.cc:251
request.hh
gem5::CheckerCPU::getHtmTransactionUid
uint64_t getHtmTransactionUid() const override
Definition: cpu.hh:238
gem5::CheckerCPU::wakeup
void wakeup(ThreadID tid) override
Definition: cpu.hh:407
gem5::Checker::handlePendingInt
void handlePendingInt()
Definition: cpu_impl.hh:86
gem5::MipsISA::is
Bitfield< 24, 22 > is
Definition: pra_constants.hh:235
gem5::RefCountingPtr< StaticInst >
gem5::BaseMMU
Definition: mmu.hh:53
gem5::CheckerCPU::youngestSN
InstSeqNum youngestSN
Definition: cpu.hh:435
gem5::RequestPort
A RequestPort is a specialisation of a Port, which implements the default protocol for the three diff...
Definition: port.hh:77
gem5::Checker::Checker
Checker(const Params &p)
Definition: cpu.hh:448
gem5::CheckerCPU::dumpAndExit
void dumpAndExit()
Definition: cpu.cc:373
gem5::Checker::unverifiedInst
DynInstPtr unverifiedInst
Definition: cpu.hh:482
gem5::SimpleThread::readStCondFailures
unsigned readStCondFailures() const override
Definition: simple_thread.hh:300
gem5::SimpleThread::mmu
BaseMMU * mmu
Definition: simple_thread.hh:132
gem5::CheckerCPU::setMiscReg
void setMiscReg(int misc_reg, RegVal val) override
Sets a miscellaneous register, handling any architectural side effects due to writing that register.
Definition: cpu.hh:307
gem5::CheckerCPU::tc
ThreadContext * tc
Definition: cpu.hh:130
gem5::SimpleThread::readMemAccPredicate
bool readMemAccPredicate()
Definition: simple_thread.hh:303
gem5::Flags< FlagsType >
gem5::CheckerCPU::setMemAccPredicate
void setMemAccPredicate(bool val) override
Definition: cpu.hh:232
gem5::System
Definition: system.hh:75
gem5::StaticInst
Base, ISA-independent static instruction class.
Definition: static_inst.hh:88
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:248
gem5::VegaISA::p
Bitfield< 54 > p
Definition: pagetable.hh:70
gem5::SimpleThread::readPredicate
bool readPredicate() const
Definition: simple_thread.hh:267
gem5::CheckerCPU::dcachePort
RequestPort * dcachePort
Definition: cpu.hh:128
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::SimpleThread::readMiscRegNoEffect
RegVal readMiscRegNoEffect(RegIndex misc_reg) const override
Definition: simple_thread.hh:271
gem5::CheckerCPU::demapPage
void demapPage(Addr vaddr, uint64_t asn) override
Invalidate a page in the DTLB and ITLB.
Definition: cpu.hh:341
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:291
gem5::CheckerCPU::newHtmTransactionUid
uint64_t newHtmTransactionUid() const override
Definition: cpu.hh:245
statistics.hh
gem5::CheckerCPU::newPCState
std::unique_ptr< PCStateBase > newPCState
Definition: cpu.hh:430
gem5::CheckerCPU
CheckerCPU class.
Definition: cpu.hh:84
gem5::SimpleThread::setMiscRegNoEffect
void setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override
Definition: simple_thread.hh:283
gem5::SimpleThread::setMemAccPredicate
void setMemAccPredicate(bool val)
Definition: simple_thread.hh:309
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::BaseMMU::demapPage
void demapPage(Addr vaddr, uint64_t asn)
Definition: mmu.cc:97
gem5::CheckerCPU::icachePort
RequestPort * icachePort
Definition: cpu.hh:127
gem5::CheckerCPU::mwaitAtomic
void mwaitAtomic(ThreadContext *tc) override
Definition: cpu.hh:351
gem5::CheckerCPU::systemPtr
System * systemPtr
Definition: cpu.hh:125
flags
uint8_t flags
Definition: helpers.cc:66
static_inst.hh
gem5::CheckerCPU::tcBase
ThreadContext * tcBase() const override
Returns a pointer to the ThreadContext.
Definition: cpu.hh:421
gem5::Checker::validateExecution
void validateExecution(const DynInstPtr &inst)
Definition: cpu_impl.hh:463
gem5::CheckerCPU::result
std::queue< InstResult > result
Definition: cpu.hh:136
gem5::CheckerCPU::numLoad
Counter numLoad
Definition: cpu.hh:159
gem5::CheckerCPU::startNumInst
Counter startNumInst
Definition: cpu.hh:143
gem5::CheckerCPU::requestorId
RequestorID requestorId
id attached to all issued requests
Definition: cpu.hh:88
gem5::SimpleThread::pcState
const PCStateBase & pcState() const override
Definition: simple_thread.hh:258
gem5::CheckerCPU::recordPCChange
void recordPCChange(const PCStateBase &val)
Definition: cpu.hh:334
gem5::CheckerCPU::changedPC
bool changedPC
Definition: cpu.hh:428
gem5::CheckerCPU::pcState
void pcState(const PCStateBase &val) override
Definition: cpu.hh:277
gem5::ArmISA::si
Bitfield< 6 > si
Definition: misc_types.hh:825
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::CheckerCPU::setMiscRegOperand
void setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override
Definition: cpu.hh:324
gem5::CheckerCPU::mmu
BaseMMU * mmu
Definition: cpu.hh:132
gem5::CheckerCPU::readMem
Fault readMem(Addr addr, uint8_t *data, unsigned size, Request::Flags flags, const std::vector< bool > &byte_enable) override
Definition: cpu.cc:167
gem5::CheckerCPU::getWritableRegOperand
void * getWritableRegOperand(const StaticInst *si, int idx) override
Definition: cpu.hh:192
gem5::CheckerCPU::exitOnError
bool exitOnError
Definition: cpu.hh:431
gem5::CheckerCPU::checkFlags
bool checkFlags(const RequestPtr &unverified_req, Addr vAddr, Addr pAddr, int flags)
Checks if the flags set by the Checker and Checkee match.
Definition: cpu.cc:356
gem5::CheckerCPU::getDataPort
Port & getDataPort() override
Definition: cpu.hh:104
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::CheckerCPU::readMiscReg
RegVal readMiscReg(int misc_reg) override
Reads a miscellaneous register, handling any architectural side effects due to reading that register.
Definition: cpu.hh:292
pcstate.hh
gem5::CheckerCPU::init
void init() override
Definition: cpu.cc:59
gem5::CheckerCPU::threadBase
SimpleThread * threadBase()
Definition: cpu.hh:422
gem5::CheckerCPU::getInstPort
Port & getInstPort() override
Definition: cpu.hh:113
gem5::CheckerCPU::unserialize
void unserialize(CheckpointIn &cp) override
Definition: cpu.cc:135
gem5::CheckerCPU::handleError
void handleError()
Definition: cpu.hh:410
simple_thread.hh
gem5::Checker::takeOverFrom
void takeOverFrom(BaseCPU *oldCPU)
Definition: cpu_impl.hh:438
gem5::CheckerCPU::curStaticInst
StaticInstPtr curStaticInst
Definition: cpu.hh:138
gem5::CheckerCPU::setDcachePort
void setDcachePort(RequestPort *dcache_port)
Definition: cpu.cc:124
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Definition: cpu.hh:220
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Ports are used to interface objects to each other.
Definition: port.hh:61
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@ MiscRegClass
Control (misc) register.
Definition: reg_class.hh:66
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Definition: cpu.hh:485
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Definition: cpu.hh:348
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Definition: types.hh:47
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Definition: cpu_impl.hh:432
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Definition: cpu.hh:433
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Definition: cpu.hh:298
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Initiate a memory management command with no valid address.
Definition: cpu.hh:252
gem5::CheckerCPU::getHtmTransactionalDepth
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Definition: cpu.hh:265
gem5::CheckerCPU::inHtmTransactionalState
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Definition: cpu.hh:259
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Definition: exec_context.hh:73
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Definition: cpu.hh:160
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Definition: inst_seq.hh:40
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Definition: serialize.hh:66
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Definition: cpu_impl.hh:550
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Definition: request.hh:95
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Definition: cpu.hh:357
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Definition: pra_constants.hh:278
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Definition: pcstate.hh:57
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Definition: cpu.cc:118
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Definition: reg_class.hh:188
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Definition: amo.hh:242
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Definition: cpu.hh:186
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Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
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Definition: cpu.hh:139
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Definition: cpu.hh:445
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Definition: cpu.hh:432
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Definition: cpu.hh:156
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Definition: simple_thread.hh:268
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Definition: inst_res.hh:50
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Definition: cpu.hh:426
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Definition: types.hh:235
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Definition: cpu.hh:424
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Definition: reg_class.hh:126
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Definition: logging.hh:178
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Definition: types.hh:84
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Definition: cpu.cc:96
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