gem5  v21.1.0.2
cpu.hh
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41 
42 #ifndef __CPU_CHECKER_CPU_HH__
43 #define __CPU_CHECKER_CPU_HH__
44 
45 #include <list>
46 #include <map>
47 #include <queue>
48 
49 #include "arch/pcstate.hh"
50 #include "base/statistics.hh"
51 #include "cpu/base.hh"
52 #include "cpu/exec_context.hh"
53 #include "cpu/inst_res.hh"
54 #include "cpu/pc_event.hh"
55 #include "cpu/simple_thread.hh"
56 #include "cpu/static_inst.hh"
57 #include "debug/Checker.hh"
58 #include "mem/request.hh"
59 #include "params/CheckerCPU.hh"
60 #include "sim/eventq.hh"
61 
62 namespace gem5
63 {
64 
65 class ThreadContext;
66 class Request;
67 
84 class CheckerCPU : public BaseCPU, public ExecContext
85 {
86  protected:
89 
91 
92  public:
93  void init() override;
94 
96  CheckerCPU(const Params &p);
97  virtual ~CheckerCPU();
98 
99  void setSystem(System *system);
100 
101  void setIcachePort(RequestPort *icache_port);
102 
103  void setDcachePort(RequestPort *dcache_port);
104 
105  Port &
106  getDataPort() override
107  {
108  // the checker does not have ports on its own so return the
109  // data port of the actual CPU core
110  assert(dcachePort);
111  return *dcachePort;
112  }
113 
114  Port &
115  getInstPort() override
116  {
117  // the checker does not have ports on its own so return the
118  // data port of the actual CPU core
119  assert(icachePort);
120  return *icachePort;
121  }
122 
123  protected:
124 
126 
128 
131 
133 
135 
136  // ISAs like ARM can have multiple destination registers to check,
137  // keep them all in a std::queue
138  std::queue<InstResult> result;
139 
142 
143  // number of simulated instructions
146 
147  std::queue<int> miscRegIdxs;
148 
149  public:
150 
151  // Primary thread being run.
153 
154  BaseMMU* getMMUPtr() { return mmu; }
155 
156  virtual Counter totalInsts() const override
157  {
158  return 0;
159  }
160 
161  virtual Counter totalOps() const override
162  {
163  return 0;
164  }
165 
166  // number of simulated loads
169 
170  void serialize(CheckpointOut &cp) const override;
171  void unserialize(CheckpointIn &cp) override;
172 
173  // The register accessor methods provide the index of the
174  // instruction's operand (e.g., 0 or 1), not the architectural
175  // register index, to simplify the implementation of register
176  // renaming. We find the architectural register index by indexing
177  // into the instruction's own operand index table. Note that a
178  // raw pointer to the StaticInst is provided instead of a
179  // ref-counted StaticInstPtr to redice overhead. This is fine as
180  // long as these methods don't copy the pointer into any long-term
181  // storage (which is pretty hard to imagine they would have reason
182  // to do).
183 
184  RegVal
185  readIntRegOperand(const StaticInst *si, int idx) override
186  {
187  const RegId& reg = si->srcRegIdx(idx);
188  assert(reg.is(IntRegClass));
189  return thread->readIntReg(reg.index());
190  }
191 
192  RegVal
193  readFloatRegOperandBits(const StaticInst *si, int idx) override
194  {
195  const RegId& reg = si->srcRegIdx(idx);
196  assert(reg.is(FloatRegClass));
197  return thread->readFloatReg(reg.index());
198  }
199 
204  readVecRegOperand(const StaticInst *si, int idx) const override
205  {
206  const RegId& reg = si->srcRegIdx(idx);
207  assert(reg.is(VecRegClass));
208  return thread->readVecReg(reg);
209  }
210 
215  getWritableVecRegOperand(const StaticInst *si, int idx) override
216  {
217  const RegId& reg = si->destRegIdx(idx);
218  assert(reg.is(VecRegClass));
219  return thread->getWritableVecReg(reg);
220  }
221 
223  readVecElemOperand(const StaticInst *si, int idx) const override
224  {
225  const RegId& reg = si->srcRegIdx(idx);
226  return thread->readVecElem(reg);
227  }
228 
230  readVecPredRegOperand(const StaticInst *si, int idx) const override
231  {
232  const RegId& reg = si->srcRegIdx(idx);
233  assert(reg.is(VecPredRegClass));
234  return thread->readVecPredReg(reg);
235  }
236 
238  getWritableVecPredRegOperand(const StaticInst *si, int idx) override
239  {
240  const RegId& reg = si->destRegIdx(idx);
241  assert(reg.is(VecPredRegClass));
243  }
244 
245  RegVal
246  readCCRegOperand(const StaticInst *si, int idx) override
247  {
248  const RegId& reg = si->srcRegIdx(idx);
249  assert(reg.is(CCRegClass));
250  return thread->readCCReg(reg.index());
251  }
252 
253  template<typename T>
254  void
256  {
257  result.push(InstResult(std::forward<T>(t),
259  }
260 
261  template<typename T>
262  void
264  {
265  result.push(InstResult(std::forward<T>(t),
267  }
268 
269  template<typename T>
270  void
272  {
273  result.push(InstResult(std::forward<T>(t),
275  }
276 
277  template<typename T>
278  void
280  {
281  result.push(InstResult(std::forward<T>(t),
283  }
284 
285  void
286  setIntRegOperand(const StaticInst *si, int idx, RegVal val) override
287  {
288  const RegId& reg = si->destRegIdx(idx);
289  assert(reg.is(IntRegClass));
290  thread->setIntReg(reg.index(), val);
292  }
293 
294  void
295  setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) override
296  {
297  const RegId& reg = si->destRegIdx(idx);
298  assert(reg.is(FloatRegClass));
299  thread->setFloatReg(reg.index(), val);
301  }
302 
303  void
304  setCCRegOperand(const StaticInst *si, int idx, RegVal val) override
305  {
306  const RegId& reg = si->destRegIdx(idx);
307  assert(reg.is(CCRegClass));
308  thread->setCCReg(reg.index(), val);
309  setScalarResult((uint64_t)val);
310  }
311 
312  void
313  setVecRegOperand(const StaticInst *si, int idx,
314  const TheISA::VecRegContainer& val) override
315  {
316  const RegId& reg = si->destRegIdx(idx);
317  assert(reg.is(VecRegClass));
318  thread->setVecReg(reg, val);
319  setVecResult(val);
320  }
321 
322  void
323  setVecElemOperand(const StaticInst *si, int idx,
324  const TheISA::VecElem val) override
325  {
326  const RegId& reg = si->destRegIdx(idx);
327  assert(reg.is(VecElemClass));
330  }
331 
332  void setVecPredRegOperand(const StaticInst *si, int idx,
333  const TheISA::VecPredRegContainer& val) override
334  {
335  const RegId& reg = si->destRegIdx(idx);
336  assert(reg.is(VecPredRegClass));
339  }
340 
341  bool readPredicate() const override { return thread->readPredicate(); }
342 
343  void
344  setPredicate(bool val) override
345  {
347  }
348 
349  bool
350  readMemAccPredicate() const override
351  {
352  return thread->readMemAccPredicate();
353  }
354 
355  void
356  setMemAccPredicate(bool val) override
357  {
359  }
360 
361  uint64_t
362  getHtmTransactionUid() const override
363  {
364  panic("not yet supported!");
365  return 0;
366  };
367 
368  uint64_t
369  newHtmTransactionUid() const override
370  {
371  panic("not yet supported!");
372  return 0;
373  };
374 
375  Fault
377  {
378  panic("not yet supported!");
379  return NoFault;
380  }
381 
382  bool
383  inHtmTransactionalState() const override
384  {
385  return (getHtmTransactionalDepth() > 0);
386  }
387 
388  uint64_t
389  getHtmTransactionalDepth() const override
390  {
393  }
394 
395  TheISA::PCState pcState() const override { return thread->pcState(); }
396  void
397  pcState(const TheISA::PCState &val) override
398  {
399  DPRINTF(Checker, "Changing PC to %s, old PC %s.\n",
400  val, thread->pcState());
401  thread->pcState(val);
402  }
403  Addr instAddr() { return thread->instAddr(); }
405  MicroPC microPC() { return thread->microPC(); }
407 
408  RegVal
409  readMiscRegNoEffect(int misc_reg) const
410  {
411  return thread->readMiscRegNoEffect(misc_reg);
412  }
413 
414  RegVal
415  readMiscReg(int misc_reg) override
416  {
417  return thread->readMiscReg(misc_reg);
418  }
419 
420  void
422  {
423  DPRINTF(Checker, "Setting misc reg %d with no effect to check later\n",
424  misc_reg);
425  miscRegIdxs.push(misc_reg);
426  return thread->setMiscRegNoEffect(misc_reg, val);
427  }
428 
429  void
430  setMiscReg(int misc_reg, RegVal val) override
431  {
432  DPRINTF(Checker, "Setting misc reg %d with effect to check later\n",
433  misc_reg);
434  miscRegIdxs.push(misc_reg);
435  return thread->setMiscReg(misc_reg, val);
436  }
437 
438  RegVal
439  readMiscRegOperand(const StaticInst *si, int idx) override
440  {
441  const RegId& reg = si->srcRegIdx(idx);
442  assert(reg.is(MiscRegClass));
443  return thread->readMiscReg(reg.index());
444  }
445 
446  void
447  setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override
448  {
449  const RegId& reg = si->destRegIdx(idx);
450  assert(reg.is(MiscRegClass));
451  return this->setMiscReg(reg.index(), val);
452  }
453 
455 
456  void
458  {
459  changedPC = true;
460  newPCState = val;
461  }
462 
463  void
464  demapPage(Addr vaddr, uint64_t asn) override
465  {
466  mmu->demapPage(vaddr, asn);
467  }
468 
469  // monitor/mwait funtions
470  void armMonitor(Addr address) override { BaseCPU::armMonitor(0, address); }
471  bool mwait(PacketPtr pkt) override { return BaseCPU::mwait(0, pkt); }
472 
473  void
475  {
476  return BaseCPU::mwaitAtomic(0, tc, thread->mmu);
477  }
478 
480  { return BaseCPU::getCpuAddrMonitor(0); }
481 
498  RequestPtr genMemFragmentRequest(Addr frag_addr, int size,
499  Request::Flags flags,
500  const std::vector<bool>& byte_enable,
501  int& frag_size, int& size_left) const;
502 
503  Fault readMem(Addr addr, uint8_t *data, unsigned size,
504  Request::Flags flags,
505  const std::vector<bool>& byte_enable)
506  override;
507 
508  Fault writeMem(uint8_t *data, unsigned size, Addr addr,
509  Request::Flags flags, uint64_t *res,
510  const std::vector<bool>& byte_enable)
511  override;
512 
513  Fault amoMem(Addr addr, uint8_t* data, unsigned size,
514  Request::Flags flags, AtomicOpFunctorPtr amo_op) override
515  {
516  panic("AMO is not supported yet in CPU checker\n");
517  }
518 
519  unsigned int
520  readStCondFailures() const override {
521  return thread->readStCondFailures();
522  }
523 
524  void setStCondFailures(unsigned int sc_failures) override {}
526 
527  void wakeup(ThreadID tid) override { }
528 
529  void
531  {
532  if (exitOnError)
533  dumpAndExit();
534  }
535 
536  bool checkFlags(const RequestPtr &unverified_req, Addr vAddr,
537  Addr pAddr, int flags);
538 
539  void dumpAndExit();
540 
541  ThreadContext *tcBase() const override { return tc; }
543 
547 
548  bool changedPC;
554 
556 };
557 
564 template <class DynInstPtr>
565 class Checker : public CheckerCPU
566 {
567  public:
568  Checker(const Params &p)
569  : CheckerCPU(p), updateThisCycle(false), unverifiedInst(NULL)
570  { }
571 
572  void switchOut();
573  void takeOverFrom(BaseCPU *oldCPU);
574 
575  void advancePC(const Fault &fault);
576 
577  void verify(const DynInstPtr &inst);
578 
579  void validateInst(const DynInstPtr &inst);
580  void validateExecution(const DynInstPtr &inst);
581  void validateState();
582 
583  void copyResult(const DynInstPtr &inst, const InstResult& mismatch_val,
584  int start_idx);
585  void handlePendingInt();
586 
587  private:
588  void handleError(const DynInstPtr &inst)
589  {
590  if (exitOnError) {
591  dumpAndExit(inst);
592  } else if (updateOnError) {
593  updateThisCycle = true;
594  }
595  }
596 
597  void dumpAndExit(const DynInstPtr &inst);
598 
600 
602 
605  void dumpInsts();
606 };
607 
608 } // namespace gem5
609 
610 #endif // __CPU_CHECKER_CPU_HH__
gem5::SimpleThread::readMiscReg
RegVal readMiscReg(RegIndex misc_reg) override
Definition: simple_thread.hh:452
gem5::CheckerCPU::CheckerCPU
CheckerCPU(const Params &p)
Definition: cpu.cc:65
gem5::SimpleThread::readIntReg
RegVal readIntReg(RegIndex reg_idx) const override
Definition: simple_thread.hh:274
gem5::VecElemClass
@ VecElemClass
Vector Register Native Elem lane.
Definition: reg_class.hh:62
gem5::SimpleThread::readVecElem
const TheISA::VecElem & readVecElem(const RegId &reg) const override
Definition: simple_thread.hh:318
gem5::CCRegClass
@ CCRegClass
Condition-code register.
Definition: reg_class.hh:64
gem5::BaseCPU::armMonitor
void armMonitor(ThreadID tid, Addr address)
Definition: base.cc:205
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:260
gem5::Checker::validateInst
void validateInst(const DynInstPtr &inst)
Definition: cpu_impl.hh:446
gem5::CheckerCPU::numInst
Counter numInst
Definition: cpu.hh:144
gem5::CheckerCPU::amoMem
Fault amoMem(Addr addr, uint8_t *data, unsigned size, Request::Flags flags, AtomicOpFunctorPtr amo_op) override
Definition: cpu.hh:513
gem5::CheckerCPU::setVecResult
void setVecResult(T &&t)
Definition: cpu.hh:263
gem5::CheckerCPU::totalInsts
virtual Counter totalInsts() const override
Definition: cpu.hh:156
gem5::Checker::verify
void verify(const DynInstPtr &inst)
Definition: cpu_impl.hh:122
gem5::SimpleThread::htmTransactionStops
int64_t htmTransactionStops
Definition: simple_thread.hh:140
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::CheckerCPU::readCCRegOperand
RegVal readCCRegOperand(const StaticInst *si, int idx) override
Definition: cpu.hh:246
gem5::SimpleThread::setIntReg
void setIntReg(RegIndex reg_idx, RegVal val) override
Definition: simple_thread.hh:367
gem5::BaseCPU::mwaitAtomic
void mwaitAtomic(ThreadID tid, ThreadContext *tc, BaseMMU *mmu)
Definition: base.cc:240
gem5::ArmISA::VecPredRegContainer
VecPredReg::Container VecPredRegContainer
Definition: vec.hh:68
gem5::SimpleThread::readVecReg
const TheISA::VecRegContainer & readVecReg(const RegId &reg) const override
Definition: simple_thread.hh:296
gem5::CheckerCPU::serialize
void serialize(CheckpointOut &cp) const override
Serialize this object to the given output stream.
Definition: cpu.cc:130
data
const char data[]
Definition: circlebuf.test.cc:48
gem5::Checker::updateThisCycle
bool updateThisCycle
Definition: cpu.hh:599
gem5::CheckerCPU::pcState
void pcState(const TheISA::PCState &val) override
Definition: cpu.hh:397
gem5::CheckerCPU::pcState
TheISA::PCState pcState() const override
Definition: cpu.hh:395
gem5::CheckerCPU::getMMUPtr
BaseMMU * getMMUPtr()
Definition: cpu.hh:154
gem5::CheckerCPU::readPredicate
bool readPredicate() const override
Definition: cpu.hh:341
gem5::CheckerCPU::readFloatRegOperandBits
RegVal readFloatRegOperandBits(const StaticInst *si, int idx) override
Reads a floating point register in its binary format, instead of by value.
Definition: cpu.hh:193
gem5::CheckerCPU::~CheckerCPU
virtual ~CheckerCPU()
Definition: cpu.cc:92
gem5::Checker::advancePC
void advancePC(const Fault &fault)
Definition: cpu_impl.hh:67
gem5::InstResult::ResultType::Scalar
@ Scalar
gem5::CheckerCPU::readMiscRegNoEffect
RegVal readMiscRegNoEffect(int misc_reg) const
Definition: cpu.hh:409
gem5::CheckerCPU::setStCondFailures
void setStCondFailures(unsigned int sc_failures) override
Sets the number of consecutive store conditional failures.
Definition: cpu.hh:524
gem5::CheckerCPU::initiateHtmCmd
Fault initiateHtmCmd(Request::Flags flags) override
Initiate an HTM command, e.g.
Definition: cpu.hh:376
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::SimpleThread::instAddr
Addr instAddr() const override
Definition: simple_thread.hh:439
gem5::CheckerCPU::unverifiedReq
RequestPtr unverifiedReq
Definition: cpu.hh:545
gem5::CheckerCPU::readStCondFailures
unsigned int readStCondFailures() const override
Returns the number of consecutive store conditional failures.
Definition: cpu.hh:520
gem5::CheckerCPU::setVecElemOperand
void setVecElemOperand(const StaticInst *si, int idx, const TheISA::VecElem val) override
Sets a vector register to a value.
Definition: cpu.hh:323
gem5::o3::DynInstPtr
RefCountingPtr< DynInst > DynInstPtr
Definition: dyn_inst_ptr.hh:55
gem5::FloatRegClass
@ FloatRegClass
Floating-point register.
Definition: reg_class.hh:58
gem5::CheckerCPU::genMemFragmentRequest
RequestPtr genMemFragmentRequest(Addr frag_addr, int size, Request::Flags flags, const std::vector< bool > &byte_enable, int &frag_size, int &size_left) const
Helper function used to generate the request for a single fragment of a memory access.
Definition: cpu.cc:140
gem5::CheckerCPU::workload
std::vector< Process * > workload
Definition: cpu.hh:125
gem5::Checker::instList
std::list< DynInstPtr > instList
Definition: cpu.hh:603
gem5::CheckerCPU::microPC
MicroPC microPC()
Definition: cpu.hh:405
gem5::CheckerCPU::armMonitor
void armMonitor(Addr address) override
Definition: cpu.hh:470
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
gem5::SimpleThread::setMiscReg
void setMiscReg(RegIndex misc_reg, RegVal val) override
Definition: simple_thread.hh:464
gem5::MiscRegClass
@ MiscRegClass
Control (misc) register.
Definition: reg_class.hh:65
gem5::Checker::handleError
void handleError(const DynInstPtr &inst)
Definition: cpu.hh:588
gem5::CheckerCPU::setCCRegOperand
void setCCRegOperand(const StaticInst *si, int idx, RegVal val) override
Definition: cpu.hh:304
gem5::VecPredRegClass
@ VecPredRegClass
Definition: reg_class.hh:63
gem5::BaseCPU::system
System * system
Definition: base.hh:376
gem5::CheckerCPU::thread
SimpleThread * thread
Definition: cpu.hh:152
gem5::SimpleThread::setVecReg
void setVecReg(const RegId &reg, const TheISA::VecRegContainer &val) override
Definition: simple_thread.hh:390
gem5::CheckerCPU::getWritableVecRegOperand
TheISA::VecRegContainer & getWritableVecRegOperand(const StaticInst *si, int idx) override
Read destination vector register operand for modification.
Definition: cpu.hh:215
std::vector
STL vector class.
Definition: stl.hh:37
gem5::CheckerCPU::readVecRegOperand
const TheISA::VecRegContainer & readVecRegOperand(const StaticInst *si, int idx) const override
Read source vector register operand.
Definition: cpu.hh:204
gem5::SimpleThread::readCCReg
RegVal readCCReg(RegIndex reg_idx) const override
Definition: simple_thread.hh:355
gem5::CheckerCPU::readMemAccPredicate
bool readMemAccPredicate() const override
Definition: cpu.hh:350
gem5::CheckerCPU::readMiscRegOperand
RegVal readMiscRegOperand(const StaticInst *si, int idx) override
Definition: cpu.hh:439
gem5::CheckerCPU::miscRegIdxs
std::queue< int > miscRegIdxs
Definition: cpu.hh:147
gem5::CheckerCPU::willChangePC
bool willChangePC
Definition: cpu.hh:549
gem5::CheckerCPU::nextInstAddr
Addr nextInstAddr()
Definition: cpu.hh:404
gem5::SimpleThread::htmTransactionStarts
int64_t htmTransactionStarts
Definition: simple_thread.hh:139
inst_res.hh
gem5::Checker::copyResult
void copyResult(const DynInstPtr &inst, const InstResult &mismatch_val, int start_idx)
Definition: cpu_impl.hh:585
gem5::SimpleThread
The SimpleThread object provides a combination of the ThreadState object and the ThreadContext interf...
Definition: simple_thread.hh:94
gem5::RegId::index
RegIndex index() const
Index accessors.
Definition: reg_class.hh:154
gem5::CheckerCPU::writeMem
Fault writeMem(uint8_t *data, unsigned size, Addr addr, Request::Flags flags, uint64_t *res, const std::vector< bool > &byte_enable) override
Definition: cpu.cc:251
request.hh
gem5::SimpleThread::setVecElem
void setVecElem(const RegId &reg, const TheISA::VecElem &val) override
Definition: simple_thread.hh:400
gem5::SimpleThread::setVecPredReg
void setVecPredReg(const RegId &reg, const TheISA::VecPredRegContainer &val) override
Definition: simple_thread.hh:410
gem5::CheckerCPU::getHtmTransactionUid
uint64_t getHtmTransactionUid() const override
Definition: cpu.hh:362
gem5::CheckerCPU::wakeup
void wakeup(ThreadID tid) override
Definition: cpu.hh:527
gem5::Checker::handlePendingInt
void handlePendingInt()
Definition: cpu_impl.hh:88
gem5::RefCountingPtr< StaticInst >
gem5::BaseMMU
Definition: mmu.hh:50
gem5::CheckerCPU::setVecPredRegOperand
void setVecPredRegOperand(const StaticInst *si, int idx, const TheISA::VecPredRegContainer &val) override
Sets a destination predicate register operand to a value.
Definition: cpu.hh:332
gem5::AddressMonitor
Definition: base.hh:73
gem5::CheckerCPU::youngestSN
InstSeqNum youngestSN
Definition: cpu.hh:555
gem5::CheckerCPU::getWritableVecPredRegOperand
TheISA::VecPredRegContainer & getWritableVecPredRegOperand(const StaticInst *si, int idx) override
Gets destination predicate register operand for modification.
Definition: cpu.hh:238
gem5::RequestPort
A RequestPort is a specialisation of a Port, which implements the default protocol for the three diff...
Definition: port.hh:77
gem5::CheckerCPU::recordPCChange
void recordPCChange(const TheISA::PCState &val)
Definition: cpu.hh:457
gem5::Checker::Checker
Checker(const Params &p)
Definition: cpu.hh:568
gem5::SimpleThread::microPC
MicroPC microPC() const override
Definition: simple_thread.hh:441
gem5::CheckerCPU::dumpAndExit
void dumpAndExit()
Definition: cpu.cc:373
gem5::Checker::unverifiedInst
DynInstPtr unverifiedInst
Definition: cpu.hh:601
gem5::SimpleThread::readStCondFailures
unsigned readStCondFailures() const override
Definition: simple_thread.hh:475
gem5::SimpleThread::mmu
BaseMMU * mmu
Definition: simple_thread.hh:134
gem5::CheckerCPU::setMiscReg
void setMiscReg(int misc_reg, RegVal val) override
Sets a miscellaneous register, handling any architectural side effects due to writing that register.
Definition: cpu.hh:430
gem5::MicroPC
uint16_t MicroPC
Definition: types.hh:149
gem5::CheckerCPU::tc
ThreadContext * tc
Definition: cpu.hh:132
gem5::SimpleThread::readMemAccPredicate
bool readMemAccPredicate()
Definition: simple_thread.hh:478
gem5::Flags< FlagsType >
gem5::CheckerCPU::readVecPredRegOperand
const TheISA::VecPredRegContainer & readVecPredRegOperand(const StaticInst *si, int idx) const override
Predicate registers interface.
Definition: cpu.hh:230
gem5::CheckerCPU::setMemAccPredicate
void setMemAccPredicate(bool val) override
Definition: cpu.hh:356
gem5::System
Definition: system.hh:77
gem5::StaticInst
Base, ISA-independent static instruction class.
Definition: static_inst.hh:88
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::SimpleThread::readPredicate
bool readPredicate() const
Definition: simple_thread.hh:442
gem5::CheckerCPU::dcachePort
RequestPort * dcachePort
Definition: cpu.hh:130
gem5::CheckerCPU::readVecElemOperand
TheISA::VecElem readVecElemOperand(const StaticInst *si, int idx) const override
Vector Elem Interfaces.
Definition: cpu.hh:223
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::SimpleThread::readMiscRegNoEffect
RegVal readMiscRegNoEffect(RegIndex misc_reg) const override
Definition: simple_thread.hh:446
gem5::CheckerCPU::demapPage
void demapPage(Addr vaddr, uint64_t asn) override
Invalidate a page in the DTLB and ITLB.
Definition: cpu.hh:464
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::CheckerCPU::setVecPredResult
void setVecPredResult(T &&t)
Definition: cpu.hh:279
gem5::CheckerCPU::newHtmTransactionUid
uint64_t newHtmTransactionUid() const override
Definition: cpu.hh:369
gem5::CheckerCPU::zeroReg
const RegIndex zeroReg
Definition: cpu.hh:90
gem5::MipsISA::PCState
GenericISA::DelaySlotPCState< 4 > PCState
Definition: pcstate.hh:40
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
statistics.hh
gem5::CheckerCPU
CheckerCPU class.
Definition: cpu.hh:84
gem5::SimpleThread::setMiscRegNoEffect
void setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override
Definition: simple_thread.hh:458
gem5::SimpleThread::setMemAccPredicate
void setMemAccPredicate(bool val)
Definition: simple_thread.hh:484
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::BaseMMU::demapPage
void demapPage(Addr vaddr, uint64_t asn)
Definition: mmu.cc:58
gem5::BaseCPU
Definition: base.hh:107
gem5::CheckerCPU::icachePort
RequestPort * icachePort
Definition: cpu.hh:129
gem5::CheckerCPU::mwaitAtomic
void mwaitAtomic(ThreadContext *tc) override
Definition: cpu.hh:474
gem5::ArmISA::VecRegContainer
gem5::VecRegContainer< NumVecElemPerVecReg *sizeof(VecElem)> VecRegContainer
Definition: vec.hh:62
gem5::CheckerCPU::systemPtr
System * systemPtr
Definition: cpu.hh:127
static_inst.hh
gem5::CheckerCPU::tcBase
ThreadContext * tcBase() const override
Returns a pointer to the ThreadContext.
Definition: cpu.hh:541
gem5::SimpleThread::pcState
TheISA::PCState pcState() const override
Definition: simple_thread.hh:430
gem5::Checker::validateExecution
void validateExecution(const DynInstPtr &inst)
Definition: cpu_impl.hh:467
gem5::CheckerCPU::result
std::queue< InstResult > result
Definition: cpu.hh:138
gem5::CheckerCPU::numLoad
Counter numLoad
Definition: cpu.hh:167
gem5::CheckerCPU::startNumInst
Counter startNumInst
Definition: cpu.hh:145
gem5::ArmISA::t
Bitfield< 5 > t
Definition: misc_types.hh:70
gem5::CheckerCPU::requestorId
RequestorID requestorId
id attached to all issued requests
Definition: cpu.hh:88
gem5::CheckerCPU::changedPC
bool changedPC
Definition: cpu.hh:548
gem5::InstResult::ResultType::VecReg
@ VecReg
gem5::ArmISA::si
Bitfield< 6 > si
Definition: misc_types.hh:772
gem5::BaseCPU::getCpuAddrMonitor
AddressMonitor * getCpuAddrMonitor(ThreadID tid)
Definition: base.hh:609
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::InstResult::ResultType::VecPredReg
@ VecPredReg
gem5::SimpleThread::setFloatReg
void setFloatReg(RegIndex reg_idx, RegVal val) override
Definition: simple_thread.hh:377
gem5::CheckerCPU::setMiscRegOperand
void setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override
Definition: cpu.hh:447
gem5::CheckerCPU::mmu
BaseMMU * mmu
Definition: cpu.hh:134
gem5::CheckerCPU::readMem
Fault readMem(Addr addr, uint8_t *data, unsigned size, Request::Flags flags, const std::vector< bool > &byte_enable) override
Definition: cpu.cc:167
gem5::SimpleThread::readFloatReg
RegVal readFloatReg(RegIndex reg_idx) const override
Definition: simple_thread.hh:285
gem5::CheckerCPU::exitOnError
bool exitOnError
Definition: cpu.hh:551
gem5::CheckerCPU::checkFlags
bool checkFlags(const RequestPtr &unverified_req, Addr vAddr, Addr pAddr, int flags)
Checks if the flags set by the Checker and Checkee match.
Definition: cpu.cc:356
gem5::CheckerCPU::setVecRegOperand
void setVecRegOperand(const StaticInst *si, int idx, const TheISA::VecRegContainer &val) override
Sets a destination vector register operand to a value.
Definition: cpu.hh:313
gem5::CheckerCPU::getDataPort
Port & getDataPort() override
Purely virtual method that returns a reference to the data port.
Definition: cpu.hh:106
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::InstResult::ResultType::VecElem
@ VecElem
gem5::SimpleThread::getWritableVecPredReg
TheISA::VecPredRegContainer & getWritableVecPredReg(const RegId &reg) override
Definition: simple_thread.hh:342
gem5::CheckerCPU::readMiscReg
RegVal readMiscReg(int misc_reg) override
Reads a miscellaneous register, handling any architectural side effects due to reading that register.
Definition: cpu.hh:415
gem5::SimpleThread::nextInstAddr
Addr nextInstAddr() const override
Definition: simple_thread.hh:440
gem5::CheckerCPU::init
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: cpu.cc:59
gem5::CheckerCPU::newPCState
TheISA::PCState newPCState
Definition: cpu.hh:550
gem5::CheckerCPU::threadBase
SimpleThread * threadBase()
Definition: cpu.hh:542
gem5::VecRegClass
@ VecRegClass
Vector Register.
Definition: reg_class.hh:60
gem5::SimpleThread::getWritableVecReg
TheISA::VecRegContainer & getWritableVecReg(const RegId &reg) override
Definition: simple_thread.hh:307
gem5::CheckerCPU::getInstPort
Port & getInstPort() override
Purely virtual method that returns a reference to the instruction port.
Definition: cpu.hh:115
gem5::CheckerCPU::unserialize
void unserialize(CheckpointIn &cp) override
Reconstruct the state of this object from a checkpoint.
Definition: cpu.cc:135
gem5::CheckerCPU::handleError
void handleError()
Definition: cpu.hh:530
simple_thread.hh
gem5::SimpleThread::readVecPredReg
const TheISA::VecPredRegContainer & readVecPredReg(const RegId &reg) const override
Definition: simple_thread.hh:330
gem5::Checker::takeOverFrom
void takeOverFrom(BaseCPU *oldCPU)
Load the state of a CPU from the previous CPU object, invoked on all new CPUs that are about to be sw...
Definition: cpu_impl.hh:442
gem5::CheckerCPU::curStaticInst
StaticInstPtr curStaticInst
Definition: cpu.hh:140
gem5::CheckerCPU::setDcachePort
void setDcachePort(RequestPort *dcache_port)
Definition: cpu.cc:124
gem5::CheckerCPU::setPredicate
void setPredicate(bool val) override
Definition: cpu.hh:344
base.hh
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
gem5::CheckerCPU::setVecElemResult
void setVecElemResult(T &&t)
Definition: cpu.hh:271
pc_event.hh
gem5::ArmISA::VecElem
uint32_t VecElem
Definition: vec.hh:60
gem5::Checker::InstListIt
std::list< DynInstPtr >::iterator InstListIt
Definition: cpu.hh:604
gem5::CheckerCPU::PARAMS
PARAMS(CheckerCPU)
gem5::CheckerCPU::mwait
bool mwait(PacketPtr pkt) override
Definition: cpu.hh:471
exec_context.hh
gem5::CheckerCPU::readIntRegOperand
RegVal readIntRegOperand(const StaticInst *si, int idx) override
Reads an integer register.
Definition: cpu.hh:185
gem5::statistics::Counter
double Counter
All counters are of 64-bit values.
Definition: types.hh:47
gem5::Checker::switchOut
void switchOut()
Prepare for another CPU to take over execution.
Definition: cpu_impl.hh:436
gem5::CheckerCPU::warnOnlyOnLoadError
bool warnOnlyOnLoadError
Definition: cpu.hh:553
gem5::CheckerCPU::setMiscRegNoEffect
void setMiscRegNoEffect(int misc_reg, RegVal val)
Definition: cpu.hh:421
gem5::CheckerCPU::getHtmTransactionalDepth
uint64_t getHtmTransactionalDepth() const override
Definition: cpu.hh:389
gem5::CheckerCPU::inHtmTransactionalState
bool inHtmTransactionalState() const override
Definition: cpu.hh:383
gem5::ExecContext
The ExecContext is an abstract base class the provides the interface used by the ISA to manipulate th...
Definition: exec_context.hh:73
gem5::CheckerCPU::startNumLoad
Counter startNumLoad
Definition: cpu.hh:168
gem5::InstSeqNum
uint64_t InstSeqNum
Definition: inst_seq.hh:40
gem5::CheckerCPU::setScalarResult
void setScalarResult(T &&t)
Definition: cpu.hh:255
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::Checker::validateState
void validateState()
Definition: cpu_impl.hh:560
gem5::RequestorID
uint16_t RequestorID
Definition: request.hh:95
gem5::ClockedObject::Params
ClockedObjectParams Params
Parameters of ClockedObject.
Definition: clocked_object.hh:240
gem5::CheckerCPU::getAddrMonitor
AddressMonitor * getAddrMonitor() override
Definition: cpu.hh:479
gem5::BaseCPU::mwait
bool mwait(ThreadID tid, PacketPtr pkt)
Definition: base.cc:217
gem5::MipsISA::vaddr
vaddr
Definition: pra_constants.hh:278
gem5::CheckerCPU::setIcachePort
void setIcachePort(RequestPort *icache_port)
Definition: cpu.cc:118
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
std::list< DynInstPtr >
gem5::AtomicOpFunctorPtr
std::unique_ptr< AtomicOpFunctor > AtomicOpFunctorPtr
Definition: amo.hh:242
gem5::IntRegClass
@ IntRegClass
Integer register.
Definition: reg_class.hh:57
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::CheckerCPU::setIntRegOperand
void setIntRegOperand(const StaticInst *si, int idx, RegVal val) override
Sets an integer register to a value.
Definition: cpu.hh:286
gem5::CheckerCPU::curMacroStaticInst
StaticInstPtr curMacroStaticInst
Definition: cpu.hh:141
gem5::Checker
Templated Checker class.
Definition: cpu.hh:565
gem5::CheckerCPU::updateOnError
bool updateOnError
Definition: cpu.hh:552
gem5::CheckerCPU::setFloatRegOperandBits
void setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) override
Sets the bits of a floating point register of single width to a binary value.
Definition: cpu.hh:295
gem5::CheckerCPU::totalOps
virtual Counter totalOps() const override
Definition: cpu.hh:161
gem5::SimpleThread::setPredicate
void setPredicate(bool val)
Definition: simple_thread.hh:443
gem5::Checker::dumpInsts
void dumpInsts()
Definition: cpu_impl.hh:678
gem5::InstResult
Definition: inst_res.hh:49
gem5::CheckerCPU::unverifiedMemData
uint8_t * unverifiedMemData
Definition: cpu.hh:546
gem5::SimpleThread::setCCReg
void setCCReg(RegIndex reg_idx, RegVal val) override
Definition: simple_thread.hh:421
gem5::ThreadID
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:242
gem5::CheckerCPU::unverifiedResult
InstResult unverifiedResult
Definition: cpu.hh:544
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:88
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::CheckerCPU::setSystem
void setSystem(System *system)
Definition: cpu.cc:97
gem5::CheckerCPU::instAddr
Addr instAddr()
Definition: cpu.hh:403
eventq.hh

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