gem5  v21.1.0.2
dma_device.cc
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40 
41 #include "dev/dma_device.hh"
42 
43 #include <algorithm>
44 #include <cassert>
45 #include <cstring>
46 #include <utility>
47 
48 #include "base/logging.hh"
49 #include "base/trace.hh"
50 #include "debug/DMA.hh"
51 #include "debug/Drain.hh"
52 #include "sim/clocked_object.hh"
53 #include "sim/system.hh"
54 
55 namespace gem5
56 {
57 
59  uint32_t sid, uint32_t ssid)
60  : RequestPort(dev->name() + ".dma", dev),
61  device(dev), sys(s), requestorId(s->getRequestorId(dev)),
62  sendEvent([this]{ sendDma(); }, dev->name()),
63  defaultSid(sid), defaultSSid(ssid), cacheLineSize(s->cacheLineSize())
64 { }
65 
66 void
68 {
69  // Should always see a response with a sender state.
70  assert(pkt->isResponse());
71 
72  // Get the DMA sender state.
73  auto *state = dynamic_cast<DmaReqState*>(pkt->senderState);
74  assert(state);
75 
76  handleResp(state, pkt->getAddr(), pkt->req->getSize(), delay);
77 
78  delete pkt;
79 }
80 
81 void
83 {
84  DPRINTF(DMA, "Received response %s for addr: %#x size: %d nb: %d," \
85  " tot: %d sched %d\n",
86  MemCmd(state->cmd).toString(), addr, size,
87  state->numBytes, state->totBytes,
88  state->completionEvent ?
89  state->completionEvent->scheduled() : 0);
90 
91  // Update the number of bytes received based on the request rather
92  // than the packet as the latter could be rounded up to line sizes.
93  state->numBytes += size;
94  assert(state->totBytes >= state->numBytes);
95 
96  // If we have reached the total number of bytes for this DMA request,
97  // then signal the completion and delete the sate.
98  if (state->totBytes == state->numBytes) {
99  assert(pendingCount != 0);
100  pendingCount--;
101  if (state->completionEvent) {
102  delay += state->delay;
103  device->schedule(state->completionEvent, curTick() + delay);
104  }
105  delete state;
106  }
107 
108  // We might be drained at this point, if so signal the drain event.
109  if (pendingCount == 0)
110  signalDrainDone();
111 }
112 
113 PacketPtr
115 {
116  RequestPtr req = std::make_shared<Request>(
117  gen.addr(), gen.size(), flags, id);
118  req->setStreamId(sid);
119  req->setSubstreamId(ssid);
120  req->taskId(context_switch_task_id::DMA);
121 
122  PacketPtr pkt = new Packet(req, cmd);
123 
124  if (data)
125  pkt->dataStatic(data + gen.complete());
126 
127  pkt->senderState = this;
128  return pkt;
129 }
130 
131 bool
133 {
134  // We shouldn't ever get a cacheable block in Modified state.
135  assert(pkt->req->isUncacheable() ||
136  !(pkt->cacheResponding() && !pkt->hasSharers()));
137 
138  handleRespPacket(pkt);
139 
140  return true;
141 }
142 
144  : PioDevice(p), dmaPort(this, sys, p.sid, p.ssid)
145 { }
146 
147 void
149 {
151  "DMA port of %s not connected to anything!", name());
152  PioDevice::init();
153 }
154 
157 {
158  if (pendingCount == 0) {
159  return DrainState::Drained;
160  } else {
161  DPRINTF(Drain, "DmaPort not drained\n");
162  return DrainState::Draining;
163  }
164 }
165 
166 void
168 {
169  assert(transmitList.size());
171 }
172 
173 void
175  uint8_t *data, uint32_t sid, uint32_t ssid, Tick delay,
176  Request::Flags flag)
177 {
178  DPRINTF(DMA, "Starting DMA for addr: %#x size: %d sched: %d\n", addr, size,
179  event ? event->scheduled() : -1);
180 
181  // One DMA request sender state for every action, that is then
182  // split into many requests and packets based on the block size,
183  // i.e. cache line size.
184  transmitList.push_back(
185  new DmaReqState(cmd, addr, cacheLineSize, size,
186  data, flag, requestorId, sid, ssid, event, delay));
187  pendingCount++;
188 
189  // In zero time, also initiate the sending of the packets for the request
190  // we have just created. For atomic this involves actually completing all
191  // the requests.
192  sendDma();
193 }
194 
195 void
197  uint8_t *data, Tick delay, Request::Flags flag)
198 {
199  dmaAction(cmd, addr, size, event, data,
200  defaultSid, defaultSSid, delay, flag);
201 }
202 
203 void
205 {
206  // Send the next packet for the first DMA request on the transmit list,
207  // and schedule the following send if it is successful
208  DmaReqState *state = transmitList.front();
209 
210  PacketPtr pkt = inRetry ? inRetry : state->createPacket();
211  inRetry = nullptr;
212 
213  DPRINTF(DMA, "Trying to send %s addr %#x\n", pkt->cmdString(),
214  pkt->getAddr());
215 
216  // Check if this was the last packet now, since hypothetically the packet
217  // response may come immediately, and state may be deleted.
218  bool last = state->gen.last();
219  if (!sendTimingReq(pkt))
220  inRetry = pkt;
221  if (!inRetry) {
222  // If that was the last packet from this request, pop it from the list.
223  if (last)
224  transmitList.pop_front();
225  else
226  state->gen.next();
227  DPRINTF(DMA, "-- Done\n");
228  // If there is more to do, then do so.
229  if (!transmitList.empty()) {
230  // This should ultimately wait for as many cycles as the device
231  // needs to send the packet, but currently the port does not have
232  // any known width so simply wait a single cycle.
234  }
235  } else {
236  DPRINTF(DMA, "-- Failed, waiting for retry\n");
237  }
238 
239  DPRINTF(DMA, "TransmitList: %d, inRetry: %d\n",
240  transmitList.size(), inRetry ? 1 : 0);
241 }
242 
243 bool
245 {
246  PacketPtr pkt = state->createPacket();
247  DPRINTF(DMA, "Sending DMA for addr: %#x size: %d\n",
248  state->gen.addr(), state->gen.size());
249  Tick lat = sendAtomic(pkt);
250 
251  // Check if we're done, since handleResp may delete state.
252  bool done = !state->gen.next();
253  handleRespPacket(pkt, lat);
254  return done;
255 }
256 
257 bool
259 {
260  bool done = false;
261 
262  auto bd_it = memBackdoors.contains(state->gen.addr());
263  if (bd_it == memBackdoors.end()) {
264  // We don't have a backdoor for this address, so use a packet.
265 
266  PacketPtr pkt = state->createPacket();
267  DPRINTF(DMA, "Sending DMA for addr: %#x size: %d\n",
268  state->gen.addr(), state->gen.size());
269 
270  MemBackdoorPtr bd = nullptr;
271  Tick lat = sendAtomicBackdoor(pkt, bd);
272 
273  // If we got a backdoor, record it.
274  if (bd && memBackdoors.insert(bd->range(), bd) != memBackdoors.end()) {
275  // Invalidation callback which finds this backdoor and removes it.
276  auto callback = [this](const MemBackdoor &backdoor) {
277  for (auto it = memBackdoors.begin();
278  it != memBackdoors.end(); it++) {
279  if (it->second == &backdoor) {
280  memBackdoors.erase(it);
281  return;
282  }
283  }
284  panic("Got invalidation for unknown memory backdoor.");
285  };
286  bd->addInvalidationCallback(callback);
287  }
288 
289  // Check if we're done now, since handleResp may delete state.
290  done = !state->gen.next();
291  handleRespPacket(pkt, lat);
292  } else {
293  // We have a backdoor that can at least partially satisfy this request.
294  DPRINTF(DMA, "Handling DMA for addr: %#x size %d through backdoor\n",
295  state->gen.addr(), state->gen.size());
296 
297  const auto *bd = bd_it->second;
298  // Offset of this access into the backdoor.
299  const Addr offset = state->gen.addr() - bd->range().start();
300  // How many bytes we still need.
301  const Addr remaining = state->totBytes - state->gen.complete();
302  // How many bytes this backdoor can provide, starting from offset.
303  const Addr available = bd->range().size() - offset;
304 
305  // How many bytes we're going to handle through this backdoor.
306  const Addr handled = std::min(remaining, available);
307 
308  // If there's a buffer for data, read/write it.
309  if (state->data) {
310  uint8_t *bd_data = bd->ptr() + offset;
311  uint8_t *state_data = state->data + state->gen.complete();
312  if (MemCmd(state->cmd).isRead())
313  memcpy(state_data, bd_data, handled);
314  else
315  memcpy(bd_data, state_data, handled);
316  }
317 
318  // Advance the chunk generator past this region of memory.
319  state->gen.setNext(state->gen.addr() + handled);
320 
321  // Check if we're done now, since handleResp may delete state.
322  done = !state->gen.next();
323  handleResp(state, state->gen.addr(), handled);
324  }
325 
326  return done;
327 }
328 
329 void
331 {
332  // Some kind of selection between access methods. More work is going to
333  // have to be done to make switching actually work.
334  assert(transmitList.size());
335 
336  if (sys->isTimingMode()) {
337  // If we are either waiting for a retry or are still waiting after
338  // sending the last packet, then do not proceed.
339  if (inRetry || sendEvent.scheduled()) {
340  DPRINTF(DMA, "Can't send immediately, waiting to send\n");
341  return;
342  }
343 
345  } else if (sys->isAtomicMode()) {
346  const bool bypass = sys->bypassCaches();
347 
348  // Send everything there is to send in zero time.
349  while (!transmitList.empty()) {
350  DmaReqState *state = transmitList.front();
351  transmitList.pop_front();
352 
353  bool done = state->gen.done();
354  while (!done)
355  done = bypass ? sendAtomicBdReq(state) : sendAtomicReq(state);
356  }
357  } else {
358  panic("Unknown memory mode.");
359  }
360 }
361 
362 Port &
363 DmaDevice::getPort(const std::string &if_name, PortID idx)
364 {
365  if (if_name == "dma") {
366  return dmaPort;
367  }
368  return PioDevice::getPort(if_name, idx);
369 }
370 
371 DmaReadFifo::DmaReadFifo(DmaPort &_port, size_t size,
372  unsigned max_req_size,
373  unsigned max_pending,
374  Request::Flags flags)
375  : maxReqSize(max_req_size), fifoSize(size),
376  reqFlags(flags), port(_port), cacheLineSize(port.sys->cacheLineSize()),
377  buffer(size)
378 {
379  freeRequests.resize(max_pending);
380  for (auto &e : freeRequests)
381  e.reset(new DmaDoneEvent(this, max_req_size));
382 
383 }
384 
386 {
387  for (auto &p : pendingRequests) {
388  DmaDoneEvent *e(p.release());
389 
390  if (e->done()) {
391  delete e;
392  } else {
393  // We can't kill in-flight DMAs, so we'll just transfer
394  // ownership to the event queue so that they get freed
395  // when they are done.
396  e->kill();
397  }
398  }
399 }
400 
401 void
403 {
404  assert(pendingRequests.empty());
405 
409 }
410 
411 void
413 {
417 }
418 
419 bool
420 DmaReadFifo::tryGet(uint8_t *dst, size_t len)
421 {
422  if (buffer.size() >= len) {
423  buffer.read(dst, len);
424  resumeFill();
425  return true;
426  } else {
427  return false;
428  }
429 }
430 
431 void
432 DmaReadFifo::get(uint8_t *dst, size_t len)
433 {
434  panic_if(!tryGet(dst, len), "Buffer underrun in DmaReadFifo::get()");
435 }
436 
437 void
438 DmaReadFifo::startFill(Addr start, size_t size)
439 {
440  assert(atEndOfBlock());
441 
442  nextAddr = start;
443  endAddr = start + size;
444  resumeFill();
445 }
446 
447 void
449 {
450  // Prevent new DMA requests by setting the next address to the end
451  // address. Pending requests will still complete.
452  nextAddr = endAddr;
453 
454  // Flag in-flight accesses as canceled. This prevents their data
455  // from being written to the FIFO.
456  for (auto &p : pendingRequests)
457  p->cancel();
458 }
459 
460 void
462 {
463  // Don't try to fetch more data if we are draining. This ensures
464  // that the DMA engine settles down before we checkpoint it.
466  return;
467 
468  const bool old_eob(atEndOfBlock());
469 
470  if (port.sys->bypassCaches())
472  else
474 
475  if (!old_eob && atEndOfBlock())
476  onEndOfBlock();
477 }
478 
479 void
481 {
482  const size_t fifo_space = buffer.capacity() - buffer.size();
483  if (fifo_space >= cacheLineSize || buffer.capacity() < cacheLineSize) {
484  const size_t block_remaining = endAddr - nextAddr;
485  const size_t xfer_size = std::min(fifo_space, block_remaining);
486  std::vector<uint8_t> tmp_buffer(xfer_size);
487 
488  assert(pendingRequests.empty());
489  DPRINTF(DMA, "Direct bypass startAddr=%#x xfer_size=%#x " \
490  "fifo_space=%#x block_remaining=%#x\n",
491  nextAddr, xfer_size, fifo_space, block_remaining);
492 
493  port.dmaAction(MemCmd::ReadReq, nextAddr, xfer_size, nullptr,
494  tmp_buffer.data(), 0, reqFlags);
495 
496  buffer.write(tmp_buffer.begin(), xfer_size);
497  nextAddr += xfer_size;
498  }
499 }
500 
501 void
503 {
504  size_t size_pending(0);
505  for (auto &e : pendingRequests)
506  size_pending += e->requestSize();
507 
508  while (!freeRequests.empty() && !atEndOfBlock()) {
509  const size_t req_size(std::min(maxReqSize, endAddr - nextAddr));
510  if (buffer.size() + size_pending + req_size > fifoSize)
511  break;
512 
513  DmaDoneEventUPtr event(std::move(freeRequests.front()));
514  freeRequests.pop_front();
515  assert(event);
516 
517  event->reset(req_size);
518  port.dmaAction(MemCmd::ReadReq, nextAddr, req_size, event.get(),
519  event->data(), 0, reqFlags);
520  nextAddr += req_size;
521  size_pending += req_size;
522 
523  pendingRequests.emplace_back(std::move(event));
524  }
525 }
526 
527 void
529 {
530  const bool old_active(isActive());
531 
532  handlePending();
533  resumeFill();
534 
535  if (old_active && !isActive())
536  onIdle();
537 }
538 
539 void
541 {
542  while (!pendingRequests.empty() && pendingRequests.front()->done()) {
543  // Get the first finished pending request
544  DmaDoneEventUPtr event(std::move(pendingRequests.front()));
545  pendingRequests.pop_front();
546 
547  if (!event->canceled())
548  buffer.write(event->data(), event->requestSize());
549 
550  // Move the event to the list of free requests
551  freeRequests.emplace_back(std::move(event));
552  }
553 
554  if (pendingRequests.empty())
555  signalDrainDone();
556 }
557 
560 {
561  return pendingRequests.empty() ?
563 }
564 
565 
567  : parent(_parent), _data(max_size, 0)
568 {
569 }
570 
571 void
573 {
574  parent = nullptr;
575  setFlags(AutoDelete);
576 }
577 
578 void
580 {
581  _canceled = true;
582 }
583 
584 void
586 {
587  assert(size <= _data.size());
588  _done = false;
589  _canceled = false;
590  _requestSize = size;
591 }
592 
593 void
595 {
596  if (!parent)
597  return;
598 
599  assert(!_done);
600  _done = true;
601  parent->dmaDone();
602 }
603 
604 } // namespace gem5
gem5::curTick
Tick curTick()
The universal simulation clock.
Definition: cur_tick.hh:46
gem5::PortID
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:252
gem5::Packet::cmdString
const std::string & cmdString() const
Return the string name of the cmd field (for debugging and tracing).
Definition: packet.hh:577
gem5::DmaReadFifo::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: dma_device.cc:412
gem5::DmaPort::sendEvent
EventFunctionWrapper sendEvent
Event used to schedule a future sending from the transmit list.
Definition: dma_device.hh:164
gem5::RequestPort::sendTimingReq
bool sendTimingReq(PacketPtr pkt)
Attempt to send a timing request to the responder port by calling its corresponding receive function.
Definition: port.hh:495
gem5::ArmISA::len
Bitfield< 18, 16 > len
Definition: misc_types.hh:444
gem5::DmaPort::device
ClockedObject *const device
The device that owns this port.
Definition: dma_device.hh:150
gem5::DmaReadFifo::endAddr
Addr endAddr
Definition: dma_device.hh:565
system.hh
gem5::DmaPort::DmaReqState::ssid
const uint32_t ssid
Definition: dma_device.hh:111
data
const char data[]
Definition: circlebuf.test.cc:48
gem5::DmaReadFifo::tryGet
bool tryGet(uint8_t *dst, size_t len)
Try to read data from the FIFO.
Definition: dma_device.cc:420
gem5::PioDevice
This device is the base class which all devices senstive to an address range inherit from.
Definition: io_device.hh:102
UNSERIALIZE_SCALAR
#define UNSERIALIZE_SCALAR(scalar)
Definition: serialize.hh:575
gem5::Drainable::drainState
DrainState drainState() const
Return the current drain state of an object.
Definition: drain.hh:324
gem5::DmaReadFifo::startFill
void startFill(Addr start, size_t size)
Start filling the FIFO.
Definition: dma_device.cc:438
gem5::DmaDevice::getPort
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
Definition: dma_device.cc:363
gem5::ChunkGenerator::next
bool next()
Advance generator to next chunk.
Definition: chunk_generator.hh:185
UNSERIALIZE_CONTAINER
#define UNSERIALIZE_CONTAINER(member)
Definition: serialize.hh:634
gem5::DmaPort::DmaReqState::flags
const Request::Flags flags
The flags to use for requests.
Definition: dma_device.hh:104
gem5::DmaReadFifo::port
DmaPort & port
Definition: dma_device.hh:512
gem5::ChunkGenerator::complete
Addr complete() const
Number of bytes we have already chunked up.
Definition: chunk_generator.hh:132
gem5::DmaReadFifo::isActive
bool isActive() const
Is the DMA engine active (i.e., are there still in-flight accesses)?
Definition: dma_device.hh:470
gem5::Packet::req
RequestPtr req
A pointer to the original request.
Definition: packet.hh:366
gem5::DmaReadFifo
Buffered DMA engine helper class.
Definition: dma_device.hh:364
gem5::DmaReadFifo::onEndOfBlock
virtual void onEndOfBlock()
End of block callback.
Definition: dma_device.hh:488
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::RequestPort::sendAtomic
Tick sendAtomic(PacketPtr pkt)
Send an atomic request packet, where the data is moved and the state is updated in zero time,...
Definition: port.hh:464
gem5::MipsISA::event
Bitfield< 10, 5 > event
Definition: pra_constants.hh:300
gem5::System::isAtomicMode
bool isAtomicMode() const
Is the system in atomic mode?
Definition: system.hh:264
gem5::DmaPort::dmaAction
void dmaAction(Packet::Command cmd, Addr addr, int size, Event *event, uint8_t *data, Tick delay, Request::Flags flag=0)
Definition: dma_device.cc:196
gem5::System::bypassCaches
bool bypassCaches() const
Should caches be bypassed?
Definition: system.hh:285
gem5::ArmISA::e
Bitfield< 9 > e
Definition: misc_types.hh:64
gem5::Packet::cacheResponding
bool cacheResponding() const
Definition: packet.hh:646
gem5::MemCmd::Command
Command
List of all commands associated with a packet.
Definition: packet.hh:83
gem5::DmaPort::DmaReqState::delay
const Tick delay
Amount to delay completion of dma by.
Definition: dma_device.hh:95
gem5::Packet::hasSharers
bool hasSharers() const
Definition: packet.hh:673
gem5::DmaPort::inRetry
PacketPtr inRetry
The packet (if any) waiting for a retry to send.
Definition: dma_device.hh:170
gem5::DmaReadFifo::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: dma_device.cc:402
gem5::EventManager::schedule
void schedule(Event &event, Tick when)
Definition: eventq.hh:1019
std::vector< uint8_t >
gem5::PowerISA::bd
Bitfield< 15, 2 > bd
Definition: types.hh:79
gem5::Fifo::size
size_t size() const
Definition: circlebuf.hh:222
gem5::DmaReadFifo::cacheLineSize
const int cacheLineSize
Definition: dma_device.hh:514
gem5::DmaPort::DmaReqState::gen
ChunkGenerator gen
Object to track what chunks of bytes to send at a time.
Definition: dma_device.hh:98
gem5::ChunkGenerator::last
bool last() const
Is this the last chunk?
Definition: chunk_generator.hh:149
gem5::Fifo::capacity
size_t capacity() const
Definition: circlebuf.hh:223
gem5::RequestPort
A RequestPort is a specialisation of a Port, which implements the default protocol for the three diff...
Definition: port.hh:77
gem5::Cycles
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:78
gem5::PioDevice::init
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: io_device.cc:59
gem5::DmaPort::DmaReqState
Definition: dma_device.hh:82
gem5::ChunkGenerator::size
Addr size() const
Return size in bytes of current chunk.
Definition: chunk_generator.hh:125
gem5::MemCmd
Definition: packet.hh:75
gem5::RequestPort::sendAtomicBackdoor
Tick sendAtomicBackdoor(PacketPtr pkt, MemBackdoorPtr &backdoor)
Send an atomic request packet like above, but also request a backdoor to the data being accessed.
Definition: port.hh:474
gem5::DmaReadFifo::size
size_t size() const
Get the amount of data stored in the FIFO.
Definition: dma_device.hh:427
gem5::DmaPort::DmaReqState::totBytes
const Addr totBytes
Total number of bytes that this transaction involves.
Definition: dma_device.hh:89
gem5::Packet::dataStatic
void dataStatic(T *p)
Set the data pointer to the following value that should not be freed.
Definition: packet.hh:1134
gem5::DmaPort::pendingCount
uint32_t pendingCount
Number of outstanding packets the dma port has.
Definition: dma_device.hh:167
gem5::DmaDevice::dmaPort
DmaPort dmaPort
Definition: dma_device.hh:206
gem5::Flags< FlagsType >
gem5::DrainState
DrainState
Object drain/handover states.
Definition: drain.hh:74
gem5::DmaPort::DmaReqState::numBytes
Addr numBytes
Number of bytes that have been acked for this transaction.
Definition: dma_device.hh:92
gem5::DmaReadFifo::nextAddr
Addr nextAddr
Definition: dma_device.hh:564
dma_device.hh
gem5::DmaPort::transmitList
std::deque< DmaReqState * > transmitList
Use a deque as we never do any insertion or removal in the middle.
Definition: dma_device.hh:161
gem5::DmaReadFifo::DmaDoneEvent::DmaDoneEvent
DmaDoneEvent(DmaReadFifo *_parent, size_t max_size)
Definition: dma_device.cc:566
gem5::System
Definition: system.hh:77
gem5::DmaReadFifo::onIdle
virtual void onIdle()
Last response received callback.
Definition: dma_device.hh:501
gem5::ChunkGenerator::done
bool done() const
Are we done? That is, did the last call to next() advance past the end of the region?
Definition: chunk_generator.hh:141
gem5::DmaPort::cacheLineSize
const int cacheLineSize
Definition: dma_device.hh:178
gem5::DmaReadFifo::freeRequests
std::deque< DmaDoneEventUPtr > freeRequests
Definition: dma_device.hh:568
gem5::Named::name
virtual std::string name() const
Definition: named.hh:47
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::Event
Definition: eventq.hh:251
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::DmaPort::sendDma
void sendDma()
For timing, attempt to send the first item on the transmit list, and if it is successful and there ar...
Definition: dma_device.cc:330
gem5::probing::Packet
ProbePointArg< PacketInfo > Packet
Packet probe point.
Definition: mem.hh:109
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::DmaDevice::init
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: dma_device.cc:148
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::ArmISA::s
Bitfield< 4 > s
Definition: misc_types.hh:561
gem5::DmaReadFifo::DmaDoneEvent::cancel
void cancel()
Definition: dma_device.cc:579
gem5::MemCmd::ReadReq
@ ReadReq
Definition: packet.hh:86
gem5::DmaPort::memBackdoors
AddrRangeMap< MemBackdoorPtr, 1 > memBackdoors
Definition: dma_device.hh:64
gem5::DmaPort::DmaReqState::cmd
const Packet::Command cmd
Command for the request.
Definition: dma_device.hh:114
gem5::DmaReadFifo::DmaDoneEvent::kill
void kill()
Definition: dma_device.cc:572
gem5::DmaReadFifo::resumeFill
void resumeFill()
Try to issue new DMA requests or bypass DMA requests.
Definition: dma_device.cc:461
gem5::DmaPort::DmaReqState::data
uint8_t *const data
Pointer to a buffer for the data.
Definition: dma_device.hh:101
gem5::DmaReadFifo::reqFlags
const Request::Flags reqFlags
Request flags.
Definition: dma_device.hh:510
gem5::ArmISA::offset
Bitfield< 23, 0 > offset
Definition: types.hh:144
gem5::DmaDevice::Params
DmaDeviceParams Params
Definition: dma_device.hh:209
gem5::DmaReadFifo::dmaDone
void dmaDone()
DMA request done, handle incoming data and issue new request.
Definition: dma_device.cc:528
gem5::Port::isConnected
bool isConnected() const
Is this port currently connected to a peer?
Definition: port.hh:133
gem5::DrainState::Drained
@ Drained
Buffers drained, ready for serialization/handover.
gem5::System::isTimingMode
bool isTimingMode() const
Is the system in timing mode?
Definition: system.hh:276
gem5::DmaReadFifo::get
T get()
Definition: dma_device.hh:419
gem5::DmaReadFifo::stopFill
void stopFill()
Stop the DMA engine.
Definition: dma_device.cc:448
gem5::DmaReadFifo::DmaDoneEvent
Definition: dma_device.hh:517
gem5::DmaReadFifo::resumeFillTiming
void resumeFillTiming()
Try to issue new DMA requests during normal execution.
Definition: dma_device.cc:502
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::DmaPort::handleResp
void handleResp(DmaReqState *state, Addr addr, Addr size, Tick delay=0)
Definition: dma_device.cc:82
gem5::Packet::senderState
SenderState * senderState
This packet's sender state.
Definition: packet.hh:534
name
const std::string & name()
Definition: trace.cc:49
SERIALIZE_SCALAR
#define SERIALIZE_SCALAR(scalar)
Definition: serialize.hh:568
gem5::MemBackdoor
Definition: backdoor.hh:41
gem5::context_switch_task_id::DMA
@ DMA
Definition: request.hh:84
gem5::ClockedObject
The ClockedObject class extends the SimObject with a clock and accessor functions to relate ticks to ...
Definition: clocked_object.hh:234
gem5::Clocked::clockEdge
Tick clockEdge(Cycles cycles=Cycles(0)) const
Determine the tick when a cycle begins, by default the current one, but the argument also enables the...
Definition: clocked_object.hh:177
gem5::DmaReadFifo::DmaDoneEvent::reset
void reset(size_t size)
Definition: dma_device.cc:585
gem5::DmaReadFifo::maxReqSize
const Addr maxReqSize
Maximum request size in bytes.
Definition: dma_device.hh:501
gem5::DmaReadFifo::fifoSize
const size_t fifoSize
Maximum FIFO size in bytes.
Definition: dma_device.hh:508
gem5::DmaReadFifo::atEndOfBlock
bool atEndOfBlock() const
Has the DMA engine sent out the last request for the active block?
Definition: dma_device.hh:463
gem5::DmaReadFifo::DmaDoneEvent::process
void process()
Definition: dma_device.cc:594
gem5::MemCmd::toString
const std::string & toString() const
Return the string to a cmd given by idx.
Definition: packet.hh:265
gem5::Drainable::signalDrainDone
void signalDrainDone() const
Signal that an object is drained.
Definition: drain.hh:305
gem5::DmaPort::sendAtomicReq
bool sendAtomicReq(DmaReqState *state)
Send the next packet from a DMA request in atomic mode.
Definition: dma_device.cc:244
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:203
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
gem5::DmaPort::handleRespPacket
void handleRespPacket(PacketPtr pkt, Tick delay=0)
Handle a response packet by updating the corresponding DMA request state to reflect the bytes receive...
Definition: dma_device.cc:67
gem5::DmaPort::recvReqRetry
void recvReqRetry() override
Called by the peer if sendTimingReq was called on this peer (causing recvTimingReq to be called on th...
Definition: dma_device.cc:167
gem5::ChunkGenerator::setNext
void setNext(Addr next)
Grow this chunk to cover additional bytes which are already handled.
Definition: chunk_generator.hh:158
gem5::ChunkGenerator::addr
Addr addr() const
Return starting address of current chunk.
Definition: chunk_generator.hh:119
clocked_object.hh
SERIALIZE_CONTAINER
#define SERIALIZE_CONTAINER(member)
Definition: serialize.hh:626
gem5::ArmISA::sendEvent
void sendEvent(ThreadContext *tc)
Send an event (SEV) to a specific PE if there isn't already a pending event.
Definition: utility.cc:63
gem5::DmaPort::recvTimingResp
bool recvTimingResp(PacketPtr pkt) override
Receive a timing response from the peer.
Definition: dma_device.cc:132
gem5::DmaPort::requestorId
const RequestorID requestorId
Id for all requests.
Definition: dma_device.hh:157
gem5::DmaPort::trySendTimingReq
void trySendTimingReq()
Take the first request on the transmit list and attempt to send a timing packet from it.
Definition: dma_device.cc:204
gem5::DmaDevice::DmaDevice
DmaDevice(const Params &p)
Definition: dma_device.cc:143
logging.hh
gem5::DmaPort::DmaReqState::createPacket
PacketPtr createPacket()
Definition: dma_device.cc:114
gem5::Fifo::write
void write(InputIterator in, size_t len)
Definition: circlebuf.hh:234
gem5::DmaReadFifo::buffer
Fifo< uint8_t > buffer
Definition: dma_device.hh:562
gem5::DmaReadFifo::DmaDoneEventUPtr
std::unique_ptr< DmaDoneEvent > DmaDoneEventUPtr
Definition: dma_device.hh:541
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::DmaPort
Definition: dma_device.hh:61
gem5::DmaPort::DmaPort
DmaPort(ClockedObject *dev, System *s, uint32_t sid=0, uint32_t ssid=0)
Definition: dma_device.cc:58
gem5::DmaReadFifo::DmaReadFifo
DmaReadFifo(DmaPort &port, size_t size, unsigned max_req_size, unsigned max_pending, Request::Flags flags=0)
Definition: dma_device.cc:371
trace.hh
gem5::DmaPort::defaultSSid
const uint32_t defaultSSid
Default substreamId.
Definition: dma_device.hh:176
gem5::DmaPort::sendAtomicBdReq
bool sendAtomicBdReq(DmaReqState *state)
Send the next packet from a DMA request in atomic mode, and request and/or use memory backdoors if po...
Definition: dma_device.cc:258
gem5::DmaPort::DmaReqState::completionEvent
Event * completionEvent
Event to call on the device when this transaction (all packets) complete.
Definition: dma_device.hh:86
gem5::Packet::getAddr
Addr getAddr() const
Definition: packet.hh:781
gem5::DmaPort::drain
DrainState drain() override
Draining is the process of clearing out the states of SimObjects.These are the SimObjects that are pa...
Definition: dma_device.cc:156
gem5::DmaPort::DmaReqState::sid
const uint32_t sid
Stream IDs.
Definition: dma_device.hh:110
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::DmaPort::sys
System *const sys
The system that device/port are in.
Definition: dma_device.hh:154
gem5::DmaReadFifo::pendingRequests
std::deque< DmaDoneEventUPtr > pendingRequests
Definition: dma_device.hh:567
gem5::Fifo::read
void read(OutputIterator out, size_t len)
Definition: circlebuf.hh:230
gem5::MemCmd::isRead
bool isRead() const
Definition: packet.hh:217
gem5::DmaReadFifo::handlePending
void handlePending()
Handle pending requests that have been flagged as done.
Definition: dma_device.cc:540
gem5::DmaReadFifo::~DmaReadFifo
~DmaReadFifo()
Definition: dma_device.cc:385
gem5::DmaReadFifo::drain
DrainState drain() override
Draining is the process of clearing out the states of SimObjects.These are the SimObjects that are pa...
Definition: dma_device.cc:559
gem5::Packet::isResponse
bool isResponse() const
Definition: packet.hh:587
gem5::DrainState::Draining
@ Draining
Draining buffers pending serialization/handover.
gem5::DmaReadFifo::resumeFillBypass
void resumeFillBypass()
Try to bypass DMA requests in non-caching mode.
Definition: dma_device.cc:480
gem5::Event::scheduled
bool scheduled() const
Determine if the current event is scheduled.
Definition: eventq.hh:465
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::PioDevice::getPort
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
Definition: io_device.cc:67
gem5::DmaPort::defaultSid
const uint32_t defaultSid
Default streamId.
Definition: dma_device.hh:173

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