gem5  v21.1.0.2
gem5_to_tlm.cc
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36  * this list of conditions and the following disclaimer.
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38  * 2. Redistributions in binary form must reproduce the above copyright
39  * notice, this list of conditions and the following disclaimer in the
40  * documentation and/or other materials provided with the distribution.
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42  * 3. Neither the name of the copyright holder nor the names of its
43  * contributors may be used to endorse or promote products derived from
44  * this software without specific prior written permission.
45  *
46  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
47  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
48  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
49  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
50  * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
51  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
52  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
53  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
54  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
55  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
56  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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58 
60 
61 #include <utility>
62 
63 #include "params/Gem5ToTlmBridge32.hh"
64 #include "params/Gem5ToTlmBridge64.hh"
65 #include "params/Gem5ToTlmBridge128.hh"
66 #include "params/Gem5ToTlmBridge256.hh"
67 #include "params/Gem5ToTlmBridge512.hh"
68 #include "sim/eventq.hh"
69 #include "sim/system.hh"
72 
73 using namespace gem5;
74 
75 namespace sc_gem5
76 {
77 
85 {
86  // In theory, for all phase change events of a specific TLM base protocol
87  // transaction, only tlm::END_REQ and tlm::BEGIN_RESP would be scheduled at
88  // the same time in the same queue. So we only need to ensure END_REQ has a
89  // higher priority (less in pri value) than BEGIN_RESP.
90  if (phase == tlm::END_REQ) {
91  return EventBase::Default_Pri - 1;
92  }
94 }
95 
101 
102 namespace
103 {
107 std::vector<PacketToPayloadConversionStep> extraPacketToPayloadSteps;
108 } // namespace
109 
117 void
119 {
120  extraPacketToPayloadSteps.push_back(std::move(step));
121 }
122 
129 {
131  trans->acquire();
132 
133  trans->set_address(packet->getAddr());
134 
135  /* Check if this transaction was allocated by mm */
136  sc_assert(trans->has_mm());
137 
138  unsigned int size = packet->getSize();
139  unsigned char *data = packet->getPtr<unsigned char>();
140 
141  trans->set_data_length(size);
142  trans->set_streaming_width(size);
143  trans->set_data_ptr(data);
144 
145  if ((packet->req->getFlags() & Request::NO_ACCESS) != 0) {
146  /* Do nothing */
148  } else if (packet->isRead()) {
150  } else if (packet->isWrite()) {
152  } else {
154  }
155 
156  // Attach the packet pointer to the TLM transaction to keep track.
157  auto *extension = new Gem5SystemC::Gem5Extension(packet);
158  trans->set_auto_extension(extension);
159 
160  if (packet->isAtomicOp()) {
161  auto *atomic_ex = new Gem5SystemC::AtomicExtension(
162  std::shared_ptr<AtomicOpFunctor>(
163  packet->req->getAtomicOpFunctor()->clone()),
164  packet->req->isAtomicReturn());
165  trans->set_auto_extension(atomic_ex);
166  }
167 
168  // Apply all conversion steps necessary in this specific setup.
169  for (auto &step : extraPacketToPayloadSteps) {
170  step(packet, *trans);
171  }
172 
173  return trans;
174 }
175 
176 template <unsigned int BITWIDTH>
177 void
179  tlm::tlm_generic_payload &trans, const tlm::tlm_phase &phase)
180 {
181  sc_core::sc_time delay;
182 
183  if (phase == tlm::END_REQ ||
184  (&trans == blockingRequest && phase == tlm::BEGIN_RESP)) {
185  sc_assert(&trans == blockingRequest);
186  blockingRequest = nullptr;
187 
188  // Did another request arrive while blocked, schedule a retry.
189  if (needToSendRequestRetry) {
190  needToSendRequestRetry = false;
191  bridgeResponsePort.sendRetryReq();
192  }
193  }
194  if (phase == tlm::BEGIN_RESP) {
195  auto &extension = Gem5SystemC::Gem5Extension::getExtension(trans);
196  auto packet = extension.getPacket();
197 
198  sc_assert(!blockingResponse);
199 
200  bool need_retry = false;
201 
202  // If there is another gem5 model under the receiver side, and already
203  // make a response packet back, we can simply send it back. Otherwise,
204  // we make a response packet before sending it back to the initiator
205  // side gem5 module.
206  if (packet->needsResponse()) {
207  packet->makeResponse();
208  }
209  if (packet->isResponse()) {
210  need_retry = !bridgeResponsePort.sendTimingResp(packet);
211  }
212 
213  if (need_retry) {
214  blockingResponse = &trans;
215  } else {
216  if (phase == tlm::BEGIN_RESP) {
217  // Send END_RESP and we're finished:
218  tlm::tlm_phase fw_phase = tlm::END_RESP;
220  socket->nb_transport_fw(trans, fw_phase, delay);
221  // Release the transaction with all the extensions.
222  trans.release();
223  }
224  }
225  }
226 }
227 
228 template <unsigned int BITWIDTH>
231 {
232  sc_dt::uint64 start = trans.get_address();
233  sc_dt::uint64 end = start + trans.get_data_length();
234 
235  // Check for a back door we already know about.
236  AddrRange r(start, end);
237  auto it = backdoorMap.contains(r);
238  if (it != backdoorMap.end())
239  return it->second;
240 
241  // If not, ask the target for one.
242  tlm::tlm_dmi dmi_data;
243  if (!socket->get_direct_mem_ptr(trans, dmi_data))
244  return nullptr;
245 
246  // If the target gave us one, translate it to a gem5 MemBackdoor and
247  // store it in our cache.
248  AddrRange dmi_r(dmi_data.get_start_address(), dmi_data.get_end_address());
249  auto backdoor = new MemBackdoor(
250  dmi_r, dmi_data.get_dmi_ptr(), MemBackdoor::NoAccess);
251  backdoor->readable(dmi_data.is_read_allowed());
252  backdoor->writeable(dmi_data.is_write_allowed());
253 
254  backdoorMap.insert(dmi_r, backdoor);
255 
256  return backdoor;
257 }
258 
259 // Similar to TLM's blocking transport (LT)
260 template <unsigned int BITWIDTH>
261 Tick
263 {
264  panic_if(packet->cacheResponding(),
265  "Should not see packets where cache is responding");
266 
267  // Prepare the transaction.
268  auto *trans = packet2payload(packet);
269 
271 
272  if (trans->get_command() != tlm::TLM_IGNORE_COMMAND) {
273  // Execute b_transport:
274  socket->b_transport(*trans, delay);
275  }
276 
277  if (packet->needsResponse())
278  packet->makeResponse();
279 
280  trans->release();
281 
282  return delay.value();
283 }
284 
285 template <unsigned int BITWIDTH>
286 Tick
288  PacketPtr packet, MemBackdoorPtr &backdoor)
289 {
290  panic_if(packet->cacheResponding(),
291  "Should not see packets where cache is responding");
292 
294 
295  // Prepare the transaction.
296  auto *trans = packet2payload(packet);
297 
298  if (trans->get_command() != tlm::TLM_IGNORE_COMMAND) {
299  // Execute b_transport:
300  socket->b_transport(*trans, delay);
301  // If the hint said we could use DMI, set that up.
302  if (trans->is_dmi_allowed())
303  backdoor = getBackdoor(*trans);
304  } else {
305  // There's no transaction to piggy back on, so just request the
306  // backdoor normally.
307  backdoor = getBackdoor(*trans);
308  }
309 
310  if (packet->needsResponse())
311  packet->makeResponse();
312 
313  trans->release();
314 
315  return delay.value();
316 }
317 
318 template <unsigned int BITWIDTH>
319 void
321 {
322  // Snooping should be implemented with tlm_dbg_transport.
323  SC_REPORT_FATAL("Gem5ToTlmBridge",
324  "unimplemented func.: recvFunctionalSnoop");
325 }
326 
327 // Similar to TLM's non-blocking transport (AT).
328 template <unsigned int BITWIDTH>
329 bool
331 {
332  panic_if(packet->cacheResponding(),
333  "Should not see packets where cache is responding");
334 
335  // We should never get a second request after noting that a retry is
336  // required.
337  sc_assert(!needToSendRequestRetry);
338 
339  // Remember if a request comes in while we're blocked so that a retry
340  // can be sent to gem5.
341  if (blockingRequest) {
342  needToSendRequestRetry = true;
343  return false;
344  }
345 
346  /*
347  * NOTE: normal tlm is blocking here. But in our case we return false
348  * and tell gem5 when a retry can be done. This is the main difference
349  * in the protocol:
350  * if (requestInProgress)
351  * {
352  * wait(endRequestEvent);
353  * }
354  * requestInProgress = trans;
355  */
356 
357  // Prepare the transaction.
358  auto *trans = packet2payload(packet);
359 
360  /*
361  * Pay for annotated transport delays.
362  *
363  * The header delay marks the point in time, when the packet first is seen
364  * by the transactor. This is the point in time when the transactor needs
365  * to send the BEGIN_REQ to the SystemC world.
366  *
367  * NOTE: We drop the payload delay here. Normally, the receiver would be
368  * responsible for handling the payload delay. In this case, however,
369  * the receiver is a SystemC module and has no notion of the gem5
370  * transport protocol and we cannot simply forward the
371  * payload delay to the receiving module. Instead, we expect the
372  * receiving SystemC module to model the payload delay by deferring
373  * the END_REQ. This could lead to incorrect delays, if the XBar
374  * payload delay is longer than the time the receiver needs to accept
375  * the request (time between BEGIN_REQ and END_REQ).
376  *
377  * TODO: We could detect the case described above by remembering the
378  * payload delay and comparing it to the time between BEGIN_REQ and
379  * END_REQ. Then, a warning should be printed.
380  */
381  auto delay = sc_core::sc_time::from_value(packet->payloadDelay);
382  // Reset the delays
383  packet->payloadDelay = 0;
384  packet->headerDelay = 0;
385 
386  // Starting TLM non-blocking sequence (AT) Refer to IEEE1666-2011 SystemC
387  // Standard Page 507 for a visualisation of the procedure.
390  status = socket->nb_transport_fw(*trans, phase, delay);
391  // Check returned value:
392  if (status == tlm::TLM_ACCEPTED) {
393  sc_assert(phase == tlm::BEGIN_REQ);
394  // Accepted but is now blocking until END_REQ (exclusion rule).
395  blockingRequest = trans;
396  } else if (status == tlm::TLM_UPDATED) {
397  // The Timing annotation must be honored:
398  sc_assert(phase == tlm::END_REQ || phase == tlm::BEGIN_RESP);
399  // Accepted but is now blocking until END_REQ (exclusion rule).
400  blockingRequest = trans;
401  auto cb = [this, trans, phase]() { pec(*trans, phase); };
402  auto event = new EventFunctionWrapper(
403  cb, "pec", true, getPriorityOfTlmPhase(phase));
404  system->schedule(event, curTick() + delay.value());
405  } else if (status == tlm::TLM_COMPLETED) {
406  // Transaction is over nothing has do be done.
407  sc_assert(phase == tlm::END_RESP);
408  trans->release();
409  }
410 
411  return true;
412 }
413 
414 template <unsigned int BITWIDTH>
415 bool
417 {
418  // Snooping should be implemented with tlm_dbg_transport.
419  SC_REPORT_FATAL("Gem5ToTlmBridge",
420  "unimplemented func.: recvTimingSnoopResp");
421  return false;
422 }
423 
424 template <unsigned int BITWIDTH>
425 bool
427 {
428  panic("tryTiming(PacketPtr) isn't implemented.");
429 }
430 
431 template <unsigned int BITWIDTH>
432 void
434 {
435  /* Retry a response */
436  sc_assert(blockingResponse);
437 
438  tlm::tlm_generic_payload *trans = blockingResponse;
439  blockingResponse = nullptr;
440  PacketPtr packet =
442 
443  bool need_retry = !bridgeResponsePort.sendTimingResp(packet);
444 
445  sc_assert(!need_retry);
446 
449  socket->nb_transport_fw(*trans, phase, delay);
450  // Release transaction with all the extensions
451  trans->release();
452 }
453 
454 // Similar to TLM's debug transport.
455 template <unsigned int BITWIDTH>
456 void
458 {
459  // Prepare the transaction.
460  auto *trans = packet2payload(packet);
461 
462  /* Execute Debug Transport: */
463  unsigned int bytes = socket->transport_dbg(*trans);
464  if (bytes != trans->get_data_length()) {
465  SC_REPORT_FATAL("Gem5ToTlmBridge",
466  "debug transport was not completed");
467  }
468 
469  trans->release();
470 }
471 
472 template <unsigned int BITWIDTH>
475  tlm::tlm_phase &phase, sc_core::sc_time &delay)
476 {
477  auto cb = [this, &trans, phase]() { pec(trans, phase); };
478  auto event = new EventFunctionWrapper(
479  cb, "pec", true, getPriorityOfTlmPhase(phase));
480  system->schedule(event, curTick() + delay.value());
481  return tlm::TLM_ACCEPTED;
482 }
483 
484 template <unsigned int BITWIDTH>
485 void
487  sc_dt::uint64 start_range, sc_dt::uint64 end_range)
488 {
489  AddrRange r(start_range, end_range);
490 
491  for (;;) {
492  auto it = backdoorMap.intersects(r);
493  if (it == backdoorMap.end())
494  break;
495 
496  it->second->invalidate();
497  delete it->second;
498  backdoorMap.erase(it);
499  };
500 }
501 
502 template <unsigned int BITWIDTH>
504  const Params &params, const sc_core::sc_module_name &mn) :
506  bridgeResponsePort(std::string(name()) + ".gem5", *this),
507  socket("tlm_socket"),
508  wrapper(socket, std::string(name()) + ".tlm", InvalidPortID),
509  system(params.system), blockingRequest(nullptr),
510  needToSendRequestRetry(false), blockingResponse(nullptr),
511  addrRanges(params.addr_ranges.begin(), params.addr_ranges.end())
512 {
513 }
514 
515 template <unsigned int BITWIDTH>
516 gem5::Port &
517 Gem5ToTlmBridge<BITWIDTH>::gem5_getPort(const std::string &if_name, int idx)
518 {
519  if (if_name == "gem5")
520  return bridgeResponsePort;
521  else if (if_name == "tlm")
522  return wrapper;
523 
524  return sc_core::sc_module::gem5_getPort(if_name, idx);
525 }
526 
527 template <unsigned int BITWIDTH>
528 void
530 {
531  bridgeResponsePort.sendRangeChange();
532 
533  socket.register_nb_transport_bw(this, &Gem5ToTlmBridge::nb_transport_bw);
534  socket.register_invalidate_direct_mem_ptr(
537 }
538 
539 } // namespace sc_gem5
540 
542 gem5::Gem5ToTlmBridge32Params::create() const
543 {
544  return new sc_gem5::Gem5ToTlmBridge<32>(
545  *this, sc_core::sc_module_name(name.c_str()));
546 }
547 
549 gem5::Gem5ToTlmBridge64Params::create() const
550 {
551  return new sc_gem5::Gem5ToTlmBridge<64>(
552  *this, sc_core::sc_module_name(name.c_str()));
553 }
554 
556 gem5::Gem5ToTlmBridge128Params::create() const
557 {
559  *this, sc_core::sc_module_name(name.c_str()));
560 }
561 
563 gem5::Gem5ToTlmBridge256Params::create() const
564 {
566  *this, sc_core::sc_module_name(name.c_str()));
567 }
568 
570 gem5::Gem5ToTlmBridge512Params::create() const
571 {
573  *this, sc_core::sc_module_name(name.c_str()));
574 }
gem5::curTick
Tick curTick()
The universal simulation clock.
Definition: cur_tick.hh:46
gem5::Packet::isAtomicOp
bool isAtomicOp() const
Definition: packet.hh:820
sc_core::sc_time::from_value
static sc_time from_value(sc_dt::uint64)
Definition: sc_time.cc:210
sc_gem5::Gem5ToTlmBridge::gem5_getPort
gem5::Port & gem5_getPort(const std::string &if_name, int idx=-1) override
Definition: gem5_to_tlm.cc:517
tlm::tlm_generic_payload::set_data_length
void set_data_length(const unsigned int length)
Definition: gp.hh:210
system.hh
data
const char data[]
Definition: circlebuf.test.cc:48
Gem5SystemC::MemoryManager
Definition: sc_mm.hh:45
tlm::tlm_phase
Definition: phase.hh:47
sc_gem5::Gem5ToTlmBridge::before_end_of_elaboration
void before_end_of_elaboration() override
Definition: gem5_to_tlm.cc:529
sc_gem5::addPacketToPayloadConversionStep
void addPacketToPayloadConversionStep(PacketToPayloadConversionStep step)
Notify the Gem5ToTlm bridge that we need an extra step to properly convert a gem5 packet to tlm paylo...
Definition: gem5_to_tlm.cc:118
tlm::TLM_COMPLETED
@ TLM_COMPLETED
Definition: fw_bw_ifs.hh:65
gem5::Packet::req
RequestPtr req
A pointer to the original request.
Definition: packet.hh:366
gem5_to_tlm.hh
tlm::tlm_dmi
Definition: dmi.hh:46
tlm::TLM_WRITE_COMMAND
@ TLM_WRITE_COMMAND
Definition: gp.hh:102
gem5::MipsISA::event
Bitfield< 10, 5 > event
Definition: pra_constants.hh:300
tlm::TLM_UPDATED
@ TLM_UPDATED
Definition: fw_bw_ifs.hh:65
sc_gem5::packet2payload
tlm::tlm_generic_payload * packet2payload(PacketPtr packet)
Convert a gem5 packet to a TLM payload by copying all the relevant information to new tlm payload.
Definition: gem5_to_tlm.cc:128
sc_ext.hh
tlm::END_REQ
@ END_REQ
Definition: phase.hh:42
gem5::Packet::cacheResponding
bool cacheResponding() const
Definition: packet.hh:646
sc_core::SC_ZERO_TIME
const sc_time SC_ZERO_TIME
Definition: sc_time.cc:290
SC_REPORT_FATAL
#define SC_REPORT_FATAL(msg_type, msg)
Definition: sc_report_handler.hh:131
gem5::Packet::isWrite
bool isWrite() const
Definition: packet.hh:583
gem5::X86ISA::system
Bitfield< 15 > system
Definition: misc.hh:1003
std::vector
STL vector class.
Definition: stl.hh:37
Gem5SystemC::Gem5Extension::getPacket
gem5::PacketPtr getPacket()
Definition: sc_ext.cc:64
tlm::tlm_generic_payload::release
void release()
Definition: gp.hh:147
gem5::InvalidPortID
const PortID InvalidPortID
Definition: types.hh:253
gem5::Packet::headerDelay
uint32_t headerDelay
The extra delay from seeing the packet until the header is transmitted.
Definition: packet.hh:420
sc_assert
#define sc_assert(expr)
Definition: sc_report_handler.hh:135
gem5::Packet::payloadDelay
uint32_t payloadDelay
The extra pipelining delay from seeing the packet until the end of payload is transmitted by the comp...
Definition: packet.hh:438
gem5::Packet::isRead
bool isRead() const
Definition: packet.hh:582
tlm::tlm_generic_payload::set_command
void set_command(const tlm_command command)
Definition: gp.hh:198
tlm::tlm_dmi::is_read_allowed
bool is_read_allowed() const
Definition: dmi.hh:100
tlm::tlm_generic_payload::get_data_length
unsigned int get_data_length() const
Definition: gp.hh:209
sc_dt::uint64
uint64_t uint64
Definition: sc_nbdefs.hh:206
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
sc_core::sc_time
Definition: sc_time.hh:49
sc_core::sc_time::value
sc_dt::uint64 value() const
Definition: sc_time.cc:115
tlm::tlm_dmi::get_end_address
sc_dt::uint64 get_end_address() const
Definition: dmi.hh:94
tlm::TLM_READ_COMMAND
@ TLM_READ_COMMAND
Definition: gp.hh:101
tlm::tlm_dmi::is_write_allowed
bool is_write_allowed() const
Definition: dmi.hh:105
sc_gem5::PacketToPayloadConversionStep
std::function< void(gem5::PacketPtr pkt, tlm::tlm_generic_payload &trans)> PacketToPayloadConversionStep
Definition: gem5_to_tlm.hh:78
tlm::tlm_dmi::get_start_address
sc_dt::uint64 get_start_address() const
Definition: dmi.hh:93
sc_core::sc_module_name
Definition: sc_module_name.hh:41
mm
Definition: mm.h:8
tlm::tlm_generic_payload::acquire
void acquire()
Definition: gp.hh:140
tlm::tlm_generic_payload::set_streaming_width
void set_streaming_width(const unsigned int streaming_width)
Definition: gp.hh:230
sc_gem5::Gem5ToTlmBridge
Definition: gem5_to_tlm.hh:91
sc_gem5::Gem5ToTlmBridge::nb_transport_bw
tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload &trans, tlm::tlm_phase &phase, sc_core::sc_time &t)
Definition: gem5_to_tlm.cc:474
sc_gem5::getPriorityOfTlmPhase
static EventBase::Priority getPriorityOfTlmPhase(const tlm::tlm_phase &phase)
Helper function to help set priority of phase change events of tlm transactions.
Definition: gem5_to_tlm.cc:84
gem5::Packet::needsResponse
bool needsResponse() const
Definition: packet.hh:597
tlm::END_RESP
@ END_RESP
Definition: phase.hh:44
tlm::TLM_IGNORE_COMMAND
@ TLM_IGNORE_COMMAND
Definition: gp.hh:103
name
const std::string & name()
Definition: trace.cc:49
gem5::MemBackdoor
Definition: backdoor.hh:41
tlm::tlm_dmi::get_dmi_ptr
unsigned char * get_dmi_ptr() const
Definition: dmi.hh:92
mm::allocate
gp_t * allocate()
Definition: mm.h:55
gem5::EventFunctionWrapper
Definition: eventq.hh:1115
tlm::BEGIN_REQ
@ BEGIN_REQ
Definition: phase.hh:41
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:203
tlm::tlm_generic_payload
Definition: gp.hh:133
Gem5SystemC::Gem5Extension::getExtension
static Gem5Extension & getExtension(const tlm::tlm_generic_payload *payload)
Definition: sc_ext.cc:49
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
std
Overload hash function for BasicBlockRange type.
Definition: types.hh:111
gem5::MemBackdoor::NoAccess
@ NoAccess
Definition: backdoor.hh:52
Gem5SystemC::AtomicExtension
Definition: sc_ext.hh:64
gem5::EventBase::Priority
int8_t Priority
Definition: eventq.hh:123
sc_core::sc_module::gem5_getPort
virtual gem5::Port & gem5_getPort(const std::string &if_name, int idx=-1)
Definition: sc_module.cc:117
gem5::Packet::makeResponse
void makeResponse()
Take a request packet and modify it in place to be suitable for returning as a response to that reque...
Definition: packet.hh:1031
sc_mm.hh
sc_core::sc_module::before_end_of_elaboration
virtual void before_end_of_elaboration()
Definition: sc_module.hh:249
tlm::tlm_generic_payload::set_address
void set_address(const sc_dt::uint64 address)
Definition: gp.hh:202
tlm::tlm_generic_payload::has_mm
bool has_mm() const
Definition: gp.hh:157
gem5::Request::NO_ACCESS
@ NO_ACCESS
The request should not cause a memory access.
Definition: request.hh:146
tlm::tlm_sync_enum
tlm_sync_enum
Definition: fw_bw_ifs.hh:48
tlm::tlm_generic_payload::set_auto_extension
T * set_auto_extension(T *ext)
Definition: gp.hh:370
gem5::MipsISA::r
r
Definition: pra_constants.hh:98
sc_gem5::Gem5ToTlmBridge::invalidate_direct_mem_ptr
void invalidate_direct_mem_ptr(sc_dt::uint64 start_range, sc_dt::uint64 end_range)
Definition: gem5_to_tlm.cc:486
sc_gem5
Definition: sc_clock.cc:41
Gem5SystemC::Gem5Extension
Definition: sc_ext.hh:46
gem5::AddrRange
The AddrRange class encapsulates an address range, and supports a number of tests to check if two ran...
Definition: addr_range.hh:71
gem5::Packet::getAddr
Addr getAddr() const
Definition: packet.hh:781
gem5::EventBase::Default_Pri
static const Priority Default_Pri
Default is zero for historical reasons.
Definition: eventq.hh:179
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
sc_gem5::Gem5ToTlmBridge::Params
gem5::Gem5ToTlmBridgeBaseParams Params
Definition: gem5_to_tlm.hh:199
sc_gem5::mm
Gem5SystemC::MemoryManager mm
Instantiate a tlm memory manager that takes care about all the tlm transactions in the system.
Definition: gem5_to_tlm.cc:100
tlm::tlm_generic_payload::get_address
sc_dt::uint64 get_address() const
Definition: gp.hh:201
sc_gem5::Gem5ToTlmBridgeBase
Definition: gem5_to_tlm.hh:84
tlm::BEGIN_RESP
@ BEGIN_RESP
Definition: phase.hh:43
gem5::Packet::getSize
unsigned getSize() const
Definition: packet.hh:791
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::ArmISA::status
Bitfield< 5, 0 > status
Definition: misc_types.hh:422
tlm::tlm_generic_payload::set_data_ptr
void set_data_ptr(unsigned char *data)
Definition: gp.hh:206
gem5::Packet::getPtr
T * getPtr()
get a pointer to the data ptr.
Definition: packet.hh:1184
eventq.hh
tlm::TLM_ACCEPTED
@ TLM_ACCEPTED
Definition: fw_bw_ifs.hh:65

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