gem5  v21.1.0.2
gic_v3_redistributor.cc
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1 /*
2  * Copyright (c) 2019-2020 ARM Limited
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4  *
5  * The license below extends only to copyright in the software and shall
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14  * Copyright (c) 2018 Metempsy Technology Consulting
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40 
42 
43 #include "arch/arm/utility.hh"
44 #include "base/compiler.hh"
45 #include "debug/GIC.hh"
48 
49 namespace gem5
50 {
51 
52 using namespace ArmISA;
53 
54 const AddrRange Gicv3Redistributor::GICR_IPRIORITYR(SGI_base + 0x0400,
55  SGI_base + 0x0420);
56 
58  : gic(gic),
59  distributor(nullptr),
60  cpuInterface(nullptr),
61  cpuId(cpu_id),
62  memProxy(nullptr),
63  peInLowPowerState(true),
64  irqGroup(Gicv3::SGI_MAX + Gicv3::PPI_MAX, 0),
65  irqEnabled(Gicv3::SGI_MAX + Gicv3::PPI_MAX, false),
66  irqPending(Gicv3::SGI_MAX + Gicv3::PPI_MAX, false),
67  irqPendingIspendr(Gicv3::SGI_MAX + Gicv3::PPI_MAX, false),
68  irqActive(Gicv3::SGI_MAX + Gicv3::PPI_MAX, false),
69  irqPriority(Gicv3::SGI_MAX + Gicv3::PPI_MAX, 0),
70  irqConfig(Gicv3::SGI_MAX + Gicv3::PPI_MAX, Gicv3::INT_EDGE_TRIGGERED),
71  irqGrpmod(Gicv3::SGI_MAX + Gicv3::PPI_MAX, 0),
72  irqNsacr(Gicv3::SGI_MAX + Gicv3::PPI_MAX, 0),
73  DPG1S(false),
74  DPG1NS(false),
75  DPG0(false),
76  EnableLPIs(false),
77  lpiConfigurationTablePtr(0),
78  lpiIDBits(0),
79  lpiPendingTablePtr(0),
80  addrRangeSize(gic->params().gicv4 ? 0x40000 : 0x20000)
81 {
82 }
83 
84 void
86 {
89 
91 }
92 
93 uint64_t
94 Gicv3Redistributor::read(Addr addr, size_t size, bool is_secure_access)
95 {
96  if (GICR_IPRIORITYR.contains(addr)) { // Interrupt Priority Registers
97  uint64_t value = 0;
98  int first_intid = addr - GICR_IPRIORITYR.start();
99 
100  for (int i = 0, int_id = first_intid; i < size; i++, int_id++) {
101  uint8_t prio = irqPriority[int_id];
102 
103  if (!distributor->DS && !is_secure_access) {
104  if (getIntGroup(int_id) != Gicv3::G1NS) {
105  // RAZ/WI for non-secure accesses for secure interrupts
106  continue;
107  } else {
108  // NS view
109  prio = (prio << 1) & 0xff;
110  }
111  }
112 
113  value |= prio << (i * 8);
114  }
115 
116  return value;
117  }
118 
119  switch (addr) {
120  case GICR_CTLR: { // Control Register
121  uint64_t value = 0;
122 
123  if (DPG1S) {
124  value |= GICR_CTLR_DPG1S;
125  }
126 
127  if (DPG1NS) {
128  value |= GICR_CTLR_DPG1NS;
129  }
130 
131  if (DPG0) {
132  value |= GICR_CTLR_DPG0;
133  }
134 
135  if (EnableLPIs) {
136  value |= GICR_CTLR_ENABLE_LPIS;
137  }
138 
139  return value;
140  }
141 
142  case GICR_IIDR: // Implementer Identification Register
143  //return 0x43b; // r0p0 GIC-500
144  return 0;
145 
146  case GICR_TYPER: { // Type Register
147  /*
148  * Affinity_Value [63:32] == X
149  * (The identity of the PE associated with this Redistributor)
150  * CommonLPIAff [25:24] == 01
151  * (All Redistributors with the same Aff3 value must share an
152  * LPI Configuration table)
153  * Processor_Number [23:8] == X
154  * (A unique identifier for the PE)
155  * DPGS [5] == 1
156  * (GICR_CTLR.DPG* bits are supported)
157  * Last [4] == X
158  * (This Redistributor is the highest-numbered Redistributor in
159  * a series of contiguous Redistributor pages)
160  * DirectLPI [3] == 1
161  * (direct injection of LPIs supported)
162  * VLPIS [1] == 0
163  * (virtual LPIs not supported)
164  * PLPIS [0] == 1
165  * (physical LPIs supported)
166  */
167  uint64_t affinity = getAffinity();
168  int last = cpuId == (gic->getSystem()->threads.size() - 1);
169  return (affinity << 32) | (1 << 24) | (cpuId << 8) |
170  (1 << 5) | (last << 4) | (1 << 3) | (1 << 0);
171  }
172 
173  case GICR_WAKER: // Wake Register
174  if (!distributor->DS && !is_secure_access) {
175  // RAZ/WI for non-secure accesses
176  return 0;
177  }
178 
179  if (peInLowPowerState) {
181  } else {
182  return 0;
183  }
184 
185  case GICR_PIDR0: { // Peripheral ID0 Register
186  return 0x92; // Part number, bits[7:0]
187  }
188 
189  case GICR_PIDR1: { // Peripheral ID1 Register
190  uint8_t des_0 = 0xB; // JEP106 identification code, bits[3:0]
191  uint8_t part_1 = 0x4; // Part number, bits[11:8]
192  return (des_0 << 4) | (part_1 << 0);
193  }
194 
195  case GICR_PIDR2: { // Peripheral ID2 Register
196  uint8_t arch_rev = 0x3; // 0x3 GICv3
197  uint8_t jedec = 0x1; // JEP code
198  uint8_t des_1 = 0x3; // JEP106 identification code, bits[6:4]
199  return (arch_rev << 4) | (jedec << 3) | (des_1 << 0);
200  }
201 
202  case GICR_PIDR3: // Peripheral ID3 Register
203  return 0x0; // Implementation defined
204 
205  case GICR_PIDR4: { // Peripheral ID4 Register
206  uint8_t size = 0x4; // 64 KB software visible page
207  uint8_t des_2 = 0x4; // ARM implementation
208  return (size << 4) | (des_2 << 0);
209  }
210 
211  case GICR_PIDR5: // Peripheral ID5 Register
212  case GICR_PIDR6: // Peripheral ID6 Register
213  case GICR_PIDR7: // Peripheral ID7 Register
214  return 0; // RES0
215 
216  case GICR_IGROUPR0: { // Interrupt Group Register 0
217  uint64_t value = 0;
218 
219  if (!distributor->DS && !is_secure_access) {
220  // RAZ/WI for non-secure accesses
221  return 0;
222  }
223 
224  for (int int_id = 0; int_id < 8 * size; int_id++) {
225  value |= (irqGroup[int_id] << int_id);
226  }
227 
228  return value;
229  }
230 
231  case GICR_ISENABLER0: // Interrupt Set-Enable Register 0
232  case GICR_ICENABLER0: { // Interrupt Clear-Enable Register 0
233  uint64_t value = 0;
234 
235  for (int int_id = 0; int_id < 8 * size; int_id++) {
236  if (!distributor->DS && !is_secure_access) {
237  // RAZ/WI for non-secure accesses for secure interrupts
238  if (getIntGroup(int_id) != Gicv3::G1NS) {
239  continue;
240  }
241  }
242 
243  if (irqEnabled[int_id]) {
244  value |= (1 << int_id);
245  }
246  }
247 
248  return value;
249  }
250 
251  case GICR_ISPENDR0: // Interrupt Set-Pending Register 0
252  case GICR_ICPENDR0: { // Interrupt Clear-Pending Register 0
253  uint64_t value = 0;
254 
255  for (int int_id = 0; int_id < 8 * size; int_id++) {
256  if (!distributor->DS && !is_secure_access) {
257  // RAZ/WI for non-secure accesses for secure interrupts
258  if (getIntGroup(int_id) != Gicv3::G1NS) {
259  continue;
260  }
261  }
262 
263  value |= (irqPending[int_id] << int_id);
264  }
265 
266  return value;
267  }
268 
269  case GICR_ISACTIVER0: // Interrupt Set-Active Register 0
270  case GICR_ICACTIVER0: { // Interrupt Clear-Active Register 0
271  uint64_t value = 0;
272 
273  for (int int_id = 0; int_id < 8 * size; int_id++) {
274  if (!distributor->DS && !is_secure_access) {
275  // RAZ/WI for non-secure accesses for secure interrupts
276  if (getIntGroup(int_id) != Gicv3::G1NS) {
277  continue;
278  }
279  }
280 
281  value |= irqActive[int_id] << int_id;
282  }
283 
284  return value;
285  }
286 
287  case GICR_ICFGR0: // SGI Configuration Register
288  case GICR_ICFGR1: { // PPI Configuration Register
289  uint64_t value = 0;
290  uint32_t first_int_id = addr == GICR_ICFGR0 ? 0 : Gicv3::SGI_MAX;
291 
292  for (int i = 0, int_id = first_int_id; i < 32;
293  i = i + 2, int_id++) {
294  if (!distributor->DS && !is_secure_access) {
295  // RAZ/WI for non-secure accesses for secure interrupts
296  if (getIntGroup(int_id) != Gicv3::G1NS) {
297  continue;
298  }
299  }
300 
301  if (irqConfig[int_id] == Gicv3::INT_EDGE_TRIGGERED) {
302  value |= (0x2) << i;
303  }
304  }
305 
306  return value;
307  }
308 
309  case GICR_IGRPMODR0: { // Interrupt Group Modifier Register 0
310  uint64_t value = 0;
311 
312  if (distributor->DS) {
313  value = 0;
314  } else {
315  if (!is_secure_access) {
316  // RAZ/WI for non-secure accesses
317  value = 0;
318  } else {
319  for (int int_id = 0; int_id < 8 * size; int_id++) {
320  value |= irqGrpmod[int_id] << int_id;
321  }
322  }
323  }
324 
325  return value;
326  }
327 
328  case GICR_NSACR: { // Non-secure Access Control Register
329  uint64_t value = 0;
330 
331  if (distributor->DS) {
332  // RAZ/WI
333  value = 0;
334  } else {
335  if (!is_secure_access) {
336  // RAZ/WI
337  value = 0;
338  } else {
339  for (int i = 0, int_id = 0; i < 8 * size;
340  i = i + 2, int_id++) {
341  value |= irqNsacr[int_id] << i;
342  }
343  }
344  }
345 
346  return value;
347  }
348 
349  case GICR_PROPBASER: // Redistributor Properties Base Address Register
350  // OuterCache, bits [58:56]
351  // 000 Memory type defined in InnerCache field
352  // Physical_Address, bits [51:12]
353  // Bits [51:12] of the physical address containing the LPI
354  // Configuration table
355  // Shareability, bits [11:10]
356  // 00 Non-shareable
357  // InnerCache, bits [9:7]
358  // 000 Device-nGnRnE
359  // IDbits, bits [4:0]
360  // limited by GICD_TYPER.IDbits
362 
363  // Redistributor LPI Pending Table Base Address Register
364  case GICR_PENDBASER:
365  // PTZ, bit [62]
366  // Pending Table Zero
367  // OuterCache, bits [58:56]
368  // 000 Memory type defined in InnerCache field
369  // Physical_Address, bits [51:16]
370  // Bits [51:16] of the physical address containing the LPI Pending
371  // table
372  // Shareability, bits [11:10]
373  // 00 Non-shareable
374  // InnerCache, bits [9:7]
375  // 000 Device-nGnRnE
376  return lpiPendingTablePtr;
377 
378  // Redistributor Synchronize Register
379  case GICR_SYNCR:
380  return 0;
381 
382  default:
383  panic("Gicv3Redistributor::read(): invalid offset %#x\n", addr);
384  break;
385  }
386 }
387 
388 void
389 Gicv3Redistributor::write(Addr addr, uint64_t data, size_t size,
390  bool is_secure_access)
391 {
392  if (GICR_IPRIORITYR.contains(addr)) { // Interrupt Priority Registers
393  int first_intid = addr - GICR_IPRIORITYR.start();
394 
395  for (int i = 0, int_id = first_intid; i < size; i++, int_id++) {
396  uint8_t prio = bits(data, (i + 1) * 8 - 1, (i * 8));
397 
398  if (!distributor->DS && !is_secure_access) {
399  if (getIntGroup(int_id) != Gicv3::G1NS) {
400  // RAZ/WI for non-secure accesses for secure interrupts
401  continue;
402  } else {
403  // NS view
404  prio = 0x80 | (prio >> 1);
405  }
406  }
407 
408  irqPriority[int_id] = prio;
409  DPRINTF(GIC, "Gicv3Redistributor::write(): "
410  "int_id %d priority %d\n", int_id, irqPriority[int_id]);
411  }
412 
413  return;
414  }
415 
416  switch (addr) {
417  case GICR_CTLR: {
418  // GICR_TYPER.LPIS is 0 so EnableLPIs is RES0
419  EnableLPIs = data & GICR_CTLR_ENABLE_LPIS;
423  break;
424  }
425 
426  case GICR_WAKER: // Wake Register
427  {
428  if (!distributor->DS && !is_secure_access) {
429  // RAZ/WI for non-secure accesses
430  return;
431  }
432 
433  bool pe_was_low_power = peInLowPowerState;
435  if (!pe_was_low_power && peInLowPowerState) {
436  DPRINTF(GIC, "Gicv3Redistributor::write(): "
437  "PE entering in low power state\n");
439  } else if (pe_was_low_power && !peInLowPowerState) {
440  DPRINTF(GIC, "Gicv3Redistributor::write(): powering up PE\n");
443  }
444  break;
445  }
446 
447  case GICR_IGROUPR0: // Interrupt Group Register 0
448  if (!distributor->DS && !is_secure_access) {
449  // RAZ/WI for non-secure accesses
450  return;
451  }
452 
453  for (int int_id = 0; int_id < 8 * size; int_id++) {
454  irqGroup[int_id] = data & (1 << int_id) ? 1 : 0;
455  DPRINTF(GIC, "Gicv3Redistributor::write(): "
456  "int_id %d group %d\n", int_id, irqGroup[int_id]);
457  }
458 
459  break;
460 
461  case GICR_ISENABLER0: // Interrupt Set-Enable Register 0
462  for (int int_id = 0; int_id < 8 * size; int_id++) {
463  if (!distributor->DS && !is_secure_access) {
464  // RAZ/WI for non-secure accesses for secure interrupts
465  if (getIntGroup(int_id) != Gicv3::G1NS) {
466  continue;
467  }
468  }
469 
470  bool enable = data & (1 << int_id) ? 1 : 0;
471 
472  if (enable) {
473  irqEnabled[int_id] = true;
474  }
475 
476  DPRINTF(GIC, "Gicv3Redistributor::write(): "
477  "int_id %d enable %i\n", int_id, irqEnabled[int_id]);
478  }
479 
480  break;
481 
482  case GICR_ICENABLER0: // Interrupt Clear-Enable Register 0
483  for (int int_id = 0; int_id < 8 * size; int_id++) {
484  if (!distributor->DS && !is_secure_access) {
485  // RAZ/WI for non-secure accesses for secure interrupts
486  if (getIntGroup(int_id) != Gicv3::G1NS) {
487  continue;
488  }
489  }
490 
491  bool disable = data & (1 << int_id) ? 1 : 0;
492 
493  if (disable) {
494  irqEnabled[int_id] = false;
495  }
496 
497  DPRINTF(GIC, "Gicv3Redistributor::write(): "
498  "int_id %d enable %i\n", int_id, irqEnabled[int_id]);
499  }
500 
501  break;
502 
503  case GICR_ISPENDR0: // Interrupt Set-Pending Register 0
504  for (int int_id = 0; int_id < 8 * size; int_id++) {
505  if (!distributor->DS && !is_secure_access) {
506  // RAZ/WI for non-secure accesses for secure interrupts
507  if (getIntGroup(int_id) != Gicv3::G1NS) {
508  continue;
509  }
510  }
511 
512  bool pending = data & (1 << int_id) ? 1 : 0;
513 
514  if (pending) {
515  DPRINTF(GIC, "Gicv3Redistributor::write() "
516  "(GICR_ISPENDR0): int_id %d (PPI) "
517  "pending bit set\n", int_id);
518  irqPending[int_id] = true;
519  irqPendingIspendr[int_id] = true;
520  }
521  }
522 
524  break;
525 
526  case GICR_ICPENDR0:// Interrupt Clear-Pending Register 0
527  for (int int_id = 0; int_id < 8 * size; int_id++) {
528  if (!distributor->DS && !is_secure_access) {
529  // RAZ/WI for non-secure accesses for secure interrupts
530  if (getIntGroup(int_id) != Gicv3::G1NS) {
531  continue;
532  }
533  }
534 
535  bool clear = data & (1 << int_id) ? 1 : 0;
536 
537  if (clear && treatAsEdgeTriggered(int_id)) {
538  irqPending[int_id] = false;
539  }
540  }
541 
542  break;
543 
544  case GICR_ISACTIVER0: // Interrupt Set-Active Register 0
545  for (int int_id = 0; int_id < 8 * size; int_id++) {
546  if (!distributor->DS && !is_secure_access) {
547  // RAZ/WI for non-secure accesses for secure interrupts
548  if (getIntGroup(int_id) != Gicv3::G1NS) {
549  continue;
550  }
551  }
552 
553  bool activate = data & (1 << int_id) ? 1 : 0;
554 
555  if (activate) {
556  if (!irqActive[int_id]) {
557  DPRINTF(GIC, "Gicv3Redistributor::write(): "
558  "int_id %d active set\n", int_id);
559  }
560 
561  irqActive[int_id] = true;
562  }
563  }
564 
565  break;
566 
567  case GICR_ICACTIVER0: // Interrupt Clear-Active Register 0
568  for (int int_id = 0; int_id < 8 * size; int_id++) {
569  if (!distributor->DS && !is_secure_access) {
570  // RAZ/WI for non-secure accesses for secure interrupts
571  if (getIntGroup(int_id) != Gicv3::G1NS) {
572  continue;
573  }
574  }
575 
576  bool clear = data & (1 << int_id) ? 1 : 0;
577 
578  if (clear) {
579  if (irqActive[int_id]) {
580  DPRINTF(GIC, "Gicv3Redistributor::write(): "
581  "int_id %d active cleared\n", int_id);
582  }
583 
584  irqActive[int_id] = false;
585  }
586  }
587 
588  break;
589 
590  case GICR_ICFGR0: // SGI Configuration Register
591  // WI
592  return;
593  case GICR_ICFGR1: { // PPI Configuration Register
594  int first_intid = Gicv3::SGI_MAX;
595 
596  for (int i = 0, int_id = first_intid; i < 8 * size;
597  i = i + 2, int_id++) {
598  if (!distributor->DS && !is_secure_access) {
599  // RAZ/WI for non-secure accesses for secure interrupts
600  if (getIntGroup(int_id) != Gicv3::G1NS) {
601  continue;
602  }
603  }
604 
605  irqConfig[int_id] = data & (0x2 << i) ?
608  DPRINTF(GIC, "Gicv3Redistributor::write(): "
609  "int_id %d (PPI) config %d\n",
610  int_id, irqConfig[int_id]);
611  }
612 
613  break;
614  }
615 
616  case GICR_IGRPMODR0: { // Interrupt Group Modifier Register 0
617  if (distributor->DS) {
618  // RAZ/WI if secutiry disabled
619  } else {
620  for (int int_id = 0; int_id < 8 * size; int_id++) {
621  if (!is_secure_access) {
622  // RAZ/WI for non-secure accesses
623  continue;
624  }
625 
626  irqGrpmod[int_id] = data & (1 << int_id);
627  }
628  }
629 
630  break;
631  }
632 
633  case GICR_NSACR: { // Non-secure Access Control Register
634  if (distributor->DS) {
635  // RAZ/WI
636  } else {
637  if (!is_secure_access) {
638  // RAZ/WI
639  } else {
640  for (int i = 0, int_id = 0; i < 8 * size;
641  i = i + 2, int_id++) {
642  irqNsacr[int_id] = (data >> i) & 0x3;
643  }
644  }
645  }
646 
647  break;
648  }
649 
650  case GICR_SETLPIR: // Set LPI Pending Register
651  setClrLPI(data, true);
652  break;
653 
654  case GICR_CLRLPIR: // Clear LPI Pending Register
655  setClrLPI(data, false);
656  break;
657 
658  case GICR_PROPBASER: { // Redistributor Properties Base Address Register
659  // OuterCache, bits [58:56]
660  // 000 Memory type defined in InnerCache field
661  // Physical_Address, bits [51:12]
662  // Bits [51:12] of the physical address containing the LPI
663  // Configuration table
664  // Shareability, bits [11:10]
665  // 00 Non-shareable
666  // InnerCache, bits [9:7]
667  // 000 Device-nGnRnE
668  // IDbits, bits [4:0]
669  // limited by GICD_TYPER.IDbits (= 0xf)
670  lpiConfigurationTablePtr = data & 0xFFFFFFFFFF000;
671  lpiIDBits = data & 0x1f;
672 
673  // 0xf here matches the value of GICD_TYPER.IDbits.
674  // TODO - make GICD_TYPER.IDbits a parameter instead of a hardcoded
675  // value
676  if (lpiIDBits > 0xf) {
677  lpiIDBits = 0xf;
678  }
679 
680  break;
681  }
682 
683  // Redistributor LPI Pending Table Base Address Register
684  case GICR_PENDBASER:
685  // PTZ, bit [62]
686  // Pending Table Zero
687  // OuterCache, bits [58:56]
688  // 000 Memory type defined in InnerCache field
689  // Physical_Address, bits [51:16]
690  // Bits [51:16] of the physical address containing the LPI Pending
691  // table
692  // Shareability, bits [11:10]
693  // 00 Non-shareable
694  // InnerCache, bits [9:7]
695  // 000 Device-nGnRnE
696  lpiPendingTablePtr = data & 0xFFFFFFFFF0000;
697  break;
698 
699  case GICR_INVLPIR: { // Redistributor Invalidate LPI Register
700  // Do nothing: no caching supported
701  break;
702  }
703 
704  case GICR_INVALLR: { // Redistributor Invalidate All Register
705  // Do nothing: no caching supported
706  break;
707  }
708 
709  default:
710  panic("Gicv3Redistributor::write(): invalid offset %#x\n", addr);
711  break;
712  }
713 }
714 
715 void
717 {
718  assert((int_id >= Gicv3::SGI_MAX) &&
719  (int_id < Gicv3::SGI_MAX + Gicv3::PPI_MAX));
720  irqPending[int_id] = true;
721  irqPendingIspendr[int_id] = false;
722  DPRINTF(GIC, "Gicv3Redistributor::sendPPInt(): "
723  "int_id %d (PPI) pending bit set\n", int_id);
725 }
726 
727 void
729 {
730  assert((int_id >= Gicv3::SGI_MAX) &&
731  (int_id < Gicv3::SGI_MAX + Gicv3::PPI_MAX));
732 
733  if (isLevelSensitive(int_id)) {
734  irqPending[int_id] = false;
735  }
736 }
737 
738 void
739 Gicv3Redistributor::sendSGI(uint32_t int_id, Gicv3::GroupId group, bool ns)
740 {
741  assert(int_id < Gicv3::SGI_MAX);
742  Gicv3::GroupId int_group = getIntGroup(int_id);
743 
744  bool forward = false;
745 
746  if (ns) {
747  // Non-Secure EL1 and EL2 access
748  int nsaccess = irqNsacr[int_id];
749  if (int_group == Gicv3::G0S) {
750 
751  forward = distributor->DS || (nsaccess >= 1);
752 
753  } else if (int_group == Gicv3::G1S) {
754  forward = ((group == Gicv3::G1S || group == Gicv3::G1NS ) &&
755  nsaccess == 2);
756  } else {
757  // G1NS
758  forward = group == Gicv3::G1NS;
759  }
760  } else {
761  // Secure EL1 and EL3 access
762  forward = (group == int_group) ||
763  (group == Gicv3::G1S && int_group == Gicv3::G0S &&
764  distributor->DS);
765  }
766 
767  if (!forward) return;
768 
769  irqPending[int_id] = true;
770  irqPendingIspendr[int_id] = false;
771  DPRINTF(GIC, "Gicv3ReDistributor::sendSGI(): "
772  "int_id %d (SGI) pending bit set\n", int_id);
774 }
775 
777 Gicv3Redistributor::intStatus(uint32_t int_id) const
778 {
779  assert(int_id < Gicv3::SGI_MAX + Gicv3::PPI_MAX);
780 
781  if (irqPending[int_id]) {
782  if (irqActive[int_id]) {
784  }
785 
786  return Gicv3::INT_PENDING;
787  } else if (irqActive[int_id]) {
788  return Gicv3::INT_ACTIVE;
789  } else {
790  return Gicv3::INT_INACTIVE;
791  }
792 }
793 
794 void
796 {
797  distributor->update();
798 }
799 
800 /*
801  * Recalculate the highest priority pending interrupt after a
802  * change to redistributor state.
803  */
804 void
806 {
807  for (int int_id = 0; int_id < Gicv3::SGI_MAX + Gicv3::PPI_MAX; int_id++) {
808  Gicv3::GroupId int_group = getIntGroup(int_id);
809  bool group_enabled = distributor->groupEnabled(int_group);
810 
811  if (irqPending[int_id] && irqEnabled[int_id] &&
812  !irqActive[int_id] && group_enabled) {
813  if ((irqPriority[int_id] < cpuInterface->hppi.prio) ||
814  /*
815  * Multiple pending ints with same priority.
816  * Implementation choice which one to signal.
817  * Our implementation selects the one with the lower id.
818  */
819  (irqPriority[int_id] == cpuInterface->hppi.prio &&
820  int_id < cpuInterface->hppi.intid)) {
821  cpuInterface->hppi.intid = int_id;
822  cpuInterface->hppi.prio = irqPriority[int_id];
823  cpuInterface->hppi.group = int_group;
824  }
825  }
826  }
827 
828  // Check LPIs
829  if (EnableLPIs) {
830 
831  const uint32_t largest_lpi_id = 1 << (lpiIDBits + 1);
832  const uint32_t number_lpis = largest_lpi_id - SMALLEST_LPI_ID + 1;
833 
834  uint8_t lpi_pending_table[largest_lpi_id / 8];
835  uint8_t lpi_config_table[number_lpis];
836 
838  lpi_pending_table,
839  sizeof(lpi_pending_table));
840 
842  lpi_config_table,
843  sizeof(lpi_config_table));
844 
845  for (int lpi_id = SMALLEST_LPI_ID; lpi_id < largest_lpi_id;
846  lpi_id++) {
847  uint32_t lpi_pending_entry_byte = lpi_id / 8;
848  uint8_t lpi_pending_entry_bit_position = lpi_id % 8;
849  bool lpi_is_pending = lpi_pending_table[lpi_pending_entry_byte] &
850  1 << lpi_pending_entry_bit_position;
851  uint32_t lpi_configuration_entry_index = lpi_id - SMALLEST_LPI_ID;
852 
853  LPIConfigurationTableEntry config_entry =
854  lpi_config_table[lpi_configuration_entry_index];
855 
856  bool lpi_is_enable = config_entry.enable;
857 
858  // LPIs are always Non-secure Group 1 interrupts,
859  // in a system where two Security states are enabled.
860  Gicv3::GroupId lpi_group = Gicv3::G1NS;
861  bool group_enabled = distributor->groupEnabled(lpi_group);
862 
863  if (lpi_is_pending && lpi_is_enable && group_enabled) {
864  uint8_t lpi_priority = config_entry.priority << 2;
865 
866  if ((lpi_priority < cpuInterface->hppi.prio) ||
867  (lpi_priority == cpuInterface->hppi.prio &&
868  lpi_id < cpuInterface->hppi.intid)) {
869  cpuInterface->hppi.intid = lpi_id;
870  cpuInterface->hppi.prio = lpi_priority;
871  cpuInterface->hppi.group = lpi_group;
872  }
873  }
874  }
875  }
876 
877  if (peInLowPowerState) {
881  }
882  } else {
883  cpuInterface->update();
884  }
885 }
886 
887 uint8_t
889 {
890  Addr lpi_pending_entry_ptr = lpiPendingTablePtr + (lpi_id / 8);
891 
892  uint8_t lpi_pending_entry;
893  memProxy->readBlob(lpi_pending_entry_ptr,
894  &lpi_pending_entry,
895  sizeof(lpi_pending_entry));
896 
897  return lpi_pending_entry;
898 }
899 
900 void
901 Gicv3Redistributor::writeEntryLPI(uint32_t lpi_id, uint8_t lpi_pending_entry)
902 {
903  Addr lpi_pending_entry_ptr = lpiPendingTablePtr + (lpi_id / 8);
904 
905  memProxy->writeBlob(lpi_pending_entry_ptr,
906  &lpi_pending_entry,
907  sizeof(lpi_pending_entry));
908 }
909 
910 bool
912 {
913  // Fetch the LPI pending entry from memory
914  uint8_t lpi_pending_entry = readEntryLPI(lpi_id);
915 
916  uint8_t lpi_pending_entry_bit_position = lpi_id % 8;
917  bool is_set = lpi_pending_entry & (1 << lpi_pending_entry_bit_position);
918 
919  return is_set;
920 }
921 
922 void
924 {
925  if (!EnableLPIs) {
926  // Writes to GICR_SETLPIR or GICR_CLRLPIR have not effect if
927  // GICR_CTLR.EnableLPIs == 0.
928  return;
929  }
930 
931  uint32_t lpi_id = data & 0xffffffff;
932  uint32_t largest_lpi_id = 1 << (lpiIDBits + 1);
933 
934  if (lpi_id > largest_lpi_id) {
935  // Writes to GICR_SETLPIR or GICR_CLRLPIR have not effect if
936  // pINTID value specifies an unimplemented LPI.
937  return;
938  }
939 
940  // Fetch the LPI pending entry from memory
941  uint8_t lpi_pending_entry = readEntryLPI(lpi_id);
942 
943  uint8_t lpi_pending_entry_bit_position = lpi_id % 8;
944  bool is_set = lpi_pending_entry & (1 << lpi_pending_entry_bit_position);
945 
946  if (set) {
947  if (is_set) {
948  // Writes to GICR_SETLPIR have not effect if the pINTID field
949  // corresponds to an LPI that is already pending.
950  return;
951  }
952 
953  lpi_pending_entry |= 1 << (lpi_pending_entry_bit_position);
954  } else {
955  if (!is_set) {
956  // Writes to GICR_SETLPIR have not effect if the pINTID field
957  // corresponds to an LPI that is not pending.
958  return;
959  }
960 
961  lpi_pending_entry &= ~(1 << (lpi_pending_entry_bit_position));
962 
963  // Remove the pending state from the cpu interface
964  cpuInterface->resetHppi(lpi_id);
965  }
966 
967  writeEntryLPI(lpi_id, lpi_pending_entry);
968 
970 }
971 
974 {
975  assert(int_id < (Gicv3::SGI_MAX + Gicv3::PPI_MAX));
976 
977  if (distributor->DS) {
978  if (irqGroup[int_id] == 0) {
979  return Gicv3::G0S;
980  } else {
981  return Gicv3::G1NS;
982  }
983  } else {
984  if (irqGrpmod[int_id] == 0 && irqGroup[int_id] == 0) {
985  return Gicv3::G0S;
986  } else if (irqGrpmod[int_id] == 0 && irqGroup[int_id] == 1) {
987  return Gicv3::G1NS;
988  } else if (irqGrpmod[int_id] == 1 && irqGroup[int_id] == 0) {
989  return Gicv3::G1S;
990  } else if (irqGrpmod[int_id] == 1 && irqGroup[int_id] == 1) {
991  return Gicv3::G1NS;
992  }
993  }
994 
995  GEM5_UNREACHABLE;
996 }
997 
998 void
1000 {
1001  if (treatAsEdgeTriggered(int_id)) {
1002  irqPending[int_id] = false;
1003  }
1004  irqActive[int_id] = true;
1005 }
1006 
1007 void
1009 {
1010  irqActive[int_id] = false;
1011 }
1012 
1013 uint32_t
1015 {
1017  uint64_t mpidr = getMPIDR(gic->getSystem(), tc);
1018  /*
1019  * Aff3 = MPIDR[39:32]
1020  * (Note getMPIDR() returns uint32_t so Aff3 is always 0...)
1021  * Aff2 = MPIDR[23:16]
1022  * Aff1 = MPIDR[15:8]
1023  * Aff0 = MPIDR[7:0]
1024  * affinity = Aff3.Aff2.Aff1.Aff0
1025  */
1026  uint64_t affinity = ((mpidr & 0xff00000000) >> 8) | (mpidr & (0xffffff));
1027  return affinity;
1028 }
1029 
1030 bool
1032 {
1033  if (peInLowPowerState) {
1034  return false;
1035  }
1036 
1037  if (!distributor->groupEnabled(group)) {
1038  return false;
1039  }
1040 
1041  if ((group == Gicv3::G1S) && DPG1S) {
1042  return false;
1043  }
1044 
1045  if ((group == Gicv3::G1NS) && DPG1NS) {
1046  return false;
1047  }
1048 
1049  if ((group == Gicv3::G0S) && DPG0) {
1050  return false;
1051  }
1052 
1053  return true;
1054 }
1055 
1056 void
1058 {
1076 }
1077 
1078 void
1080 {
1098 }
1099 
1100 } // namespace gem5
gem5::Gicv3::G1NS
@ G1NS
Definition: gic_v3.hh:97
gem5::Gicv3::GroupId
GroupId
Definition: gic_v3.hh:93
gic_v3_cpu_interface.hh
gem5::Gicv3Redistributor::GICR_ICACTIVER0
@ GICR_ICACTIVER0
Definition: gic_v3_redistributor.hh:126
gem5::Gicv3Redistributor::irqGrpmod
std::vector< uint8_t > irqGrpmod
Definition: gic_v3_redistributor.hh:166
gem5::Trace::disable
void disable()
Definition: trace.cc:100
gem5::Gicv3Redistributor::GICR_CTLR
@ GICR_CTLR
Definition: gic_v3_redistributor.hh:81
gem5::BaseGic::getSystem
ArmSystem * getSystem() const
Definition: base_gic.hh:114
gem5::AddrRange::start
Addr start() const
Get the start address of the range.
Definition: addr_range.hh:317
gem5::System::Threads::size
int size() const
Definition: system.hh:216
gem5::PortProxy::writeBlob
void writeBlob(Addr addr, const void *p, int size) const
Same as tryWriteBlob, but insists on success.
Definition: port_proxy.hh:192
gem5::Gicv3Redistributor::GICR_CTLR_DPG1S
static const uint32_t GICR_CTLR_DPG1S
Definition: gic_v3_redistributor.hh:187
gic_v3_redistributor.hh
gem5::Gicv3Redistributor::DPG1NS
bool DPG1NS
Definition: gic_v3_redistributor.hh:170
data
const char data[]
Definition: circlebuf.test.cc:48
gem5::Gicv3::getCPUInterface
Gicv3CPUInterface * getCPUInterface(int cpu_id) const
Definition: gic_v3.hh:138
UNSERIALIZE_SCALAR
#define UNSERIALIZE_SCALAR(scalar)
Definition: serialize.hh:575
gem5::Gicv3Redistributor::GICR_IGRPMODR0
@ GICR_IGRPMODR0
Definition: gic_v3_redistributor.hh:132
gem5::Gicv3Redistributor::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: gic_v3_redistributor.cc:1079
gem5::Gicv3Redistributor::GICR_CLRLPIR
@ GICR_CLRLPIR
Definition: gic_v3_redistributor.hh:146
gem5::Gicv3Redistributor::GICR_ISENABLER0
@ GICR_ISENABLER0
Definition: gic_v3_redistributor.hh:116
gem5::Gicv3::getDistributor
Gicv3Distributor * getDistributor() const
Definition: gic_v3.hh:145
gem5::Gicv3Redistributor::update
void update()
Definition: gic_v3_redistributor.cc:805
UNSERIALIZE_CONTAINER
#define UNSERIALIZE_CONTAINER(member)
Definition: serialize.hh:634
gem5::System::physProxy
PortProxy physProxy
Port to physical memory used for writing object files into ram at boot.
Definition: system.hh:332
gem5::Gicv3Redistributor::GICR_ICPENDR0
@ GICR_ICPENDR0
Definition: gic_v3_redistributor.hh:122
gem5::Gicv3Redistributor::read
uint64_t read(Addr addr, size_t size, bool is_secure_access)
Definition: gic_v3_redistributor.cc:94
gem5::Gicv3Redistributor::GICR_INVLPIR
@ GICR_INVLPIR
Definition: gic_v3_redistributor.hh:152
gem5::Gicv3Redistributor::irqConfig
std::vector< Gicv3::IntTriggerType > irqConfig
Definition: gic_v3_redistributor.hh:165
gem5::Gicv3CPUInterface::deassertWakeRequest
void deassertWakeRequest(void)
Definition: gic_v3_cpu_interface.cc:2608
gem5::AddrRange::contains
bool contains(const Addr &a) const
Determine if the range contains an address.
Definition: addr_range.hh:438
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::Gicv3Redistributor::updateDistributor
void updateDistributor()
Definition: gic_v3_redistributor.cc:795
gem5::Gicv3Redistributor::GICR_PROPBASER
@ GICR_PROPBASER
Definition: gic_v3_redistributor.hh:148
gem5::Gicv3Redistributor::gic
Gicv3 * gic
Definition: gic_v3_redistributor.hh:65
gem5::Gicv3Redistributor::GICR_ICFGR1
@ GICR_ICFGR1
Definition: gic_v3_redistributor.hh:130
gem5::Gicv3::INT_EDGE_TRIGGERED
@ INT_EDGE_TRIGGERED
Definition: gic_v3.hh:103
gem5::Gicv3Redistributor::GICR_WAKER_ProcessorSleep
static const uint32_t GICR_WAKER_ProcessorSleep
Definition: gic_v3_redistributor.hh:106
gem5::Gicv3Redistributor::init
void init()
Definition: gic_v3_redistributor.cc:85
gem5::Gicv3::PPI_MAX
static const int PPI_MAX
Definition: gic_v3.hh:81
gem5::Gicv3Redistributor::GICR_CTLR_DPG0
static const uint32_t GICR_CTLR_DPG0
Definition: gic_v3_redistributor.hh:185
gem5::Gicv3Redistributor::GICR_TYPER
@ GICR_TYPER
Definition: gic_v3_redistributor.hh:85
gem5::Gicv3Redistributor::isPendingLPI
bool isPendingLPI(uint32_t intid)
Definition: gic_v3_redistributor.cc:911
gem5::ArmISA::ns
Bitfield< 0 > ns
Definition: misc_types.hh:331
gem5::Gicv3Distributor::update
void update()
Definition: gic_v3_distributor.cc:1085
gem5::Gicv3Redistributor::GICR_IGROUPR0
@ GICR_IGROUPR0
Definition: gic_v3_redistributor.hh:114
gem5::Gicv3Redistributor::irqPending
std::vector< bool > irqPending
Definition: gic_v3_redistributor.hh:161
gem5::Gicv3Redistributor::GICR_PIDR4
@ GICR_PIDR4
Definition: gic_v3_redistributor.hh:97
gem5::Gicv3Redistributor::write
void write(Addr addr, uint64_t data, size_t size, bool is_secure_access)
Definition: gic_v3_redistributor.cc:389
gem5::Gicv3CPUInterface::clearPendingInterrupts
void clearPendingInterrupts(void)
Definition: gic_v3_cpu_interface.cc:2591
gem5::Gicv3Redistributor::EnableLPIs
bool EnableLPIs
Definition: gic_v3_redistributor.hh:172
gem5::Gicv3CPUInterface::update
void update()
Definition: gic_v3_cpu_interface.cc:2033
gem5::Gicv3Redistributor::lpiPendingTablePtr
Addr lpiPendingTablePtr
Definition: gic_v3_redistributor.hh:176
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
gem5::Gicv3Redistributor::cpuId
uint32_t cpuId
Definition: gic_v3_redistributor.hh:68
gem5::Gicv3CPUInterface::resetHppi
void resetHppi(uint32_t intid)
Definition: gic_v3_cpu_interface.cc:77
gem5::Gicv3Redistributor::getIntGroup
Gicv3::GroupId getIntGroup(int int_id) const
Definition: gic_v3_redistributor.cc:973
gem5::Gicv3Redistributor::DPG1S
bool DPG1S
Definition: gic_v3_redistributor.hh:169
gem5::Gicv3Redistributor::memProxy
PortProxy * memProxy
Definition: gic_v3_redistributor.hh:69
gem5::Gicv3CPUInterface::havePendingInterrupts
bool havePendingInterrupts(void) const
Definition: gic_v3_cpu_interface.cc:2585
gem5::Gicv3Redistributor::GICR_PIDR0
@ GICR_PIDR0
Definition: gic_v3_redistributor.hh:89
gem5::Gicv3Redistributor::clearPPInt
void clearPPInt(uint32_t int_id)
Definition: gic_v3_redistributor.cc:728
gem5::Gicv3Redistributor::GICR_PIDR3
@ GICR_PIDR3
Definition: gic_v3_redistributor.hh:95
gem5::ArmISA::gic
Bitfield< 27, 24 > gic
Definition: misc_types.hh:174
gem5::Gicv3Distributor::DS
bool DS
Definition: gic_v3_distributor.hh:153
gem5::Gicv3Redistributor::distributor
Gicv3Distributor * distributor
Definition: gic_v3_redistributor.hh:66
gem5::Gicv3Redistributor::GICR_ICENABLER0
@ GICR_ICENABLER0
Definition: gic_v3_redistributor.hh:118
gem5::Gicv3::INT_LEVEL_SENSITIVE
@ INT_LEVEL_SENSITIVE
Definition: gic_v3.hh:102
gem5::Gicv3Redistributor::cpuInterface
Gicv3CPUInterface * cpuInterface
Definition: gic_v3_redistributor.hh:67
gem5::Gicv3::INT_PENDING
@ INT_PENDING
Definition: gic_v3.hh:87
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::Gicv3Redistributor::GICR_WAKER
@ GICR_WAKER
Definition: gic_v3_redistributor.hh:87
gem5::Gicv3::INT_ACTIVE
@ INT_ACTIVE
Definition: gic_v3.hh:88
gem5::Gicv3Distributor::groupEnabled
bool groupEnabled(Gicv3::GroupId group) const
Definition: gic_v3_distributor.hh:188
gem5::Gicv3Redistributor::writeEntryLPI
void writeEntryLPI(uint32_t intid, uint8_t lpi_entry)
Definition: gic_v3_redistributor.cc:901
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::Gicv3Redistributor::GICR_IIDR
@ GICR_IIDR
Definition: gic_v3_redistributor.hh:83
gem5::Gicv3::INT_INACTIVE
@ INT_INACTIVE
Definition: gic_v3.hh:86
gem5::Gicv3Redistributor::irqPriority
std::vector< uint8_t > irqPriority
Definition: gic_v3_redistributor.hh:164
gem5::Gicv3Redistributor::treatAsEdgeTriggered
bool treatAsEdgeTriggered(uint32_t int_id) const
This helper is used to check if an interrupt should be treated as edge triggered in the following sce...
Definition: gic_v3_redistributor.hh:249
gem5::Gicv3Redistributor::irqActive
std::vector< bool > irqActive
Definition: gic_v3_redistributor.hh:163
gem5::Gicv3Redistributor::peInLowPowerState
bool peInLowPowerState
Definition: gic_v3_redistributor.hh:109
gem5::Gicv3CPUInterface::hppi_t::intid
uint32_t intid
Definition: gic_v3_cpu_interface.hh:159
gem5::Gicv3Redistributor::irqNsacr
std::vector< uint8_t > irqNsacr
Definition: gic_v3_redistributor.hh:167
gem5::Gicv3Redistributor::sendPPInt
void sendPPInt(uint32_t int_id)
Definition: gic_v3_redistributor.cc:716
gem5::Gicv3Redistributor::GICR_ICFGR0
@ GICR_ICFGR0
Definition: gic_v3_redistributor.hh:128
gem5::Gicv3Redistributor::enable
Bitfield< 0 > enable
Definition: gic_v3_redistributor.hh:181
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
compiler.hh
gem5::Gicv3Redistributor::GICR_NSACR
@ GICR_NSACR
Definition: gic_v3_redistributor.hh:134
gem5::Gicv3CPUInterface::hppi
hppi_t hppi
Definition: gic_v3_cpu_interface.hh:164
gem5::Gicv3Redistributor::isLevelSensitive
bool isLevelSensitive(uint32_t int_id) const
Definition: gic_v3_redistributor.hh:233
gem5::Gicv3Redistributor::GICR_ISACTIVER0
@ GICR_ISACTIVER0
Definition: gic_v3_redistributor.hh:124
gem5::PortProxy::readBlob
void readBlob(Addr addr, void *p, int size) const
Higher level interfaces based on the above.
Definition: port_proxy.hh:182
gem5::Gicv3Redistributor::DPG0
bool DPG0
Definition: gic_v3_redistributor.hh:171
gem5::Gicv3Redistributor::GICR_PENDBASER
@ GICR_PENDBASER
Definition: gic_v3_redistributor.hh:150
gem5::Gicv3Redistributor::irqGroup
std::vector< uint8_t > irqGroup
Definition: gic_v3_redistributor.hh:159
gem5::Gicv3Redistributor::GICR_SETLPIR
@ GICR_SETLPIR
Definition: gic_v3_redistributor.hh:144
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::Gicv3Redistributor::GICR_PIDR1
@ GICR_PIDR1
Definition: gic_v3_redistributor.hh:91
gem5::Gicv3Redistributor::irqPendingIspendr
std::vector< bool > irqPendingIspendr
Definition: gic_v3_redistributor.hh:162
SERIALIZE_SCALAR
#define SERIALIZE_SCALAR(scalar)
Definition: serialize.hh:568
gem5::Gicv3Redistributor::GICR_PIDR2
@ GICR_PIDR2
Definition: gic_v3_redistributor.hh:93
utility.hh
gem5::Gicv3::G0S
@ G0S
Definition: gic_v3.hh:95
gem5::Gicv3
Definition: gic_v3.hh:56
gem5::Gicv3Redistributor::lpiIDBits
uint8_t lpiIDBits
Definition: gic_v3_redistributor.hh:175
gem5::Gicv3Redistributor::GICR_PIDR7
@ GICR_PIDR7
Definition: gic_v3_redistributor.hh:103
gem5::Gicv3Redistributor::lpiConfigurationTablePtr
Addr lpiConfigurationTablePtr
Definition: gic_v3_redistributor.hh:174
gem5::Gicv3Redistributor::deactivateIRQ
void deactivateIRQ(uint32_t int_id)
Definition: gic_v3_redistributor.cc:1008
gem5::Gicv3CPUInterface::hppi_t::group
Gicv3::GroupId group
Definition: gic_v3_cpu_interface.hh:161
gem5::System::threads
Threads threads
Definition: system.hh:316
gem5::Gicv3Redistributor::SMALLEST_LPI_ID
static const uint32_t SMALLEST_LPI_ID
Definition: gic_v3_redistributor.hh:200
gem5::Gicv3Redistributor::irqEnabled
std::vector< bool > irqEnabled
Definition: gic_v3_redistributor.hh:160
gem5::Gicv3::IntStatus
IntStatus
Definition: gic_v3.hh:84
gem5::Gicv3Redistributor::Gicv3Redistributor
Gicv3Redistributor(Gicv3 *gic, uint32_t cpu_id)
Definition: gic_v3_redistributor.cc:57
gem5::Gicv3::SGI_MAX
static const int SGI_MAX
Definition: gic_v3.hh:79
SERIALIZE_CONTAINER
#define SERIALIZE_CONTAINER(member)
Definition: serialize.hh:626
gem5::Gicv3Redistributor::intStatus
Gicv3::IntStatus intStatus(uint32_t int_id) const
Definition: gic_v3_redistributor.cc:777
gem5::Gicv3Redistributor::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: gic_v3_redistributor.cc:1057
gem5::Gicv3Redistributor::GICR_CTLR_DPG1NS
static const uint32_t GICR_CTLR_DPG1NS
Definition: gic_v3_redistributor.hh:186
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::Gicv3::G1S
@ G1S
Definition: gic_v3.hh:96
gem5::Gicv3Redistributor::GICR_PIDR6
@ GICR_PIDR6
Definition: gic_v3_redistributor.hh:101
gem5::Gicv3::INT_ACTIVE_PENDING
@ INT_ACTIVE_PENDING
Definition: gic_v3.hh:89
gem5::Gicv3Redistributor::setClrLPI
void setClrLPI(uint64_t data, bool set)
Definition: gic_v3_redistributor.cc:923
gem5::Gicv3Redistributor::GICR_PIDR5
@ GICR_PIDR5
Definition: gic_v3_redistributor.hh:99
gem5::Gicv3CPUInterface::assertWakeRequest
void assertWakeRequest(void)
Definition: gic_v3_cpu_interface.cc:2598
gem5::Gicv3Redistributor::canBeSelectedFor1toNInterrupt
bool canBeSelectedFor1toNInterrupt(Gicv3::GroupId group) const
Definition: gic_v3_redistributor.cc:1031
gem5::Gicv3Redistributor::readEntryLPI
uint8_t readEntryLPI(uint32_t intid)
Definition: gic_v3_redistributor.cc:888
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gic_v3_distributor.hh
gem5::Gicv3Redistributor::GICR_WAKER_ChildrenAsleep
static const uint32_t GICR_WAKER_ChildrenAsleep
Definition: gic_v3_redistributor.hh:107
gem5::Gicv3Redistributor::sendSGI
void sendSGI(uint32_t int_id, Gicv3::GroupId group, bool ns)
Definition: gic_v3_redistributor.cc:739
gem5::Gicv3Redistributor::activateIRQ
void activateIRQ(uint32_t int_id)
Definition: gic_v3_redistributor.cc:999
gem5::Gicv3Redistributor::GICR_IPRIORITYR
static const AddrRange GICR_IPRIORITYR
Definition: gic_v3_redistributor.hh:138
gem5::Gicv3CPUInterface::hppi_t::prio
uint8_t prio
Definition: gic_v3_cpu_interface.hh:160
gem5::Gicv3Redistributor::GICR_SYNCR
@ GICR_SYNCR
Definition: gic_v3_redistributor.hh:156
gem5::Gicv3Redistributor::GICR_INVALLR
@ GICR_INVALLR
Definition: gic_v3_redistributor.hh:154
gem5::Gicv3Redistributor::GICR_ISPENDR0
@ GICR_ISPENDR0
Definition: gic_v3_redistributor.hh:120
gem5::ArmISA::getMPIDR
RegVal getMPIDR(ArmSystem *arm_sys, ThreadContext *tc)
This helper function is returning the value of MPIDR_EL1.
Definition: utility.cc:162
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::Gicv3Redistributor::getAffinity
uint32_t getAffinity() const
Definition: gic_v3_redistributor.cc:1014

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