gem5  v21.1.0.2
i8254xGBe.hh
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1 /*
2  * Copyright (c) 2006 The Regents of The University of Michigan
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions are
7  * met: redistributions of source code must retain the above copyright
8  * notice, this list of conditions and the following disclaimer;
9  * redistributions in binary form must reproduce the above copyright
10  * notice, this list of conditions and the following disclaimer in the
11  * documentation and/or other materials provided with the distribution;
12  * neither the name of the copyright holders nor the names of its
13  * contributors may be used to endorse or promote products derived from
14  * this software without specific prior written permission.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27  */
28 
29 /* @file
30  * Device model for Intel's 8254x line of gigabit ethernet controllers.
31  */
32 
33 #ifndef __DEV_NET_I8254XGBE_HH__
34 #define __DEV_NET_I8254XGBE_HH__
35 
36 #include <cstdint>
37 #include <deque>
38 #include <string>
39 
40 #include "base/inet.hh"
41 #include "base/trace.hh"
42 #include "base/types.hh"
43 #include "debug/EthernetDesc.hh"
44 #include "debug/EthernetIntr.hh"
45 #include "dev/net/etherdevice.hh"
46 #include "dev/net/etherint.hh"
47 #include "dev/net/etherpkt.hh"
49 #include "dev/net/pktfifo.hh"
50 #include "dev/pci/device.hh"
51 #include "params/IGbE.hh"
52 #include "sim/eventq.hh"
53 #include "sim/serialize.hh"
54 
55 namespace gem5
56 {
57 
58 class IGbEInt;
59 
60 class IGbE : public EtherDevice
61 {
62  private:
64 
65  // device registers
67 
68  // eeprom data, status and control bits
70  uint8_t eeOpcode, eeAddr;
72 
73  // packet fifos
76 
77  // Packet that we are currently putting into the txFifo
79 
80  // Should to Rx/Tx State machine tick?
81  bool inTick;
82  bool rxTick;
83  bool txTick;
84  bool txFifoTick;
85 
87 
88  // Number of bytes copied from current RX packet
89  unsigned pktOffset;
90 
91  // Delays in managaging descriptors
95 
96  // Event and function to deal with RDTR timer expiring
97  void rdtrProcess() {
99  DPRINTF(EthernetIntr,
100  "Posting RXT interrupt because RDTR timer expired\n");
102  }
103 
105 
106  // Event and function to deal with RADV timer expiring
107  void radvProcess() {
109  DPRINTF(EthernetIntr,
110  "Posting RXT interrupt because RADV timer expired\n");
112  }
113 
115 
116  // Event and function to deal with TADV timer expiring
117  void tadvProcess() {
119  DPRINTF(EthernetIntr,
120  "Posting TXDW interrupt because TADV timer expired\n");
122  }
123 
125 
126  // Event and function to deal with TIDV timer expiring
127  void tidvProcess() {
129  DPRINTF(EthernetIntr,
130  "Posting TXDW interrupt because TIDV timer expired\n");
132  }
134 
135  // Main event to tick the device
136  void tick();
138 
139 
140  uint64_t macAddr;
141 
142  void rxStateMachine();
143  void txStateMachine();
144  void txWire();
145 
151  void postInterrupt(igbreg::IntTypes t, bool now = false);
152 
156  void chkInterrupt();
157 
160  void delayIntEvent();
161  void cpuPostInt();
162  // Event to moderate interrupts
164 
167  void cpuClearInt();
168 
169  Tick intClock() { return sim_clock::as_int::ns * 1024; }
170 
173  void restartClock();
174 
178  void checkDrain();
179 
180  template<class T>
181  class DescCache : public Serializable
182  {
183  protected:
184  virtual Addr descBase() const = 0;
185  virtual long descHead() const = 0;
186  virtual long descTail() const = 0;
187  virtual long descLen() const = 0;
188  virtual void updateHead(long h) = 0;
189  virtual void enableSm() = 0;
190  virtual void actionAfterWb() {}
191  virtual void fetchAfterWb() = 0;
192 
196 
198  T *wbBuf;
199 
200  // Pointer to the device we cache for
202 
203  // Name of this descriptor cache
204  std::string _name;
205 
206  // How far we've cached
207  int cachePnt;
208 
209  // The size of the descriptor cache
210  int size;
211 
212  // How many descriptors we are currently fetching
214 
215  // How many descriptors we are currently writing back
216  int wbOut;
217 
218  // if the we wrote back to the end of the descriptor ring and are going
219  // to have to wrap and write more
220  bool moreToWb;
221 
222  // What the alignment is of the next descriptor writeback
224 
227 
229  Addr pciToDma(Addr a) { return igbe->pciToDma(a); }
230 
231  public:
235 
236  DescCache(IGbE *i, const std::string n, int s);
237  virtual ~DescCache();
238 
239  std::string name() { return _name; }
240 
245  void areaChanged();
246 
247  void writeback(Addr aMask);
248  void writeback1();
250 
254  void fetchDescriptors();
255  void fetchDescriptors1();
257 
260  void fetchComplete();
262 
265  void wbComplete();
267 
268  /* Return the number of descriptors left in the ring, so the device has
269  * a way to figure out if it needs to interrupt.
270  */
271  unsigned
272  descLeft() const
273  {
274  unsigned left = unusedCache.size();
275  if (cachePnt > descTail())
276  left += (descLen() - cachePnt + descTail());
277  else
278  left += (descTail() - cachePnt);
279 
280  return left;
281  }
282 
283  /* Return the number of descriptors used and not written back.
284  */
285  unsigned descUsed() const { return usedCache.size(); }
286 
287  /* Return the number of cache unused descriptors we have. */
288  unsigned descUnused() const { return unusedCache.size(); }
289 
290  /* Get into a state where the descriptor address/head/etc colud be
291  * changed */
292  void reset();
293 
294 
295  void serialize(CheckpointOut &cp) const override;
296  void unserialize(CheckpointIn &cp) override;
297 
298  virtual bool hasOutstandingEvents() {
299  return wbEvent.scheduled() || fetchEvent.scheduled();
300  }
301 
302  };
303 
304 
305  class RxDescCache : public DescCache<igbreg::RxDesc>
306  {
307  protected:
308  Addr descBase() const override { return igbe->regs.rdba(); }
309  long descHead() const override { return igbe->regs.rdh(); }
310  long descLen() const override { return igbe->regs.rdlen() >> 4; }
311  long descTail() const override { return igbe->regs.rdt(); }
312  void updateHead(long h) override { igbe->regs.rdh(h); }
313  void enableSm() override;
314  void fetchAfterWb() override {
317  }
318 
319  bool pktDone;
320 
323 
326  unsigned bytesCopied;
327 
328  public:
329  RxDescCache(IGbE *i, std::string n, int s);
330 
338  int writePacket(EthPacketPtr packet, int pkt_offset);
339 
342  void pktComplete();
343 
347  bool packetDone();
348 
350 
351  // Event to handle issuing header and data write at the same time
352  // and only callking pktComplete() when both are completed
353  void pktSplitDone();
356 
357  bool hasOutstandingEvents() override;
358 
359  void serialize(CheckpointOut &cp) const override;
360  void unserialize(CheckpointIn &cp) override;
361  };
362  friend class RxDescCache;
363 
365 
366  class TxDescCache : public DescCache<igbreg::TxDesc>
367  {
368  protected:
369  Addr descBase() const override { return igbe->regs.tdba(); }
370  long descHead() const override { return igbe->regs.tdh(); }
371  long descTail() const override { return igbe->regs.tdt(); }
372  long descLen() const override { return igbe->regs.tdlen() >> 4; }
373  void updateHead(long h) override { igbe->regs.tdh(h); }
374  void enableSm() override;
375  void actionAfterWb() override;
376  void fetchAfterWb() override {
379  }
380 
381 
382 
383  bool pktDone;
384  bool isTcp;
389  uint32_t descEnd;
390 
391 
392  // tso variables
393  bool useTso;
402  uint8_t tsoHeader[256];
405  int tsoPkts;
406 
407  public:
408  TxDescCache(IGbE *i, std::string n, int s);
409 
414  unsigned getPacketSize(EthPacketPtr p);
416  void processContextDesc();
417 
421  unsigned
422  descInBlock(unsigned num_desc)
423  {
424  return num_desc / igbe->cacheBlockSize() / sizeof(igbreg::TxDesc);
425  }
426 
431  bool packetAvailable();
432 
436  bool packetWaiting() { return pktWaiting; }
437 
444  bool packetMultiDesc() { return pktMultiDesc;}
445 
448  void pktComplete();
450 
451  void headerComplete();
453 
454 
456  DPRINTF(EthernetDesc,
457  "Completion writeback Addr: %#x enabled: %d\n",
458  a, enabled);
461  }
462 
463  bool hasOutstandingEvents() override;
464 
465  void nullCallback() {
466  DPRINTF(EthernetDesc, "Completion writeback complete\n");
467  }
469 
470  void serialize(CheckpointOut &cp) const override;
471  void unserialize(CheckpointIn &cp) override;
472  };
473 
474  friend class TxDescCache;
475 
477 
478  public:
479  PARAMS(IGbE);
480 
481  IGbE(const Params &params);
482  ~IGbE();
483  void init() override;
484 
485  Port &getPort(const std::string &if_name,
486  PortID idx=InvalidPortID) override;
487 
489 
490  Tick read(PacketPtr pkt) override;
491  Tick write(PacketPtr pkt) override;
492 
493  Tick writeConfig(PacketPtr pkt) override;
494 
495  bool ethRxPkt(EthPacketPtr packet);
496  void ethTxDone();
497 
498  void serialize(CheckpointOut &cp) const override;
499  void unserialize(CheckpointIn &cp) override;
500 
501  DrainState drain() override;
502  void drainResume() override;
503 
504 };
505 
506 class IGbEInt : public EtherInt
507 {
508  private:
510 
511  public:
512  IGbEInt(const std::string &name, IGbE *d)
513  : EtherInt(name), dev(d)
514  { }
515 
516  virtual bool recvPacket(EthPacketPtr pkt) { return dev->ethRxPkt(pkt); }
517  virtual void sendDone() { dev->ethTxDone(); }
518 };
519 
520 } // namespace gem5
521 
522 #endif //__DEV_NET_I8254XGBE_HH__
gem5::IGbE::DescCache::_name
std::string _name
Definition: i8254xGBe.hh:204
gem5::IGbE::TxDescCache::nullEvent
EventFunctionWrapper nullEvent
Definition: i8254xGBe.hh:468
gem5::PortID
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:252
gem5::IGbE::DescCache::wbComplete
void wbComplete()
Called by event when dma to writeback descriptors is completed.
Definition: i8254xGBe.cc:1017
gem5::IGbE::TxDescCache::getPacketData
void getPacketData(EthPacketPtr p)
Definition: i8254xGBe.cc:1658
gem5::IGbE::DescCache::annUsedCacheQ
std::string annUsedCacheQ
Definition: i8254xGBe.hh:233
gem5::IGbE::read
Tick read(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: i8254xGBe.cc:170
gem5::IGbE
Definition: i8254xGBe.hh:60
gem5::IGbE::TxDescCache::tsoMss
Addr tsoMss
Definition: i8254xGBe.hh:395
gem5::IGbE::DescCache::hasOutstandingEvents
virtual bool hasOutstandingEvents()
Definition: i8254xGBe.hh:298
gem5::IGbE::TxDescCache::tsoPktHasHeader
bool tsoPktHasHeader
Definition: i8254xGBe.hh:401
gem5::IGbE::RxDescCache::descHead
long descHead() const override
Definition: i8254xGBe.hh:309
gem5::IGbE::RxDescCache::pktHdrEvent
EventFunctionWrapper pktHdrEvent
Definition: i8254xGBe.hh:354
serialize.hh
gem5::IGbE::DescCache::curFetching
int curFetching
Definition: i8254xGBe.hh:213
gem5::IGbE::TxDescCache::headerEvent
EventFunctionWrapper headerEvent
Definition: i8254xGBe.hh:452
gem5::IGbE::writeConfig
Tick writeConfig(PacketPtr pkt) override
Write to the PCI config space data that is stored locally.
Definition: i8254xGBe.cc:151
gem5::Drainable::drainState
DrainState drainState() const
Return the current drain state of an object.
Definition: drain.hh:324
gem5::IGbE::DescCache::descLen
virtual long descLen() const =0
gem5::igbreg::TxDesc
Definition: i8254xGBe_defs.hh:236
gem5::IGbE::postInterrupt
void postInterrupt(igbreg::IntTypes t, bool now=false)
Write an interrupt into the interrupt pending register and check mask and interrupt limit timer befor...
Definition: i8254xGBe.cc:695
gem5::IGbE::inTick
bool inTick
Definition: i8254xGBe.hh:81
gem5::IGbE::DescCache::cachePnt
int cachePnt
Definition: i8254xGBe.hh:207
gem5::IGbE::rxDmaPacket
bool rxDmaPacket
Definition: i8254xGBe.hh:86
gem5::IGbE::TxDescCache::completionWriteback
void completionWriteback(Addr a, bool enabled)
Definition: i8254xGBe.hh:455
gem5::IGbE::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: i8254xGBe.cc:2412
gem5::IGbE::DescCache::fetchAfterWb
virtual void fetchAfterWb()=0
gem5::IGbE::DescCache::areaChanged
void areaChanged()
If the address/len/head change when we've got descriptors that are dirty that is very bad.
Definition: i8254xGBe.cc:848
gem5::igbreg::IT_TXDW
@ IT_TXDW
Definition: i8254xGBe_defs.hh:177
gem5::IGbE::RxDescCache::bytesCopied
unsigned bytesCopied
Bytes of packet that have been copied, so we know when to set EOP.
Definition: i8254xGBe.hh:326
gem5::IGbE::TxDescCache::tsoTotalLen
Addr tsoTotalLen
Definition: i8254xGBe.hh:396
gem5::IGbE::cpuClearInt
void cpuClearInt()
Clear the interupt line to the cpu.
Definition: i8254xGBe.cc:779
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::IGbE::TxDescCache::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: i8254xGBe.cc:1946
gem5::IGbE::DescCache::descBase
virtual Addr descBase() const =0
gem5::IGbE::DescCache
Definition: i8254xGBe.hh:181
gem5::IGbE::TxDescCache::descInBlock
unsigned descInBlock(unsigned num_desc)
Return the number of dsecriptors in a cache block for threshold operations.
Definition: i8254xGBe.hh:422
etherint.hh
gem5::IGbE::TxDescCache::tsoDescBytesUsed
Addr tsoDescBytesUsed
Definition: i8254xGBe.hh:403
gem5::IGbE::RxDescCache::pktSplitDone
void pktSplitDone()
Definition: i8254xGBe.cc:1164
gem5::IGbE::DescCache::~DescCache
virtual ~DescCache()
Definition: i8254xGBe.cc:839
gem5::ArmISA::a
Bitfield< 8 > a
Definition: misc_types.hh:65
gem5::IGbE::DescCache::moreToWb
bool moreToWb
Definition: i8254xGBe.hh:220
gem5::IGbE::TxDescCache::pktMultiDesc
bool pktMultiDesc
Definition: i8254xGBe.hh:386
gem5::EtherInt::name
const std::string & name() const
Return port name (for DPRINTF).
Definition: etherint.hh:62
gem5::IGbE::DescCache::writeback
void writeback(Addr aMask)
Definition: i8254xGBe.cc:858
gem5::IGbE::PARAMS
PARAMS(IGbE)
gem5::igbreg::Regs::tdlen
TDLEN tdlen
Definition: i8254xGBe_defs.hh:688
gem5::IGbE::TxDescCache::descBase
Addr descBase() const override
Definition: i8254xGBe.hh:369
gem5::IGbE::RxDescCache::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: i8254xGBe.cc:1486
gem5::IGbE::DescCache::wbDelayEvent
EventFunctionWrapper wbDelayEvent
Definition: i8254xGBe.hh:249
gem5::IGbE::DescCache::fetchDescriptors1
void fetchDescriptors1()
Definition: i8254xGBe.cc:969
gem5::IGbE::TxDescCache::tsoCopyBytes
Addr tsoCopyBytes
Definition: i8254xGBe.hh:404
gem5::IGbE::DescCache::pciToDma
Addr pciToDma(Addr a)
Shortcut for DMA address translation.
Definition: i8254xGBe.hh:229
gem5::IGbE::wbDelay
Tick wbDelay
Definition: i8254xGBe.hh:92
gem5::IGbE::drainResume
void drainResume() override
Resume execution after a successful drain.
Definition: i8254xGBe.cc:2035
gem5::IGbE::TxDescCache::descTail
long descTail() const override
Definition: i8254xGBe.hh:371
gem5::IGbE::drain
DrainState drain() override
Draining is the process of clearing out the states of SimObjects.These are the SimObjects that are pa...
Definition: i8254xGBe.cc:2012
gem5::EtherDevice
Definition: etherdevice.hh:48
gem5::IGbE::chkInterrupt
void chkInterrupt()
Check and see if changes to the mask register have caused an interrupt to need to be sent or perhaps ...
Definition: i8254xGBe.cc:791
gem5::EtherInt
Definition: etherint.hh:50
gem5::InvalidPortID
const PortID InvalidPortID
Definition: types.hh:253
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
gem5::IGbE::getPort
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
Definition: i8254xGBe.cc:143
gem5::IGbE::~IGbE
~IGbE()
Definition: i8254xGBe.cc:131
gem5::igbreg::Regs::rdh
RDH rdh
Definition: i8254xGBe_defs.hh:625
device.hh
gem5::IGbEInt
Definition: i8254xGBe.hh:506
gem5::IGbE::TxDescCache::descHead
long descHead() const override
Definition: i8254xGBe.hh:370
gem5::IGbE::eeOpBits
int eeOpBits
Definition: i8254xGBe.hh:69
gem5::IGbE::DescCache::pktPtr
EthPacketPtr pktPtr
The packet that is currently being dmad to memory if any.
Definition: i8254xGBe.hh:226
gem5::IGbE::IGbE
IGbE(const Params &params)
Definition: i8254xGBe.cc:61
gem5::igbreg::Regs::tdba
TDBA tdba
Definition: i8254xGBe_defs.hh:680
gem5::IGbE::TxDescCache::packetAvailable
bool packetAvailable()
Ask if the packet has been transfered so the state machine can give it to the fifo.
Definition: i8254xGBe.cc:1975
gem5::IGbE::DescCache::wbAlignment
Addr wbAlignment
Definition: i8254xGBe.hh:223
gem5::IGbE::RxDescCache::splitCount
int splitCount
Variable to head with header/data completion events.
Definition: i8254xGBe.hh:322
gem5::IGbE::DescCache::DescCache
DescCache(IGbE *i, const std::string n, int s)
Definition: i8254xGBe.cc:826
gem5::IGbE::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: i8254xGBe.cc:2361
gem5::IGbE::etherInt
IGbEInt * etherInt
Definition: i8254xGBe.hh:63
gem5::IGbE::DescCache::annUsedDescQ
std::string annUsedDescQ
Definition: i8254xGBe.hh:234
gem5::IGbE::TxDescCache::pktComplete
void pktComplete()
Called by event when dma to write packet is completed.
Definition: i8254xGBe.cc:1706
gem5::IGbE::txReadDelay
Tick txReadDelay
Definition: i8254xGBe.hh:94
gem5::IGbE::DescCache::fetchDelayEvent
EventFunctionWrapper fetchDelayEvent
Definition: i8254xGBe.hh:256
gem5::IGbE::RxDescCache::pktComplete
void pktComplete()
Called by event when dma to write packet is completed.
Definition: i8254xGBe.cc:1287
gem5::IGbEInt::recvPacket
virtual bool recvPacket(EthPacketPtr pkt)
Definition: i8254xGBe.hh:516
gem5::IGbE::TxDescCache::pktDone
bool pktDone
Definition: i8254xGBe.hh:383
gem5::IGbE::DescCache::descUnused
unsigned descUnused() const
Definition: i8254xGBe.hh:288
gem5::IGbE::eeAddrBits
int eeAddrBits
Definition: i8254xGBe.hh:69
gem5::IGbE::TxDescCache::completionAddress
Addr completionAddress
Definition: i8254xGBe.hh:387
gem5::IGbE::TxDescCache::hasOutstandingEvents
bool hasOutstandingEvents() override
Definition: i8254xGBe.cc:1994
gem5::IGbE::restartClock
void restartClock()
This function is used to restart the clock so it can handle things like draining and resume in one pl...
Definition: i8254xGBe.cc:2004
gem5::IGbE::macAddr
uint64_t macAddr
Definition: i8254xGBe.hh:140
gem5::Serializable
Basic support for object serialization.
Definition: serialize.hh:169
gem5::IGbE::TxDescCache::tsoUsedLen
Addr tsoUsedLen
Definition: i8254xGBe.hh:397
gem5::IGbE::txStateMachine
void txStateMachine()
Definition: i8254xGBe.cc:2064
gem5::IGbE::fetchCompDelay
Tick fetchCompDelay
Definition: i8254xGBe.hh:93
gem5::DrainState
DrainState
Object drain/handover states.
Definition: drain.hh:74
gem5::igbreg::IntTypes
IntTypes
Definition: i8254xGBe_defs.hh:174
gem5::IGbE::txDescCache
TxDescCache txDescCache
Definition: i8254xGBe.hh:476
gem5::IGbE::DescCache::wbEvent
EventFunctionWrapper wbEvent
Definition: i8254xGBe.hh:266
gem5::IGbE::tadvEvent
EventFunctionWrapper tadvEvent
Definition: i8254xGBe.hh:124
gem5::IGbE::RxDescCache::descBase
Addr descBase() const override
Definition: i8254xGBe.hh:308
gem5::IGbE::eeOpcode
uint8_t eeOpcode
Definition: i8254xGBe.hh:70
gem5::IGbE::TxDescCache::nullCallback
void nullCallback()
Definition: i8254xGBe.hh:465
gem5::IGbE::TxDescCache::tsoLoadedHeader
bool tsoLoadedHeader
Definition: i8254xGBe.hh:400
gem5::IGbE::DescCache::igbe
IGbE * igbe
Definition: i8254xGBe.hh:201
gem5::IGbE::txPacket
EthPacketPtr txPacket
Definition: i8254xGBe.hh:78
gem5::IGbE::TxDescCache::pktEvent
EventFunctionWrapper pktEvent
Definition: i8254xGBe.hh:449
gem5::EthPacketPtr
std::shared_ptr< EthPacketData > EthPacketPtr
Definition: etherpkt.hh:90
gem5::IGbE::RxDescCache::fetchAfterWb
void fetchAfterWb() override
Definition: i8254xGBe.hh:314
gem5::SimObject::params
const Params & params() const
Definition: sim_object.hh:176
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::IGbE::DescCache::size
int size
Definition: i8254xGBe.hh:210
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::ArmISA::d
Bitfield< 9 > d
Definition: misc_types.hh:63
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::IGbE::TxDescCache::TxDescCache
TxDescCache(IGbE *i, std::string n, int s)
Definition: i8254xGBe.cc:1497
gem5::IGbE::txFifoTick
bool txFifoTick
Definition: i8254xGBe.hh:84
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::IGbE::lastInterrupt
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Definition: i8254xGBe_defs.hh:696
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Definition: i8254xGBe.hh:349
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Definition: i8254xGBe.cc:1477
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Definition: i8254xGBe.hh:310
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Definition: i8254xGBe.cc:358
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Definition: i8254xGBe.hh:373
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Definition: i8254xGBe.hh:399
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Definition: i8254xGBe.hh:234
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Definition: i8254xGBe.hh:233
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Definition: i8254xGBe.cc:989
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Definition: i8254xGBe.cc:137
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Definition: types.hh:147
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Definition: i8254xGBe.hh:388
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Definition: i8254xGBe.hh:512
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Definition: i8254xGBe.hh:444
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Definition: i8254xGBe.hh:133
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Definition: eventq.hh:1115
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Serialize an object.
Definition: i8254xGBe.cc:1917
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Definition: i8254xGBe.hh:198
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Definition: i8254xGBe.hh:93
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Definition: i8254xGBe.hh:305
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Definition: i8254xGBe.cc:2048
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Definition: i8254xGBe.cc:1985
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Definition: i8254xGBe.hh:114
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Definition: i8254xGBe.hh:82
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Definition: i8254xGBe_defs.hh:183
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Definition: i8254xGBe.hh:70
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Definition: i8254xGBe.hh:193
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Definition: i8254xGBe.hh:239
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Definition: port.hh:61
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Definition: i8254xGBe.hh:89
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Definition: i8254xGBe.cc:1518
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Definition: misc_types.hh:455
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Definition: i8254xGBe.cc:2289
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Definition: i8254xGBe.hh:272
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virtual long descHead() const =0
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Definition: i8254xGBe.hh:312
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Definition: i8254xGBe.hh:402
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Definition: i8254xGBe.hh:92
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Definition: i8254xGBe_defs.hh:604
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Definition: i8254xGBe.cc:1056
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Definition: i8254xGBe.hh:385
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Definition: i8254xGBe.hh:194
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Send an interrupt to the cpu.
Definition: i8254xGBe.cc:728
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TDT tdt
Definition: i8254xGBe_defs.hh:714
gem5::igbreg::Regs
Definition: i8254xGBe_defs.hh:313
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Definition: i8254xGBe.hh:195
pktfifo.hh
etherpkt.hh
gem5::IGbE::TxDescCache::getPacketSize
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Tell the cache to DMA a packet from main memory into its buffer and return the size the of the packet...
Definition: i8254xGBe.cc:1618
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void ethTxDone()
Definition: i8254xGBe.cc:2346
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std::string annSmFetch
Annotate sm.
Definition: i8254xGBe.hh:233
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Definition: i8254xGBe.hh:233
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Definition: serialize.hh:66
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Definition: i8254xGBe.hh:376
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Definition: i8254xGBe.hh:197
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Definition: i8254xGBe.hh:71
etherdevice.hh
trace.hh
gem5::IGbE::tidvProcess
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Definition: i8254xGBe.hh:127
gem5::IGbE::RxDescCache::packetDone
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Check if the dma on the packet has completed and RX state machine can continue.
Definition: i8254xGBe.cc:1458
gem5::IGbE::radvProcess
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Definition: i8254xGBe.hh:107
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@ Running
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Definition: pktfifo.hh:79
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Definition: i8254xGBe.hh:394
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Definition: device.hh:359
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Definition: i8254xGBe.hh:169
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Definition: i8254xGBe.cc:2154
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Unserialize an object.
Definition: i8254xGBe.cc:1108
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virtual void sendDone()
Definition: i8254xGBe.hh:517
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gem5::IGbE::tickEvent
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Definition: i8254xGBe.hh:137
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
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virtual void enableSm()=0
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RDT rdt
Definition: i8254xGBe_defs.hh:633
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Definition: i8254xGBe.hh:364
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void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: i8254xGBe.cc:1073
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EventFunctionWrapper pktDataEvent
Definition: i8254xGBe.hh:355
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long descTail() const override
Definition: i8254xGBe.hh:311
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Definition: i8254xGBe.cc:1147
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int wbOut
Definition: i8254xGBe.hh:216
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Definition: i8254xGBe.hh:398
gem5::IGbE::txFifo
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Definition: i8254xGBe.hh:75
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Definition: i8254xGBe.hh:97
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Definition: i8254xGBe.hh:104
gem5::IGbE::DescCache::descTail
virtual long descTail() const =0
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bool scheduled() const
Determine if the current event is scheduled.
Definition: eventq.hh:465
gem5::IGbE::RxDescCache::pktDone
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Definition: i8254xGBe.hh:319
gem5::IGbE::TxDescCache::headerComplete
void headerComplete()
Definition: i8254xGBe.cc:1593
gem5::IGbE::RxDescCache::writePacket
int writePacket(EthPacketPtr packet, int pkt_offset)
Write the given packet into the buffer(s) pointed to by the descriptor and update the book keeping.
Definition: i8254xGBe.cc:1179
gem5::IGbE::DescCache::actionAfterWb
virtual void actionAfterWb()
Definition: i8254xGBe.hh:190
gem5::IGbE::DescCache::fetchDescriptors
void fetchDescriptors()
Fetch a chunk of descriptors into the descriptor cache.
Definition: i8254xGBe.cc:930
gem5::IGbE::TxDescCache::packetWaiting
bool packetWaiting()
Ask if we are still waiting for the packet to be transfered.
Definition: i8254xGBe.hh:436
gem5::IGbE::eeDataBits
int eeDataBits
Definition: i8254xGBe.hh:69
gem5::IGbE::txTick
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Definition: i8254xGBe.hh:83
gem5::IGbE::rxFifo
PacketFifo rxFifo
Definition: i8254xGBe.hh:74
gem5::IGbE::TxDescCache::tsoPkts
int tsoPkts
Definition: i8254xGBe.hh:405
gem5::igbreg::Regs::rdba
RDBA rdba
Definition: i8254xGBe_defs.hh:596
i8254xGBe_defs.hh
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gem5::IGbE::TxDescCache::isTcp
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Definition: i8254xGBe.hh:384
gem5::sim_clock::as_int::ns
Tick ns
nanosecond
Definition: core.cc:71

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