#include <i8254xGBe.hh>

Inheritance diagram for gem5::IGbE:

Classes
class	DescCache

class	RxDescCache

class	TxDescCache

Public Member Functions
	PARAMS (IGbE)

	IGbE (const Params &params)

	~IGbE ()

void	init () override
	init() is called after all C++ SimObjects have been created and all ports are connected.

Port &	getPort (const std::string &if_name, PortID idx=InvalidPortID) override
	Get a port with a given name and index.

Tick	read (PacketPtr pkt) override
	Pure virtual function that the device must implement.

Tick	write (PacketPtr pkt) override
	Pure virtual function that the device must implement.

Tick	writeConfig (PacketPtr pkt) override
	Write to the PCI config space data that is stored locally.

bool	ethRxPkt (EthPacketPtr packet)

void	ethTxDone ()

void	serialize (CheckpointOut &cp) const override
	Serialize an object.

void	unserialize (CheckpointIn &cp) override
	Unserialize an object.

DrainState	drain () override
	Draining is the process of clearing out the states of SimObjects.These are the SimObjects that are partially executed or are partially in flight.

void	drainResume () override
	Resume execution after a successful drain.

Public Member Functions inherited from gem5::EtherDevice
	EtherDevice (const Params &params)

Public Member Functions inherited from gem5::PciDevice
virtual Tick	readConfig (PacketPtr pkt)
	Read from the PCI config space data that is stored locally.

Addr	pciToDma (Addr pci_addr) const

void	intrPost ()

void	intrClear ()

uint8_t	interruptLine () const

AddrRangeList	getAddrRanges () const override
	Determine the address ranges that this device responds to.

	PciDevice (const PciDeviceParams &params)
	Constructor for PCI Dev.

void	serialize (CheckpointOut &cp) const override
	Serialize this object to the given output stream.

void	unserialize (CheckpointIn &cp) override
	Reconstruct the state of this object from a checkpoint.

const PciBusAddr &	busAddr () const

Public Member Functions inherited from gem5::DmaDevice
	DmaDevice (const Params &p)

virtual	~DmaDevice ()=default

void	dmaWrite (Addr addr, int size, Event event, uint8_t data, uint32_t sid, uint32_t ssid, Tick delay=0)

void	dmaWrite (Addr addr, int size, Event event, uint8_t data, Tick delay=0)

void	dmaRead (Addr addr, int size, Event event, uint8_t data, uint32_t sid, uint32_t ssid, Tick delay=0)

void	dmaRead (Addr addr, int size, Event event, uint8_t data, Tick delay=0)

bool	dmaPending () const

Addr	cacheBlockSize () const

Public Member Functions inherited from gem5::PioDevice
	PioDevice (const Params &p)

virtual	~PioDevice ()

void	init () override
	init() is called after all C++ SimObjects have been created and all ports are connected.

Port &	getPort (const std::string &if_name, PortID idx=InvalidPortID) override
	Get a port with a given name and index.

Public Member Functions inherited from gem5::ClockedObject
	ClockedObject (const ClockedObjectParams &p)

Public Member Functions inherited from gem5::SimObject
const Params &	params () const

	SimObject (const Params &p)

virtual	~SimObject ()

virtual void	loadState (CheckpointIn &cp)
	loadState() is called on each SimObject when restoring from a checkpoint.

virtual void	initState ()
	initState() is called on each SimObject when not restoring from a checkpoint.

virtual void	regProbePoints ()
	Register probe points for this object.

virtual void	regProbeListeners ()
	Register probe listeners for this object.

ProbeManager *	getProbeManager ()
	Get the probe manager for this object.

virtual void	startup ()
	startup() is the final initialization call before simulation.

DrainState	drain () override
	Provide a default implementation of the drain interface for objects that don't need draining.

virtual void	memWriteback ()
	Write back dirty buffers to memory using functional writes.

virtual void	memInvalidate ()
	Invalidate the contents of memory buffers.

void	serialize (CheckpointOut &cp) const override
	Serialize an object.

void	unserialize (CheckpointIn &cp) override
	Unserialize an object.

Public Member Functions inherited from gem5::EventManager
EventQueue *	eventQueue () const

void	schedule (Event &event, Tick when)

void	deschedule (Event &event)

void	reschedule (Event &event, Tick when, bool always=false)

void	schedule (Event *event, Tick when)

void	deschedule (Event *event)

void	reschedule (Event *event, Tick when, bool always=false)

void	wakeupEventQueue (Tick when=(Tick) -1)
	This function is not needed by the usual gem5 event loop but may be necessary in derived EventQueues which host gem5 on other schedulers.

void	setCurTick (Tick newVal)

	EventManager (EventManager &em)
	Event manger manages events in the event queue.

	EventManager (EventManager *em)

	EventManager (EventQueue *eq)

Public Member Functions inherited from gem5::Serializable
	Serializable ()

virtual	~Serializable ()

void	serializeSection (CheckpointOut &cp, const char *name) const
	Serialize an object into a new section.

void	serializeSection (CheckpointOut &cp, const std::string &name) const

void	unserializeSection (CheckpointIn &cp, const char *name)
	Unserialize an a child object.

void	unserializeSection (CheckpointIn &cp, const std::string &name)

Public Member Functions inherited from gem5::Drainable
DrainState	drainState () const
	Return the current drain state of an object.

virtual void	notifyFork ()
	Notify a child process of a fork.

Public Member Functions inherited from gem5::statistics::Group
	Group (Group parent, const char name=nullptr)
	Construct a new statistics group.

virtual	~Group ()

virtual void	regStats ()
	Callback to set stat parameters.

virtual void	resetStats ()
	Callback to reset stats.

virtual void	preDumpStats ()
	Callback before stats are dumped.

void	addStat (statistics::Info *info)
	Register a stat with this group.

const std::map< std::string, Group * > &	getStatGroups () const
	Get all child groups associated with this object.

const std::vector< Info * > &	getStats () const
	Get all stats associated with this object.

void	addStatGroup (const char name, Group block)
	Add a stat block as a child of this block.

const Info *	resolveStat (std::string name) const
	Resolve a stat by its name within this group.

void	mergeStatGroup (Group *block)
	Merge the contents (stats & children) of a block to this block.

	Group ()=delete

	Group (const Group &)=delete

Group &	operator= (const Group &)=delete

Public Member Functions inherited from gem5::Named
	Named (const std::string &name_)

virtual	~Named ()=default

virtual std::string	name () const

Public Member Functions inherited from gem5::Clocked
void	updateClockPeriod ()
	Update the tick to the current tick.

Tick	clockEdge (Cycles cycles=Cycles(0)) const
	Determine the tick when a cycle begins, by default the current one, but the argument also enables the caller to determine a future cycle.

Cycles	curCycle () const
	Determine the current cycle, corresponding to a tick aligned to a clock edge.

Tick	nextCycle () const
	Based on the clock of the object, determine the start tick of the first cycle that is at least one cycle in the future.

uint64_t	frequency () const

Tick	clockPeriod () const

double	voltage () const

Cycles	ticksToCycles (Tick t) const

Tick	cyclesToTicks (Cycles c) const

Public Attributes
Tick	lastInterrupt

Public Attributes inherited from gem5::ClockedObject
PowerState *	powerState

Private Member Functions
void	rdtrProcess ()

void	radvProcess ()

void	tadvProcess ()

void	tidvProcess ()

void	tick ()

void	rxStateMachine ()

void	txStateMachine ()

void	txWire ()

void	postInterrupt (igbreg::IntTypes t, bool now=false)
	Write an interrupt into the interrupt pending register and check mask and interrupt limit timer before sending interrupt to CPU.

void	chkInterrupt ()
	Check and see if changes to the mask register have caused an interrupt to need to be sent or perhaps removed an interrupt cause.

void	delayIntEvent ()
	Send an interrupt to the cpu.

void	cpuPostInt ()

void	cpuClearInt ()
	Clear the interupt line to the cpu.

Tick	intClock ()

void	restartClock ()
	This function is used to restart the clock so it can handle things like draining and resume in one place.

void	checkDrain ()
	Check if all the draining things that need to occur have occured and handle the drain event if so.

Private Attributes
IGbEInt *	etherInt

igbreg::Regs	regs

int	eeOpBits

int	eeAddrBits

int	eeDataBits

uint8_t	eeOpcode

uint8_t	eeAddr

uint16_t	flash [igbreg::EEPROM_SIZE]

PacketFifo	rxFifo

PacketFifo	txFifo

EthPacketPtr	txPacket

bool	inTick

bool	rxTick

bool	txTick

bool	txFifoTick

bool	rxDmaPacket

unsigned	pktOffset

Tick	fetchDelay

Tick	wbDelay

Tick	fetchCompDelay

Tick	wbCompDelay

Tick	rxWriteDelay

Tick	txReadDelay

EventFunctionWrapper	rdtrEvent

EventFunctionWrapper	radvEvent

EventFunctionWrapper	tadvEvent

EventFunctionWrapper	tidvEvent

EventFunctionWrapper	tickEvent

uint64_t	macAddr

EventFunctionWrapper	interEvent

RxDescCache	rxDescCache

TxDescCache	txDescCache

Friends
class	RxDescCache

class	TxDescCache

Additional Inherited Members
Public Types inherited from gem5::EtherDevice
using	Params = EtherDeviceParams

Public Types inherited from gem5::DmaDevice
typedef DmaDeviceParams	Params

Public Types inherited from gem5::PioDevice
using	Params = PioDeviceParams

Public Types inherited from gem5::ClockedObject
using	Params = ClockedObjectParams
	Parameters of ClockedObject.

Public Types inherited from gem5::SimObject
typedef SimObjectParams	Params

Static Public Member Functions inherited from gem5::SimObject
static void	serializeAll (const std::string &cpt_dir)
	Create a checkpoint by serializing all SimObjects in the system.

static SimObject *	find (const char *name)
	Find the SimObject with the given name and return a pointer to it.

static void	setSimObjectResolver (SimObjectResolver *resolver)
	There is a single object name resolver, and it is only set when simulation is restoring from checkpoints.

static SimObjectResolver *	getSimObjectResolver ()
	There is a single object name resolver, and it is only set when simulation is restoring from checkpoints.

Static Public Member Functions inherited from gem5::Serializable
static const std::string &	currentSection ()
	Gets the fully-qualified name of the active section.

static void	generateCheckpointOut (const std::string &cpt_dir, std::ofstream &outstream)
	Generate a checkpoint file so that the serialization can be routed to it.

Protected Member Functions inherited from gem5::PciDevice
bool	getBAR (Addr addr, int &num, Addr &offs)
	Which base address register (if any) maps the given address?

Protected Member Functions inherited from gem5::Drainable
	Drainable ()

virtual	~Drainable ()

void	signalDrainDone () const
	Signal that an object is drained.

Protected Member Functions inherited from gem5::Clocked
	Clocked (ClockDomain &clk_domain)
	Create a clocked object and set the clock domain based on the parameters.

	Clocked (Clocked &)=delete

Clocked &	operator= (Clocked &)=delete

virtual	~Clocked ()
	Virtual destructor due to inheritance.

void	resetClock () const
	Reset the object's clock using the current global tick value.

virtual void	clockPeriodUpdated ()
	A hook subclasses can implement so they can do any extra work that's needed when the clock rate is changed.

Protected Attributes inherited from gem5::EtherDevice
gem5::EtherDevice::EtherDeviceStats	etherDeviceStats

Protected Attributes inherited from gem5::PciDevice
const PciBusAddr	_busAddr

PCIConfig	config
	The current config space.

std::vector< MSIXTable >	msix_table
	MSIX Table and PBA Structures.

std::vector< MSIXPbaEntry >	msix_pba

std::array< PciBar *, 6 >	BARs {}

PciHost::DeviceInterface	hostInterface

Tick	pioDelay

Tick	configDelay

const int	PMCAP_BASE
	The capability list structures and base addresses.

const int	PMCAP_ID_OFFSET

const int	PMCAP_PC_OFFSET

const int	PMCAP_PMCS_OFFSET

PMCAP	pmcap

const int	MSICAP_BASE

MSICAP	msicap

const int	MSIXCAP_BASE

const int	MSIXCAP_ID_OFFSET

const int	MSIXCAP_MXC_OFFSET

const int	MSIXCAP_MTAB_OFFSET

const int	MSIXCAP_MPBA_OFFSET

int	MSIX_TABLE_OFFSET

int	MSIX_TABLE_END

int	MSIX_PBA_OFFSET

int	MSIX_PBA_END

MSIXCAP	msixcap

const int	PXCAP_BASE

PXCAP	pxcap

Protected Attributes inherited from gem5::DmaDevice
DmaPort	dmaPort

Protected Attributes inherited from gem5::PioDevice
System *	sys

PioPort< PioDevice >	pioPort
	The pioPort that handles the requests for us and provides us requests that it sees.

Protected Attributes inherited from gem5::SimObject
const SimObjectParams &	_params
	Cached copy of the object parameters.

Protected Attributes inherited from gem5::EventManager
EventQueue *	eventq
	A pointer to this object's event queue.

Detailed Description

Definition at line 60 of file i8254xGBe.hh.

Constructor & Destructor Documentation

◆ IGbE()

gem5::IGbE::IGbE ( const Params & params )

Definition at line 61 of file i8254xGBe.cc.

References rdtrProcess().

◆ ~IGbE()

gem5::IGbE::~IGbE ( )

Definition at line 131 of file i8254xGBe.cc.

References etherInt.

Member Function Documentation

◆ checkDrain()

void gem5::IGbE::checkDrain ( )

private

Check if all the draining things that need to occur have occured and handle the drain event if so.

Definition at line 2049 of file i8254xGBe.cc.

References DPRINTF, gem5::Draining, gem5::Drainable::drainState(), gem5::IGbE::RxDescCache::hasOutstandingEvents(), gem5::IGbE::TxDescCache::hasOutstandingEvents(), rxDescCache, rxTick, gem5::Drainable::signalDrainDone(), txDescCache, txFifoTick, and txTick.

◆ chkInterrupt()

void gem5::IGbE::chkInterrupt ( )

private

Check and see if changes to the mask register have caused an interrupt to need to be sent or perhaps removed an interrupt cause.

Definition at line 792 of file i8254xGBe.cc.

References cpuClearInt(), cpuPostInt(), gem5::curTick(), gem5::EventManager::deschedule(), DPRINTF, gem5::igbreg::Regs::icr, gem5::igbreg::Regs::imr, interEvent, gem5::igbreg::Regs::itr, gem5::sim_clock::as_int::ns, regs, gem5::EventManager::schedule(), gem5::Event::scheduled(), and gem5::ArmISA::t.

Referenced by read(), and write().

◆ cpuClearInt()

void gem5::IGbE::cpuClearInt ( )

private

Clear the interupt line to the cpu.

Definition at line 780 of file i8254xGBe.cc.

References DPRINTF, gem5::igbreg::Regs::icr, gem5::PciDevice::intrClear(), and regs.

Referenced by chkInterrupt().

◆ cpuPostInt()

void gem5::IGbE::cpuPostInt ( )

private

Definition at line 736 of file i8254xGBe.cc.

References gem5::curTick(), gem5::EventManager::deschedule(), DPRINTF, gem5::EtherDevice::etherDeviceStats, gem5::igbreg::Regs::icr, gem5::igbreg::Regs::imr, interEvent, gem5::PciDevice::intrPost(), lastInterrupt, gem5::EtherDevice::EtherDeviceStats::postedInterrupts, radvEvent, rdtrEvent, regs, gem5::Event::scheduled(), tadvEvent, and tidvEvent.

Referenced by chkInterrupt(), delayIntEvent(), and postInterrupt().

◆ delayIntEvent()

void gem5::IGbE::delayIntEvent ( )

private

Send an interrupt to the cpu.

Definition at line 729 of file i8254xGBe.cc.

References cpuPostInt().

◆ drain()

DrainState gem5::IGbE::drain ( )

overridevirtual

Draining is the process of clearing out the states of SimObjects.These are the SimObjects that are partially executed or are partially in flight.

Draining is mostly used before forking and creating a check point.

This function notifies an object that it needs to drain its state.

If the object does not need further simulation to drain internal buffers, it returns DrainState::Drained and automatically switches to the Drained state. If the object needs more simulation, it returns DrainState::Draining and automatically enters the Draining state. Other return values are invalid.

Note: An object that has entered the Drained state can be disturbed by other objects in the system and consequently stop being drained. These perturbations are not visible in the drain state. The simulator therefore repeats the draining process until all objects return DrainState::Drained on the first call to drain().

Returns: DrainState::Drained if the object is drained at this point in time, DrainState::Draining if it needs further simulation.

Implements gem5::Drainable.

Definition at line 2013 of file i8254xGBe.cc.

References gem5::X86ISA::count, gem5::EventManager::deschedule(), DPRINTF, gem5::Drained, gem5::Draining, gem5::IGbE::RxDescCache::hasOutstandingEvents(), gem5::IGbE::TxDescCache::hasOutstandingEvents(), rxDescCache, rxTick, gem5::Event::scheduled(), tickEvent, txDescCache, txFifoTick, and txTick.

◆ drainResume()

void gem5::IGbE::drainResume ( )

overridevirtual

Resume execution after a successful drain.

Reimplemented from gem5::Drainable.

Definition at line 2036 of file i8254xGBe.cc.

References DPRINTF, gem5::Drainable::drainResume(), restartClock(), rxTick, txFifoTick, and txTick.

◆ ethRxPkt()

bool gem5::IGbE::ethRxPkt ( EthPacketPtr packet )

Definition at line 2155 of file i8254xGBe.cc.

References DPRINTF, gem5::Draining, gem5::Drainable::drainState(), gem5::EtherDevice::etherDeviceStats, gem5::igbreg::IT_RXO, postInterrupt(), gem5::PacketFifo::push(), gem5::igbreg::Regs::rctl, regs, restartClock(), gem5::EtherDevice::EtherDeviceStats::rxBytes, rxFifo, gem5::EtherDevice::EtherDeviceStats::rxPackets, rxTick, gem5::Event::scheduled(), tickEvent, and txTick.

Referenced by gem5::IGbEInt::recvPacket().

◆ ethTxDone()

void gem5::IGbE::ethTxDone ( )

Definition at line 2347 of file i8254xGBe.cc.

References gem5::IGbE::DescCache< T >::descLeft(), DPRINTF, gem5::Draining, gem5::Drainable::drainState(), inTick, restartClock(), txDescCache, txFifoTick, and txTick.

Referenced by gem5::IGbEInt::sendDone().

◆ getPort()

Port & gem5::IGbE::getPort	(	const std::string &	if_name,
		PortID	idx = InvalidPortID )

overridevirtual

Get a port with a given name and index.

This is used at binding time and returns a reference to a protocol-agnostic port.

gem5 has a request and response port interface. All memory objects are connected together via ports. These ports provide a rigid interface between these memory objects. These ports implement three different memory system modes: timing, atomic, and functional. The most important mode is the timing mode and here timing mode is used for conducting cycle-level timing experiments. The other modes are only used in special circumstances and should not be used to conduct cycle-level timing experiments. The other modes are only used in special circumstances. These ports allow SimObjects to communicate with each other.

Parameters

if_name	Port name
idx	Index in the case of a VectorPort

Returns: A reference to the given port

Reimplemented from gem5::DmaDevice.

Definition at line 143 of file i8254xGBe.cc.

References etherInt, and gem5::DmaDevice::getPort().

◆ init()

void gem5::IGbE::init ( )

overridevirtual

init() is called after all C++ SimObjects have been created and all ports are connected.

Initializations that are independent of unserialization but rely on a fully instantiated and connected SimObject graph should be done here.

Reimplemented from gem5::DmaDevice.

Definition at line 137 of file i8254xGBe.cc.

References gem5::DmaDevice::init().

◆ intClock()

Tick gem5::IGbE::intClock ( )

inlineprivate

Definition at line 169 of file i8254xGBe.hh.

References gem5::sim_clock::as_int::ns.

◆ PARAMS()

gem5::IGbE::PARAMS ( IGbE )

◆ postInterrupt()

void gem5::IGbE::postInterrupt	(	igbreg::IntTypes	t,
		bool	now = false )

private

Write an interrupt into the interrupt pending register and check mask and interrupt limit timer before sending interrupt to CPU.

Parameters

t	the type of interrupt we are posting
now	should we ignore the interrupt limiting timer

Definition at line 696 of file i8254xGBe.cc.

References cpuPostInt(), gem5::curTick(), gem5::EventManager::deschedule(), DPRINTF, gem5::igbreg::Regs::icr, interEvent, gem5::igbreg::Regs::itr, lastInterrupt, gem5::sim_clock::as_int::ns, regs, gem5::EventManager::schedule(), gem5::Event::scheduled(), and gem5::ArmISA::t.

Referenced by ethRxPkt(), radvProcess(), rdtrProcess(), rxStateMachine(), tadvProcess(), tidvProcess(), txStateMachine(), gem5::IGbE::DescCache< igbreg::RxDesc >::wbComplete(), and write().

◆ radvProcess()

void gem5::IGbE::radvProcess ( )

inlineprivate

Definition at line 107 of file i8254xGBe.hh.

References DPRINTF, gem5::igbreg::IT_RXT, postInterrupt(), rxDescCache, and gem5::IGbE::DescCache< T >::writeback().

◆ rdtrProcess()

void gem5::IGbE::rdtrProcess ( )

inlineprivate

Definition at line 97 of file i8254xGBe.hh.

References DPRINTF, gem5::igbreg::IT_RXT, postInterrupt(), rxDescCache, and gem5::IGbE::DescCache< T >::writeback().

Referenced by IGbE().

◆ read()

Tick gem5::IGbE::read ( PacketPtr pkt )

overridevirtual

Pure virtual function that the device must implement.

Called when a read command is recieved by the port.

Parameters

pkt	Packet describing this request

Returns: number of ticks it took to complete

Implements gem5::PioDevice.

Definition at line 170 of file i8254xGBe.cc.

◆ restartClock()

void gem5::IGbE::restartClock ( )

private

This function is used to restart the clock so it can handle things like draining and resume in one place.

Definition at line 2005 of file i8254xGBe.cc.

References gem5::Clocked::clockEdge(), gem5::Drainable::drainState(), gem5::Running, rxTick, gem5::EventManager::schedule(), gem5::Event::scheduled(), tickEvent, txFifoTick, and txTick.

Referenced by drainResume(), ethRxPkt(), ethTxDone(), and write().

◆ rxStateMachine()

void gem5::IGbE::rxStateMachine ( )

private

◆ serialize()

void gem5::IGbE::serialize ( CheckpointOut & cp ) const

overridevirtual

Serialize an object.

Output an object's state into the current checkpoint section.

Parameters

cp	Checkpoint state

Reimplemented from gem5::ClockedObject.

Definition at line 2362 of file i8254xGBe.cc.

References eeAddr, eeAddrBits, eeDataBits, eeOpBits, eeOpcode, gem5::igbreg::EEPROM_SIZE, flash, interEvent, lastInterrupt, pktOffset, radvEvent, rdtrEvent, regs, rxDescCache, rxFifo, gem5::Event::scheduled(), gem5::igbreg::Regs::serialize(), gem5::PacketFifo::serialize(), gem5::PciDevice::serialize(), SERIALIZE_ARRAY, SERIALIZE_SCALAR, gem5::Serializable::serializeSection(), tadvEvent, tidvEvent, txDescCache, txFifo, txPacket, and gem5::Event::when().

◆ tadvProcess()

void gem5::IGbE::tadvProcess ( )

inlineprivate

Definition at line 117 of file i8254xGBe.hh.

References DPRINTF, gem5::igbreg::IT_TXDW, postInterrupt(), txDescCache, and gem5::IGbE::DescCache< T >::writeback().

◆ tick()

void gem5::IGbE::tick ( )

private

Definition at line 2319 of file i8254xGBe.cc.

References gem5::Clocked::clockPeriod(), gem5::curTick(), DPRINTF, inTick, rxStateMachine(), rxTick, gem5::EventManager::schedule(), tickEvent, txFifoTick, txStateMachine(), txTick, and txWire().

◆ tidvProcess()

void gem5::IGbE::tidvProcess ( )

inlineprivate

Definition at line 127 of file i8254xGBe.hh.

References DPRINTF, gem5::igbreg::IT_TXDW, postInterrupt(), txDescCache, and gem5::IGbE::DescCache< T >::writeback().

◆ txStateMachine()

void gem5::IGbE::txStateMachine ( )

private

Definition at line 2065 of file i8254xGBe.cc.

References gem5::PacketFifo::avail(), gem5::DmaDevice::cacheBlockSize(), gem5::IGbE::DescCache< T >::descLeft(), gem5::IGbE::DescCache< T >::descUnused(), DPRINTF, gem5::Draining, gem5::Drainable::drainState(), gem5::IGbE::DescCache< T >::fetchDescriptors(), gem5::IGbE::TxDescCache::getPacketData(), gem5::IGbE::TxDescCache::getPacketSize(), gem5::igbreg::IT_TXDLOW, gem5::igbreg::IT_TXQE, gem5::IGbE::TxDescCache::packetAvailable(), gem5::IGbE::TxDescCache::packetMultiDesc(), gem5::IGbE::TxDescCache::packetWaiting(), postInterrupt(), gem5::IGbE::TxDescCache::processContextDesc(), gem5::PacketFifo::push(), regs, gem5::PacketFifo::reserve(), gem5::igbreg::Regs::tctl, gem5::igbreg::Regs::txdctl, txDescCache, txFifo, txFifoTick, txPacket, txTick, and gem5::IGbE::DescCache< T >::writeback().

Referenced by tick().

◆ txWire()

void gem5::IGbE::txWire ( )

private

Definition at line 2290 of file i8254xGBe.cc.

References gem5::PacketFifo::avail(), DPRINTF, gem5::PacketFifo::empty(), gem5::EtherDevice::etherDeviceStats, etherInt, gem5::PacketFifo::front(), gem5::PacketFifo::pop(), gem5::EtherInt::sendPacket(), gem5::EtherDevice::EtherDeviceStats::txBytes, txFifo, txFifoTick, and gem5::EtherDevice::EtherDeviceStats::txPackets.

Referenced by tick().

◆ unserialize()

void gem5::IGbE::unserialize ( CheckpointIn & cp )

overridevirtual

Unserialize an object.

Read an object's state from the current checkpoint section.

Parameters

cp	Checkpoint state

Reimplemented from gem5::ClockedObject.

Definition at line 2413 of file i8254xGBe.cc.

References eeAddr, eeAddrBits, eeDataBits, eeOpBits, eeOpcode, gem5::igbreg::EEPROM_SIZE, flash, interEvent, lastInterrupt, pktOffset, radvEvent, rdtrEvent, regs, rxDescCache, rxFifo, rxTick, gem5::EventManager::schedule(), tadvEvent, tidvEvent, txDescCache, txFifo, txFifoTick, txPacket, txTick, gem5::igbreg::Regs::unserialize(), gem5::PacketFifo::unserialize(), gem5::PciDevice::unserialize(), UNSERIALIZE_ARRAY, UNSERIALIZE_SCALAR, and gem5::Serializable::unserializeSection().

◆ write()

Tick gem5::IGbE::write ( PacketPtr pkt )

overridevirtual

Pure virtual function that the device must implement.

Called when a write command is recieved by the port.

Parameters

pkt	Packet describing this request

Returns: number of ticks it took to complete

Implements gem5::PioDevice.

Definition at line 358 of file i8254xGBe.cc.

◆ writeConfig()

Tick gem5::IGbE::writeConfig ( PacketPtr pkt )

overridevirtual

Write to the PCI config space data that is stored locally.

This may be overridden by the device but at some point it will eventually call this for normal operations that it does not need to override.

Parameters

pkt	packet containing the write the offset into config space

Reimplemented from gem5::PciDevice.

Definition at line 151 of file i8254xGBe.cc.

References gem5::PciDevice::configDelay, gem5::Packet::getAddr(), gem5::ArmISA::offset, panic, PCI_CONFIG_SIZE, PCI_DEVICE_SPECIFIC, and gem5::PciDevice::writeConfig().

Friends And Related Symbol Documentation

◆ RxDescCache

friend class RxDescCache

friend

Definition at line 362 of file i8254xGBe.hh.

◆ TxDescCache

friend class TxDescCache

friend

Definition at line 474 of file i8254xGBe.hh.

Member Data Documentation

◆ eeAddr

uint8_t gem5::IGbE::eeAddr

private

Definition at line 70 of file i8254xGBe.hh.

Referenced by serialize(), unserialize(), and write().

◆ eeAddrBits

int gem5::IGbE::eeAddrBits

private

Definition at line 69 of file i8254xGBe.hh.

Referenced by serialize(), unserialize(), and write().

◆ eeDataBits

int gem5::IGbE::eeDataBits

private

Definition at line 69 of file i8254xGBe.hh.

Referenced by serialize(), unserialize(), and write().

◆ eeOpBits

int gem5::IGbE::eeOpBits

private

Definition at line 69 of file i8254xGBe.hh.

Referenced by serialize(), unserialize(), and write().

◆ eeOpcode

uint8_t gem5::IGbE::eeOpcode

private

Definition at line 70 of file i8254xGBe.hh.

Referenced by serialize(), unserialize(), and write().

◆ etherInt

IGbEInt* gem5::IGbE::etherInt

private

Definition at line 63 of file i8254xGBe.hh.

Referenced by getPort(), txWire(), and ~IGbE().

◆ fetchCompDelay

Tick gem5::IGbE::fetchCompDelay

private

Definition at line 93 of file i8254xGBe.hh.

◆ fetchDelay

Tick gem5::IGbE::fetchDelay

private

Definition at line 92 of file i8254xGBe.hh.

◆ flash

uint16_t gem5::IGbE::flash[igbreg::EEPROM_SIZE]

private

Definition at line 71 of file i8254xGBe.hh.

Referenced by serialize(), unserialize(), and write().

◆ interEvent

EventFunctionWrapper gem5::IGbE::interEvent

private

Definition at line 163 of file i8254xGBe.hh.

Referenced by chkInterrupt(), cpuPostInt(), postInterrupt(), serialize(), and unserialize().

◆ inTick

bool gem5::IGbE::inTick

private

Definition at line 81 of file i8254xGBe.hh.

Referenced by ethTxDone(), and tick().

◆ lastInterrupt

Tick gem5::IGbE::lastInterrupt

Definition at line 488 of file i8254xGBe.hh.

Referenced by cpuPostInt(), postInterrupt(), serialize(), and unserialize().

◆ macAddr

uint64_t gem5::IGbE::macAddr

private

Definition at line 140 of file i8254xGBe.hh.

◆ pktOffset

unsigned gem5::IGbE::pktOffset

private

Definition at line 89 of file i8254xGBe.hh.

Referenced by rxStateMachine(), serialize(), and unserialize().

◆ radvEvent

EventFunctionWrapper gem5::IGbE::radvEvent

private

Definition at line 114 of file i8254xGBe.hh.

Referenced by cpuPostInt(), serialize(), and unserialize().

◆ rdtrEvent

EventFunctionWrapper gem5::IGbE::rdtrEvent

private

Definition at line 104 of file i8254xGBe.hh.

Referenced by cpuPostInt(), serialize(), and unserialize().

◆ regs

◆ rxDescCache

RxDescCache gem5::IGbE::rxDescCache

private

Definition at line 364 of file i8254xGBe.hh.

Referenced by checkDrain(), drain(), radvProcess(), rdtrProcess(), rxStateMachine(), serialize(), unserialize(), gem5::IGbE::DescCache< igbreg::RxDesc >::wbComplete(), and write().

◆ rxDmaPacket

bool gem5::IGbE::rxDmaPacket

private

Definition at line 86 of file i8254xGBe.hh.

Referenced by rxStateMachine().

◆ rxFifo

PacketFifo gem5::IGbE::rxFifo

private

Definition at line 74 of file i8254xGBe.hh.

Referenced by ethRxPkt(), rxStateMachine(), serialize(), unserialize(), and write().

◆ rxTick

bool gem5::IGbE::rxTick

private

Definition at line 82 of file i8254xGBe.hh.

Referenced by checkDrain(), drain(), drainResume(), ethRxPkt(), gem5::IGbE::RxDescCache::fetchAfterWb(), restartClock(), rxStateMachine(), tick(), unserialize(), and write().

◆ rxWriteDelay

Tick gem5::IGbE::rxWriteDelay

private

Definition at line 94 of file i8254xGBe.hh.

◆ tadvEvent

EventFunctionWrapper gem5::IGbE::tadvEvent

private

Definition at line 124 of file i8254xGBe.hh.

Referenced by cpuPostInt(), serialize(), and unserialize().

◆ tickEvent

EventFunctionWrapper gem5::IGbE::tickEvent

private

Definition at line 137 of file i8254xGBe.hh.

Referenced by drain(), ethRxPkt(), restartClock(), and tick().

◆ tidvEvent

EventFunctionWrapper gem5::IGbE::tidvEvent

private

Definition at line 133 of file i8254xGBe.hh.

Referenced by cpuPostInt(), serialize(), and unserialize().

◆ txDescCache

TxDescCache gem5::IGbE::txDescCache

private

Definition at line 476 of file i8254xGBe.hh.

Referenced by checkDrain(), drain(), ethTxDone(), serialize(), tadvProcess(), tidvProcess(), txStateMachine(), unserialize(), and write().

◆ txFifo

PacketFifo gem5::IGbE::txFifo

private

Definition at line 75 of file i8254xGBe.hh.

Referenced by serialize(), txStateMachine(), txWire(), and unserialize().

◆ txFifoTick

bool gem5::IGbE::txFifoTick

private

Definition at line 84 of file i8254xGBe.hh.

Referenced by checkDrain(), drain(), drainResume(), ethTxDone(), restartClock(), tick(), txStateMachine(), txWire(), and unserialize().

◆ txPacket

EthPacketPtr gem5::IGbE::txPacket

private

Definition at line 78 of file i8254xGBe.hh.

Referenced by serialize(), txStateMachine(), and unserialize().

◆ txReadDelay

Tick gem5::IGbE::txReadDelay

private

Definition at line 94 of file i8254xGBe.hh.

◆ txTick

bool gem5::IGbE::txTick

private

Definition at line 83 of file i8254xGBe.hh.

Referenced by checkDrain(), drain(), drainResume(), ethRxPkt(), ethTxDone(), gem5::IGbE::TxDescCache::fetchAfterWb(), restartClock(), tick(), txStateMachine(), unserialize(), and write().

◆ wbCompDelay

Tick gem5::IGbE::wbCompDelay

private

Definition at line 93 of file i8254xGBe.hh.

◆ wbDelay

Tick gem5::IGbE::wbDelay

private

Definition at line 92 of file i8254xGBe.hh.

The documentation for this class was generated from the following files:

dev/net/i8254xGBe.hh
dev/net/i8254xGBe.cc

Classes

Public Member Functions

Public Attributes

Private Member Functions

Private Attributes

Friends

Additional Inherited Members

Detailed Description

Constructor & Destructor Documentation

◆ IGbE()

◆ ~IGbE()

Member Function Documentation

◆ checkDrain()

◆ chkInterrupt()

◆ cpuClearInt()

◆ cpuPostInt()

◆ delayIntEvent()

◆ drain()

◆ drainResume()

◆ ethRxPkt()

◆ ethTxDone()

◆ getPort()

◆ init()

◆ intClock()

◆ PARAMS()

◆ postInterrupt()

◆ radvProcess()

◆ rdtrProcess()

◆ read()

◆ restartClock()

◆ rxStateMachine()

◆ serialize()

◆ tadvProcess()

◆ tick()

◆ tidvProcess()

◆ txStateMachine()

◆ txWire()

◆ unserialize()

◆ write()

◆ writeConfig()

Friends And Related Symbol Documentation

◆ RxDescCache

◆ TxDescCache

Member Data Documentation

◆ eeAddr

◆ eeAddrBits

◆ eeDataBits

◆ eeOpBits

◆ eeOpcode

◆ etherInt

◆ fetchCompDelay

◆ fetchDelay

◆ flash

◆ interEvent

◆ inTick

◆ lastInterrupt

◆ macAddr

◆ pktOffset

◆ radvEvent

◆ rdtrEvent

◆ regs

◆ rxDescCache

◆ rxDmaPacket

◆ rxFifo

◆ rxTick

◆ rxWriteDelay

◆ tadvEvent

◆ tickEvent

◆ tidvEvent

◆ txDescCache

◆ txFifo

◆ txFifoTick

◆ txPacket

◆ txReadDelay

◆ txTick

◆ wbCompDelay

◆ wbDelay