gem5  v21.1.0.2
micro.hh
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28 
29 #ifndef __ARCH_SPARC_INSTS_MICRO_HH__
30 #define __ARCH_SPARC_INSTS_MICRO_HH__
31 
33 
34 namespace gem5
35 {
36 
37 namespace SparcISA
38 {
39 
41 {
42  protected:
43  const uint32_t numMicroops;
44 
45  // Constructor.
46  SparcMacroInst(const char *mnem, ExtMachInst _machInst,
47  OpClass __opClass, uint32_t _numMicroops) :
48  SparcStaticInst(mnem, _machInst, __opClass),
49  numMicroops(_numMicroops)
50  {
51  assert(numMicroops);
53  flags[IsMacroop] = true;
54  }
55 
57  {
58  delete [] microops;
59  }
60 
61  std::string generateDisassembly(
62  Addr pc, const loader::SymbolTable *symtab) const override;
63 
65 
67  fetchMicroop(MicroPC upc) const override
68  {
69  assert(upc < numMicroops);
70  return microops[upc];
71  }
72 
73  Fault
74  execute(ExecContext *, Trace::InstRecord *) const override
75  {
76  panic("Tried to execute a macroop directly!\n");
77  }
78 
79  Fault
81  {
82  panic("Tried to execute a macroop directly!\n");
83  }
84 
85  Fault
87  {
88  panic("Tried to execute a macroop directly!\n");
89  }
90 };
91 
93 {
94  protected:
95  // Constructor.
96  SparcMicroInst(const char *mnem, ExtMachInst _machInst,
97  OpClass __opClass) :
98  SparcStaticInst(mnem, _machInst, __opClass)
99  {
100  flags[IsMicroop] = true;
101  }
102 
103  void
104  advancePC(SparcISA::PCState &pcState) const override
105  {
106  if (flags[IsLastMicroop])
107  pcState.uEnd();
108  else
109  pcState.uAdvance();
110  }
111 };
112 
114 {
115  protected:
116  // Constructor.
117  SparcDelayedMicroInst(const char *mnem, ExtMachInst _machInst,
118  OpClass __opClass) :
119  SparcMicroInst(mnem, _machInst, __opClass)
120  {
121  flags[IsDelayedCommit] = true;
122  }
123 };
124 
125 } // namespace SparcISA
126 } // namespace gem5
127 
128 #endif // __ARCH_SPARC_INSTS_MICRO_HH__
gem5::SparcISA::SparcMicroInst::SparcMicroInst
SparcMicroInst(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
Definition: micro.hh:96
gem5::SparcISA::SparcStaticInst
Base class for all SPARC static instructions.
Definition: static_inst.hh:91
gem5::SparcISA::SparcMacroInst
Definition: micro.hh:40
gem5::SparcISA::ExtMachInst
uint64_t ExtMachInst
Definition: types.hh:42
gem5::loader::SymbolTable
Definition: symtab.hh:65
gem5::SparcISA::SparcMacroInst::microops
StaticInstPtr * microops
Definition: micro.hh:64
gem5::SparcISA::SparcMacroInst::SparcMacroInst
SparcMacroInst(const char *mnem, ExtMachInst _machInst, OpClass __opClass, uint32_t _numMicroops)
Definition: micro.hh:46
gem5::SparcISA::SparcMacroInst::execute
Fault execute(ExecContext *, Trace::InstRecord *) const override
Definition: micro.hh:74
gem5::RefCountingPtr< StaticInst >
gem5::SparcISA::SparcMacroInst::fetchMicroop
StaticInstPtr fetchMicroop(MicroPC upc) const override
Return the microop that goes with a particular micropc.
Definition: micro.hh:67
gem5::SparcISA::SparcMacroInst::numMicroops
const uint32_t numMicroops
Definition: micro.hh:43
gem5::MicroPC
uint16_t MicroPC
Definition: types.hh:149
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::SparcISA::SparcMacroInst::~SparcMacroInst
~SparcMacroInst()
Definition: micro.hh:56
gem5::GenericISA::DelaySlotUPCState::uAdvance
void uAdvance()
Definition: types.hh:425
gem5::SparcISA::SparcMacroInst::initiateAcc
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override
Definition: micro.hh:80
gem5::StaticInst::flags
std::bitset< Num_Flags > flags
Flag values for this instruction.
Definition: static_inst.hh:103
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::SparcISA::SparcDelayedMicroInst
Definition: micro.hh:113
gem5::SparcISA::SparcMicroInst
Definition: micro.hh:92
gem5::SparcISA::SparcMicroInst::advancePC
void advancePC(SparcISA::PCState &pcState) const override
Definition: micro.hh:104
static_inst.hh
gem5::GenericISA::DelaySlotUPCState
Definition: types.hh:384
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::SparcISA::SparcDelayedMicroInst::SparcDelayedMicroInst
SparcDelayedMicroInst(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
Definition: micro.hh:117
gem5::ExecContext
The ExecContext is an abstract base class the provides the interface used by the ISA to manipulate th...
Definition: exec_context.hh:73
gem5::SparcISA::SparcMacroInst::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: micro.cc:38
gem5::Trace::InstRecord
Definition: insttracer.hh:58
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::SparcISA::SparcMacroInst::completeAcc
Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const override
Definition: micro.hh:86
gem5::GenericISA::DelaySlotUPCState::uEnd
void uEnd()
Definition: types.hh:433

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