gem5
v22.0.0.1
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Derived ThreadContext class for use with the O3CPU. More...
#include <thread_context.hh>
Public Member Functions | |
bool | schedule (PCEvent *e) override |
bool | remove (PCEvent *e) override |
void | scheduleInstCountEvent (Event *event, Tick count) override |
void | descheduleInstCountEvent (Event *event) override |
Tick | getCurrentInstCount () override |
BaseMMU * | getMMUPtr () override |
Returns a pointer to the MMU. More... | |
CheckerCPU * | getCheckerCpuPtr () override |
BaseISA * | getIsaPtr () const override |
InstDecoder * | getDecoderPtr () override |
BaseCPU * | getCpuPtr () override |
Returns a pointer to this CPU. More... | |
int | cpuId () const override |
Reads this CPU's ID. More... | |
uint32_t | socketId () const override |
Reads this CPU's Socket ID. More... | |
ContextID | contextId () const override |
void | setContextId (ContextID id) override |
int | threadId () const override |
Returns this thread's ID number. More... | |
void | setThreadId (int id) override |
System * | getSystemPtr () override |
Returns a pointer to the system. More... | |
Process * | getProcessPtr () override |
Returns a pointer to this thread's process. More... | |
void | setProcessPtr (Process *p) override |
Status | status () const override |
Returns this thread's status. More... | |
void | setStatus (Status new_status) override |
Sets this thread's status. More... | |
void | activate () override |
Set the status to Active. More... | |
void | suspend () override |
Set the status to Suspended. More... | |
void | halt () override |
Set the status to Halted. More... | |
void | takeOverFrom (gem5::ThreadContext *old_context) override |
Takes over execution of a thread from another CPU. More... | |
Tick | readLastActivate () override |
Reads the last tick that this thread was activated on. More... | |
Tick | readLastSuspend () override |
Reads the last tick that this thread was suspended on. More... | |
void | copyArchRegs (gem5::ThreadContext *tc) override |
Copies the architectural registers from another TC into this TC. More... | |
void | clearArchRegs () override |
Resets all architectural registers to 0. More... | |
const PCStateBase & | pcState () const override |
Reads this thread's PC state. More... | |
void | pcState (const PCStateBase &val) override |
Sets this thread's PC state. More... | |
void | pcStateNoRecord (const PCStateBase &val) override |
RegVal | readMiscRegNoEffect (RegIndex misc_reg) const override |
Reads a miscellaneous register. More... | |
RegVal | readMiscReg (RegIndex misc_reg) override |
Reads a misc. More... | |
void | setMiscRegNoEffect (RegIndex misc_reg, RegVal val) override |
Sets a misc. More... | |
void | setMiscReg (RegIndex misc_reg, RegVal val) override |
Sets a misc. More... | |
RegId | flattenRegId (const RegId ®Id) const override |
unsigned | readStCondFailures () const override |
Returns the number of consecutive store conditional failures. More... | |
void | setStCondFailures (unsigned sc_failures) override |
Sets the number of consecutive store conditional failures. More... | |
void | conditionalSquash () |
check if the cpu is currently in state update mode and squash if not. More... | |
RegVal | getRegFlat (const RegId ®) const override |
Flat register interfaces. More... | |
void | getRegFlat (const RegId ®, void *val) const override |
void * | getWritableRegFlat (const RegId ®) override |
void | setRegFlat (const RegId ®, RegVal val) override |
void | setRegFlat (const RegId ®, const void *val) override |
void | htmAbortTransaction (uint64_t htm_uid, HtmFailureFaultCause cause) override |
BaseHTMCheckpointPtr & | getHtmCheckpointPtr () override |
void | setHtmCheckpointPtr (BaseHTMCheckpointPtr new_cpt) override |
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bool | getUseForClone () |
void | setUseForClone (bool new_val) |
virtual | ~ThreadContext () |
virtual void | sendFunctional (PacketPtr pkt) |
void | quiesce () |
Quiesce thread context. More... | |
void | quiesceTick (Tick resume) |
Quiesce, suspend, and schedule activate at resume. More... | |
virtual void | regStats (const std::string &name) |
virtual RegVal | getReg (const RegId ®) const |
virtual void | getReg (const RegId ®, void *val) const |
virtual void * | getWritableReg (const RegId ®) |
virtual void | setReg (const RegId ®, RegVal val) |
virtual void | setReg (const RegId ®, const void *val) |
RegVal | readIntReg (RegIndex reg_idx) const |
RegVal | readFloatReg (RegIndex reg_idx) const |
TheISA::VecRegContainer | readVecReg (const RegId ®) const |
TheISA::VecRegContainer & | getWritableVecReg (const RegId ®) |
RegVal | readVecElem (const RegId ®) const |
RegVal | readCCReg (RegIndex reg_idx) const |
void | setIntReg (RegIndex reg_idx, RegVal val) |
void | setFloatReg (RegIndex reg_idx, RegVal val) |
void | setVecReg (const RegId ®, const TheISA::VecRegContainer &val) |
void | setVecElem (const RegId ®, RegVal val) |
void | setCCReg (RegIndex reg_idx, RegVal val) |
void | pcState (Addr addr) |
virtual int | exit () |
RegVal | readIntRegFlat (RegIndex idx) const |
void | setIntRegFlat (RegIndex idx, RegVal val) |
RegVal | readFloatRegFlat (RegIndex idx) const |
void | setFloatRegFlat (RegIndex idx, RegVal val) |
TheISA::VecRegContainer | readVecRegFlat (RegIndex idx) const |
TheISA::VecRegContainer & | getWritableVecRegFlat (RegIndex idx) |
void | setVecRegFlat (RegIndex idx, const TheISA::VecRegContainer &val) |
RegVal | readVecElemFlat (RegIndex idx) const |
void | setVecElemFlat (RegIndex idx, RegVal val) |
RegVal | readCCRegFlat (RegIndex idx) const |
void | setCCRegFlat (RegIndex idx, RegVal val) |
Public Attributes | |
CPU * | cpu |
Pointer to the CPU. More... | |
ThreadState * | thread |
Pointer to the thread state that this TC corrseponds to. More... | |
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int | intResult = DefaultIntResult |
double | floatResult = DefaultFloatResult |
int | intOffset = 0 |
Additional Inherited Members | |
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enum | Status { Active, Suspended, Halting, Halted } |
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static void | compare (ThreadContext *one, ThreadContext *two) |
function to compare two thread contexts (for debugging) More... | |
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static const int | ints [] |
static const double | floats [] |
static const int | DefaultIntResult = 0 |
static const double | DefaultFloatResult = 0.0 |
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bool | useForClone = false |
Derived ThreadContext class for use with the O3CPU.
It provides the interface for any external objects to access a single thread's state and some general CPU state. Any time external objects try to update state through this interface, the CPU will create an event to squash all in-flight instructions in order to ensure state is maintained correctly. It must be defined specifically for the O3CPU because not all architectural state is located within the ThreadState (such as the commit PC, and registers), and specific actions must be taken when using this interface (such as squashing all in-flight instructions when doing a write to this interface).
Definition at line 68 of file thread_context.hh.
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overridevirtual |
Set the status to Active.
Implements gem5::ThreadContext.
Definition at line 70 of file thread_context.cc.
References gem5::o3::CPU::activateContext(), gem5::ThreadContext::Active, cpu, gem5::curTick(), DPRINTF, gem5::ThreadState::lastActivate, gem5::ThreadState::setStatus(), gem5::ThreadState::status(), thread, gem5::ThreadState::threadId(), and threadId().
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overridevirtual |
Resets all architectural registers to 0.
Implements gem5::ThreadContext.
Definition at line 147 of file thread_context.cc.
References cpu, gem5::o3::CPU::isa, thread, and gem5::ThreadState::threadId().
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check if the cpu is currently in state update mode and squash if not.
This function will return true if a trap is pending or if a fault or similar is currently writing to the thread context and doesn't want reset all the state (see noSquashFromTC).
Definition at line 236 of file thread_context.hh.
References cpu, gem5::o3::ThreadState::noSquashFromTC, gem5::o3::CPU::squashFromTC(), thread, gem5::ThreadState::threadId(), and gem5::o3::ThreadState::trapPending.
Referenced by htmAbortTransaction(), pcState(), pcStateNoRecord(), setMiscReg(), setMiscRegNoEffect(), and setRegFlat().
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inlineoverridevirtual |
Implements gem5::ThreadContext.
Definition at line 130 of file thread_context.hh.
References gem5::ThreadState::contextId(), and thread.
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overridevirtual |
Copies the architectural registers from another TC into this TC.
Implements gem5::ThreadContext.
Definition at line 138 of file thread_context.cc.
References gem5::BaseISA::copyRegsFrom(), getIsaPtr(), gem5::o3::ThreadState::noSquashFromTC, and thread.
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inlineoverridevirtual |
Reads this CPU's ID.
Implements gem5::ThreadContext.
Definition at line 125 of file thread_context.hh.
References cpu.
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inlineoverridevirtual |
Implements gem5::ThreadContext.
Definition at line 91 of file thread_context.hh.
References gem5::o3::ThreadState::comInstEventQueue, gem5::EventQueue::deschedule(), gem5::MipsISA::event, and thread.
Implements gem5::ThreadContext.
Definition at line 201 of file thread_context.cc.
References cpu, gem5::o3::CPU::isa, thread, and gem5::ThreadState::threadId().
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inlineoverridevirtual |
Implements gem5::ThreadContext.
Definition at line 107 of file thread_context.hh.
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inlineoverridevirtual |
Returns a pointer to this CPU.
Implements gem5::ThreadContext.
Definition at line 122 of file thread_context.hh.
References cpu.
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inlineoverridevirtual |
Implements gem5::ThreadContext.
Definition at line 96 of file thread_context.hh.
References gem5::o3::ThreadState::comInstEventQueue, gem5::EventQueue::getCurTick(), and thread.
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inlineoverridevirtual |
Implements gem5::ThreadContext.
Definition at line 116 of file thread_context.hh.
References cpu, gem5::o3::Fetch::decoder, gem5::o3::CPU::fetch, thread, and gem5::ThreadState::threadId().
Referenced by takeOverFrom().
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overridevirtual |
Implements gem5::ThreadContext.
Definition at line 233 of file thread_context.cc.
References gem5::o3::ThreadState::htmCheckpoint, and thread.
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inlineoverridevirtual |
Implements gem5::ThreadContext.
Definition at line 110 of file thread_context.hh.
References cpu, gem5::o3::CPU::isa, thread, and gem5::ThreadState::threadId().
Referenced by copyArchRegs(), and takeOverFrom().
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inlineoverridevirtual |
Returns a pointer to the MMU.
Implements gem5::ThreadContext.
Definition at line 105 of file thread_context.hh.
References cpu, and gem5::o3::CPU::mmu.
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inlineoverridevirtual |
Returns a pointer to this thread's process.
Implements gem5::ThreadContext.
Definition at line 142 of file thread_context.hh.
References gem5::ThreadState::getProcessPtr(), and thread.
Flat register interfaces.
Some architectures have different registers visible in different modes. Such architectures "flatten" a register (see flattenRegId()) to map it into the gem5 register file. This interface provides a flat interface to the underlying register file, which allows for example serialization code to access all registers.
Reimplemented from gem5::ThreadContext.
Definition at line 153 of file thread_context.cc.
References cpu, gem5::o3::CPU::getArchReg(), gem5::X86ISA::reg, thread, and gem5::ThreadState::threadId().
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overridevirtual |
Implements gem5::ThreadContext.
Definition at line 165 of file thread_context.cc.
References cpu, gem5::o3::CPU::getArchReg(), gem5::X86ISA::reg, thread, gem5::ThreadState::threadId(), and gem5::X86ISA::val.
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inlineoverridevirtual |
Returns a pointer to the system.
Implements gem5::ThreadContext.
Definition at line 139 of file thread_context.hh.
References cpu, and gem5::o3::CPU::system.
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overridevirtual |
Implements gem5::ThreadContext.
Definition at line 159 of file thread_context.cc.
References cpu, gem5::o3::CPU::getWritableArchReg(), gem5::X86ISA::reg, thread, and gem5::ThreadState::threadId().
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overridevirtual |
Set the status to Halted.
Implements gem5::ThreadContext.
Definition at line 107 of file thread_context.cc.
References gem5::o3::CPU::addThreadToExitingList(), cpu, DPRINTF, gem5::ThreadContext::Halted, gem5::ThreadContext::Halting, gem5::ThreadState::setStatus(), gem5::ThreadState::status(), thread, gem5::ThreadState::threadId(), and threadId().
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overridevirtual |
Implements gem5::ThreadContext.
Definition at line 224 of file thread_context.cc.
References conditionalSquash(), cpu, gem5::o3::CPU::htmSendAbortSignal(), thread, and gem5::ThreadState::threadId().
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inlineoverridevirtual |
Reads this thread's PC state.
Implements gem5::ThreadContext.
Definition at line 181 of file thread_context.hh.
References cpu, gem5::o3::CPU::pcState(), thread, and gem5::ThreadState::threadId().
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overridevirtual |
Sets this thread's PC state.
Implements gem5::ThreadContext.
Definition at line 185 of file thread_context.cc.
References conditionalSquash(), cpu, gem5::o3::CPU::pcState(), thread, gem5::ThreadState::threadId(), and gem5::X86ISA::val.
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overridevirtual |
Implements gem5::ThreadContext.
Definition at line 193 of file thread_context.cc.
References conditionalSquash(), cpu, gem5::o3::CPU::pcState(), thread, gem5::ThreadState::threadId(), and gem5::X86ISA::val.
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overridevirtual |
Reads the last tick that this thread was activated on.
Implements gem5::ThreadContext.
Definition at line 126 of file thread_context.cc.
References gem5::ThreadState::lastActivate, and thread.
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overridevirtual |
Reads the last tick that this thread was suspended on.
Implements gem5::ThreadContext.
Definition at line 132 of file thread_context.cc.
References gem5::ThreadState::lastSuspend, and thread.
Reads a misc.
register, including any side-effects the read might have as defined by the architecture.
Implements gem5::ThreadContext.
Definition at line 201 of file thread_context.hh.
References cpu, gem5::o3::CPU::readMiscReg(), thread, and gem5::ThreadState::threadId().
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inlineoverridevirtual |
Reads a miscellaneous register.
Implements gem5::ThreadContext.
Definition at line 193 of file thread_context.hh.
References cpu, gem5::o3::CPU::readMiscRegNoEffect(), thread, and gem5::ThreadState::threadId().
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inlineoverridevirtual |
Returns the number of consecutive store conditional failures.
Implements gem5::ThreadContext.
Definition at line 218 of file thread_context.hh.
References gem5::ThreadState::storeCondFailures, and thread.
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inlineoverridevirtual |
Implements gem5::PCEventScope.
Definition at line 80 of file thread_context.hh.
References gem5::ArmISA::e, gem5::o3::ThreadState::pcEventQueue, gem5::PCEventQueue::remove(), and thread.
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inlineoverridevirtual |
Implements gem5::PCEventScope.
Definition at line 75 of file thread_context.hh.
References gem5::ArmISA::e, gem5::o3::ThreadState::pcEventQueue, gem5::PCEventQueue::schedule(), and thread.
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inlineoverridevirtual |
Implements gem5::ThreadContext.
Definition at line 86 of file thread_context.hh.
References gem5::o3::ThreadState::comInstEventQueue, gem5::X86ISA::count, gem5::MipsISA::event, gem5::EventQueue::schedule(), and thread.
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inlineoverridevirtual |
Implements gem5::ThreadContext.
Definition at line 132 of file thread_context.hh.
References gem5::ThreadState::setContextId(), and thread.
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overridevirtual |
Implements gem5::ThreadContext.
Definition at line 239 of file thread_context.cc.
References gem5::o3::ThreadState::htmCheckpoint, and thread.
Sets a misc.
register, including any side-effects the write might have as defined by the architecture.
Implements gem5::ThreadContext.
Definition at line 215 of file thread_context.cc.
References conditionalSquash(), cpu, gem5::o3::CPU::setMiscReg(), thread, gem5::ThreadState::threadId(), and gem5::X86ISA::val.
Sets a misc.
register.
Implements gem5::ThreadContext.
Definition at line 207 of file thread_context.cc.
References conditionalSquash(), cpu, gem5::o3::CPU::setMiscRegNoEffect(), thread, gem5::ThreadState::threadId(), and gem5::X86ISA::val.
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inlineoverridevirtual |
Implements gem5::ThreadContext.
Definition at line 144 of file thread_context.hh.
References gem5::VegaISA::p, gem5::ThreadState::setProcessPtr(), and thread.
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overridevirtual |
Implements gem5::ThreadContext.
Definition at line 178 of file thread_context.cc.
References conditionalSquash(), cpu, gem5::X86ISA::reg, gem5::o3::CPU::setArchReg(), thread, gem5::ThreadState::threadId(), and gem5::X86ISA::val.
Reimplemented from gem5::ThreadContext.
Definition at line 171 of file thread_context.cc.
References conditionalSquash(), cpu, gem5::X86ISA::reg, gem5::o3::CPU::setArchReg(), thread, gem5::ThreadState::threadId(), and gem5::X86ISA::val.
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inlineoverridevirtual |
Sets this thread's status.
Implements gem5::ThreadContext.
Definition at line 151 of file thread_context.hh.
References gem5::ThreadState::setStatus(), and thread.
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inlineoverridevirtual |
Sets the number of consecutive store conditional failures.
Implements gem5::ThreadContext.
Definition at line 225 of file thread_context.hh.
References gem5::ThreadState::storeCondFailures, and thread.
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inlineoverridevirtual |
Implements gem5::ThreadContext.
Definition at line 136 of file thread_context.hh.
References gem5::ThreadState::setThreadId(), and thread.
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inlineoverridevirtual |
Reads this CPU's Socket ID.
Implements gem5::ThreadContext.
Definition at line 128 of file thread_context.hh.
References cpu.
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inlineoverridevirtual |
Returns this thread's status.
Implements gem5::ThreadContext.
Definition at line 147 of file thread_context.hh.
References gem5::ThreadState::status(), and thread.
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overridevirtual |
Set the status to Suspended.
Implements gem5::ThreadContext.
Definition at line 86 of file thread_context.cc.
References cpu, gem5::curTick(), DPRINTF, gem5::o3::CPU::isDraining(), gem5::ThreadState::lastActivate, gem5::ThreadState::lastSuspend, gem5::ThreadState::setStatus(), gem5::ThreadState::status(), gem5::o3::CPU::suspendContext(), gem5::ThreadContext::Suspended, thread, gem5::ThreadState::threadId(), and threadId().
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overridevirtual |
Takes over execution of a thread from another CPU.
Implements gem5::ThreadContext.
Definition at line 55 of file thread_context.cc.
References getDecoderPtr(), gem5::ThreadContext::getDecoderPtr(), getIsaPtr(), gem5::o3::ThreadState::noSquashFromTC, gem5::BaseISA::takeOverFrom(), gem5::InstDecoder::takeOverFrom(), gem5::takeOverFrom(), thread, and gem5::o3::ThreadState::trapPending.
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inlineoverridevirtual |
Returns this thread's ID number.
Implements gem5::ThreadContext.
Definition at line 135 of file thread_context.hh.
References thread, and gem5::ThreadState::threadId().
Referenced by activate(), halt(), and suspend().
CPU* gem5::o3::ThreadContext::cpu |
Pointer to the CPU.
Definition at line 72 of file thread_context.hh.
Referenced by activate(), clearArchRegs(), conditionalSquash(), cpuId(), flattenRegId(), getCpuPtr(), getDecoderPtr(), getIsaPtr(), getMMUPtr(), getRegFlat(), getSystemPtr(), getWritableRegFlat(), halt(), htmAbortTransaction(), pcState(), pcStateNoRecord(), readMiscReg(), readMiscRegNoEffect(), setMiscReg(), setMiscRegNoEffect(), setRegFlat(), socketId(), and suspend().
ThreadState* gem5::o3::ThreadContext::thread |
Pointer to the thread state that this TC corrseponds to.
Definition at line 102 of file thread_context.hh.
Referenced by activate(), clearArchRegs(), conditionalSquash(), contextId(), copyArchRegs(), descheduleInstCountEvent(), flattenRegId(), getCurrentInstCount(), getDecoderPtr(), getHtmCheckpointPtr(), getIsaPtr(), getProcessPtr(), getRegFlat(), getWritableRegFlat(), halt(), htmAbortTransaction(), pcState(), pcStateNoRecord(), readLastActivate(), readLastSuspend(), readMiscReg(), readMiscRegNoEffect(), readStCondFailures(), remove(), schedule(), scheduleInstCountEvent(), setContextId(), setHtmCheckpointPtr(), setMiscReg(), setMiscRegNoEffect(), setProcessPtr(), setRegFlat(), setStatus(), setStCondFailures(), setThreadId(), status(), suspend(), takeOverFrom(), and threadId().