gem5  v22.0.0.2
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gem5::o3::DynInst Class Reference

#include <dyn_inst.hh>

Inheritance diagram for gem5::o3::DynInst:
gem5::ExecContext gem5::RefCounted

Classes

struct  Arrays
 

Public Types

typedef std::list< DynInstPtr >::iterator ListIt
 

Public Member Functions

 DynInst (const Arrays &arrays, const StaticInstPtr &staticInst, const StaticInstPtr &macroop, InstSeqNum seq_num, CPU *cpu)
 BaseDynInst constructor given a binary instruction. More...
 
 DynInst (const Arrays &arrays, const StaticInstPtr &staticInst, const StaticInstPtr &macroop, const PCStateBase &pc, const PCStateBase &pred_pc, InstSeqNum seq_num, CPU *cpu)
 
 DynInst (const Arrays &arrays, const StaticInstPtr &_staticInst, const StaticInstPtr &_macroop)
 BaseDynInst constructor given a static inst pointer. More...
 
 ~DynInst ()
 
Fault execute ()
 Executes the instruction. More...
 
Fault initiateAcc ()
 Initiates the access. More...
 
Fault completeAcc (PacketPtr pkt)
 Completes the access. More...
 
BaseCPU * getCpuPtr ()
 
size_t numSrcs () const
 
size_t numDests () const
 
const RegIdflattenedDestIdx (int idx) const
 
void flattenedDestIdx (int idx, const RegId &reg_id)
 
PhysRegIdPtr renamedDestIdx (int idx) const
 
void renamedDestIdx (int idx, PhysRegIdPtr phys_reg_id)
 
PhysRegIdPtr prevDestIdx (int idx) const
 
void prevDestIdx (int idx, PhysRegIdPtr phys_reg_id)
 
PhysRegIdPtr renamedSrcIdx (int idx) const
 
void renamedSrcIdx (int idx, PhysRegIdPtr phys_reg_id)
 
bool readySrcIdx (int idx) const
 
void readySrcIdx (int idx, bool ready)
 
void recordResult (bool f)
 Records changes to result? More...
 
bool effAddrValid () const
 Is the effective virtual address valid. More...
 
void effAddrValid (bool b)
 
bool memOpDone () const
 Whether or not the memory operation is done. More...
 
void memOpDone (bool f)
 
bool notAnInst () const
 
void setNotAnInst ()
 
void demapPage (Addr vaddr, uint64_t asn) override
 Invalidate a page in the DTLB and ITLB. More...
 
Fault initiateMemRead (Addr addr, unsigned size, Request::Flags flags, const std::vector< bool > &byte_enable) override
 
Fault initiateMemMgmtCmd (Request::Flags flags) override
 Initiate a memory management command with no valid address. More...
 
Fault writeMem (uint8_t *data, unsigned size, Addr addr, Request::Flags flags, uint64_t *res, const std::vector< bool > &byte_enable) override
 
Fault initiateMemAMO (Addr addr, unsigned size, Request::Flags flags, AtomicOpFunctorPtr amo_op) override
 
bool translationStarted () const
 True if the DTB address translation has started. More...
 
void translationStarted (bool f)
 
bool translationCompleted () const
 True if the DTB address translation has completed. More...
 
void translationCompleted (bool f)
 
bool possibleLoadViolation () const
 True if this address was found to match a previous load and they issued out of order. More...
 
void possibleLoadViolation (bool f)
 
bool hitExternalSnoop () const
 True if the address hit a external snoop while sitting in the LSQ. More...
 
void hitExternalSnoop (bool f)
 
bool isTranslationDelayed () const
 Returns true if the DTB address translation is being delayed due to a hw page table walk. More...
 
void renameDestReg (int idx, PhysRegIdPtr renamed_dest, PhysRegIdPtr previous_rename)
 Renames a destination register to a physical register. More...
 
void renameSrcReg (int idx, PhysRegIdPtr renamed_src)
 Renames a source logical register to the physical register which has/will produce that logical register's result. More...
 
void dump ()
 Dumps out contents of this BaseDynInst. More...
 
void dump (std::string &outstring)
 Dumps out contents of this BaseDynInst into given string. More...
 
int cpuId () const
 Read this CPU's ID. More...
 
uint32_t socketId () const
 Read this CPU's Socket ID. More...
 
RequestorID requestorId () const
 Read this CPU's data requestor ID. More...
 
ContextID contextId () const
 Read this context's system-wide ID. More...
 
Fault getFault () const
 Returns the fault type. More...
 
FaultgetFault ()
 TODO: This I added for the LSQRequest side to be able to modify the fault. More...
 
bool doneTargCalc ()
 Checks whether or not this instruction has had its branch target calculated yet. More...
 
void setPredTarg (const PCStateBase &pred_pc)
 Set the predicted target of this current instruction. More...
 
const PCStateBasereadPredTarg ()
 
bool readPredTaken ()
 Returns whether the instruction was predicted taken or not. More...
 
void setPredTaken (bool predicted_taken)
 
bool mispredicted ()
 Returns whether the instruction mispredicted. More...
 
bool isNop () const
 
bool isMemRef () const
 
bool isLoad () const
 
bool isStore () const
 
bool isAtomic () const
 
bool isStoreConditional () const
 
bool isInstPrefetch () const
 
bool isDataPrefetch () const
 
bool isInteger () const
 
bool isFloating () const
 
bool isVector () const
 
bool isControl () const
 
bool isCall () const
 
bool isReturn () const
 
bool isDirectCtrl () const
 
bool isIndirectCtrl () const
 
bool isCondCtrl () const
 
bool isUncondCtrl () const
 
bool isSerializing () const
 
bool isSerializeBefore () const
 
bool isSerializeAfter () const
 
bool isSquashAfter () const
 
bool isFullMemBarrier () const
 
bool isReadBarrier () const
 
bool isWriteBarrier () const
 
bool isNonSpeculative () const
 
bool isQuiesce () const
 
bool isUnverifiable () const
 
bool isSyscall () const
 
bool isMacroop () const
 
bool isMicroop () const
 
bool isDelayedCommit () const
 
bool isLastMicroop () const
 
bool isFirstMicroop () const
 
bool isHtmStart () const
 
bool isHtmStop () const
 
bool isHtmCancel () const
 
bool isHtmCmd () const
 
uint64_t getHtmTransactionUid () const override
 
uint64_t newHtmTransactionUid () const override
 
bool inHtmTransactionalState () const override
 
uint64_t getHtmTransactionalDepth () const override
 
void setHtmTransactionalState (uint64_t htm_uid, uint64_t htm_depth)
 
void clearHtmTransactionalState ()
 
void setSerializeBefore ()
 Temporarily sets this instruction as a serialize before instruction. More...
 
void clearSerializeBefore ()
 Clears the serializeBefore part of this instruction. More...
 
bool isTempSerializeBefore ()
 Checks if this serializeBefore is only temporarily set. More...
 
void setSerializeAfter ()
 Temporarily sets this instruction as a serialize after instruction. More...
 
void clearSerializeAfter ()
 Clears the serializeAfter part of this instruction. More...
 
bool isTempSerializeAfter ()
 Checks if this serializeAfter is only temporarily set. More...
 
void setSerializeHandled ()
 Sets the serialization part of this instruction as handled. More...
 
bool isSerializeHandled ()
 Checks if the serialization part of this instruction has been handled. More...
 
OpClass opClass () const
 Returns the opclass of this instruction. More...
 
std::unique_ptr< PCStateBasebranchTarget () const
 Returns the branch target address. More...
 
size_t numSrcRegs () const
 Returns the number of source registers. More...
 
size_t numDestRegs () const
 Returns the number of destination registers. More...
 
size_t numDestRegs (RegClassType type) const
 
const RegIddestRegIdx (int i) const
 Returns the logical register index of the i'th destination register. More...
 
const RegIdsrcRegIdx (int i) const
 Returns the logical register index of the i'th source register. More...
 
uint8_t resultSize ()
 Return the size of the instResult queue. More...
 
InstResult popResult (InstResult dflt=InstResult())
 Pops a result off the instResult queue. More...
 
void markSrcRegReady ()
 Records that one of the source registers is ready. More...
 
void markSrcRegReady (RegIndex src_idx)
 Marks a specific register as ready. More...
 
void setCompleted ()
 Sets this instruction as completed. More...
 
bool isCompleted () const
 Returns whether or not this instruction is completed. More...
 
void setResultReady ()
 Marks the result as ready. More...
 
bool isResultReady () const
 Returns whether or not the result is ready. More...
 
void setCanIssue ()
 Sets this instruction as ready to issue. More...
 
bool readyToIssue () const
 Returns whether or not this instruction is ready to issue. More...
 
void clearCanIssue ()
 Clears this instruction being able to issue. More...
 
void setIssued ()
 Sets this instruction as issued from the IQ. More...
 
bool isIssued () const
 Returns whether or not this instruction has issued. More...
 
void clearIssued ()
 Clears this instruction as being issued. More...
 
void setExecuted ()
 Sets this instruction as executed. More...
 
bool isExecuted () const
 Returns whether or not this instruction has executed. More...
 
void setCanCommit ()
 Sets this instruction as ready to commit. More...
 
void clearCanCommit ()
 Clears this instruction as being ready to commit. More...
 
bool readyToCommit () const
 Returns whether or not this instruction is ready to commit. More...
 
void setAtCommit ()
 
bool isAtCommit ()
 
void setCommitted ()
 Sets this instruction as committed. More...
 
bool isCommitted () const
 Returns whether or not this instruction is committed. More...
 
void setSquashed ()
 Sets this instruction as squashed. More...
 
bool isSquashed () const
 Returns whether or not this instruction is squashed. More...
 
void setInIQ ()
 Sets this instruction as a entry the IQ. More...
 
void clearInIQ ()
 Sets this instruction as a entry the IQ. More...
 
bool isInIQ () const
 Returns whether or not this instruction has issued. More...
 
void setSquashedInIQ ()
 Sets this instruction as squashed in the IQ. More...
 
bool isSquashedInIQ () const
 Returns whether or not this instruction is squashed in the IQ. More...
 
void setInLSQ ()
 Sets this instruction as a entry the LSQ. More...
 
void removeInLSQ ()
 Sets this instruction as a entry the LSQ. More...
 
bool isInLSQ () const
 Returns whether or not this instruction is in the LSQ. More...
 
void setSquashedInLSQ ()
 Sets this instruction as squashed in the LSQ. More...
 
bool isSquashedInLSQ () const
 Returns whether or not this instruction is squashed in the LSQ. More...
 
void setInROB ()
 Sets this instruction as a entry the ROB. More...
 
void clearInROB ()
 Sets this instruction as a entry the ROB. More...
 
bool isInROB () const
 Returns whether or not this instruction is in the ROB. More...
 
void setSquashedInROB ()
 Sets this instruction as squashed in the ROB. More...
 
bool isSquashedInROB () const
 Returns whether or not this instruction is squashed in the ROB. More...
 
bool isPinnedRegsRenamed () const
 Returns whether pinned registers are renamed. More...
 
void setPinnedRegsRenamed ()
 Sets the destination registers as renamed. More...
 
bool isPinnedRegsWritten () const
 Returns whether destination registers are written. More...
 
void setPinnedRegsWritten ()
 Sets destination registers as written. More...
 
bool isPinnedRegsSquashDone () const
 Return whether dest registers' pinning status updated after squash. More...
 
void setPinnedRegsSquashDone ()
 Sets dest registers' status updated after squash. More...
 
const PCStateBasepcState () const override
 Read the PC state of this instruction. More...
 
void pcState (const PCStateBase &val) override
 Set the PC state of this instruction. More...
 
bool readPredicate () const override
 
void setPredicate (bool val) override
 
bool readMemAccPredicate () const override
 
void setMemAccPredicate (bool val) override
 
void setTid (ThreadID tid)
 Sets the thread id. More...
 
void setThreadState (ThreadState *state)
 Sets the pointer to the thread state. More...
 
gem5::ThreadContexttcBase () const override
 Returns the thread context. More...
 
bool strictlyOrdered () const
 Is this instruction's memory access strictly ordered? More...
 
void strictlyOrdered (bool so)
 
bool hasRequest () const
 Has this instruction generated a memory request. More...
 
void setRequest ()
 Assert this instruction has generated a memory request. More...
 
ListItgetInstListIt ()
 Returns iterator to this instruction in the list of all insts. More...
 
void setInstListIt (ListIt _instListIt)
 Sets iterator for this instruction in the list of all insts. More...
 
unsigned int readStCondFailures () const override
 Returns the number of consecutive store conditional failures. More...
 
void setStCondFailures (unsigned int sc_failures) override
 Sets the number of consecutive store conditional failures. More...
 
void armMonitor (Addr address) override
 
bool mwait (PacketPtr pkt) override
 
void mwaitAtomic (gem5::ThreadContext *tc) override
 
AddressMonitor * getAddrMonitor () override
 
RegVal readMiscReg (int misc_reg) override
 Reads a misc. More...
 
void setMiscReg (int misc_reg, RegVal val) override
 Sets a misc. More...
 
RegVal readMiscRegOperand (const StaticInst *si, int idx) override
 Reads a misc. More...
 
void setMiscRegOperand (const StaticInst *si, int idx, RegVal val) override
 Sets a misc. More...
 
void updateMiscRegs ()
 Called at the commit stage to update the misc. More...
 
void forwardOldRegs ()
 
void trap (const Fault &fault)
 Traps to handle specified fault. More...
 
RegVal getRegOperand (const StaticInst *si, int idx) override
 
void getRegOperand (const StaticInst *si, int idx, void *val) override
 
void * getWritableRegOperand (const StaticInst *si, int idx) override
 
void setRegOperand (const StaticInst *si, int idx, RegVal val) override
 
void setRegOperand (const StaticInst *si, int idx, const void *val) override
 
template<typename T >
void setResult (T &&t)
 Pushes a result onto the instResult queue. More...
 
- Public Member Functions inherited from gem5::ExecContext
virtual Fault readMem (Addr addr, uint8_t *data, unsigned int size, Request::Flags flags, const std::vector< bool > &byte_enable)
 Perform an atomic memory read operation. More...
 
virtual Fault initiateMemRead (Addr addr, unsigned int size, Request::Flags flags, const std::vector< bool > &byte_enable)
 Initiate a timing memory read operation. More...
 
virtual Fault writeMem (uint8_t *data, unsigned int size, Addr addr, Request::Flags flags, uint64_t *res, const std::vector< bool > &byte_enable)=0
 For atomic-mode contexts, perform an atomic memory write operation. More...
 
virtual Fault amoMem (Addr addr, uint8_t *data, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op)
 For atomic-mode contexts, perform an atomic AMO (a.k.a., Atomic Read-Modify-Write Memory Operation) More...
 
virtual Fault initiateMemAMO (Addr addr, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op)
 For timing-mode contexts, initiate an atomic AMO (atomic read-modify-write memory operation) More...
 
- Public Member Functions inherited from gem5::RefCounted
 RefCounted ()
 We initialize the reference count to zero and the first object to take ownership of it must increment it to one. More...
 
virtual ~RefCounted ()
 We make the destructor virtual because we're likely to have virtual functions on reference counted objects. More...
 
void incref () const
 Increment the reference count. More...
 
void decref () const
 Decrement the reference count and destroy the object if all references are gone. More...
 

Static Public Member Functions

static void * operator new (size_t count, Arrays &arrays)
 

Public Attributes

InstSeqNum seqNum = 0
 The sequence number of the instruction. More...
 
const StaticInstPtr staticInst
 The StaticInst used by this BaseDynInst. More...
 
CPUcpu = nullptr
 Pointer to the Impl's CPU object. More...
 
ThreadStatethread = nullptr
 Pointer to the thread state. More...
 
Fault fault = NoFault
 The kind of fault this instruction has generated. More...
 
Trace::InstRecordtraceData = nullptr
 InstRecord that tracks this instructions. More...
 
ThreadID threadNumber = 0
 The thread this instruction is from. More...
 
ListIt instListIt
 Iterator pointing to this BaseDynInst in the list of all insts. More...
 
std::unique_ptr< PCStateBasepredPC
 Predicted PC state after this instruction. More...
 
const StaticInstPtr macroop
 The Macroop if one exists. More...
 
uint8_t readyRegs = 0
 How many source registers are ready. More...
 
Addr effAddr = 0
 The effective virtual address (lds & stores only). More...
 
Addr physEffAddr = 0
 The effective physical address. More...
 
unsigned memReqFlags = 0
 The memory request flags (from translation). More...
 
unsigned effSize
 The size of the request. More...
 
uint8_t * memData = nullptr
 Pointer to the data for the memory access. More...
 
ssize_t lqIdx = -1
 Load queue index. More...
 
LSQUnit::LQIterator lqIt
 
ssize_t sqIdx = -1
 Store queue index. More...
 
LSQUnit::SQIterator sqIt
 
LSQ::LSQRequestsavedRequest
 Saved memory request (needed when the DTB address translation is delayed due to a hw page table walk). More...
 
RequestPtr reqToVerify
 
Tick firstIssue = -1
 
Tick lastWakeDependents = -1
 

Protected Types

enum  Status {
  IqEntry, RobEntry, LsqEntry, Completed,
  ResultReady, CanIssue, Issued, Executed,
  CanCommit, AtCommit, Committed, Squashed,
  SquashedInIQ, SquashedInLSQ, SquashedInROB, PinnedRegsRenamed,
  PinnedRegsWritten, PinnedRegsSquashDone, RecoverInst, BlockingInst,
  ThreadsyncWait, SerializeBefore, SerializeAfter, SerializeHandled,
  NumStatus
}
 
enum  Flags {
  NotAnInst, TranslationStarted, TranslationCompleted, PossibleLoadViolation,
  HitExternalSnoop, EffAddrValid, RecordResult, Predicate,
  MemAccPredicate, PredTaken, IsStrictlyOrdered, ReqMade,
  MemOpDone, HtmFromTransaction, MaxFlags
}
 

Protected Attributes

std::queue< InstResultinstResult
 The result of the instruction; assumes an instruction can have many destination registers. More...
 
std::unique_ptr< PCStateBasepc
 PC state for this instruction. More...
 
std::vector< RegVal_destMiscRegVal
 Values to be written to the destination misc. More...
 
std::vector< short > _destMiscRegIdx
 Indexes of the destination misc. More...
 
size_t _numSrcs
 
size_t _numDests
 
RegId_flatDestIdx
 
PhysRegIdPtr_destIdx
 
PhysRegIdPtr_prevDestIdx
 
PhysRegIdPtr_srcIdx
 
uint8_t * _readySrcIdx
 

Private Member Functions

 DynInst (const StaticInstPtr &staticInst, const StaticInstPtr &macroop, InstSeqNum seq_num, CPU *cpu)
 

Private Attributes

std::bitset< MaxFlagsinstFlags
 
std::bitset< NumStatusstatus
 The status of this BaseDynInst. More...
 
uint64_t htmUid = -1
 
uint64_t htmDepth = 0
 

Detailed Description

Definition at line 76 of file dyn_inst.hh.

Member Typedef Documentation

◆ ListIt

Definition at line 84 of file dyn_inst.hh.

Member Enumeration Documentation

◆ Flags

enum gem5::o3::DynInst::Flags
protected
Enumerator
NotAnInst 
TranslationStarted 
TranslationCompleted 
PossibleLoadViolation 
HitExternalSnoop 
EffAddrValid 
RecordResult 
Predicate 
MemAccPredicate 
PredTaken 
IsStrictlyOrdered 
ReqMade 
MemOpDone 
HtmFromTransaction 
MaxFlags 

Definition at line 174 of file dyn_inst.hh.

◆ Status

enum gem5::o3::DynInst::Status
protected
Enumerator
IqEntry 
RobEntry 

Instruction is in the IQ.

LsqEntry 

Instruction is in the ROB.

Completed 

Instruction is in the LSQ.

ResultReady 

Instruction has completed.

CanIssue 

Instruction has its result.

Issued 

Instruction can issue and execute.

Executed 

Instruction has issued.

CanCommit 

Instruction has executed.

AtCommit 

Instruction can commit.

Committed 

Instruction has reached commit.

Squashed 

Instruction has committed.

SquashedInIQ 

Instruction is squashed.

SquashedInLSQ 

Instruction is squashed in the IQ.

SquashedInROB 

Instruction is squashed in the LSQ.

PinnedRegsRenamed 

Instruction is squashed in the ROB.

PinnedRegsWritten 

Pinned registers are renamed.

PinnedRegsSquashDone 

Pinned registers are written back.

RecoverInst 

Regs pinning status updated after squash.

BlockingInst 

Is a recover instruction.

ThreadsyncWait 

Is a blocking instruction.

SerializeBefore 

Is a thread synchronization instruction.

SerializeAfter 

Needs to serialize on instructions ahead of it.

SerializeHandled 

Needs to serialize instructions behind it.

NumStatus 

Serialization has been handled.

Definition at line 144 of file dyn_inst.hh.

Constructor & Destructor Documentation

◆ DynInst() [1/4]

gem5::o3::DynInst::DynInst ( const StaticInstPtr staticInst,
const StaticInstPtr macroop,
InstSeqNum  seq_num,
CPU cpu 
)
private

◆ DynInst() [2/4]

gem5::o3::DynInst::DynInst ( const Arrays arrays,
const StaticInstPtr staticInst,
const StaticInstPtr macroop,
InstSeqNum  seq_num,
CPU cpu 
)

BaseDynInst constructor given a binary instruction.

Definition at line 56 of file dyn_inst.cc.

References _readySrcIdx, cpu, DPRINTF, gem5::o3::CPU::dumpInsts(), gem5::MipsISA::fill, gem5::o3::CPU::instcount, instFlags, MemAccPredicate, numSrcs(), Predicate, RecordResult, seqNum, and status.

◆ DynInst() [3/4]

gem5::o3::DynInst::DynInst ( const Arrays arrays,
const StaticInstPtr staticInst,
const StaticInstPtr macroop,
const PCStateBase pc,
const PCStateBase pred_pc,
InstSeqNum  seq_num,
CPU cpu 
)

Definition at line 95 of file dyn_inst.cc.

References pc, predPC, and gem5::ArmISA::set.

◆ DynInst() [4/4]

gem5::o3::DynInst::DynInst ( const Arrays arrays,
const StaticInstPtr _staticInst,
const StaticInstPtr _macroop 
)

BaseDynInst constructor given a static inst pointer.

Definition at line 104 of file dyn_inst.cc.

◆ ~DynInst()

gem5::o3::DynInst::~DynInst ( )

Member Function Documentation

◆ armMonitor()

void gem5::o3::DynInst::armMonitor ( Addr  address)
inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 960 of file dyn_inst.hh.

References cpu, and threadNumber.

◆ branchTarget()

std::unique_ptr<PCStateBase> gem5::o3::DynInst::branchTarget ( ) const
inline

Returns the branch target address.

Definition at line 672 of file dyn_inst.hh.

References gem5::StaticInst::branchTarget(), pc, and staticInst.

◆ clearCanCommit()

void gem5::o3::DynInst::clearCanCommit ( )
inline

Clears this instruction as being ready to commit.

Definition at line 770 of file dyn_inst.hh.

References CanCommit, and status.

◆ clearCanIssue()

void gem5::o3::DynInst::clearCanIssue ( )
inline

Clears this instruction being able to issue.

Definition at line 749 of file dyn_inst.hh.

References CanIssue, and status.

◆ clearHtmTransactionalState()

void gem5::o3::DynInst::clearHtmTransactionalState ( )
inline

◆ clearInIQ()

void gem5::o3::DynInst::clearInIQ ( )
inline

Sets this instruction as a entry the IQ.

Definition at line 797 of file dyn_inst.hh.

References IqEntry, and status.

◆ clearInROB()

void gem5::o3::DynInst::clearInROB ( )
inline

Sets this instruction as a entry the ROB.

Definition at line 833 of file dyn_inst.hh.

References RobEntry, and status.

◆ clearIssued()

void gem5::o3::DynInst::clearIssued ( )
inline

Clears this instruction as being issued.

Definition at line 758 of file dyn_inst.hh.

References Issued, and status.

◆ clearSerializeAfter()

void gem5::o3::DynInst::clearSerializeAfter ( )
inline

Clears the serializeAfter part of this instruction.

Definition at line 652 of file dyn_inst.hh.

References SerializeAfter, and status.

◆ clearSerializeBefore()

void gem5::o3::DynInst::clearSerializeBefore ( )
inline

Clears the serializeBefore part of this instruction.

Definition at line 643 of file dyn_inst.hh.

References SerializeBefore, and status.

◆ completeAcc()

Fault gem5::o3::DynInst::completeAcc ( PacketPtr  pkt)

Completes the access.

Only valid for memory operations.

Definition at line 373 of file dyn_inst.cc.

References gem5::o3::CPU::checker, gem5::StaticInst::completeAcc(), cpu, fault, isStoreConditional(), gem5::o3::ThreadState::noSquashFromTC, gem5::Packet::req, reqToVerify, staticInst, thread, and traceData.

◆ contextId()

ContextID gem5::o3::DynInst::contextId ( ) const
inline

Read this context's system-wide ID.

Definition at line 498 of file dyn_inst.hh.

References gem5::ThreadState::contextId(), and thread.

◆ cpuId()

int gem5::o3::DynInst::cpuId ( ) const
inline

Read this CPU's ID.

Definition at line 489 of file dyn_inst.hh.

References cpu.

◆ demapPage()

void gem5::o3::DynInst::demapPage ( Addr  vaddr,
uint64_t  asn 
)
inlineoverridevirtual

Invalidate a page in the DTLB and ITLB.

Implements gem5::ExecContext.

Definition at line 392 of file dyn_inst.hh.

References cpu, gem5::o3::CPU::demapPage(), and gem5::MipsISA::vaddr.

◆ destRegIdx()

const RegId& gem5::o3::DynInst::destRegIdx ( int  i) const
inline

Returns the logical register index of the i'th destination register.

Definition at line 690 of file dyn_inst.hh.

References gem5::StaticInst::destRegIdx(), gem5::ArmISA::i, and staticInst.

◆ doneTargCalc()

bool gem5::o3::DynInst::doneTargCalc ( )
inline

Checks whether or not this instruction has had its branch target calculated yet.

For now it is not utilized and is hacked to be always false.

Todo:
: Actually use this instruction.

Definition at line 511 of file dyn_inst.hh.

◆ dump() [1/2]

void gem5::o3::DynInst::dump ( )

Dumps out contents of this BaseDynInst.

Definition at line 278 of file dyn_inst.cc.

References gem5::cprintf(), gem5::StaticInst::disassemble(), pc, staticInst, and threadNumber.

◆ dump() [2/2]

void gem5::o3::DynInst::dump ( std::string &  outstring)

Dumps out contents of this BaseDynInst into given string.

Definition at line 286 of file dyn_inst.cc.

References gem5::StaticInst::disassemble(), pc, gem5::VegaISA::s, staticInst, and threadNumber.

◆ effAddrValid() [1/2]

bool gem5::o3::DynInst::effAddrValid ( ) const
inline

Is the effective virtual address valid.

Definition at line 374 of file dyn_inst.hh.

References EffAddrValid, and instFlags.

◆ effAddrValid() [2/2]

void gem5::o3::DynInst::effAddrValid ( bool  b)
inline

Definition at line 375 of file dyn_inst.hh.

References gem5::ArmISA::b, EffAddrValid, and instFlags.

◆ execute()

Fault gem5::o3::DynInst::execute ( )

Executes the instruction.

Definition at line 339 of file dyn_inst.cc.

References gem5::StaticInst::execute(), fault, gem5::o3::ThreadState::noSquashFromTC, staticInst, thread, and traceData.

◆ flattenedDestIdx() [1/2]

const RegId& gem5::o3::DynInst::flattenedDestIdx ( int  idx) const
inline

Definition at line 246 of file dyn_inst.hh.

References _flatDestIdx.

◆ flattenedDestIdx() [2/2]

void gem5::o3::DynInst::flattenedDestIdx ( int  idx,
const RegId reg_id 
)
inline

Definition at line 254 of file dyn_inst.hh.

References _flatDestIdx.

◆ forwardOldRegs()

void gem5::o3::DynInst::forwardOldRegs ( )
inline

◆ getAddrMonitor()

AddressMonitor* gem5::o3::DynInst::getAddrMonitor ( )
inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 975 of file dyn_inst.hh.

References cpu, and threadNumber.

◆ getCpuPtr()

BaseCPU* gem5::o3::DynInst::getCpuPtr ( )
inline

Definition at line 132 of file dyn_inst.hh.

References cpu.

◆ getFault() [1/2]

Fault& gem5::o3::DynInst::getFault ( )
inline

TODO: This I added for the LSQRequest side to be able to modify the fault.

There should be a better mechanism in place.

Definition at line 504 of file dyn_inst.hh.

References fault.

◆ getFault() [2/2]

Fault gem5::o3::DynInst::getFault ( ) const
inline

Returns the fault type.

Definition at line 501 of file dyn_inst.hh.

References fault.

◆ getHtmTransactionalDepth()

uint64_t gem5::o3::DynInst::getHtmTransactionalDepth ( ) const
inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 609 of file dyn_inst.hh.

References htmDepth, and inHtmTransactionalState().

◆ getHtmTransactionUid()

uint64_t gem5::o3::DynInst::getHtmTransactionUid ( ) const
inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 589 of file dyn_inst.hh.

References HtmFromTransaction, htmUid, and instFlags.

Referenced by clearHtmTransactionalState().

◆ getInstListIt()

ListIt& gem5::o3::DynInst::getInstListIt ( )
inline

Returns iterator to this instruction in the list of all insts.

Definition at line 937 of file dyn_inst.hh.

References instListIt.

◆ getRegOperand() [1/2]

RegVal gem5::o3::DynInst::getRegOperand ( const StaticInst si,
int  idx 
)
inlineoverridevirtual

◆ getRegOperand() [2/2]

void gem5::o3::DynInst::getRegOperand ( const StaticInst si,
int  idx,
void *  val 
)
inlineoverridevirtual

◆ getWritableRegOperand()

void* gem5::o3::DynInst::getWritableRegOperand ( const StaticInst si,
int  idx 
)
inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 1151 of file dyn_inst.hh.

References cpu, gem5::o3::CPU::getWritableReg(), and renamedDestIdx().

◆ hasRequest()

bool gem5::o3::DynInst::hasRequest ( ) const
inline

Has this instruction generated a memory request.

Definition at line 932 of file dyn_inst.hh.

References instFlags, and ReqMade.

◆ hitExternalSnoop() [1/2]

bool gem5::o3::DynInst::hitExternalSnoop ( ) const
inline

True if the address hit a external snoop while sitting in the LSQ.

If this is true and a older instruction sees it, this instruction must reexecute

Definition at line 441 of file dyn_inst.hh.

References HitExternalSnoop, and instFlags.

◆ hitExternalSnoop() [2/2]

void gem5::o3::DynInst::hitExternalSnoop ( bool  f)
inline

Definition at line 442 of file dyn_inst.hh.

References gem5::VegaISA::f, HitExternalSnoop, and instFlags.

◆ inHtmTransactionalState()

bool gem5::o3::DynInst::inHtmTransactionalState ( ) const
inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 603 of file dyn_inst.hh.

References HtmFromTransaction, and instFlags.

Referenced by clearHtmTransactionalState(), and getHtmTransactionalDepth().

◆ initiateAcc()

Fault gem5::o3::DynInst::initiateAcc ( )

Initiates the access.

Only valid for memory operations.

Definition at line 356 of file dyn_inst.cc.

References fault, gem5::StaticInst::initiateAcc(), gem5::o3::ThreadState::noSquashFromTC, staticInst, thread, and traceData.

◆ initiateMemAMO()

Fault gem5::o3::DynInst::initiateMemAMO ( Addr  addr,
unsigned  size,
Request::Flags  flags,
AtomicOpFunctorPtr  amo_op 
)
override

Definition at line 435 of file dyn_inst.cc.

References gem5::X86ISA::addr, cpu, flags, and gem5::o3::CPU::pushRequest().

◆ initiateMemMgmtCmd()

Fault gem5::o3::DynInst::initiateMemMgmtCmd ( Request::Flags  flags)
overridevirtual

Initiate a memory management command with no valid address.

Currently, these instructions need to bypass squashing in the O3 model Examples include HTM commands and TLBI commands. e.g. tell Ruby we're starting/stopping a HTM transaction, or tell Ruby to issue a TLBI operation

Implements gem5::ExecContext.

Definition at line 413 of file dyn_inst.cc.

References cpu, flags, and gem5::o3::CPU::pushRequest().

◆ initiateMemRead()

Fault gem5::o3::DynInst::initiateMemRead ( Addr  addr,
unsigned  size,
Request::Flags  flags,
const std::vector< bool > &  byte_enable 
)
override

Definition at line 402 of file dyn_inst.cc.

References gem5::X86ISA::addr, cpu, flags, and gem5::o3::CPU::pushRequest().

◆ isAtCommit()

bool gem5::o3::DynInst::isAtCommit ( )
inline

Definition at line 777 of file dyn_inst.hh.

References AtCommit, and status.

◆ isAtomic()

bool gem5::o3::DynInst::isAtomic ( ) const
inline

Definition at line 543 of file dyn_inst.hh.

References gem5::StaticInst::isAtomic(), and staticInst.

◆ isCall()

bool gem5::o3::DynInst::isCall ( ) const
inline

Definition at line 552 of file dyn_inst.hh.

References gem5::StaticInst::isCall(), and staticInst.

◆ isCommitted()

bool gem5::o3::DynInst::isCommitted ( ) const
inline

Returns whether or not this instruction is committed.

Definition at line 783 of file dyn_inst.hh.

References Committed, and status.

◆ isCompleted()

bool gem5::o3::DynInst::isCompleted ( ) const
inline

Returns whether or not this instruction is completed.

Definition at line 734 of file dyn_inst.hh.

References Completed, and status.

◆ isCondCtrl()

bool gem5::o3::DynInst::isCondCtrl ( ) const
inline

Definition at line 556 of file dyn_inst.hh.

References gem5::StaticInst::isCondCtrl(), and staticInst.

◆ isControl()

bool gem5::o3::DynInst::isControl ( ) const
inline

Definition at line 551 of file dyn_inst.hh.

References gem5::StaticInst::isControl(), and staticInst.

◆ isDataPrefetch()

bool gem5::o3::DynInst::isDataPrefetch ( ) const
inline

Definition at line 547 of file dyn_inst.hh.

References gem5::StaticInst::isDataPrefetch(), and staticInst.

◆ isDelayedCommit()

bool gem5::o3::DynInst::isDelayedCommit ( ) const
inline

Definition at line 579 of file dyn_inst.hh.

References gem5::StaticInst::isDelayedCommit(), and staticInst.

◆ isDirectCtrl()

bool gem5::o3::DynInst::isDirectCtrl ( ) const
inline

Definition at line 554 of file dyn_inst.hh.

References gem5::StaticInst::isDirectCtrl(), and staticInst.

◆ isExecuted()

bool gem5::o3::DynInst::isExecuted ( ) const
inline

Returns whether or not this instruction has executed.

Definition at line 764 of file dyn_inst.hh.

References Executed, and status.

◆ isFirstMicroop()

bool gem5::o3::DynInst::isFirstMicroop ( ) const
inline

Definition at line 581 of file dyn_inst.hh.

References gem5::StaticInst::isFirstMicroop(), and staticInst.

◆ isFloating()

bool gem5::o3::DynInst::isFloating ( ) const
inline

Definition at line 549 of file dyn_inst.hh.

References gem5::StaticInst::isFloating(), and staticInst.

◆ isFullMemBarrier()

bool gem5::o3::DynInst::isFullMemBarrier ( ) const
inline

Definition at line 570 of file dyn_inst.hh.

References gem5::StaticInst::isFullMemBarrier(), and staticInst.

◆ isHtmCancel()

bool gem5::o3::DynInst::isHtmCancel ( ) const
inline

Definition at line 585 of file dyn_inst.hh.

References gem5::StaticInst::isHtmCancel(), and staticInst.

◆ isHtmCmd()

bool gem5::o3::DynInst::isHtmCmd ( ) const
inline

Definition at line 586 of file dyn_inst.hh.

References gem5::StaticInst::isHtmCmd(), and staticInst.

◆ isHtmStart()

bool gem5::o3::DynInst::isHtmStart ( ) const
inline

Definition at line 583 of file dyn_inst.hh.

References gem5::StaticInst::isHtmStart(), and staticInst.

◆ isHtmStop()

bool gem5::o3::DynInst::isHtmStop ( ) const
inline

Definition at line 584 of file dyn_inst.hh.

References gem5::StaticInst::isHtmStop(), and staticInst.

◆ isIndirectCtrl()

bool gem5::o3::DynInst::isIndirectCtrl ( ) const
inline

Definition at line 555 of file dyn_inst.hh.

References gem5::StaticInst::isIndirectCtrl(), and staticInst.

◆ isInIQ()

bool gem5::o3::DynInst::isInIQ ( ) const
inline

Returns whether or not this instruction has issued.

Definition at line 800 of file dyn_inst.hh.

References IqEntry, and status.

◆ isInLSQ()

bool gem5::o3::DynInst::isInLSQ ( ) const
inline

Returns whether or not this instruction is in the LSQ.

Definition at line 818 of file dyn_inst.hh.

References LsqEntry, and status.

◆ isInROB()

bool gem5::o3::DynInst::isInROB ( ) const
inline

Returns whether or not this instruction is in the ROB.

Definition at line 836 of file dyn_inst.hh.

References RobEntry, and status.

◆ isInstPrefetch()

bool gem5::o3::DynInst::isInstPrefetch ( ) const
inline

Definition at line 546 of file dyn_inst.hh.

References gem5::StaticInst::isInstPrefetch(), and staticInst.

◆ isInteger()

bool gem5::o3::DynInst::isInteger ( ) const
inline

Definition at line 548 of file dyn_inst.hh.

References gem5::StaticInst::isInteger(), and staticInst.

◆ isIssued()

bool gem5::o3::DynInst::isIssued ( ) const
inline

Returns whether or not this instruction has issued.

Definition at line 755 of file dyn_inst.hh.

References Issued, and status.

◆ isLastMicroop()

bool gem5::o3::DynInst::isLastMicroop ( ) const
inline

Definition at line 580 of file dyn_inst.hh.

References gem5::StaticInst::isLastMicroop(), and staticInst.

◆ isLoad()

bool gem5::o3::DynInst::isLoad ( ) const
inline

Definition at line 541 of file dyn_inst.hh.

References gem5::StaticInst::isLoad(), and staticInst.

◆ isMacroop()

bool gem5::o3::DynInst::isMacroop ( ) const
inline

Definition at line 577 of file dyn_inst.hh.

References gem5::StaticInst::isMacroop(), and staticInst.

◆ isMemRef()

bool gem5::o3::DynInst::isMemRef ( ) const
inline

Definition at line 540 of file dyn_inst.hh.

References gem5::StaticInst::isMemRef(), and staticInst.

◆ isMicroop()

bool gem5::o3::DynInst::isMicroop ( ) const
inline

Definition at line 578 of file dyn_inst.hh.

References gem5::StaticInst::isMicroop(), and staticInst.

◆ isNonSpeculative()

bool gem5::o3::DynInst::isNonSpeculative ( ) const
inline

Definition at line 573 of file dyn_inst.hh.

References gem5::StaticInst::isNonSpeculative(), and staticInst.

◆ isNop()

bool gem5::o3::DynInst::isNop ( ) const
inline

Definition at line 539 of file dyn_inst.hh.

References gem5::StaticInst::isNop(), and staticInst.

◆ isPinnedRegsRenamed()

bool gem5::o3::DynInst::isPinnedRegsRenamed ( ) const
inline

Returns whether pinned registers are renamed.

Definition at line 845 of file dyn_inst.hh.

References PinnedRegsRenamed, and status.

Referenced by setSquashed().

◆ isPinnedRegsSquashDone()

bool gem5::o3::DynInst::isPinnedRegsSquashDone ( ) const
inline

Return whether dest registers' pinning status updated after squash.

Definition at line 870 of file dyn_inst.hh.

References PinnedRegsSquashDone, and status.

Referenced by setSquashed().

◆ isPinnedRegsWritten()

bool gem5::o3::DynInst::isPinnedRegsWritten ( ) const
inline

Returns whether destination registers are written.

Definition at line 857 of file dyn_inst.hh.

References PinnedRegsWritten, and status.

Referenced by setSquashed().

◆ isQuiesce()

bool gem5::o3::DynInst::isQuiesce ( ) const
inline

Definition at line 574 of file dyn_inst.hh.

References gem5::StaticInst::isQuiesce(), and staticInst.

◆ isReadBarrier()

bool gem5::o3::DynInst::isReadBarrier ( ) const
inline

Definition at line 571 of file dyn_inst.hh.

References gem5::StaticInst::isReadBarrier(), and staticInst.

◆ isResultReady()

bool gem5::o3::DynInst::isResultReady ( ) const
inline

Returns whether or not the result is ready.

Definition at line 740 of file dyn_inst.hh.

References ResultReady, and status.

◆ isReturn()

bool gem5::o3::DynInst::isReturn ( ) const
inline

Definition at line 553 of file dyn_inst.hh.

References gem5::StaticInst::isReturn(), and staticInst.

◆ isSerializeAfter()

bool gem5::o3::DynInst::isSerializeAfter ( ) const
inline

Definition at line 565 of file dyn_inst.hh.

References gem5::StaticInst::isSerializeAfter(), SerializeAfter, staticInst, and status.

◆ isSerializeBefore()

bool gem5::o3::DynInst::isSerializeBefore ( ) const
inline

◆ isSerializeHandled()

bool gem5::o3::DynInst::isSerializeHandled ( )
inline

Checks if the serialization part of this instruction has been handled.

This does not apply to the temporary serializing state; it only applies to this instruction's own permanent serializing state.

Definition at line 665 of file dyn_inst.hh.

References SerializeHandled, and status.

◆ isSerializing()

bool gem5::o3::DynInst::isSerializing ( ) const
inline

Definition at line 558 of file dyn_inst.hh.

References gem5::StaticInst::isSerializing(), and staticInst.

◆ isSquashAfter()

bool gem5::o3::DynInst::isSquashAfter ( ) const
inline

Definition at line 569 of file dyn_inst.hh.

References gem5::StaticInst::isSquashAfter(), and staticInst.

◆ isSquashed()

bool gem5::o3::DynInst::isSquashed ( ) const
inline

Returns whether or not this instruction is squashed.

Definition at line 789 of file dyn_inst.hh.

References Squashed, and status.

◆ isSquashedInIQ()

bool gem5::o3::DynInst::isSquashedInIQ ( ) const
inline

Returns whether or not this instruction is squashed in the IQ.

Definition at line 806 of file dyn_inst.hh.

References SquashedInIQ, and status.

◆ isSquashedInLSQ()

bool gem5::o3::DynInst::isSquashedInLSQ ( ) const
inline

Returns whether or not this instruction is squashed in the LSQ.

Definition at line 824 of file dyn_inst.hh.

References SquashedInLSQ, and status.

◆ isSquashedInROB()

bool gem5::o3::DynInst::isSquashedInROB ( ) const
inline

Returns whether or not this instruction is squashed in the ROB.

Definition at line 842 of file dyn_inst.hh.

References SquashedInROB, and status.

◆ isStore()

bool gem5::o3::DynInst::isStore ( ) const
inline

Definition at line 542 of file dyn_inst.hh.

References gem5::StaticInst::isStore(), and staticInst.

◆ isStoreConditional()

bool gem5::o3::DynInst::isStoreConditional ( ) const
inline

Definition at line 544 of file dyn_inst.hh.

References gem5::StaticInst::isStoreConditional(), and staticInst.

Referenced by completeAcc().

◆ isSyscall()

bool gem5::o3::DynInst::isSyscall ( ) const
inline

Definition at line 576 of file dyn_inst.hh.

References gem5::StaticInst::isSyscall(), and staticInst.

◆ isTempSerializeAfter()

bool gem5::o3::DynInst::isTempSerializeAfter ( )
inline

Checks if this serializeAfter is only temporarily set.

Definition at line 655 of file dyn_inst.hh.

References SerializeAfter, and status.

◆ isTempSerializeBefore()

bool gem5::o3::DynInst::isTempSerializeBefore ( )
inline

Checks if this serializeBefore is only temporarily set.

Definition at line 646 of file dyn_inst.hh.

References SerializeBefore, and status.

◆ isTranslationDelayed()

bool gem5::o3::DynInst::isTranslationDelayed ( ) const
inline

Returns true if the DTB address translation is being delayed due to a hw page table walk.

Definition at line 449 of file dyn_inst.hh.

References translationCompleted(), and translationStarted().

◆ isUncondCtrl()

bool gem5::o3::DynInst::isUncondCtrl ( ) const
inline

Definition at line 557 of file dyn_inst.hh.

References gem5::StaticInst::isUncondCtrl(), and staticInst.

◆ isUnverifiable()

bool gem5::o3::DynInst::isUnverifiable ( ) const
inline

Definition at line 575 of file dyn_inst.hh.

References gem5::StaticInst::isUnverifiable(), and staticInst.

◆ isVector()

bool gem5::o3::DynInst::isVector ( ) const
inline

Definition at line 550 of file dyn_inst.hh.

References gem5::StaticInst::isVector(), and staticInst.

◆ isWriteBarrier()

bool gem5::o3::DynInst::isWriteBarrier ( ) const
inline

Definition at line 572 of file dyn_inst.hh.

References gem5::StaticInst::isWriteBarrier(), and staticInst.

◆ markSrcRegReady() [1/2]

void gem5::o3::DynInst::markSrcRegReady ( )

Records that one of the source registers is ready.

Definition at line 296 of file dyn_inst.cc.

References DPRINTF, numSrcRegs(), readyRegs, readyToIssue(), seqNum, and setCanIssue().

Referenced by markSrcRegReady().

◆ markSrcRegReady() [2/2]

void gem5::o3::DynInst::markSrcRegReady ( RegIndex  src_idx)

Marks a specific register as ready.

Definition at line 306 of file dyn_inst.cc.

References markSrcRegReady(), and readySrcIdx().

◆ memOpDone() [1/2]

bool gem5::o3::DynInst::memOpDone ( ) const
inline

Whether or not the memory operation is done.

Definition at line 378 of file dyn_inst.hh.

References instFlags, and MemOpDone.

◆ memOpDone() [2/2]

void gem5::o3::DynInst::memOpDone ( bool  f)
inline

Definition at line 379 of file dyn_inst.hh.

References gem5::VegaISA::f, instFlags, and MemOpDone.

◆ mispredicted()

bool gem5::o3::DynInst::mispredicted ( )
inline

Returns whether the instruction mispredicted.

Definition at line 529 of file dyn_inst.hh.

References gem5::StaticInst::advancePC(), pc, predPC, and staticInst.

◆ mwait()

bool gem5::o3::DynInst::mwait ( PacketPtr  pkt)
inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 965 of file dyn_inst.hh.

References cpu, and threadNumber.

◆ mwaitAtomic()

void gem5::o3::DynInst::mwaitAtomic ( gem5::ThreadContext tc)
inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 970 of file dyn_inst.hh.

References cpu, gem5::o3::CPU::mmu, and threadNumber.

◆ newHtmTransactionUid()

uint64_t gem5::o3::DynInst::newHtmTransactionUid ( ) const
inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 596 of file dyn_inst.hh.

References panic.

◆ notAnInst()

bool gem5::o3::DynInst::notAnInst ( ) const
inline

Definition at line 381 of file dyn_inst.hh.

References instFlags, and NotAnInst.

◆ numDestRegs() [1/2]

size_t gem5::o3::DynInst::numDestRegs ( ) const
inline

Returns the number of destination registers.

Definition at line 681 of file dyn_inst.hh.

References numDests().

Referenced by forwardOldRegs(), and setSquashed().

◆ numDestRegs() [2/2]

size_t gem5::o3::DynInst::numDestRegs ( RegClassType  type) const
inline

Definition at line 684 of file dyn_inst.hh.

References gem5::StaticInst::numDestRegs(), staticInst, and gem5::X86ISA::type.

◆ numDests()

size_t gem5::o3::DynInst::numDests ( ) const
inline

Definition at line 241 of file dyn_inst.hh.

References _numDests.

Referenced by numDestRegs(), and operator new().

◆ numSrcRegs()

size_t gem5::o3::DynInst::numSrcRegs ( ) const
inline

Returns the number of source registers.

Definition at line 678 of file dyn_inst.hh.

References numSrcs().

Referenced by markSrcRegReady().

◆ numSrcs()

size_t gem5::o3::DynInst::numSrcs ( ) const
inline

Definition at line 240 of file dyn_inst.hh.

References _numSrcs.

Referenced by DynInst(), and numSrcRegs().

◆ opClass()

OpClass gem5::o3::DynInst::opClass ( ) const
inline

Returns the opclass of this instruction.

Definition at line 668 of file dyn_inst.hh.

References gem5::StaticInst::opClass(), and staticInst.

◆ operator new()

void * gem5::o3::DynInst::operator new ( size_t  count,
Arrays arrays 
)
static

Definition at line 137 of file dyn_inst.cc.

References gem5::X86ISA::count, numDests(), and gem5::roundUp().

◆ pcState() [1/2]

const PCStateBase& gem5::o3::DynInst::pcState ( ) const
inlineoverridevirtual

Read the PC state of this instruction.

Implements gem5::ExecContext.

Definition at line 885 of file dyn_inst.hh.

References pc.

Referenced by gem5::o3::DependencyGraph< gem5::RefCountingPtr >::dump(), and ~DynInst().

◆ pcState() [2/2]

void gem5::o3::DynInst::pcState ( const PCStateBase val)
inlineoverridevirtual

Set the PC state of this instruction.

Implements gem5::ExecContext.

Definition at line 891 of file dyn_inst.hh.

References pc, gem5::ArmISA::set, and gem5::X86ISA::val.

◆ popResult()

InstResult gem5::o3::DynInst::popResult ( InstResult  dflt = InstResult())
inline

Pops a result off the instResult queue.

If the result stack is empty, return the default value.

Definition at line 702 of file dyn_inst.hh.

References instResult, and gem5::VegaISA::t.

◆ possibleLoadViolation() [1/2]

bool gem5::o3::DynInst::possibleLoadViolation ( ) const
inline

True if this address was found to match a previous load and they issued out of order.

If that happend, then it's only a problem if an incoming snoop invalidate modifies the line, in which case we need to squash. If nothing modified the line the order doesn't matter.

Definition at line 427 of file dyn_inst.hh.

References instFlags, and PossibleLoadViolation.

◆ possibleLoadViolation() [2/2]

void gem5::o3::DynInst::possibleLoadViolation ( bool  f)
inline

Definition at line 432 of file dyn_inst.hh.

References gem5::VegaISA::f, instFlags, and PossibleLoadViolation.

◆ prevDestIdx() [1/2]

PhysRegIdPtr gem5::o3::DynInst::prevDestIdx ( int  idx) const
inline

Definition at line 277 of file dyn_inst.hh.

References _prevDestIdx.

Referenced by forwardOldRegs(), and renameDestReg().

◆ prevDestIdx() [2/2]

void gem5::o3::DynInst::prevDestIdx ( int  idx,
PhysRegIdPtr  phys_reg_id 
)
inline

Definition at line 284 of file dyn_inst.hh.

References _prevDestIdx.

◆ readMemAccPredicate()

bool gem5::o3::DynInst::readMemAccPredicate ( ) const
inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 906 of file dyn_inst.hh.

References instFlags, and MemAccPredicate.

◆ readMiscReg()

RegVal gem5::o3::DynInst::readMiscReg ( int  misc_reg)
inlineoverridevirtual

Reads a misc.

register, including any side-effects the read might have as defined by the architecture.

Implements gem5::ExecContext.

Definition at line 1008 of file dyn_inst.hh.

References cpu, gem5::o3::CPU::readMiscReg(), and threadNumber.

◆ readMiscRegOperand()

RegVal gem5::o3::DynInst::readMiscRegOperand ( const StaticInst si,
int  idx 
)
inlineoverridevirtual

Reads a misc.

register, including any side-effects the read might have as defined by the architecture.

Implements gem5::ExecContext.

Definition at line 1038 of file dyn_inst.hh.

References cpu, gem5::MiscRegClass, gem5::o3::CPU::readMiscReg(), gem5::X86ISA::reg, gem5::ArmISA::si, and threadNumber.

◆ readPredicate()

bool gem5::o3::DynInst::readPredicate ( ) const
inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 893 of file dyn_inst.hh.

References instFlags, and Predicate.

◆ readPredTaken()

bool gem5::o3::DynInst::readPredTaken ( )
inline

Returns whether the instruction was predicted taken or not.

Definition at line 519 of file dyn_inst.hh.

References instFlags, and PredTaken.

◆ readPredTarg()

const PCStateBase& gem5::o3::DynInst::readPredTarg ( )
inline

Definition at line 516 of file dyn_inst.hh.

References predPC.

◆ readStCondFailures()

unsigned int gem5::o3::DynInst::readStCondFailures ( ) const
inlineoverridevirtual

Returns the number of consecutive store conditional failures.

Implements gem5::ExecContext.

Definition at line 945 of file dyn_inst.hh.

References gem5::ThreadState::storeCondFailures, and thread.

◆ readySrcIdx() [1/2]

bool gem5::o3::DynInst::readySrcIdx ( int  idx) const
inline

Definition at line 303 of file dyn_inst.hh.

References _readySrcIdx, and gem5::bits().

Referenced by markSrcRegReady().

◆ readySrcIdx() [2/2]

void gem5::o3::DynInst::readySrcIdx ( int  idx,
bool  ready 
)
inline

Definition at line 310 of file dyn_inst.hh.

References _readySrcIdx, and gem5::replaceBits().

◆ readyToCommit()

bool gem5::o3::DynInst::readyToCommit ( ) const
inline

Returns whether or not this instruction is ready to commit.

Definition at line 773 of file dyn_inst.hh.

References CanCommit, and status.

◆ readyToIssue()

bool gem5::o3::DynInst::readyToIssue ( ) const
inline

Returns whether or not this instruction is ready to issue.

Definition at line 746 of file dyn_inst.hh.

References CanIssue, and status.

Referenced by markSrcRegReady().

◆ recordResult()

void gem5::o3::DynInst::recordResult ( bool  f)
inline

Records changes to result?

Definition at line 371 of file dyn_inst.hh.

References gem5::VegaISA::f, instFlags, and RecordResult.

◆ removeInLSQ()

void gem5::o3::DynInst::removeInLSQ ( )
inline

Sets this instruction as a entry the LSQ.

Definition at line 815 of file dyn_inst.hh.

References LsqEntry, and status.

◆ renamedDestIdx() [1/2]

PhysRegIdPtr gem5::o3::DynInst::renamedDestIdx ( int  idx) const
inline

Definition at line 262 of file dyn_inst.hh.

References _destIdx.

Referenced by getWritableRegOperand(), renameDestReg(), setRegOperand(), and setSquashed().

◆ renamedDestIdx() [2/2]

void gem5::o3::DynInst::renamedDestIdx ( int  idx,
PhysRegIdPtr  phys_reg_id 
)
inline

Definition at line 269 of file dyn_inst.hh.

References _destIdx.

◆ renameDestReg()

void gem5::o3::DynInst::renameDestReg ( int  idx,
PhysRegIdPtr  renamed_dest,
PhysRegIdPtr  previous_rename 
)
inline

Renames a destination register to a physical register.

Also records the previous physical register that the logical register mapped to.

Definition at line 463 of file dyn_inst.hh.

References gem5::PhysRegId::isPinned(), prevDestIdx(), renamedDestIdx(), and setPinnedRegsRenamed().

◆ renamedSrcIdx() [1/2]

PhysRegIdPtr gem5::o3::DynInst::renamedSrcIdx ( int  idx) const
inline

Definition at line 291 of file dyn_inst.hh.

References _srcIdx.

Referenced by getRegOperand(), and renameSrcReg().

◆ renamedSrcIdx() [2/2]

void gem5::o3::DynInst::renamedSrcIdx ( int  idx,
PhysRegIdPtr  phys_reg_id 
)
inline

Definition at line 297 of file dyn_inst.hh.

References _srcIdx.

◆ renameSrcReg()

void gem5::o3::DynInst::renameSrcReg ( int  idx,
PhysRegIdPtr  renamed_src 
)
inline

Renames a source logical register to the physical register which has/will produce that logical register's result.

Todo:
: add in whether or not the source register is ready.

Definition at line 477 of file dyn_inst.hh.

References renamedSrcIdx().

◆ requestorId()

RequestorID gem5::o3::DynInst::requestorId ( ) const
inline

Read this CPU's data requestor ID.

Definition at line 495 of file dyn_inst.hh.

References cpu.

◆ resultSize()

uint8_t gem5::o3::DynInst::resultSize ( )
inline

Return the size of the instResult queue.

Definition at line 696 of file dyn_inst.hh.

References instResult.

◆ setAtCommit()

void gem5::o3::DynInst::setAtCommit ( )
inline

Definition at line 775 of file dyn_inst.hh.

References AtCommit, and status.

◆ setCanCommit()

void gem5::o3::DynInst::setCanCommit ( )
inline

Sets this instruction as ready to commit.

Definition at line 767 of file dyn_inst.hh.

References CanCommit, and status.

◆ setCanIssue()

void gem5::o3::DynInst::setCanIssue ( )
inline

Sets this instruction as ready to issue.

Definition at line 743 of file dyn_inst.hh.

References CanIssue, and status.

Referenced by markSrcRegReady().

◆ setCommitted()

void gem5::o3::DynInst::setCommitted ( )
inline

Sets this instruction as committed.

Definition at line 780 of file dyn_inst.hh.

References Committed, and status.

◆ setCompleted()

void gem5::o3::DynInst::setCompleted ( )
inline

Sets this instruction as completed.

Definition at line 731 of file dyn_inst.hh.

References Completed, and status.

◆ setExecuted()

void gem5::o3::DynInst::setExecuted ( )
inline

Sets this instruction as executed.

Definition at line 761 of file dyn_inst.hh.

References Executed, and status.

◆ setHtmTransactionalState()

void gem5::o3::DynInst::setHtmTransactionalState ( uint64_t  htm_uid,
uint64_t  htm_depth 
)
inline

Definition at line 618 of file dyn_inst.hh.

References htmDepth, HtmFromTransaction, htmUid, and instFlags.

◆ setInIQ()

void gem5::o3::DynInst::setInIQ ( )
inline

Sets this instruction as a entry the IQ.

Definition at line 794 of file dyn_inst.hh.

References IqEntry, and status.

◆ setInLSQ()

void gem5::o3::DynInst::setInLSQ ( )
inline

Sets this instruction as a entry the LSQ.

Definition at line 812 of file dyn_inst.hh.

References LsqEntry, and status.

◆ setInROB()

void gem5::o3::DynInst::setInROB ( )
inline

Sets this instruction as a entry the ROB.

Definition at line 830 of file dyn_inst.hh.

References RobEntry, and status.

◆ setInstListIt()

void gem5::o3::DynInst::setInstListIt ( ListIt  _instListIt)
inline

Sets iterator for this instruction in the list of all insts.

Definition at line 940 of file dyn_inst.hh.

References instListIt.

◆ setIssued()

void gem5::o3::DynInst::setIssued ( )
inline

Sets this instruction as issued from the IQ.

Definition at line 752 of file dyn_inst.hh.

References Issued, and status.

◆ setMemAccPredicate()

void gem5::o3::DynInst::setMemAccPredicate ( bool  val)
inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 912 of file dyn_inst.hh.

References instFlags, MemAccPredicate, and gem5::X86ISA::val.

◆ setMiscReg()

void gem5::o3::DynInst::setMiscReg ( int  misc_reg,
RegVal  val 
)
inlineoverridevirtual

Sets a misc.

register, including any side-effects the write might have as defined by the architecture.

Writes to misc. registers are recorded and deferred until the commit stage, when updateMiscRegs() is called. First, check if the misc reg has been written before and update its value to be committed instead of making a new entry. If not, make a new entry and record the write.

Implements gem5::ExecContext.

Definition at line 1017 of file dyn_inst.hh.

References _destMiscRegIdx, _destMiscRegVal, and gem5::X86ISA::val.

Referenced by setMiscRegOperand().

◆ setMiscRegOperand()

void gem5::o3::DynInst::setMiscRegOperand ( const StaticInst si,
int  idx,
RegVal  val 
)
inlineoverridevirtual

Sets a misc.

register, including any side-effects the write might have as defined by the architecture.

Implements gem5::ExecContext.

Definition at line 1049 of file dyn_inst.hh.

References gem5::MiscRegClass, gem5::X86ISA::reg, setMiscReg(), gem5::ArmISA::si, and gem5::X86ISA::val.

◆ setNotAnInst()

void gem5::o3::DynInst::setNotAnInst ( )
inline

Definition at line 382 of file dyn_inst.hh.

References instFlags, and NotAnInst.

◆ setPinnedRegsRenamed()

void gem5::o3::DynInst::setPinnedRegsRenamed ( )
inline

Sets the destination registers as renamed.

Definition at line 849 of file dyn_inst.hh.

References PinnedRegsRenamed, PinnedRegsSquashDone, PinnedRegsWritten, and status.

Referenced by renameDestReg().

◆ setPinnedRegsSquashDone()

void gem5::o3::DynInst::setPinnedRegsSquashDone ( )
inline

Sets dest registers' status updated after squash.

Definition at line 877 of file dyn_inst.hh.

References PinnedRegsSquashDone, and status.

Referenced by setSquashed().

◆ setPinnedRegsWritten()

void gem5::o3::DynInst::setPinnedRegsWritten ( )
inline

Sets destination registers as written.

Definition at line 861 of file dyn_inst.hh.

References PinnedRegsRenamed, PinnedRegsSquashDone, PinnedRegsWritten, and status.

◆ setPredicate()

void gem5::o3::DynInst::setPredicate ( bool  val)
inlineoverridevirtual

◆ setPredTaken()

void gem5::o3::DynInst::setPredTaken ( bool  predicted_taken)
inline

Definition at line 522 of file dyn_inst.hh.

References instFlags, and PredTaken.

◆ setPredTarg()

void gem5::o3::DynInst::setPredTarg ( const PCStateBase pred_pc)
inline

Set the predicted target of this current instruction.

Definition at line 514 of file dyn_inst.hh.

References predPC, and gem5::ArmISA::set.

◆ setRegOperand() [1/2]

void gem5::o3::DynInst::setRegOperand ( const StaticInst si,
int  idx,
const void *  val 
)
inlineoverridevirtual

◆ setRegOperand() [2/2]

void gem5::o3::DynInst::setRegOperand ( const StaticInst si,
int  idx,
RegVal  val 
)
inlineoverridevirtual
Todo:
: Make results into arrays so they can handle multiple dest registers.

Implements gem5::ExecContext.

Definition at line 1160 of file dyn_inst.hh.

References cpu, gem5::InvalidRegClass, gem5::X86ISA::reg, renamedDestIdx(), gem5::o3::CPU::setReg(), setResult(), and gem5::X86ISA::val.

Referenced by forwardOldRegs().

◆ setRequest()

void gem5::o3::DynInst::setRequest ( )
inline

Assert this instruction has generated a memory request.

Definition at line 934 of file dyn_inst.hh.

References instFlags, and ReqMade.

◆ setResult()

template<typename T >
void gem5::o3::DynInst::setResult ( T &&  t)
inline

Pushes a result onto the instResult queue.

Definition at line 716 of file dyn_inst.hh.

References instFlags, instResult, RecordResult, and gem5::VegaISA::t.

Referenced by setRegOperand().

◆ setResultReady()

void gem5::o3::DynInst::setResultReady ( )
inline

Marks the result as ready.

Definition at line 737 of file dyn_inst.hh.

References ResultReady, and status.

◆ setSerializeAfter()

void gem5::o3::DynInst::setSerializeAfter ( )
inline

Temporarily sets this instruction as a serialize after instruction.

Definition at line 649 of file dyn_inst.hh.

References SerializeAfter, and status.

◆ setSerializeBefore()

void gem5::o3::DynInst::setSerializeBefore ( )
inline

Temporarily sets this instruction as a serialize before instruction.

Definition at line 640 of file dyn_inst.hh.

References SerializeBefore, and status.

◆ setSerializeHandled()

void gem5::o3::DynInst::setSerializeHandled ( )
inline

Sets the serialization part of this instruction as handled.

Definition at line 658 of file dyn_inst.hh.

References SerializeHandled, and status.

◆ setSquashed()

void gem5::o3::DynInst::setSquashed ( )

◆ setSquashedInIQ()

void gem5::o3::DynInst::setSquashedInIQ ( )
inline

Sets this instruction as squashed in the IQ.

Definition at line 803 of file dyn_inst.hh.

References Squashed, SquashedInIQ, and status.

◆ setSquashedInLSQ()

void gem5::o3::DynInst::setSquashedInLSQ ( )
inline

Sets this instruction as squashed in the LSQ.

Definition at line 821 of file dyn_inst.hh.

References Squashed, SquashedInLSQ, and status.

◆ setSquashedInROB()

void gem5::o3::DynInst::setSquashedInROB ( )
inline

Sets this instruction as squashed in the ROB.

Definition at line 839 of file dyn_inst.hh.

References SquashedInROB, and status.

◆ setStCondFailures()

void gem5::o3::DynInst::setStCondFailures ( unsigned int  sc_failures)
inlineoverridevirtual

Sets the number of consecutive store conditional failures.

Implements gem5::ExecContext.

Definition at line 952 of file dyn_inst.hh.

References gem5::ThreadState::storeCondFailures, and thread.

◆ setThreadState()

void gem5::o3::DynInst::setThreadState ( ThreadState state)
inline

Sets the pointer to the thread state.

Definition at line 921 of file dyn_inst.hh.

References state, and thread.

◆ setTid()

void gem5::o3::DynInst::setTid ( ThreadID  tid)
inline

Sets the thread id.

Definition at line 918 of file dyn_inst.hh.

References threadNumber.

◆ socketId()

uint32_t gem5::o3::DynInst::socketId ( ) const
inline

Read this CPU's Socket ID.

Definition at line 492 of file dyn_inst.hh.

References cpu.

◆ srcRegIdx()

const RegId& gem5::o3::DynInst::srcRegIdx ( int  i) const
inline

Returns the logical register index of the i'th source register.

Definition at line 693 of file dyn_inst.hh.

References gem5::ArmISA::i, gem5::StaticInst::srcRegIdx(), and staticInst.

◆ strictlyOrdered() [1/2]

bool gem5::o3::DynInst::strictlyOrdered ( ) const
inline

Is this instruction's memory access strictly ordered?

Definition at line 928 of file dyn_inst.hh.

References instFlags, and IsStrictlyOrdered.

◆ strictlyOrdered() [2/2]

void gem5::o3::DynInst::strictlyOrdered ( bool  so)
inline

Definition at line 929 of file dyn_inst.hh.

References instFlags, IsStrictlyOrdered, and gem5::PowerISA::so.

◆ tcBase()

gem5::ThreadContext* gem5::o3::DynInst::tcBase ( ) const
inlineoverridevirtual

Returns the thread context.

Implements gem5::ExecContext.

Definition at line 924 of file dyn_inst.hh.

References gem5::o3::ThreadState::getTC(), and thread.

◆ translationCompleted() [1/2]

bool gem5::o3::DynInst::translationCompleted ( ) const
inline

True if the DTB address translation has completed.

Definition at line 415 of file dyn_inst.hh.

References instFlags, and TranslationCompleted.

Referenced by isTranslationDelayed().

◆ translationCompleted() [2/2]

void gem5::o3::DynInst::translationCompleted ( bool  f)
inline

Definition at line 419 of file dyn_inst.hh.

References gem5::VegaISA::f, instFlags, and TranslationCompleted.

◆ translationStarted() [1/2]

bool gem5::o3::DynInst::translationStarted ( ) const
inline

True if the DTB address translation has started.

Definition at line 410 of file dyn_inst.hh.

References instFlags, and TranslationStarted.

Referenced by isTranslationDelayed().

◆ translationStarted() [2/2]

void gem5::o3::DynInst::translationStarted ( bool  f)
inline

Definition at line 411 of file dyn_inst.hh.

References gem5::VegaISA::f, instFlags, and TranslationStarted.

◆ trap()

void gem5::o3::DynInst::trap ( const Fault fault)

Traps to handle specified fault.

Definition at line 396 of file dyn_inst.cc.

References cpu, fault, staticInst, threadNumber, and gem5::o3::CPU::trap().

◆ updateMiscRegs()

void gem5::o3::DynInst::updateMiscRegs ( )
inline

Called at the commit stage to update the misc.

registers.

Definition at line 1058 of file dyn_inst.hh.

References _destMiscRegIdx, _destMiscRegVal, cpu, gem5::ArmISA::i, gem5::o3::ThreadState::noSquashFromTC, gem5::o3::CPU::setMiscReg(), thread, and threadNumber.

◆ writeMem()

Fault gem5::o3::DynInst::writeMem ( uint8_t *  data,
unsigned  size,
Addr  addr,
Request::Flags  flags,
uint64_t *  res,
const std::vector< bool > &  byte_enable 
)
override

Definition at line 423 of file dyn_inst.cc.

References gem5::X86ISA::addr, cpu, data, flags, and gem5::o3::CPU::pushRequest().

Member Data Documentation

◆ _destIdx

PhysRegIdPtr* gem5::o3::DynInst::_destIdx
protected

Definition at line 227 of file dyn_inst.hh.

Referenced by renamedDestIdx(), and ~DynInst().

◆ _destMiscRegIdx

std::vector<short> gem5::o3::DynInst::_destMiscRegIdx
protected

Indexes of the destination misc.

registers. They are needed to defer the write accesses to the misc. registers until the commit stage, when the instruction is out of its speculative state.

Definition at line 216 of file dyn_inst.hh.

Referenced by setMiscReg(), and updateMiscRegs().

◆ _destMiscRegVal

std::vector<RegVal> gem5::o3::DynInst::_destMiscRegVal
protected

Values to be written to the destination misc.

registers.

Definition at line 210 of file dyn_inst.hh.

Referenced by setMiscReg(), and updateMiscRegs().

◆ _flatDestIdx

RegId* gem5::o3::DynInst::_flatDestIdx
protected

Definition at line 223 of file dyn_inst.hh.

Referenced by flattenedDestIdx(), and ~DynInst().

◆ _numDests

size_t gem5::o3::DynInst::_numDests
protected

Definition at line 219 of file dyn_inst.hh.

Referenced by numDests(), and ~DynInst().

◆ _numSrcs

size_t gem5::o3::DynInst::_numSrcs
protected

Definition at line 218 of file dyn_inst.hh.

Referenced by numSrcs(), and ~DynInst().

◆ _prevDestIdx

PhysRegIdPtr* gem5::o3::DynInst::_prevDestIdx
protected

Definition at line 231 of file dyn_inst.hh.

Referenced by prevDestIdx(), and ~DynInst().

◆ _readySrcIdx

uint8_t* gem5::o3::DynInst::_readySrcIdx
protected

Definition at line 237 of file dyn_inst.hh.

Referenced by DynInst(), readySrcIdx(), and ~DynInst().

◆ _srcIdx

PhysRegIdPtr* gem5::o3::DynInst::_srcIdx
protected

Definition at line 234 of file dyn_inst.hh.

Referenced by renamedSrcIdx(), and ~DynInst().

◆ cpu

CPU* gem5::o3::DynInst::cpu = nullptr

◆ effAddr

Addr gem5::o3::DynInst::effAddr = 0

The effective virtual address (lds & stores only).

Definition at line 335 of file dyn_inst.hh.

◆ effSize

unsigned gem5::o3::DynInst::effSize

The size of the request.

Definition at line 344 of file dyn_inst.hh.

◆ fault

Fault gem5::o3::DynInst::fault = NoFault

The kind of fault this instruction has generated.

Definition at line 138 of file dyn_inst.hh.

Referenced by completeAcc(), execute(), getFault(), initiateAcc(), trap(), and ~DynInst().

◆ firstIssue

Tick gem5::o3::DynInst::firstIssue = -1

Definition at line 1001 of file dyn_inst.hh.

◆ htmDepth

uint64_t gem5::o3::DynInst::htmDepth = 0
private

◆ htmUid

uint64_t gem5::o3::DynInst::htmUid = -1
private

◆ instFlags

std::bitset<MaxFlags> gem5::o3::DynInst::instFlags
private

◆ instListIt

ListIt gem5::o3::DynInst::instListIt

Iterator pointing to this BaseDynInst in the list of all insts.

Definition at line 320 of file dyn_inst.hh.

Referenced by getInstListIt(), and setInstListIt().

◆ instResult

std::queue<InstResult> gem5::o3::DynInst::instResult
protected

The result of the instruction; assumes an instruction can have many destination registers.

Definition at line 204 of file dyn_inst.hh.

Referenced by popResult(), resultSize(), and setResult().

◆ lastWakeDependents

Tick gem5::o3::DynInst::lastWakeDependents = -1

Definition at line 1002 of file dyn_inst.hh.

◆ lqIdx

ssize_t gem5::o3::DynInst::lqIdx = -1

Load queue index.

Definition at line 350 of file dyn_inst.hh.

◆ lqIt

LSQUnit::LQIterator gem5::o3::DynInst::lqIt

Definition at line 351 of file dyn_inst.hh.

◆ macroop

const StaticInstPtr gem5::o3::DynInst::macroop

The Macroop if one exists.

Definition at line 327 of file dyn_inst.hh.

◆ memData

uint8_t* gem5::o3::DynInst::memData = nullptr

Pointer to the data for the memory access.

Definition at line 347 of file dyn_inst.hh.

Referenced by ~DynInst().

◆ memReqFlags

unsigned gem5::o3::DynInst::memReqFlags = 0

The memory request flags (from translation).

Definition at line 341 of file dyn_inst.hh.

◆ pc

std::unique_ptr<PCStateBase> gem5::o3::DynInst::pc
protected

PC state for this instruction.

Definition at line 207 of file dyn_inst.hh.

Referenced by branchTarget(), dump(), DynInst(), mispredicted(), and pcState().

◆ physEffAddr

Addr gem5::o3::DynInst::physEffAddr = 0

The effective physical address.

Definition at line 338 of file dyn_inst.hh.

◆ predPC

std::unique_ptr<PCStateBase> gem5::o3::DynInst::predPC

Predicted PC state after this instruction.

Definition at line 324 of file dyn_inst.hh.

Referenced by DynInst(), mispredicted(), readPredTarg(), and setPredTarg().

◆ readyRegs

uint8_t gem5::o3::DynInst::readyRegs = 0

How many source registers are ready.

Definition at line 330 of file dyn_inst.hh.

Referenced by markSrcRegReady().

◆ reqToVerify

RequestPtr gem5::o3::DynInst::reqToVerify

Definition at line 367 of file dyn_inst.hh.

Referenced by completeAcc().

◆ savedRequest

LSQ::LSQRequest* gem5::o3::DynInst::savedRequest

Saved memory request (needed when the DTB address translation is delayed due to a hw page table walk).

Definition at line 363 of file dyn_inst.hh.

◆ seqNum

InstSeqNum gem5::o3::DynInst::seqNum = 0

The sequence number of the instruction.

Definition at line 124 of file dyn_inst.hh.

Referenced by gem5::o3::DependencyGraph< gem5::RefCountingPtr >::dump(), DynInst(), markSrcRegReady(), and ~DynInst().

◆ sqIdx

ssize_t gem5::o3::DynInst::sqIdx = -1

Store queue index.

Definition at line 354 of file dyn_inst.hh.

◆ sqIt

LSQUnit::SQIterator gem5::o3::DynInst::sqIt

Definition at line 355 of file dyn_inst.hh.

◆ staticInst

const StaticInstPtr gem5::o3::DynInst::staticInst

◆ status

std::bitset<NumStatus> gem5::o3::DynInst::status
private

◆ thread

ThreadState* gem5::o3::DynInst::thread = nullptr

Pointer to the thread state.

Definition at line 135 of file dyn_inst.hh.

Referenced by completeAcc(), contextId(), execute(), initiateAcc(), readStCondFailures(), setStCondFailures(), setThreadState(), tcBase(), and updateMiscRegs().

◆ threadNumber

ThreadID gem5::o3::DynInst::threadNumber = 0

The thread this instruction is from.

Definition at line 317 of file dyn_inst.hh.

Referenced by armMonitor(), dump(), getAddrMonitor(), mwait(), mwaitAtomic(), readMiscReg(), readMiscRegOperand(), setTid(), trap(), and updateMiscRegs().

◆ traceData

Trace::InstRecord* gem5::o3::DynInst::traceData = nullptr

InstRecord that tracks this instructions.

Definition at line 141 of file dyn_inst.hh.

Referenced by completeAcc(), execute(), initiateAcc(), setPredicate(), and ~DynInst().


The documentation for this class was generated from the following files:

Generated on Thu Jul 28 2022 13:34:10 for gem5 by doxygen 1.8.17