gem5  v21.1.0.2
Classes | Public Types | Public Member Functions | Public Attributes | Protected Attributes | Private Member Functions | Private Attributes | List of all members
gem5::o3::Fetch Class Reference

Fetch class handles both single threaded and SMT fetch. More...

#include <fetch.hh>

Classes

struct  FetchStatGroup
 
class  FetchTranslation
 
class  FinishTranslationEvent
 
class  IcachePort
 IcachePort class for instruction fetch. More...
 
struct  Stalls
 Source of possible stalls. More...
 

Public Types

enum  FetchStatus { Active, Inactive }
 Overall fetch status. More...
 
enum  ThreadStatus {
  Running, Idle, Squashing, Blocked,
  Fetching, TrapPending, QuiescePending, ItlbWait,
  IcacheWaitResponse, IcacheWaitRetry, IcacheAccessComplete, NoGoodAddr
}
 Individual thread status. More...
 

Public Member Functions

 Fetch (CPU *_cpu, const O3CPUParams &params)
 Fetch constructor. More...
 
std::string name () const
 Returns the name of fetch. More...
 
void regProbePoints ()
 Registers probes. More...
 
void setTimeBuffer (TimeBuffer< TimeStruct > *time_buffer)
 Sets the main backwards communication time buffer pointer. More...
 
void setActiveThreads (std::list< ThreadID > *at_ptr)
 Sets pointer to list of active threads. More...
 
void setFetchQueue (TimeBuffer< FetchStruct > *fq_ptr)
 Sets pointer to time buffer used to communicate to the next stage. More...
 
void startupStage ()
 Initialize stage. More...
 
void clearStates (ThreadID tid)
 Clear all thread-specific states. More...
 
void recvReqRetry ()
 Handles retrying the fetch access. More...
 
void processCacheCompletion (PacketPtr pkt)
 Processes cache completion event. More...
 
void drainResume ()
 Resume after a drain. More...
 
void drainSanityCheck () const
 Perform sanity checks after a drain. More...
 
bool isDrained () const
 Has the stage drained? More...
 
void takeOverFrom ()
 Takes over from another CPU's thread. More...
 
void drainStall (ThreadID tid)
 Stall the fetch stage after reaching a safe drain point. More...
 
void wakeFromQuiesce ()
 Tells fetch to wake up from a quiesce instruction. More...
 
void deactivateThread (ThreadID tid)
 For priority-based fetch policies, need to keep update priorityList. More...
 
void squash (const TheISA::PCState &newPC, const InstSeqNum seq_num, DynInstPtr squashInst, ThreadID tid)
 Squashes a specific thread and resets the PC. More...
 
void tick ()
 Ticks the fetch stage, processing all inputs signals and fetching as many instructions as possible. More...
 
bool checkSignalsAndUpdate (ThreadID tid)
 Checks all input signals and updates the status as necessary. More...
 
void fetch (bool &status_change)
 Does the actual fetching of instructions and passing them on to the next stage. More...
 
Addr fetchBufferAlignPC (Addr addr)
 Align a PC to the start of a fetch buffer block. More...
 
RequestPortgetInstPort ()
 

Public Attributes

TheISA::Decoder * decoder [MaxThreads]
 The decoder. More...
 

Protected Attributes

gem5::o3::Fetch::FetchStatGroup fetchStats
 

Private Member Functions

void resetStage ()
 Reset this pipeline stage. More...
 
void switchToActive ()
 Changes the status of this stage to active, and indicates this to the CPU. More...
 
void switchToInactive ()
 Changes the status of this stage to inactive, and indicates this to the CPU. More...
 
bool lookupAndUpdateNextPC (const DynInstPtr &inst, TheISA::PCState &pc)
 Looks up in the branch predictor to see if the next PC should be either next PC+=MachInst or a branch target. More...
 
bool fetchCacheLine (Addr vaddr, ThreadID tid, Addr pc)
 Fetches the cache line that contains the fetch PC. More...
 
void finishTranslation (const Fault &fault, const RequestPtr &mem_req)
 
bool checkInterrupt (Addr pc)
 Check if an interrupt is pending and that we need to handle. More...
 
void doSquash (const TheISA::PCState &newPC, const DynInstPtr squashInst, ThreadID tid)
 Squashes a specific thread and resets the PC. More...
 
void squashFromDecode (const TheISA::PCState &newPC, const DynInstPtr squashInst, const InstSeqNum seq_num, ThreadID tid)
 Squashes a specific thread and resets the PC. More...
 
bool checkStall (ThreadID tid) const
 Checks if a thread is stalled. More...
 
FetchStatus updateFetchStatus ()
 Updates overall fetch stage status; to be called at the end of each cycle. More...
 
DynInstPtr buildInst (ThreadID tid, StaticInstPtr staticInst, StaticInstPtr curMacroop, TheISA::PCState thisPC, TheISA::PCState nextPC, bool trace)
 
ThreadID getFetchingThread ()
 Returns the appropriate thread to fetch, given the fetch policy. More...
 
ThreadID roundRobin ()
 Returns the appropriate thread to fetch using a round robin policy. More...
 
ThreadID iqCount ()
 Returns the appropriate thread to fetch using the IQ count policy. More...
 
ThreadID lsqCount ()
 Returns the appropriate thread to fetch using the LSQ count policy. More...
 
ThreadID branchCount ()
 Returns the appropriate thread to fetch using the branch count policy. More...
 
void pipelineIcacheAccesses (ThreadID tid)
 Pipeline the next I-cache access to the current one. More...
 
void profileStall (ThreadID tid)
 Profile the reasons of fetch stall. More...
 

Private Attributes

FetchStatus _status
 Fetch status. More...
 
ThreadStatus fetchStatus [MaxThreads]
 Per-thread status. More...
 
SMTFetchPolicy fetchPolicy
 Fetch policy. More...
 
std::list< ThreadIDpriorityList
 List that has the threads organized by priority. More...
 
ProbePointArg< DynInstPtr > * ppFetch
 Probe points. More...
 
ProbePointArg< RequestPtr > * ppFetchRequestSent
 To probe when a fetch request is successfully sent. More...
 
CPUcpu
 Pointer to the O3CPU. More...
 
TimeBuffer< TimeStruct > * timeBuffer
 Time buffer interface. More...
 
TimeBuffer< TimeStruct >::wire fromDecode
 Wire to get decode's information from backwards time buffer. More...
 
TimeBuffer< TimeStruct >::wire fromRename
 Wire to get rename's information from backwards time buffer. More...
 
TimeBuffer< TimeStruct >::wire fromIEW
 Wire to get iew's information from backwards time buffer. More...
 
TimeBuffer< TimeStruct >::wire fromCommit
 Wire to get commit's information from backwards time buffer. More...
 
TimeBuffer< FetchStruct >::wire toDecode
 Wire used to write any information heading to decode. More...
 
branch_prediction::BPredUnitbranchPred
 BPredUnit. More...
 
TheISA::PCState pc [MaxThreads]
 
Addr fetchOffset [MaxThreads]
 
StaticInstPtr macroop [MaxThreads]
 
bool delayedCommit [MaxThreads]
 Can the fetch stage redirect from an interrupt on this instruction? More...
 
RequestPtr memReq [MaxThreads]
 Memory request used to access cache. More...
 
bool wroteToTimeBuffer
 Variable that tracks if fetch has written to the time buffer this cycle. More...
 
int numInst
 Tracks how many instructions has been fetched this cycle. More...
 
Stalls stalls [MaxThreads]
 Tracks which stages are telling fetch to stall. More...
 
Cycles decodeToFetchDelay
 Decode to fetch delay. More...
 
Cycles renameToFetchDelay
 Rename to fetch delay. More...
 
Cycles iewToFetchDelay
 IEW to fetch delay. More...
 
Cycles commitToFetchDelay
 Commit to fetch delay. More...
 
unsigned fetchWidth
 The width of fetch in instructions. More...
 
unsigned decodeWidth
 The width of decode in instructions. More...
 
bool cacheBlocked
 Is the cache blocked? If so no threads can access it. More...
 
PacketPtr retryPkt
 The packet that is waiting to be retried. More...
 
ThreadID retryTid
 The thread that is waiting on the cache to tell fetch to retry. More...
 
unsigned int cacheBlkSize
 Cache block size. More...
 
unsigned fetchBufferSize
 The size of the fetch buffer in bytes. More...
 
Addr fetchBufferMask
 Mask to align a fetch address to a fetch buffer boundary. More...
 
uint8_t * fetchBuffer [MaxThreads]
 The fetch data that is being fetched and buffered. More...
 
Addr fetchBufferPC [MaxThreads]
 The PC of the first instruction loaded into the fetch buffer. More...
 
unsigned fetchQueueSize
 The size of the fetch queue in micro-ops. More...
 
std::deque< DynInstPtrfetchQueue [MaxThreads]
 Queue of fetched instructions. More...
 
bool fetchBufferValid [MaxThreads]
 Whether or not the fetch buffer data is valid. More...
 
int instSize
 Size of instructions. More...
 
Counter lastIcacheStall [MaxThreads]
 Icache stall statistics. More...
 
std::list< ThreadID > * activeThreads
 List of Active Threads. More...
 
ThreadID numThreads
 Number of threads. More...
 
ThreadID numFetchingThreads
 Number of threads that are actively fetching. More...
 
ThreadID threadFetched
 Thread ID being fetched. More...
 
bool interruptPending
 Checks if there is an interrupt pending. More...
 
IcachePort icachePort
 Instruction port. More...
 
bool issuePipelinedIfetch [MaxThreads]
 Set to true if a pipelined I-cache request should be issued. More...
 
FinishTranslationEvent finishTranslationEvent
 Event used to delay fault generation of translation faults. More...
 

Detailed Description

Fetch class handles both single threaded and SMT fetch.

Its width is specified by the parameters; each cycle it tries to fetch that many instructions. It supports using a branch predictor to predict direction and targets. It supports the idling functionality of the CPU by indicating to the CPU when it is active and inactive.

Definition at line 79 of file fetch.hh.

Member Enumeration Documentation

◆ FetchStatus

Overall fetch status.

Used to determine if the CPU can deschedule itsef due to a lack of activity.

Enumerator
Active 
Inactive 

Definition at line 163 of file fetch.hh.

◆ ThreadStatus

Individual thread status.

Enumerator
Running 
Idle 
Squashing 
Blocked 
Fetching 
TrapPending 
QuiescePending 
ItlbWait 
IcacheWaitResponse 
IcacheWaitRetry 
IcacheAccessComplete 
NoGoodAddr 

Definition at line 170 of file fetch.hh.

Constructor & Destructor Documentation

◆ Fetch()

gem5::o3::Fetch::Fetch ( CPU _cpu,
const O3CPUParams &  params 
)

Member Function Documentation

◆ branchCount()

ThreadID gem5::o3::Fetch::branchCount ( )
private

Returns the appropriate thread to fetch using the branch count policy.

Definition at line 1524 of file fetch.cc.

References gem5::InvalidThreadID, and panic.

Referenced by getFetchingThread().

◆ buildInst()

DynInstPtr gem5::o3::Fetch::buildInst ( ThreadID  tid,
StaticInstPtr  staticInst,
StaticInstPtr  curMacroop,
TheISA::PCState  thisPC,
TheISA::PCState  nextPC,
bool  trace 
)
private

◆ checkInterrupt()

bool gem5::o3::Fetch::checkInterrupt ( Addr  pc)
inlineprivate

Check if an interrupt is pending and that we need to handle.

Definition at line 306 of file fetch.hh.

References interruptPending.

Referenced by fetch(), and fetchCacheLine().

◆ checkSignalsAndUpdate()

bool gem5::o3::Fetch::checkSignalsAndUpdate ( ThreadID  tid)

Checks all input signals and updates the status as necessary.

Returns
: Returns if the status has changed due to input signals.

Definition at line 942 of file fetch.cc.

References Blocked, branchPred, checkStall(), gem5::o3::Fetch::Stalls::decode, DPRINTF, fetchStatus, fromCommit, fromDecode, IcacheWaitResponse, IcacheWaitRetry, ItlbWait, QuiescePending, Running, gem5::branch_prediction::BPredUnit::squash(), squash(), squashFromDecode(), Squashing, stalls, and gem5::branch_prediction::BPredUnit::update().

Referenced by tick().

◆ checkStall()

bool gem5::o3::Fetch::checkStall ( ThreadID  tid) const
private

Checks if a thread is stalled.

Definition at line 775 of file fetch.cc.

References cpu, DPRINTF, gem5::o3::CPU::isDraining(), and stalls.

Referenced by checkSignalsAndUpdate(), and processCacheCompletion().

◆ clearStates()

void gem5::o3::Fetch::clearStates ( ThreadID  tid)

◆ deactivateThread()

void gem5::o3::Fetch::deactivateThread ( ThreadID  tid)

For priority-based fetch policies, need to keep update priorityList.

Definition at line 501 of file fetch.cc.

References priorityList.

Referenced by gem5::o3::CPU::deactivateThread().

◆ doSquash()

void gem5::o3::Fetch::doSquash ( const TheISA::PCState &  newPC,
const DynInstPtr  squashInst,
ThreadID  tid 
)
private

◆ drainResume()

void gem5::o3::Fetch::drainResume ( )

Resume after a drain.

Definition at line 395 of file fetch.cc.

References gem5::o3::Fetch::Stalls::decode, gem5::o3::Fetch::Stalls::drain, gem5::ArmISA::i, numThreads, and stalls.

Referenced by gem5::o3::CPU::drainResume().

◆ drainSanityCheck()

void gem5::o3::Fetch::drainSanityCheck ( ) const

◆ drainStall()

void gem5::o3::Fetch::drainStall ( ThreadID  tid)

Stall the fetch stage after reaching a safe drain point.

The CPU uses this method to stop fetching instructions from a thread that has been drained. The drain stall is different from all other stalls in that it is signaled instantly from the commit stage (without the normal communication delay) when it has reached a safe point to drain from.

Definition at line 459 of file fetch.cc.

References cpu, DPRINTF, gem5::o3::Fetch::Stalls::drain, gem5::o3::CPU::isDraining(), and stalls.

Referenced by gem5::o3::CPU::commitDrained().

◆ fetch()

void gem5::o3::Fetch::fetch ( bool &  status_change)

◆ fetchBufferAlignPC()

Addr gem5::o3::Fetch::fetchBufferAlignPC ( Addr  addr)
inline

Align a PC to the start of a fetch buffer block.

Definition at line 353 of file fetch.hh.

References gem5::X86ISA::addr, and fetchBufferMask.

Referenced by fetch(), fetchCacheLine(), and pipelineIcacheAccesses().

◆ fetchCacheLine()

bool gem5::o3::Fetch::fetchCacheLine ( Addr  vaddr,
ThreadID  tid,
Addr  pc 
)
private

Fetches the cache line that contains the fetch PC.

Returns any fault that happened. Puts the data into the class variable fetchBuffer, which may not hold the entire fetched cache line.

Parameters
vaddrThe memory address that is being fetched from.
ret_faultThe fault reference that will be set to the result of the icache access.
tidThread id.
pcThe actual PC of the current instruction.
Returns
Any fault that occured.

Definition at line 555 of file fetch.cc.

References cacheBlocked, checkInterrupt(), cpu, delayedCommit, DPRINTF, gem5::BaseMMU::Execute, fetchBufferAlignPC(), fetchBufferSize, fetchStatus, gem5::Request::INST_FETCH, gem5::BaseCPU::instRequestorId(), ItlbWait, memReq, gem5::o3::CPU::mmu, gem5::NoFault, pc, gem5::BaseCPU::switchedOut(), gem5::BaseCPU::taskId(), gem5::o3::CPU::thread, gem5::BaseMMU::translateTiming(), and gem5::MipsISA::vaddr.

Referenced by fetch(), and pipelineIcacheAccesses().

◆ finishTranslation()

void gem5::o3::Fetch::finishTranslation ( const Fault fault,
const RequestPtr mem_req 
)
private

◆ getFetchingThread()

ThreadID gem5::o3::Fetch::getFetchingThread ( )
private

Returns the appropriate thread to fetch, given the fetch policy.

Definition at line 1389 of file fetch.cc.

References activeThreads, branchCount(), fetchPolicy, fetchStatus, IcacheAccessComplete, Idle, gem5::InvalidThreadID, iqCount(), lsqCount(), numThreads, roundRobin(), and Running.

Referenced by fetch().

◆ getInstPort()

RequestPort& gem5::o3::Fetch::getInstPort ( )
inline

Definition at line 361 of file fetch.hh.

References icachePort.

Referenced by gem5::o3::CPU::getInstPort().

◆ iqCount()

ThreadID gem5::o3::Fetch::iqCount ( )
private

Returns the appropriate thread to fetch using the IQ count policy.

Definition at line 1453 of file fetch.cc.

References activeThreads, fetchStatus, fromIEW, IcacheAccessComplete, Idle, gem5::InvalidThreadID, and Running.

Referenced by getFetchingThread().

◆ isDrained()

bool gem5::o3::Fetch::isDrained ( ) const

◆ lookupAndUpdateNextPC()

bool gem5::o3::Fetch::lookupAndUpdateNextPC ( const DynInstPtr inst,
TheISA::PCState &  pc 
)
private

Looks up in the branch predictor to see if the next PC should be either next PC+=MachInst or a branch target.

Parameters
next_PCNext PC variable passed in by reference. It is expected to be set to the current PC; it will be updated with what the next PC will be.
next_NPCUsed for ISAs which use delay slots.
Returns
Whether or not a branch was predicted as taken.

Definition at line 511 of file fetch.cc.

References gem5::o3::Fetch::FetchStatGroup::branches, branchPred, DPRINTF, fetchStats, gem5::branch_prediction::BPredUnit::predict(), and gem5::o3::Fetch::FetchStatGroup::predictedBranches.

Referenced by fetch().

◆ lsqCount()

ThreadID gem5::o3::Fetch::lsqCount ( )
private

Returns the appropriate thread to fetch using the LSQ count policy.

Definition at line 1489 of file fetch.cc.

References activeThreads, fetchStatus, fromIEW, IcacheAccessComplete, Idle, gem5::InvalidThreadID, and Running.

Referenced by getFetchingThread().

◆ name()

std::string gem5::o3::Fetch::name ( ) const

Returns the name of fetch.

Definition at line 150 of file fetch.cc.

References cpu, and gem5::Named::name().

Referenced by finishTranslation().

◆ pipelineIcacheAccesses()

void gem5::o3::Fetch::pipelineIcacheAccesses ( ThreadID  tid)
private

Pipeline the next I-cache access to the current one.

Definition at line 1531 of file fetch.cc.

References decoder, DPRINTF, fetchBufferAlignPC(), fetchBufferPC, fetchBufferValid, fetchCacheLine(), fetchOffset, gem5::isRomMicroPC(), issuePipelinedIfetch, and pc.

Referenced by tick().

◆ processCacheCompletion()

void gem5::o3::Fetch::processCacheCompletion ( PacketPtr  pkt)

◆ profileStall()

void gem5::o3::Fetch::profileStall ( ThreadID  tid)
private

◆ recvReqRetry()

void gem5::o3::Fetch::recvReqRetry ( )

◆ regProbePoints()

void gem5::o3::Fetch::regProbePoints ( )

Registers probes.

Definition at line 153 of file fetch.cc.

References cpu, gem5::SimObject::getProbeManager(), ppFetch, and ppFetchRequestSent.

Referenced by gem5::o3::CPU::regProbePoints().

◆ resetStage()

void gem5::o3::Fetch::resetStage ( )
private

◆ roundRobin()

ThreadID gem5::o3::Fetch::roundRobin ( )
private

Returns the appropriate thread to fetch using a round robin policy.

Definition at line 1424 of file fetch.cc.

References fetchStatus, IcacheAccessComplete, Idle, gem5::InvalidThreadID, numThreads, priorityList, and Running.

Referenced by getFetchingThread().

◆ setActiveThreads()

void gem5::o3::Fetch::setActiveThreads ( std::list< ThreadID > *  at_ptr)

Sets pointer to list of active threads.

Definition at line 275 of file fetch.cc.

References activeThreads.

◆ setFetchQueue()

void gem5::o3::Fetch::setFetchQueue ( TimeBuffer< FetchStruct > *  fq_ptr)

Sets pointer to time buffer used to communicate to the next stage.

Definition at line 281 of file fetch.cc.

References gem5::TimeBuffer< T >::getWire(), and toDecode.

◆ setTimeBuffer()

void gem5::o3::Fetch::setTimeBuffer ( TimeBuffer< TimeStruct > *  time_buffer)

Sets the main backwards communication time buffer pointer.

Definition at line 263 of file fetch.cc.

References commitToFetchDelay, decodeToFetchDelay, fromCommit, fromDecode, fromIEW, fromRename, iewToFetchDelay, renameToFetchDelay, and timeBuffer.

◆ squash()

void gem5::o3::Fetch::squash ( const TheISA::PCState &  newPC,
const InstSeqNum  seq_num,
DynInstPtr  squashInst,
ThreadID  tid 
)

Squashes a specific thread and resets the PC.

Also tells the CPU to remove any instructions that are not in the ROB. The source of this squash should be the commit stage.

Definition at line 828 of file fetch.cc.

References cpu, doSquash(), DPRINTF, and gem5::o3::CPU::removeInstsNotInROB().

Referenced by checkSignalsAndUpdate().

◆ squashFromDecode()

void gem5::o3::Fetch::squashFromDecode ( const TheISA::PCState &  newPC,
const DynInstPtr  squashInst,
const InstSeqNum  seq_num,
ThreadID  tid 
)
private

Squashes a specific thread and resets the PC.

Also tells the CPU to remove any instructions between fetch and decode that should be sqaushed.

Definition at line 762 of file fetch.cc.

References cpu, doSquash(), DPRINTF, and gem5::o3::CPU::removeInstsUntil().

Referenced by checkSignalsAndUpdate().

◆ startupStage()

void gem5::o3::Fetch::startupStage ( )

Initialize stage.

Definition at line 288 of file fetch.cc.

References priorityList, resetStage(), and switchToActive().

Referenced by gem5::o3::CPU::startup().

◆ switchToActive()

void gem5::o3::Fetch::switchToActive ( )
private

Changes the status of this stage to active, and indicates this to the CPU.

Definition at line 477 of file fetch.cc.

References _status, gem5::o3::CPU::activateStage(), Active, cpu, DPRINTF, gem5::o3::CPU::FetchIdx, and Inactive.

Referenced by processCacheCompletion(), and startupStage().

◆ switchToInactive()

void gem5::o3::Fetch::switchToInactive ( )
private

Changes the status of this stage to inactive, and indicates this to the CPU.

Definition at line 489 of file fetch.cc.

References _status, Active, cpu, gem5::o3::CPU::deactivateStage(), DPRINTF, gem5::o3::CPU::FetchIdx, and Inactive.

◆ takeOverFrom()

void gem5::o3::Fetch::takeOverFrom ( )

Takes over from another CPU's thread.

Definition at line 451 of file fetch.cc.

References cpu, gem5::o3::CPU::getInstPort(), gem5::Port::isConnected(), and resetStage().

Referenced by gem5::o3::CPU::takeOverFrom().

◆ tick()

void gem5::o3::Fetch::tick ( )

◆ updateFetchStatus()

Fetch::FetchStatus gem5::o3::Fetch::updateFetchStatus ( )
private

Updates overall fetch stage status; to be called at the end of each cycle.

Definition at line 789 of file fetch.cc.

References _status, gem5::o3::CPU::activateStage(), Active, activeThreads, cpu, gem5::o3::CPU::deactivateStage(), DPRINTF, gem5::o3::CPU::FetchIdx, fetchStatus, IcacheAccessComplete, Inactive, Running, and Squashing.

Referenced by finishTranslation(), and tick().

◆ wakeFromQuiesce()

void gem5::o3::Fetch::wakeFromQuiesce ( )

Tells fetch to wake up from a quiesce instruction.

Definition at line 468 of file fetch.cc.

References DPRINTF, fetchStatus, and Running.

Referenced by gem5::o3::CPU::activateContext().

Member Data Documentation

◆ _status

FetchStatus gem5::o3::Fetch::_status
private

◆ activeThreads

std::list<ThreadID>* gem5::o3::Fetch::activeThreads
private

List of Active Threads.

Definition at line 506 of file fetch.hh.

Referenced by getFetchingThread(), iqCount(), lsqCount(), profileStall(), setActiveThreads(), tick(), and updateFetchStatus().

◆ branchPred

branch_prediction::BPredUnit* gem5::o3::Fetch::branchPred
private

BPredUnit.

Definition at line 414 of file fetch.hh.

Referenced by checkSignalsAndUpdate(), drainSanityCheck(), Fetch(), and lookupAndUpdateNextPC().

◆ cacheBlkSize

unsigned int gem5::o3::Fetch::cacheBlkSize
private

Cache block size.

Definition at line 474 of file fetch.hh.

Referenced by Fetch().

◆ cacheBlocked

bool gem5::o3::Fetch::cacheBlocked
private

Is the cache blocked? If so no threads can access it.

Definition at line 465 of file fetch.hh.

Referenced by doSquash(), drainSanityCheck(), fetchCacheLine(), finishTranslation(), recvReqRetry(), and resetStage().

◆ commitToFetchDelay

Cycles gem5::o3::Fetch::commitToFetchDelay
private

Commit to fetch delay.

Definition at line 456 of file fetch.hh.

Referenced by setTimeBuffer().

◆ cpu

CPU* gem5::o3::Fetch::cpu
private

◆ decoder

TheISA::Decoder* gem5::o3::Fetch::decoder[MaxThreads]

The decoder.

Definition at line 359 of file fetch.hh.

Referenced by doSquash(), Fetch(), fetch(), gem5::o3::ThreadContext::getDecoderPtr(), and pipelineIcacheAccesses().

◆ decodeToFetchDelay

Cycles gem5::o3::Fetch::decodeToFetchDelay
private

Decode to fetch delay.

Definition at line 447 of file fetch.hh.

Referenced by setTimeBuffer().

◆ decodeWidth

unsigned gem5::o3::Fetch::decodeWidth
private

The width of decode in instructions.

Definition at line 462 of file fetch.hh.

Referenced by tick().

◆ delayedCommit

bool gem5::o3::Fetch::delayedCommit[MaxThreads]
private

Can the fetch stage redirect from an interrupt on this instruction?

Definition at line 423 of file fetch.hh.

Referenced by buildInst(), clearStates(), doSquash(), Fetch(), fetch(), fetchCacheLine(), and resetStage().

◆ fetchBuffer

uint8_t* gem5::o3::Fetch::fetchBuffer[MaxThreads]
private

The fetch data that is being fetched and buffered.

Definition at line 485 of file fetch.hh.

Referenced by Fetch(), fetch(), and processCacheCompletion().

◆ fetchBufferMask

Addr gem5::o3::Fetch::fetchBufferMask
private

Mask to align a fetch address to a fetch buffer boundary.

Definition at line 482 of file fetch.hh.

Referenced by fetchBufferAlignPC().

◆ fetchBufferPC

Addr gem5::o3::Fetch::fetchBufferPC[MaxThreads]
private

The PC of the first instruction loaded into the fetch buffer.

Definition at line 488 of file fetch.hh.

Referenced by clearStates(), Fetch(), fetch(), finishTranslation(), pipelineIcacheAccesses(), and resetStage().

◆ fetchBufferSize

unsigned gem5::o3::Fetch::fetchBufferSize
private

The size of the fetch buffer in bytes.

The fetch buffer itself may be smaller than a cache line.

Definition at line 479 of file fetch.hh.

Referenced by Fetch(), fetch(), fetchCacheLine(), finishTranslation(), and processCacheCompletion().

◆ fetchBufferValid

bool gem5::o3::Fetch::fetchBufferValid[MaxThreads]
private

Whether or not the fetch buffer data is valid.

Definition at line 497 of file fetch.hh.

Referenced by clearStates(), Fetch(), fetch(), finishTranslation(), pipelineIcacheAccesses(), processCacheCompletion(), and resetStage().

◆ fetchOffset

Addr gem5::o3::Fetch::fetchOffset[MaxThreads]
private

Definition at line 418 of file fetch.hh.

Referenced by clearStates(), doSquash(), Fetch(), fetch(), pipelineIcacheAccesses(), and resetStage().

◆ fetchPolicy

SMTFetchPolicy gem5::o3::Fetch::fetchPolicy
private

Fetch policy.

Definition at line 194 of file fetch.hh.

Referenced by getFetchingThread().

◆ fetchQueue

std::deque<DynInstPtr> gem5::o3::Fetch::fetchQueue[MaxThreads]
private

Queue of fetched instructions.

Per-thread to prevent HoL blocking.

Definition at line 494 of file fetch.hh.

Referenced by buildInst(), clearStates(), doSquash(), fetch(), finishTranslation(), isDrained(), resetStage(), and tick().

◆ fetchQueueSize

unsigned gem5::o3::Fetch::fetchQueueSize
private

The size of the fetch queue in micro-ops.

Definition at line 491 of file fetch.hh.

Referenced by buildInst(), fetch(), and finishTranslation().

◆ fetchStats

gem5::o3::Fetch::FetchStatGroup gem5::o3::Fetch::fetchStats
protected

◆ fetchStatus

ThreadStatus gem5::o3::Fetch::fetchStatus[MaxThreads]
private

◆ fetchWidth

unsigned gem5::o3::Fetch::fetchWidth
private

The width of fetch in instructions.

Definition at line 459 of file fetch.hh.

Referenced by buildInst(), Fetch(), fetch(), finishTranslation(), and gem5::o3::Fetch::FinishTranslationEvent::process().

◆ finishTranslationEvent

FinishTranslationEvent gem5::o3::Fetch::finishTranslationEvent
private

Event used to delay fault generation of translation faults.

Definition at line 529 of file fetch.hh.

Referenced by finishTranslation(), and isDrained().

◆ fromCommit

TimeBuffer<TimeStruct>::wire gem5::o3::Fetch::fromCommit
private

Wire to get commit's information from backwards time buffer.

Definition at line 407 of file fetch.hh.

Referenced by checkSignalsAndUpdate(), setTimeBuffer(), and tick().

◆ fromDecode

TimeBuffer<TimeStruct>::wire gem5::o3::Fetch::fromDecode
private

Wire to get decode's information from backwards time buffer.

Definition at line 398 of file fetch.hh.

Referenced by checkSignalsAndUpdate(), and setTimeBuffer().

◆ fromIEW

TimeBuffer<TimeStruct>::wire gem5::o3::Fetch::fromIEW
private

Wire to get iew's information from backwards time buffer.

Definition at line 404 of file fetch.hh.

Referenced by iqCount(), lsqCount(), and setTimeBuffer().

◆ fromRename

TimeBuffer<TimeStruct>::wire gem5::o3::Fetch::fromRename
private

Wire to get rename's information from backwards time buffer.

Definition at line 401 of file fetch.hh.

Referenced by setTimeBuffer().

◆ icachePort

IcachePort gem5::o3::Fetch::icachePort
private

Instruction port.

Note that it has to appear after the fetch stage.

Definition at line 523 of file fetch.hh.

Referenced by finishTranslation(), getInstPort(), and recvReqRetry().

◆ iewToFetchDelay

Cycles gem5::o3::Fetch::iewToFetchDelay
private

IEW to fetch delay.

Definition at line 453 of file fetch.hh.

Referenced by setTimeBuffer().

◆ instSize

int gem5::o3::Fetch::instSize
private

Size of instructions.

Definition at line 500 of file fetch.hh.

Referenced by Fetch(), and fetch().

◆ interruptPending

bool gem5::o3::Fetch::interruptPending
private

Checks if there is an interrupt pending.

If there is, fetch must stop once it is not fetching PAL instructions.

Definition at line 520 of file fetch.hh.

Referenced by checkInterrupt(), drainSanityCheck(), resetStage(), and tick().

◆ issuePipelinedIfetch

bool gem5::o3::Fetch::issuePipelinedIfetch[MaxThreads]
private

Set to true if a pipelined I-cache request should be issued.

Definition at line 526 of file fetch.hh.

Referenced by Fetch(), fetch(), pipelineIcacheAccesses(), and tick().

◆ lastIcacheStall

Counter gem5::o3::Fetch::lastIcacheStall[MaxThreads]
private

Icache stall statistics.

Definition at line 503 of file fetch.hh.

Referenced by Fetch(), and finishTranslation().

◆ macroop

StaticInstPtr gem5::o3::Fetch::macroop[MaxThreads]
private

Definition at line 420 of file fetch.hh.

Referenced by clearStates(), doSquash(), Fetch(), fetch(), and resetStage().

◆ memReq

RequestPtr gem5::o3::Fetch::memReq[MaxThreads]
private

Memory request used to access cache.

Definition at line 426 of file fetch.hh.

Referenced by clearStates(), doSquash(), drainSanityCheck(), Fetch(), fetchCacheLine(), finishTranslation(), processCacheCompletion(), and resetStage().

◆ numFetchingThreads

ThreadID gem5::o3::Fetch::numFetchingThreads
private

Number of threads that are actively fetching.

Definition at line 512 of file fetch.hh.

Referenced by fetch(), and tick().

◆ numInst

int gem5::o3::Fetch::numInst
private

Tracks how many instructions has been fetched this cycle.

Definition at line 434 of file fetch.hh.

Referenced by buildInst(), fetch(), finishTranslation(), gem5::o3::Fetch::FinishTranslationEvent::process(), resetStage(), and tick().

◆ numThreads

ThreadID gem5::o3::Fetch::numThreads
private

Number of threads.

Definition at line 509 of file fetch.hh.

Referenced by drainResume(), drainSanityCheck(), Fetch(), fetch(), getFetchingThread(), isDrained(), resetStage(), roundRobin(), and tick().

◆ pc

TheISA::PCState gem5::o3::Fetch::pc[MaxThreads]
private

◆ ppFetch

ProbePointArg<DynInstPtr>* gem5::o3::Fetch::ppFetch
private

Probe points.

Definition at line 200 of file fetch.hh.

Referenced by fetch(), and regProbePoints().

◆ ppFetchRequestSent

ProbePointArg<RequestPtr>* gem5::o3::Fetch::ppFetchRequestSent
private

To probe when a fetch request is successfully sent.

Definition at line 202 of file fetch.hh.

Referenced by finishTranslation(), recvReqRetry(), and regProbePoints().

◆ priorityList

std::list<ThreadID> gem5::o3::Fetch::priorityList
private

List that has the threads organized by priority.

Definition at line 197 of file fetch.hh.

Referenced by deactivateThread(), resetStage(), roundRobin(), and startupStage().

◆ renameToFetchDelay

Cycles gem5::o3::Fetch::renameToFetchDelay
private

Rename to fetch delay.

Definition at line 450 of file fetch.hh.

Referenced by setTimeBuffer().

◆ retryPkt

PacketPtr gem5::o3::Fetch::retryPkt
private

The packet that is waiting to be retried.

Definition at line 468 of file fetch.hh.

Referenced by doSquash(), drainSanityCheck(), finishTranslation(), and recvReqRetry().

◆ retryTid

ThreadID gem5::o3::Fetch::retryTid
private

The thread that is waiting on the cache to tell fetch to retry.

Definition at line 471 of file fetch.hh.

Referenced by doSquash(), drainSanityCheck(), finishTranslation(), and recvReqRetry().

◆ stalls

Stalls gem5::o3::Fetch::stalls[MaxThreads]
private

Tracks which stages are telling fetch to stall.

Definition at line 444 of file fetch.hh.

Referenced by checkSignalsAndUpdate(), checkStall(), clearStates(), drainResume(), drainSanityCheck(), drainStall(), Fetch(), isDrained(), profileStall(), resetStage(), and tick().

◆ threadFetched

ThreadID gem5::o3::Fetch::threadFetched
private

Thread ID being fetched.

Definition at line 515 of file fetch.hh.

Referenced by fetch(), and tick().

◆ timeBuffer

TimeBuffer<TimeStruct>* gem5::o3::Fetch::timeBuffer
private

Time buffer interface.

Definition at line 395 of file fetch.hh.

Referenced by setTimeBuffer().

◆ toDecode

TimeBuffer<FetchStruct>::wire gem5::o3::Fetch::toDecode
private

Wire used to write any information heading to decode.

Definition at line 411 of file fetch.hh.

Referenced by setFetchQueue(), and tick().

◆ wroteToTimeBuffer

bool gem5::o3::Fetch::wroteToTimeBuffer
private

Variable that tracks if fetch has written to the time buffer this cycle.

Used to tell CPU if there is activity this cycle.

Definition at line 431 of file fetch.hh.

Referenced by fetch(), finishTranslation(), resetStage(), and tick().


The documentation for this class was generated from the following files:

Generated on Tue Sep 21 2021 12:31:43 for gem5 by doxygen 1.8.17