59 #include "debug/Activity.hh"
60 #include "debug/Drain.hh"
61 #include "debug/Fetch.hh"
62 #include "debug/O3CPU.hh"
63 #include "debug/O3PipeView.hh"
65 #include "params/BaseO3CPU.hh"
105 fatal(
"numThreads (%d) is larger than compiled limit (%d),\n"
106 "\tincrease MaxThreads in src/cpu/o3/limits.hh\n",
109 fatal(
"fetchWidth (%d) is larger than compiled limit (%d),\n"
110 "\tincrease MaxWidth in src/cpu/o3/limits.hh\n",
113 fatal(
"fetch buffer size (%u bytes) is greater than the cache "
116 fatal(
"cache block (%u bytes) is not a multiple of the "
122 pc[
i].reset(params.isa[0]->newPCState());
138 decoder[tid] = params.decoder[tid];
160 : statistics::
Group(cpu,
"fetch"),
161 ADD_STAT(icacheStallCycles, statistics::units::Cycle::get(),
162 "Number of cycles fetch is stalled on an Icache miss"),
164 "Number of instructions fetch has processed"),
166 "Number of branches that fetch encountered"),
168 "Number of branches that fetch has predicted taken"),
169 ADD_STAT(cycles, statistics::units::Cycle::get(),
170 "Number of cycles fetch has run and was not squashing or "
172 ADD_STAT(squashCycles, statistics::units::Cycle::get(),
173 "Number of cycles fetch has spent squashing"),
174 ADD_STAT(tlbCycles, statistics::units::Cycle::get(),
175 "Number of cycles fetch has spent waiting for tlb"),
176 ADD_STAT(idleCycles, statistics::units::Cycle::get(),
177 "Number of cycles fetch was idle"),
178 ADD_STAT(blockedCycles, statistics::units::Cycle::get(),
179 "Number of cycles fetch has spent blocked"),
180 ADD_STAT(miscStallCycles, statistics::units::Cycle::get(),
181 "Number of cycles fetch has spent waiting on interrupts, or bad "
182 "addresses, or out of MSHRs"),
183 ADD_STAT(pendingDrainCycles, statistics::units::Cycle::get(),
184 "Number of cycles fetch has spent waiting on pipes to drain"),
185 ADD_STAT(noActiveThreadStallCycles, statistics::units::Cycle::get(),
186 "Number of stall cycles due to no active thread to fetch from"),
187 ADD_STAT(pendingTrapStallCycles, statistics::units::Cycle::get(),
188 "Number of stall cycles due to pending traps"),
189 ADD_STAT(pendingQuiesceStallCycles, statistics::units::Cycle::get(),
190 "Number of stall cycles due to pending quiesce instructions"),
191 ADD_STAT(icacheWaitRetryStallCycles, statistics::units::Cycle::get(),
192 "Number of stall cycles due to full MSHR"),
194 "Number of cache lines fetched"),
196 "Number of outstanding Icache misses that were squashed"),
198 "Number of outstanding ITLB misses that were squashed"),
200 "Number of instructions fetched each cycle (Total)"),
201 ADD_STAT(idleRate, statistics::units::Ratio::get(),
202 "Ratio of cycles fetch was idle",
203 idleCycles / cpu->baseStats.numCycles),
204 ADD_STAT(branchRate, statistics::units::Ratio::get(),
205 "Number of branch fetches per cycle",
206 branches / cpu->baseStats.numCycles),
207 ADD_STAT(rate, statistics::units::Rate<
208 statistics::units::
Count, statistics::units::Cycle>::get(),
209 "Number of inst fetches per cycle",
210 insts / cpu->baseStats.numCycles)
354 DPRINTF(
Fetch,
"[tid:%i] Waking up from cache miss.\n", tid);
373 DPRINTF(Activity,
"[tid:%i] Activating fetch due to cache completion\n",
385 pkt->
req->setAccessLatency();
460 assert(!
stalls[tid].drain);
461 DPRINTF(Drain,
"%i: Thread drained.\n", tid);
478 DPRINTF(Activity,
"Activating stage.\n");
490 DPRINTF(Activity,
"Deactivating stage.\n");
516 if (!inst->isControl()) {
517 inst->staticInst->advancePC(next_pc);
518 inst->setPredTarg(next_pc);
519 inst->setPredTaken(
false);
529 "predicted to be taken to %s\n",
530 tid, inst->seqNum, inst->pcState().instAddr(), next_pc);
533 "predicted to be not taken\n",
534 tid, inst->seqNum, inst->pcState().instAddr());
538 "predicted to go to %s\n",
539 tid, inst->seqNum, inst->pcState().instAddr(), next_pc);
540 inst->setPredTarg(next_pc);
541 inst->setPredTaken(predict_taken);
549 return predict_taken;
562 DPRINTF(
Fetch,
"[tid:%i] Can't fetch cache line, cache blocked\n",
570 DPRINTF(
Fetch,
"[tid:%i] Can't fetch cache line, interrupt pending\n",
578 DPRINTF(
Fetch,
"[tid:%i] Fetching cache line %#x for addr %#x\n",
579 tid, fetchBufferBlockPC,
vaddr);
584 RequestPtr mem_req = std::make_shared<Request>(
605 Addr fetchBufferBlockPC = mem_req->getVaddr();
613 mem_req->getVaddr() !=
memReq[tid]->getVaddr()) {
614 DPRINTF(
Fetch,
"[tid:%i] Ignoring itlb completed after squash\n",
627 warn(
"Address %#x is outside of physical memory, stopping fetch\n",
628 mem_req->getPaddr());
656 DPRINTF(Activity,
"[tid:%i] Activity: Waiting on I-cache "
676 "[tid:%i] Got back req with addr %#x but expected %#x\n",
677 tid, mem_req->getVaddr(),
memReq[tid]->getVaddr());
686 DPRINTF(
Fetch,
"[tid:%i] Translation faulted, building noop.\n", tid);
689 fetch_pc, fetch_pc,
false);
690 instruction->setNotAnInst();
692 instruction->setPredTarg(fetch_pc);
693 instruction->fault = fault;
696 DPRINTF(Activity,
"Activity this cycle.\n");
701 DPRINTF(
Fetch,
"[tid:%i] Blocked, need to handle the trap.\n", tid);
702 DPRINTF(
Fetch,
"[tid:%i] fault (%s) detected @ PC %s.\n",
703 tid, fault->
name(), *
pc[tid]);
712 DPRINTF(
Fetch,
"[tid:%i] Squashing, setting PC to: %s.\n",
715 set(
pc[tid], new_pc);
717 if (squashInst && squashInst->pcState().instAddr() == new_pc.
instAddr())
718 macroop[tid] = squashInst->macroop;
725 DPRINTF(
Fetch,
"[tid:%i] Squashing outstanding Icache miss.\n",
729 DPRINTF(
Fetch,
"[tid:%i] Squashing outstanding ITLB miss.\n",
763 DPRINTF(
Fetch,
"[tid:%i] Squashing from decode.\n", tid);
775 bool ret_val =
false;
793 while (threads != end) {
801 DPRINTF(Activity,
"[tid:%i] Activating stage.\n",tid);
804 DPRINTF(Activity,
"[tid:%i] Activating fetch due to cache"
817 DPRINTF(Activity,
"Deactivating stage.\n");
842 bool status_change =
false;
850 while (threads != end) {
856 status_change = status_change || updated_status;
862 if (
fromCommit->commitInfo[0].interruptPending) {
866 if (
fromCommit->commitInfo[0].clearInterrupt) {
874 fetch(status_change);
894 unsigned insts_to_decode = 0;
895 unsigned available_insts = 0;
898 if (!
stalls[tid].decode) {
905 std::advance(tid_itr,
908 while (available_insts != 0 && insts_to_decode <
decodeWidth) {
913 DPRINTF(
Fetch,
"[tid:%i] [sn:%llu] Sending instruction to decode "
914 "from fetch queue. Fetch queue size: %i.\n",
931 DPRINTF(Activity,
"Activity this cycle.\n");
948 assert(
stalls[tid].decode);
956 DPRINTF(
Fetch,
"[tid:%i] Squashing instructions due to squash "
957 "from commit.\n",tid);
966 if (
fromCommit->commitInfo[tid].mispredictInst &&
967 fromCommit->commitInfo[tid].mispredictInst->isControl()) {
970 fromCommit->commitInfo[tid].branchTaken, tid);
977 }
else if (
fromCommit->commitInfo[tid].doneSeqNum) {
985 DPRINTF(
Fetch,
"[tid:%i] Squashing instructions due to squash "
986 "from decode.\n",tid);
989 if (
fromDecode->decodeInfo[tid].branchMispredict) {
992 fromDecode->decodeInfo[tid].branchTaken, tid);
1028 DPRINTF(
Fetch,
"[tid:%i] Done squashing, switching to running.\n",
1055 arrays, staticInst, curMacroop, this_pc, next_pc, seq,
cpu);
1056 instruction->setTid(tid);
1058 instruction->setThreadState(
cpu->
thread[tid]);
1060 DPRINTF(
Fetch,
"[tid:%i] Instruction PC %s created [sn:%lli].\n",
1064 instruction->staticInst->disassemble(this_pc.
instAddr()));
1068 instruction->traceData =
1070 instruction->staticInst, this_pc, curMacroop);
1073 instruction->traceData = NULL;
1077 instruction->setInstListIt(
cpu->
addInst(instruction));
1084 DPRINTF(
Fetch,
"[tid:%i] Fetch queue entry created (%i/%i).\n",
1115 DPRINTF(
Fetch,
"Attempting to fetch from [tid:%i]\n", tid);
1129 DPRINTF(
Fetch,
"[tid:%i] Icache miss is complete.\n", tid);
1132 status_change =
true;
1143 DPRINTF(
Fetch,
"[tid:%i] Attempting to translate and read "
1144 "instruction, starting at PC %s.\n", tid, this_pc);
1176 std::unique_ptr<PCStateBase> next_pc(this_pc.
clone());
1185 DPRINTF(
Fetch,
"[tid:%i] Adding instructions to queue to "
1190 bool predictedBranch =
false;
1205 && !predictedBranch && !
quiesce) {
1209 bool needMem = !inRom && !curMacroop && !dec_ptr->instReady();
1210 fetchAddr = (this_pc.
instAddr() + pcOffset) & pc_mask;
1220 if (blkOffset >= numInsts) {
1226 memcpy(dec_ptr->moreBytesPtr(),
1230 if (dec_ptr->needMoreBytes()) {
1240 if (!(curMacroop || inRom)) {
1241 if (dec_ptr->instReady()) {
1242 staticInst = dec_ptr->decode(this_pc);
1248 curMacroop = staticInst;
1261 bool newMacro =
false;
1262 if (curMacroop || inRom) {
1264 staticInst = dec_ptr->fetchRomMicroop(
1265 this_pc.
microPC(), curMacroop);
1273 tid, staticInst, curMacroop, this_pc, *next_pc,
true);
1279 if (debug::O3PipeView) {
1280 instruction->fetchTick =
curTick();
1284 set(next_pc, this_pc);
1290 if (predictedBranch) {
1291 DPRINTF(
Fetch,
"Branch detected with PC = %s\n", this_pc);
1294 newMacro |= this_pc.
instAddr() != next_pc->instAddr();
1297 set(this_pc, *next_pc);
1301 fetchAddr = this_pc.
instAddr() & pc_mask;
1307 if (instruction->isQuiesce()) {
1309 "Quiesce instruction encountered, halting fetch!\n");
1311 status_change =
true;
1315 }
while ((curMacroop || dec_ptr->instReady()) &&
1324 if (predictedBranch) {
1325 DPRINTF(
Fetch,
"[tid:%i] Done fetching, predicted branch "
1326 "instruction encountered.\n", tid);
1328 DPRINTF(
Fetch,
"[tid:%i] Done fetching, reached fetch bandwidth "
1329 "for this cycle.\n", tid);
1331 DPRINTF(
Fetch,
"[tid:%i] Done fetching, reached the end of the"
1332 "fetch buffer.\n", tid);
1344 fetchAddr = (this_pc.
instAddr() + pcOffset) & pc_mask;
1389 case SMTFetchPolicy::RoundRobin:
1391 case SMTFetchPolicy::IQCount:
1393 case SMTFetchPolicy::LSQCount:
1395 case SMTFetchPolicy::Branch:
1427 while (pri_iter != end) {
1428 high_pri = *pri_iter;
1452 std::priority_queue<unsigned, std::vector<unsigned>,
1453 std::greater<unsigned> > PQ;
1454 std::map<unsigned, ThreadID> threadMap;
1459 while (threads != end) {
1469 while (!PQ.empty()) {
1470 ThreadID high_pri = threadMap[PQ.top()];
1488 std::priority_queue<unsigned, std::vector<unsigned>,
1489 std::greater<unsigned> > PQ;
1490 std::map<unsigned, ThreadID> threadMap;
1495 while (threads != end) {
1497 unsigned ldstqCount =
fromIEW->iewInfo[tid].ldstqCount;
1501 PQ.push(ldstqCount);
1502 threadMap[ldstqCount] = tid;
1505 while (!PQ.empty()) {
1506 ThreadID high_pri = threadMap[PQ.top()];
1522 panic(
"Branch Count Fetch policy unimplemented\n");
1548 DPRINTF(
Fetch,
"[tid:%i] Issuing a pipelined I-cache access, "
1549 "starting at PC %s.\n", tid, this_pc);
1558 DPRINTF(
Fetch,
"There are no more threads available to fetch from.\n");
1576 DPRINTF(
Fetch,
"[tid:%i] Fetch is waiting cache response!\n",
1580 DPRINTF(
Fetch,
"[tid:%i] Fetch is waiting ITLB walk to "
1584 DPRINTF(
Fetch,
"[tid:%i] Fetch is waiting for a pending trap!\n",
1588 DPRINTF(
Fetch,
"[tid:%i] Fetch is waiting for a pending quiesce "
1589 "instruction!\n", tid);
1592 DPRINTF(
Fetch,
"[tid:%i] Fetch is waiting for an I-cache retry!\n",
1595 DPRINTF(
Fetch,
"[tid:%i] Fetch predicted non-executable address\n",
1598 DPRINTF(
Fetch,
"[tid:%i] Unexpected fetch stall reason "
1607 DPRINTF(O3CPU,
"Fetch unit received timing\n");
1609 assert(pkt->
req->isUncacheable() ||
1611 fetch->processCacheCompletion(pkt);
1619 fetch->recvReqRetry();
Defines global host-dependent types: Counter, Tick, and (indirectly) {int,uint}{8,...
RequestorID instRequestorId() const
Reads this CPU's unique instruction requestor ID.
uint32_t taskId() const
Get cpu task id.
ThreadID contextToThread(ContextID cid)
Convert ContextID to threadID.
bool switchedOut() const
Determine if the CPU is switched out.
trace::InstTracer * getTracer()
Provide access to the tracer pointer.
virtual void translateTiming(const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode)
Tick clockEdge(Cycles cycles=Cycles(0)) const
Determine the tick when a cycle begins, by default the current one, but the argument also enables the...
Cycles is a wrapper class for representing cycle counts, i.e.
size_t moreBytesSize() const
virtual void moreBytes(const PCStateBase &pc, Addr fetchPC)=0
Feed data to the decoder.
virtual std::string name() const
virtual bool branching() const =0
MicroPC microPC() const
Returns the current micropc.
Addr instAddr() const
Returns the memory address of the instruction this PC points to.
virtual PCStateBase * clone() const =0
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
RequestPtr req
A pointer to the original request.
void dataDynamic(T *p)
Set the data pointer to a value that should have delete [] called on it.
const T * getConstPtr() const
bool cacheResponding() const
bool isConnected() const
Is this port currently connected to a peer?
ProbePointArg generates a point for the class of Arg.
void notify(const Arg &arg)
called at the ProbePoint call site, passes arg to each listener.
A RequestPort is a specialisation of a Port, which implements the default protocol for the three diff...
bool sendTimingReq(PacketPtr pkt)
Attempt to send a timing request to the responder port by calling its corresponding receive function.
@ INST_FETCH
The request was an instruction fetch.
uint8_t numSrcRegs() const
Number of source registers.
virtual StaticInstPtr fetchMicroop(MicroPC upc) const
Return the microop that goes with a particular micropc.
uint8_t numDestRegs() const
Number of destination registers.
bool isLastMicroop() const
bool isMemAddr(Addr addr) const
Check if a physical address is within a range of a memory that is part of the global address map.
void update(const InstSeqNum &done_sn, ThreadID tid)
Tells the branch predictor to commit any updates until the given sequence number.
bool predict(const StaticInstPtr &inst, const InstSeqNum &seqNum, PCStateBase &pc, ThreadID tid)
Predicts whether or not the instruction is a taken branch, and the target of the branch if it is take...
void drainSanityCheck() const
Perform sanity checks after a drain.
void squash(const InstSeqNum &squashed_sn, ThreadID tid)
Squashes all outstanding updates until a given sequence number.
O3CPU class, has each of the stages (fetch through commit) within it, as well as all of the time buff...
ListIt addInst(const DynInstPtr &inst)
Function to add instruction onto the head of the list of the instructions.
ProbePointArg< PacketPtr > * ppInstAccessComplete
std::vector< ThreadState * > thread
Pointers to all of the threads in the CPU.
Port & getInstPort() override
Used by the fetch unit to get a hold of the instruction port.
void activityThisCycle()
Records that there was time buffer activity this cycle.
void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
Remove all instructions younger than the given sequence number.
bool isDraining() const
Is the CPU draining?
void removeInstsNotInROB(ThreadID tid)
Remove all instructions that are not currently in the ROB.
void deactivateStage(const StageIdx idx)
Changes a stage's status to inactive within the activity recorder.
System * system
Pointer to the system.
gem5::ThreadContext * tcBase(ThreadID tid)
Returns a pointer to a thread context.
InstSeqNum getAndIncrementInstSeq()
Get the current instruction sequence number, and increment it.
void pcState(const PCStateBase &new_pc_state, ThreadID tid)
Sets the commit PC state of a specific thread.
void activateStage(const StageIdx idx)
Changes a stage's status to active within the activity recorder.
void wakeCPU()
Wakes the CPU, rescheduling the CPU if it's not already active.
void setReq(const RequestPtr &_req)
void setFault(Fault _fault)
virtual bool recvTimingResp(PacketPtr pkt)
Timing version of receive.
IcachePort(Fetch *_fetch, CPU *_cpu)
Default constructor.
virtual void recvReqRetry()
Handles doing a retry of a failed fetch.
Fetch class handles both single threaded and SMT fetch.
gem5::o3::Fetch::FetchStatGroup fetchStats
bool wroteToTimeBuffer
Variable that tracks if fetch has written to the time buffer this cycle.
void deactivateThread(ThreadID tid)
For priority-based fetch policies, need to keep update priorityList.
FetchStatus
Overall fetch status.
std::list< ThreadID > * activeThreads
List of Active Threads.
TimeBuffer< TimeStruct >::wire fromCommit
Wire to get commit's information from backwards time buffer.
Cycles renameToFetchDelay
Rename to fetch delay.
StaticInstPtr macroop[MaxThreads]
void fetch(bool &status_change)
Does the actual fetching of instructions and passing them on to the next stage.
void takeOverFrom()
Takes over from another CPU's thread.
unsigned int cacheBlkSize
Cache block size.
uint8_t * fetchBuffer[MaxThreads]
The fetch data that is being fetched and buffered.
void doSquash(const PCStateBase &new_pc, const DynInstPtr squashInst, ThreadID tid)
Squashes a specific thread and resets the PC.
TimeBuffer< FetchStruct >::wire toDecode
Wire used to write any information heading to decode.
void setActiveThreads(std::list< ThreadID > *at_ptr)
Sets pointer to list of active threads.
bool lookupAndUpdateNextPC(const DynInstPtr &inst, PCStateBase &pc)
Looks up in the branch predictor to see if the next PC should be either next PC+=MachInst or a branch...
ThreadStatus fetchStatus[MaxThreads]
Per-thread status.
ThreadID numThreads
Number of threads.
TimeBuffer< TimeStruct >::wire fromDecode
Wire to get decode's information from backwards time buffer.
ProbePointArg< DynInstPtr > * ppFetch
Probe points.
TimeBuffer< TimeStruct >::wire fromRename
Wire to get rename's information from backwards time buffer.
void squash(const PCStateBase &new_pc, const InstSeqNum seq_num, DynInstPtr squashInst, ThreadID tid)
Squashes a specific thread and resets the PC.
void squashFromDecode(const PCStateBase &new_pc, const DynInstPtr squashInst, const InstSeqNum seq_num, ThreadID tid)
Squashes a specific thread and resets the PC.
FetchStatus updateFetchStatus()
Updates overall fetch stage status; to be called at the end of each cycle.
ThreadID getFetchingThread()
Returns the appropriate thread to fetch, given the fetch policy.
bool fetchBufferValid[MaxThreads]
Whether or not the fetch buffer data is valid.
void startupStage()
Initialize stage.
void pipelineIcacheAccesses(ThreadID tid)
Pipeline the next I-cache access to the current one.
std::string name() const
Returns the name of fetch.
void wakeFromQuiesce()
Tells fetch to wake up from a quiesce instruction.
void switchToActive()
Changes the status of this stage to active, and indicates this to the CPU.
void switchToInactive()
Changes the status of this stage to inactive, and indicates this to the CPU.
int numInst
Tracks how many instructions has been fetched this cycle.
bool fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc)
Fetches the cache line that contains the fetch PC.
Cycles decodeToFetchDelay
Decode to fetch delay.
bool issuePipelinedIfetch[MaxThreads]
Set to true if a pipelined I-cache request should be issued.
Addr fetchBufferAlignPC(Addr addr)
Align a PC to the start of a fetch buffer block.
FetchStatus _status
Fetch status.
bool delayedCommit[MaxThreads]
Can the fetch stage redirect from an interrupt on this instruction?
ThreadID threadFetched
Thread ID being fetched.
SMTFetchPolicy fetchPolicy
Fetch policy.
branch_prediction::BPredUnit * branchPred
BPredUnit.
void drainSanityCheck() const
Perform sanity checks after a drain.
unsigned fetchWidth
The width of fetch in instructions.
unsigned fetchQueueSize
The size of the fetch queue in micro-ops.
InstDecoder * decoder[MaxThreads]
The decoder.
TimeBuffer< TimeStruct >::wire fromIEW
Wire to get iew's information from backwards time buffer.
void regProbePoints()
Registers probes.
bool checkSignalsAndUpdate(ThreadID tid)
Checks all input signals and updates the status as necessary.
bool checkStall(ThreadID tid) const
Checks if a thread is stalled.
IcachePort icachePort
Instruction port.
void setTimeBuffer(TimeBuffer< TimeStruct > *time_buffer)
Sets the main backwards communication time buffer pointer.
void processCacheCompletion(PacketPtr pkt)
Processes cache completion event.
ThreadID iqCount()
Returns the appropriate thread to fetch using the IQ count policy.
Addr fetchBufferMask
Mask to align a fetch address to a fetch buffer boundary.
void recvReqRetry()
Handles retrying the fetch access.
bool checkInterrupt(Addr pc)
Check if an interrupt is pending and that we need to handle.
Cycles iewToFetchDelay
IEW to fetch delay.
void resetStage()
Reset this pipeline stage.
Fetch(CPU *_cpu, const BaseO3CPUParams ¶ms)
Fetch constructor.
void drainStall(ThreadID tid)
Stall the fetch stage after reaching a safe drain point.
Counter lastIcacheStall[MaxThreads]
Icache stall statistics.
int instSize
Size of instructions.
ProbePointArg< RequestPtr > * ppFetchRequestSent
To probe when a fetch request is successfully sent.
Cycles commitToFetchDelay
Commit to fetch delay.
RequestPtr memReq[MaxThreads]
Memory request used to access cache.
TimeBuffer< TimeStruct > * timeBuffer
Time buffer interface.
void profileStall(ThreadID tid)
Profile the reasons of fetch stall.
ThreadID roundRobin()
Returns the appropriate thread to fetch using a round robin policy.
Addr fetchBufferPC[MaxThreads]
The PC of the first instruction loaded into the fetch buffer.
void drainResume()
Resume after a drain.
void clearStates(ThreadID tid)
Clear all thread-specific states.
void finishTranslation(const Fault &fault, const RequestPtr &mem_req)
bool interruptPending
Checks if there is an interrupt pending.
std::unique_ptr< PCStateBase > pc[MaxThreads]
ThreadID lsqCount()
Returns the appropriate thread to fetch using the LSQ count policy.
Stalls stalls[MaxThreads]
Tracks which stages are telling fetch to stall.
DynInstPtr buildInst(ThreadID tid, StaticInstPtr staticInst, StaticInstPtr curMacroop, const PCStateBase &this_pc, const PCStateBase &next_pc, bool trace)
bool isDrained() const
Has the stage drained?
Addr fetchOffset[MaxThreads]
std::deque< DynInstPtr > fetchQueue[MaxThreads]
Queue of fetched instructions.
PacketPtr retryPkt
The packet that is waiting to be retried.
std::list< ThreadID > priorityList
List that has the threads organized by priority.
FinishTranslationEvent finishTranslationEvent
Event used to delay fault generation of translation faults.
ThreadID retryTid
The thread that is waiting on the cache to tell fetch to retry.
void tick()
Ticks the fetch stage, processing all inputs signals and fetching as many instructions as possible.
ThreadID numFetchingThreads
Number of threads that are actively fetching.
unsigned fetchBufferSize
The size of the fetch buffer in bytes.
void setFetchQueue(TimeBuffer< FetchStruct > *fq_ptr)
Sets pointer to time buffer used to communicate to the next stage.
CPU * cpu
Pointer to the O3CPU.
unsigned decodeWidth
The width of decode in instructions.
bool cacheBlocked
Is the cache blocked? If so no threads can access it.
ThreadID branchCount()
Returns the appropriate thread to fetch using the branch count policy.
Derived & flags(Flags _flags)
Set the flags and marks this stat to print at the end of simulation.
Derived & prereq(const Stat &prereq)
Set the prerequisite stat and marks this stat to print at the end of simulation.
void sample(const U &v, int n=1)
Add a value to the distribtion n times.
Distribution & init(Counter min, Counter max, Counter bkt)
Set the parameters of this distribution.
virtual InstRecord * getInstRecord(Tick when, ThreadContext *tc, const StaticInstPtr staticInst, const PCStateBase &pc, const StaticInstPtr macroStaticInst=nullptr)=0
#define ADD_STAT(n,...)
Convenience macro to add a stat to a statistics group.
std::enable_if_t< std::is_integral_v< T >, T > random()
Use the SFINAE idiom to choose an implementation based on whether the type is integral or floating po...
bool scheduled() const
Determine if the current event is scheduled.
void schedule(Event &event, Tick when)
#define panic(...)
This implements a cprintf based panic() function.
#define fatal(...)
This implements a cprintf based fatal() function.
ProbeManager * getProbeManager()
Get the probe manager for this object.
static constexpr int MaxThreads
static constexpr int MaxWidth
ProbePointArg< PacketInfo > Packet
Packet probe point.
void quiesce(ThreadContext *tc)
const FlagsType pdf
Print the percent of the total that this entry represents.
const FlagsType total
Print the total.
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
std::shared_ptr< FaultBase > Fault
int16_t ThreadID
Thread index/ID type.
std::shared_ptr< Request > RequestPtr
const ThreadID InvalidThreadID
Tick curTick()
The universal simulation clock.
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
static bool isRomMicroPC(MicroPC upc)
StaticInstPtr nopStaticInstPtr
Pointer to a statically allocated generic "nop" instruction object.
constexpr decltype(nullptr) NoFault
Declaration of the Packet class.
statistics::Scalar icacheSquashes
Total number of outstanding icache accesses that were dropped due to a squash.
statistics::Scalar pendingDrainCycles
Total number of cycles spent in waiting for drains.
statistics::Scalar cacheLines
Stat for total number of fetched cache lines.
statistics::Formula branchRate
Number of branch fetches per cycle.
statistics::Scalar blockedCycles
Total number of cycles spent blocked.
statistics::Scalar idleCycles
Stat for total number of cycles spent blocked due to other stages in the pipeline.
statistics::Scalar predictedBranches
Stat for total number of predicted branches.
statistics::Scalar noActiveThreadStallCycles
Total number of stall cycles caused by no active threads to run.
statistics::Scalar pendingQuiesceStallCycles
Total number of stall cycles caused by pending quiesce instructions.
statistics::Scalar icacheWaitRetryStallCycles
Total number of stall cycles caused by I-cache wait retrys.
statistics::Scalar pendingTrapStallCycles
Total number of stall cycles caused by pending traps.
statistics::Scalar cycles
Stat for total number of cycles spent fetching.
statistics::Scalar icacheStallCycles
Stat for total number of cycles stalled due to an icache miss.
statistics::Scalar miscStallCycles
Total number of cycles spent in any other state.
statistics::Scalar tlbCycles
Stat for total number of cycles spent waiting for translation.
statistics::Scalar squashCycles
Stat for total number of cycles spent squashing.
FetchStatGroup(CPU *cpu, Fetch *fetch)
statistics::Scalar branches
Total number of fetched branches.
statistics::Formula idleRate
Rate of how often fetch was idle.
statistics::Scalar insts
Stat for total number of fetched instructions.
statistics::Formula rate
Number of instruction fetched per cycle.
statistics::Scalar tlbSquashes
Total number of outstanding tlb accesses that were dropped due to a squash.
statistics::Distribution nisnDist
Distribution of number of instructions fetched each cycle.
const std::string & name()