gem5  v22.0.0.1
fetch.cc
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41 
42 #include "cpu/o3/fetch.hh"
43 
44 #include <algorithm>
45 #include <cstring>
46 #include <list>
47 #include <map>
48 #include <queue>
49 
50 #include "arch/generic/tlb.hh"
51 #include "base/random.hh"
52 #include "base/types.hh"
53 #include "config/the_isa.hh"
54 #include "cpu/base.hh"
55 #include "cpu/exetrace.hh"
56 #include "cpu/nop_static_inst.hh"
57 #include "cpu/o3/cpu.hh"
58 #include "cpu/o3/dyn_inst.hh"
59 #include "cpu/o3/limits.hh"
60 #include "debug/Activity.hh"
61 #include "debug/Drain.hh"
62 #include "debug/Fetch.hh"
63 #include "debug/O3CPU.hh"
64 #include "debug/O3PipeView.hh"
65 #include "mem/packet.hh"
66 #include "params/BaseO3CPU.hh"
67 #include "sim/byteswap.hh"
68 #include "sim/core.hh"
69 #include "sim/eventq.hh"
70 #include "sim/full_system.hh"
71 #include "sim/system.hh"
72 
73 namespace gem5
74 {
75 
76 namespace o3
77 {
78 
80  RequestPort(_cpu->name() + ".icache_port", _cpu), fetch(_fetch)
81 {}
82 
83 
84 Fetch::Fetch(CPU *_cpu, const BaseO3CPUParams &params)
85  : fetchPolicy(params.smtFetchPolicy),
86  cpu(_cpu),
87  branchPred(nullptr),
92  fetchWidth(params.fetchWidth),
93  decodeWidth(params.decodeWidth),
94  retryPkt(NULL),
96  cacheBlkSize(cpu->cacheLineSize()),
100  numThreads(params.numThreads),
101  numFetchingThreads(params.smtNumFetchingThreads),
102  icachePort(this, _cpu),
103  finishTranslationEvent(this), fetchStats(_cpu, this)
104 {
105  if (numThreads > MaxThreads)
106  fatal("numThreads (%d) is larger than compiled limit (%d),\n"
107  "\tincrease MaxThreads in src/cpu/o3/limits.hh\n",
108  numThreads, static_cast<int>(MaxThreads));
109  if (fetchWidth > MaxWidth)
110  fatal("fetchWidth (%d) is larger than compiled limit (%d),\n"
111  "\tincrease MaxWidth in src/cpu/o3/limits.hh\n",
112  fetchWidth, static_cast<int>(MaxWidth));
114  fatal("fetch buffer size (%u bytes) is greater than the cache "
115  "block size (%u bytes)\n", fetchBufferSize, cacheBlkSize);
117  fatal("cache block (%u bytes) is not a multiple of the "
118  "fetch buffer (%u bytes)\n", cacheBlkSize, fetchBufferSize);
119 
120  for (int i = 0; i < MaxThreads; i++) {
121  fetchStatus[i] = Idle;
122  decoder[i] = nullptr;
123  pc[i].reset(params.isa[0]->newPCState());
124  fetchOffset[i] = 0;
125  macroop[i] = nullptr;
126  delayedCommit[i] = false;
127  memReq[i] = nullptr;
128  stalls[i] = {false, false};
129  fetchBuffer[i] = NULL;
130  fetchBufferPC[i] = 0;
131  fetchBufferValid[i] = false;
132  lastIcacheStall[i] = 0;
133  issuePipelinedIfetch[i] = false;
134  }
135 
136  branchPred = params.branchPred;
137 
138  for (ThreadID tid = 0; tid < numThreads; tid++) {
139  decoder[tid] = params.decoder[tid];
140  // Create space to buffer the cache line data,
141  // which may not hold the entire cache line.
142  fetchBuffer[tid] = new uint8_t[fetchBufferSize];
143  }
144 
145  // Get the size of an instruction.
147 }
148 
149 std::string Fetch::name() const { return cpu->name() + ".fetch"; }
150 
151 void
153 {
154  ppFetch = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Fetch");
155  ppFetchRequestSent = new ProbePointArg<RequestPtr>(cpu->getProbeManager(),
156  "FetchRequest");
157 
158 }
159 
161  : statistics::Group(cpu, "fetch"),
162  ADD_STAT(icacheStallCycles, statistics::units::Cycle::get(),
163  "Number of cycles fetch is stalled on an Icache miss"),
164  ADD_STAT(insts, statistics::units::Count::get(),
165  "Number of instructions fetch has processed"),
166  ADD_STAT(branches, statistics::units::Count::get(),
167  "Number of branches that fetch encountered"),
168  ADD_STAT(predictedBranches, statistics::units::Count::get(),
169  "Number of branches that fetch has predicted taken"),
170  ADD_STAT(cycles, statistics::units::Cycle::get(),
171  "Number of cycles fetch has run and was not squashing or "
172  "blocked"),
173  ADD_STAT(squashCycles, statistics::units::Cycle::get(),
174  "Number of cycles fetch has spent squashing"),
175  ADD_STAT(tlbCycles, statistics::units::Cycle::get(),
176  "Number of cycles fetch has spent waiting for tlb"),
177  ADD_STAT(idleCycles, statistics::units::Cycle::get(),
178  "Number of cycles fetch was idle"),
179  ADD_STAT(blockedCycles, statistics::units::Cycle::get(),
180  "Number of cycles fetch has spent blocked"),
181  ADD_STAT(miscStallCycles, statistics::units::Cycle::get(),
182  "Number of cycles fetch has spent waiting on interrupts, or bad "
183  "addresses, or out of MSHRs"),
184  ADD_STAT(pendingDrainCycles, statistics::units::Cycle::get(),
185  "Number of cycles fetch has spent waiting on pipes to drain"),
186  ADD_STAT(noActiveThreadStallCycles, statistics::units::Cycle::get(),
187  "Number of stall cycles due to no active thread to fetch from"),
188  ADD_STAT(pendingTrapStallCycles, statistics::units::Cycle::get(),
189  "Number of stall cycles due to pending traps"),
190  ADD_STAT(pendingQuiesceStallCycles, statistics::units::Cycle::get(),
191  "Number of stall cycles due to pending quiesce instructions"),
192  ADD_STAT(icacheWaitRetryStallCycles, statistics::units::Cycle::get(),
193  "Number of stall cycles due to full MSHR"),
194  ADD_STAT(cacheLines, statistics::units::Count::get(),
195  "Number of cache lines fetched"),
196  ADD_STAT(icacheSquashes, statistics::units::Count::get(),
197  "Number of outstanding Icache misses that were squashed"),
198  ADD_STAT(tlbSquashes, statistics::units::Count::get(),
199  "Number of outstanding ITLB misses that were squashed"),
200  ADD_STAT(nisnDist, statistics::units::Count::get(),
201  "Number of instructions fetched each cycle (Total)"),
202  ADD_STAT(idleRate, statistics::units::Ratio::get(),
203  "Ratio of cycles fetch was idle",
204  idleCycles / cpu->baseStats.numCycles),
205  ADD_STAT(branchRate, statistics::units::Ratio::get(),
206  "Number of branch fetches per cycle",
207  branches / cpu->baseStats.numCycles),
208  ADD_STAT(rate, statistics::units::Rate<
209  statistics::units::Count, statistics::units::Cycle>::get(),
210  "Number of inst fetches per cycle",
211  insts / cpu->baseStats.numCycles)
212 {
215  insts
216  .prereq(insts);
217  branches
218  .prereq(branches);
221  cycles
222  .prereq(cycles);
225  tlbCycles
226  .prereq(tlbCycles);
227  idleCycles
228  .prereq(idleCycles);
231  cacheLines
232  .prereq(cacheLines);
249  nisnDist
250  .init(/* base value */ 0,
251  /* last value */ fetch->fetchWidth,
252  /* bucket size */ 1)
254  idleRate
255  .prereq(idleRate);
256  branchRate
258  rate
260 }
261 void
263 {
264  timeBuffer = time_buffer;
265 
266  // Create wires to get information from proper places in time buffer.
269  fromIEW = timeBuffer->getWire(-iewToFetchDelay);
271 }
272 
273 void
275 {
276  activeThreads = at_ptr;
277 }
278 
279 void
281 {
282  // Create wire to write information to proper place in fetch time buf.
283  toDecode = ftb_ptr->getWire(0);
284 }
285 
286 void
288 {
289  assert(priorityList.empty());
290  resetStage();
291 
292  // Fetch needs to start fetching instructions at the very beginning,
293  // so it must start up in active state.
294  switchToActive();
295 }
296 
297 void
299 {
300  fetchStatus[tid] = Running;
301  set(pc[tid], cpu->pcState(tid));
302  fetchOffset[tid] = 0;
303  macroop[tid] = NULL;
304  delayedCommit[tid] = false;
305  memReq[tid] = NULL;
306  stalls[tid].decode = false;
307  stalls[tid].drain = false;
308  fetchBufferPC[tid] = 0;
309  fetchBufferValid[tid] = false;
310  fetchQueue[tid].clear();
311 
312  // TODO not sure what to do with priorityList for now
313  // priorityList.push_back(tid);
314 }
315 
316 void
318 {
319  numInst = 0;
320  interruptPending = false;
321  cacheBlocked = false;
322 
323  priorityList.clear();
324 
325  // Setup PC and nextPC with initial state.
326  for (ThreadID tid = 0; tid < numThreads; ++tid) {
327  fetchStatus[tid] = Running;
328  set(pc[tid], cpu->pcState(tid));
329  fetchOffset[tid] = 0;
330  macroop[tid] = NULL;
331 
332  delayedCommit[tid] = false;
333  memReq[tid] = NULL;
334 
335  stalls[tid].decode = false;
336  stalls[tid].drain = false;
337 
338  fetchBufferPC[tid] = 0;
339  fetchBufferValid[tid] = false;
340 
341  fetchQueue[tid].clear();
342 
343  priorityList.push_back(tid);
344  }
345 
346  wroteToTimeBuffer = false;
347  _status = Inactive;
348 }
349 
350 void
352 {
353  ThreadID tid = cpu->contextToThread(pkt->req->contextId());
354 
355  DPRINTF(Fetch, "[tid:%i] Waking up from cache miss.\n", tid);
356  assert(!cpu->switchedOut());
357 
358  // Only change the status if it's still waiting on the icache access
359  // to return.
360  if (fetchStatus[tid] != IcacheWaitResponse ||
361  pkt->req != memReq[tid]) {
363  delete pkt;
364  return;
365  }
366 
367  memcpy(fetchBuffer[tid], pkt->getConstPtr<uint8_t>(), fetchBufferSize);
368  fetchBufferValid[tid] = true;
369 
370  // Wake up the CPU (if it went to sleep and was waiting on
371  // this completion event).
372  cpu->wakeCPU();
373 
374  DPRINTF(Activity, "[tid:%i] Activating fetch due to cache completion\n",
375  tid);
376 
377  switchToActive();
378 
379  // Only switch to IcacheAccessComplete if we're not stalled as well.
380  if (checkStall(tid)) {
381  fetchStatus[tid] = Blocked;
382  } else {
384  }
385 
386  pkt->req->setAccessLatency();
387  cpu->ppInstAccessComplete->notify(pkt);
388  // Reset the mem req to NULL.
389  delete pkt;
390  memReq[tid] = NULL;
391 }
392 
393 void
395 {
396  for (ThreadID i = 0; i < numThreads; ++i) {
397  stalls[i].decode = false;
398  stalls[i].drain = false;
399  }
400 }
401 
402 void
404 {
405  assert(isDrained());
406  assert(retryPkt == NULL);
407  assert(retryTid == InvalidThreadID);
408  assert(!cacheBlocked);
409  assert(!interruptPending);
410 
411  for (ThreadID i = 0; i < numThreads; ++i) {
412  assert(!memReq[i]);
413  assert(fetchStatus[i] == Idle || stalls[i].drain);
414  }
415 
417 }
418 
419 bool
421 {
422  /* Make sure that threads are either idle of that the commit stage
423  * has signaled that draining has completed by setting the drain
424  * stall flag. This effectively forces the pipeline to be disabled
425  * until the whole system is drained (simulation may continue to
426  * drain other components).
427  */
428  for (ThreadID i = 0; i < numThreads; ++i) {
429  // Verify fetch queues are drained
430  if (!fetchQueue[i].empty())
431  return false;
432 
433  // Return false if not idle or drain stalled
434  if (fetchStatus[i] != Idle) {
435  if (fetchStatus[i] == Blocked && stalls[i].drain)
436  continue;
437  else
438  return false;
439  }
440  }
441 
442  /* The pipeline might start up again in the middle of the drain
443  * cycle if the finish translation event is scheduled, so make
444  * sure that's not the case.
445  */
447 }
448 
449 void
451 {
452  assert(cpu->getInstPort().isConnected());
453  resetStage();
454 
455 }
456 
457 void
459 {
460  assert(cpu->isDraining());
461  assert(!stalls[tid].drain);
462  DPRINTF(Drain, "%i: Thread drained.\n", tid);
463  stalls[tid].drain = true;
464 }
465 
466 void
468 {
469  DPRINTF(Fetch, "Waking up from quiesce\n");
470  // Hopefully this is safe
471  // @todo: Allow other threads to wake from quiesce.
472  fetchStatus[0] = Running;
473 }
474 
475 void
477 {
478  if (_status == Inactive) {
479  DPRINTF(Activity, "Activating stage.\n");
480 
482 
483  _status = Active;
484  }
485 }
486 
487 void
489 {
490  if (_status == Active) {
491  DPRINTF(Activity, "Deactivating stage.\n");
492 
494 
495  _status = Inactive;
496  }
497 }
498 
499 void
501 {
502  // Update priority list
503  auto thread_it = std::find(priorityList.begin(), priorityList.end(), tid);
504  if (thread_it != priorityList.end()) {
505  priorityList.erase(thread_it);
506  }
507 }
508 
509 bool
511 {
512  // Do branch prediction check here.
513  // A bit of a misnomer...next_PC is actually the current PC until
514  // this function updates it.
515  bool predict_taken;
516 
517  if (!inst->isControl()) {
518  inst->staticInst->advancePC(next_pc);
519  inst->setPredTarg(next_pc);
520  inst->setPredTaken(false);
521  return false;
522  }
523 
524  ThreadID tid = inst->threadNumber;
525  predict_taken = branchPred->predict(inst->staticInst, inst->seqNum,
526  next_pc, tid);
527 
528  if (predict_taken) {
529  DPRINTF(Fetch, "[tid:%i] [sn:%llu] Branch at PC %#x "
530  "predicted to be taken to %s\n",
531  tid, inst->seqNum, inst->pcState().instAddr(), next_pc);
532  } else {
533  DPRINTF(Fetch, "[tid:%i] [sn:%llu] Branch at PC %#x "
534  "predicted to be not taken\n",
535  tid, inst->seqNum, inst->pcState().instAddr());
536  }
537 
538  DPRINTF(Fetch, "[tid:%i] [sn:%llu] Branch at PC %#x "
539  "predicted to go to %s\n",
540  tid, inst->seqNum, inst->pcState().instAddr(), next_pc);
541  inst->setPredTarg(next_pc);
542  inst->setPredTaken(predict_taken);
543 
545 
546  if (predict_taken) {
548  }
549 
550  return predict_taken;
551 }
552 
553 bool
555 {
556  Fault fault = NoFault;
557 
558  assert(!cpu->switchedOut());
559 
560  // @todo: not sure if these should block translation.
561  //AlphaDep
562  if (cacheBlocked) {
563  DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, cache blocked\n",
564  tid);
565  return false;
566  } else if (checkInterrupt(pc) && !delayedCommit[tid]) {
567  // Hold off fetch from getting new instructions when:
568  // Cache is blocked, or
569  // while an interrupt is pending and we're not in PAL mode, or
570  // fetch is switched out.
571  DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, interrupt pending\n",
572  tid);
573  return false;
574  }
575 
576  // Align the fetch address to the start of a fetch buffer segment.
577  Addr fetchBufferBlockPC = fetchBufferAlignPC(vaddr);
578 
579  DPRINTF(Fetch, "[tid:%i] Fetching cache line %#x for addr %#x\n",
580  tid, fetchBufferBlockPC, vaddr);
581 
582  // Setup the memReq to do a read of the first instruction's address.
583  // Set the appropriate read size and flags as well.
584  // Build request here.
585  RequestPtr mem_req = std::make_shared<Request>(
586  fetchBufferBlockPC, fetchBufferSize,
587  Request::INST_FETCH, cpu->instRequestorId(), pc,
588  cpu->thread[tid]->contextId());
589 
590  mem_req->taskId(cpu->taskId());
591 
592  memReq[tid] = mem_req;
593 
594  // Initiate translation of the icache block
595  fetchStatus[tid] = ItlbWait;
596  FetchTranslation *trans = new FetchTranslation(this);
597  cpu->mmu->translateTiming(mem_req, cpu->thread[tid]->getTC(),
598  trans, BaseMMU::Execute);
599  return true;
600 }
601 
602 void
603 Fetch::finishTranslation(const Fault &fault, const RequestPtr &mem_req)
604 {
605  ThreadID tid = cpu->contextToThread(mem_req->contextId());
606  Addr fetchBufferBlockPC = mem_req->getVaddr();
607 
608  assert(!cpu->switchedOut());
609 
610  // Wake up CPU if it was idle
611  cpu->wakeCPU();
612 
613  if (fetchStatus[tid] != ItlbWait || mem_req != memReq[tid] ||
614  mem_req->getVaddr() != memReq[tid]->getVaddr()) {
615  DPRINTF(Fetch, "[tid:%i] Ignoring itlb completed after squash\n",
616  tid);
618  return;
619  }
620 
621 
622  // If translation was successful, attempt to read the icache block.
623  if (fault == NoFault) {
624  // Check that we're not going off into random memory
625  // If we have, just wait around for commit to squash something and put
626  // us on the right track
627  if (!cpu->system->isMemAddr(mem_req->getPaddr())) {
628  warn("Address %#x is outside of physical memory, stopping fetch\n",
629  mem_req->getPaddr());
630  fetchStatus[tid] = NoGoodAddr;
631  memReq[tid] = NULL;
632  return;
633  }
634 
635  // Build packet here.
636  PacketPtr data_pkt = new Packet(mem_req, MemCmd::ReadReq);
637  data_pkt->dataDynamic(new uint8_t[fetchBufferSize]);
638 
639  fetchBufferPC[tid] = fetchBufferBlockPC;
640  fetchBufferValid[tid] = false;
641  DPRINTF(Fetch, "Fetch: Doing instruction read.\n");
642 
644 
645  // Access the cache.
646  if (!icachePort.sendTimingReq(data_pkt)) {
647  assert(retryPkt == NULL);
648  assert(retryTid == InvalidThreadID);
649  DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid);
650 
652  retryPkt = data_pkt;
653  retryTid = tid;
654  cacheBlocked = true;
655  } else {
656  DPRINTF(Fetch, "[tid:%i] Doing Icache access.\n", tid);
657  DPRINTF(Activity, "[tid:%i] Activity: Waiting on I-cache "
658  "response.\n", tid);
659  lastIcacheStall[tid] = curTick();
661  // Notify Fetch Request probe when a packet containing a fetch
662  // request is successfully sent
663  ppFetchRequestSent->notify(mem_req);
664  }
665  } else {
666  // Don't send an instruction to decode if we can't handle it.
667  if (!(numInst < fetchWidth) ||
668  !(fetchQueue[tid].size() < fetchQueueSize)) {
672  cpu->schedule(finishTranslationEvent,
673  cpu->clockEdge(Cycles(1)));
674  return;
675  }
676  DPRINTF(Fetch,
677  "[tid:%i] Got back req with addr %#x but expected %#x\n",
678  tid, mem_req->getVaddr(), memReq[tid]->getVaddr());
679  // Translation faulted, icache request won't be sent.
680  memReq[tid] = NULL;
681 
682  // Send the fault to commit. This thread will not do anything
683  // until commit handles the fault. The only other way it can
684  // wake up is if a squash comes along and changes the PC.
685  const PCStateBase &fetch_pc = *pc[tid];
686 
687  DPRINTF(Fetch, "[tid:%i] Translation faulted, building noop.\n", tid);
688  // We will use a nop in ordier to carry the fault.
689  DynInstPtr instruction = buildInst(tid, nopStaticInstPtr, nullptr,
690  fetch_pc, fetch_pc, false);
691  instruction->setNotAnInst();
692 
693  instruction->setPredTarg(fetch_pc);
694  instruction->fault = fault;
695  wroteToTimeBuffer = true;
696 
697  DPRINTF(Activity, "Activity this cycle.\n");
699 
700  fetchStatus[tid] = TrapPending;
701 
702  DPRINTF(Fetch, "[tid:%i] Blocked, need to handle the trap.\n", tid);
703  DPRINTF(Fetch, "[tid:%i] fault (%s) detected @ PC %s.\n",
704  tid, fault->name(), *pc[tid]);
705  }
707 }
708 
709 void
710 Fetch::doSquash(const PCStateBase &new_pc, const DynInstPtr squashInst,
711  ThreadID tid)
712 {
713  DPRINTF(Fetch, "[tid:%i] Squashing, setting PC to: %s.\n",
714  tid, new_pc);
715 
716  set(pc[tid], new_pc);
717  fetchOffset[tid] = 0;
718  if (squashInst && squashInst->pcState().instAddr() == new_pc.instAddr())
719  macroop[tid] = squashInst->macroop;
720  else
721  macroop[tid] = NULL;
722  decoder[tid]->reset();
723 
724  // Clear the icache miss if it's outstanding.
725  if (fetchStatus[tid] == IcacheWaitResponse) {
726  DPRINTF(Fetch, "[tid:%i] Squashing outstanding Icache miss.\n",
727  tid);
728  memReq[tid] = NULL;
729  } else if (fetchStatus[tid] == ItlbWait) {
730  DPRINTF(Fetch, "[tid:%i] Squashing outstanding ITLB miss.\n",
731  tid);
732  memReq[tid] = NULL;
733  }
734 
735  // Get rid of the retrying packet if it was from this thread.
736  if (retryTid == tid) {
737  assert(cacheBlocked);
738  if (retryPkt) {
739  delete retryPkt;
740  }
741  retryPkt = NULL;
743  }
744 
745  fetchStatus[tid] = Squashing;
746 
747  // Empty fetch queue
748  fetchQueue[tid].clear();
749 
750  // microops are being squashed, it is not known wheather the
751  // youngest non-squashed microop was marked delayed commit
752  // or not. Setting the flag to true ensures that the
753  // interrupts are not handled when they cannot be, though
754  // some opportunities to handle interrupts may be missed.
755  delayedCommit[tid] = true;
756 
758 }
759 
760 void
761 Fetch::squashFromDecode(const PCStateBase &new_pc, const DynInstPtr squashInst,
762  const InstSeqNum seq_num, ThreadID tid)
763 {
764  DPRINTF(Fetch, "[tid:%i] Squashing from decode.\n", tid);
765 
766  doSquash(new_pc, squashInst, tid);
767 
768  // Tell the CPU to remove any instructions that are in flight between
769  // fetch and decode.
770  cpu->removeInstsUntil(seq_num, tid);
771 }
772 
773 bool
775 {
776  bool ret_val = false;
777 
778  if (stalls[tid].drain) {
779  assert(cpu->isDraining());
780  DPRINTF(Fetch,"[tid:%i] Drain stall detected.\n",tid);
781  ret_val = true;
782  }
783 
784  return ret_val;
785 }
786 
789 {
790  //Check Running
791  std::list<ThreadID>::iterator threads = activeThreads->begin();
793 
794  while (threads != end) {
795  ThreadID tid = *threads++;
796 
797  if (fetchStatus[tid] == Running ||
798  fetchStatus[tid] == Squashing ||
800 
801  if (_status == Inactive) {
802  DPRINTF(Activity, "[tid:%i] Activating stage.\n",tid);
803 
804  if (fetchStatus[tid] == IcacheAccessComplete) {
805  DPRINTF(Activity, "[tid:%i] Activating fetch due to cache"
806  "completion\n",tid);
807  }
808 
810  }
811 
812  return Active;
813  }
814  }
815 
816  // Stage is switching from active to inactive, notify CPU of it.
817  if (_status == Active) {
818  DPRINTF(Activity, "Deactivating stage.\n");
819 
821  }
822 
823  return Inactive;
824 }
825 
826 void
827 Fetch::squash(const PCStateBase &new_pc, const InstSeqNum seq_num,
828  DynInstPtr squashInst, ThreadID tid)
829 {
830  DPRINTF(Fetch, "[tid:%i] Squash from commit.\n", tid);
831 
832  doSquash(new_pc, squashInst, tid);
833 
834  // Tell the CPU to remove any instructions that are not in the ROB.
835  cpu->removeInstsNotInROB(tid);
836 }
837 
838 void
840 {
841  std::list<ThreadID>::iterator threads = activeThreads->begin();
843  bool status_change = false;
844 
845  wroteToTimeBuffer = false;
846 
847  for (ThreadID i = 0; i < numThreads; ++i) {
848  issuePipelinedIfetch[i] = false;
849  }
850 
851  while (threads != end) {
852  ThreadID tid = *threads++;
853 
854  // Check the signals for each thread to determine the proper status
855  // for each thread.
856  bool updated_status = checkSignalsAndUpdate(tid);
857  status_change = status_change || updated_status;
858  }
859 
860  DPRINTF(Fetch, "Running stage.\n");
861 
862  if (FullSystem) {
863  if (fromCommit->commitInfo[0].interruptPending) {
864  interruptPending = true;
865  }
866 
867  if (fromCommit->commitInfo[0].clearInterrupt) {
868  interruptPending = false;
869  }
870  }
871 
873  threadFetched++) {
874  // Fetch each of the actively fetching threads.
875  fetch(status_change);
876  }
877 
878  // Record number of instructions fetched this cycle for distribution.
880 
881  if (status_change) {
882  // Change the fetch stage status if there was a status change.
884  }
885 
886  // Issue the next I-cache request if possible.
887  for (ThreadID i = 0; i < numThreads; ++i) {
888  if (issuePipelinedIfetch[i]) {
890  }
891  }
892 
893  // Send instructions enqueued into the fetch queue to decode.
894  // Limit rate by fetchWidth. Stall if decode is stalled.
895  unsigned insts_to_decode = 0;
896  unsigned available_insts = 0;
897 
898  for (auto tid : *activeThreads) {
899  if (!stalls[tid].decode) {
900  available_insts += fetchQueue[tid].size();
901  }
902  }
903 
904  // Pick a random thread to start trying to grab instructions from
905  auto tid_itr = activeThreads->begin();
906  std::advance(tid_itr,
907  random_mt.random<uint8_t>(0, activeThreads->size() - 1));
908 
909  while (available_insts != 0 && insts_to_decode < decodeWidth) {
910  ThreadID tid = *tid_itr;
911  if (!stalls[tid].decode && !fetchQueue[tid].empty()) {
912  const auto& inst = fetchQueue[tid].front();
913  toDecode->insts[toDecode->size++] = inst;
914  DPRINTF(Fetch, "[tid:%i] [sn:%llu] Sending instruction to decode "
915  "from fetch queue. Fetch queue size: %i.\n",
916  tid, inst->seqNum, fetchQueue[tid].size());
917 
918  wroteToTimeBuffer = true;
919  fetchQueue[tid].pop_front();
920  insts_to_decode++;
921  available_insts--;
922  }
923 
924  tid_itr++;
925  // Wrap around if at end of active threads list
926  if (tid_itr == activeThreads->end())
927  tid_itr = activeThreads->begin();
928  }
929 
930  // If there was activity this cycle, inform the CPU of it.
931  if (wroteToTimeBuffer) {
932  DPRINTF(Activity, "Activity this cycle.\n");
934  }
935 
936  // Reset the number of the instruction we've fetched.
937  numInst = 0;
938 }
939 
940 bool
942 {
943  // Update the per thread stall statuses.
944  if (fromDecode->decodeBlock[tid]) {
945  stalls[tid].decode = true;
946  }
947 
948  if (fromDecode->decodeUnblock[tid]) {
949  assert(stalls[tid].decode);
950  assert(!fromDecode->decodeBlock[tid]);
951  stalls[tid].decode = false;
952  }
953 
954  // Check squash signals from commit.
955  if (fromCommit->commitInfo[tid].squash) {
956 
957  DPRINTF(Fetch, "[tid:%i] Squashing instructions due to squash "
958  "from commit.\n",tid);
959  // In any case, squash.
960  squash(*fromCommit->commitInfo[tid].pc,
961  fromCommit->commitInfo[tid].doneSeqNum,
962  fromCommit->commitInfo[tid].squashInst, tid);
963 
964  // If it was a branch mispredict on a control instruction, update the
965  // branch predictor with that instruction, otherwise just kill the
966  // invalid state we generated in after sequence number
967  if (fromCommit->commitInfo[tid].mispredictInst &&
968  fromCommit->commitInfo[tid].mispredictInst->isControl()) {
969  branchPred->squash(fromCommit->commitInfo[tid].doneSeqNum,
970  *fromCommit->commitInfo[tid].pc,
971  fromCommit->commitInfo[tid].branchTaken, tid);
972  } else {
973  branchPred->squash(fromCommit->commitInfo[tid].doneSeqNum,
974  tid);
975  }
976 
977  return true;
978  } else if (fromCommit->commitInfo[tid].doneSeqNum) {
979  // Update the branch predictor if it wasn't a squashed instruction
980  // that was broadcasted.
981  branchPred->update(fromCommit->commitInfo[tid].doneSeqNum, tid);
982  }
983 
984  // Check squash signals from decode.
985  if (fromDecode->decodeInfo[tid].squash) {
986  DPRINTF(Fetch, "[tid:%i] Squashing instructions due to squash "
987  "from decode.\n",tid);
988 
989  // Update the branch predictor.
990  if (fromDecode->decodeInfo[tid].branchMispredict) {
991  branchPred->squash(fromDecode->decodeInfo[tid].doneSeqNum,
992  *fromDecode->decodeInfo[tid].nextPC,
993  fromDecode->decodeInfo[tid].branchTaken, tid);
994  } else {
995  branchPred->squash(fromDecode->decodeInfo[tid].doneSeqNum,
996  tid);
997  }
998 
999  if (fetchStatus[tid] != Squashing) {
1000 
1001  DPRINTF(Fetch, "Squashing from decode with PC = %s\n",
1002  *fromDecode->decodeInfo[tid].nextPC);
1003  // Squash unless we're already squashing
1004  squashFromDecode(*fromDecode->decodeInfo[tid].nextPC,
1005  fromDecode->decodeInfo[tid].squashInst,
1006  fromDecode->decodeInfo[tid].doneSeqNum,
1007  tid);
1008 
1009  return true;
1010  }
1011  }
1012 
1013  if (checkStall(tid) &&
1014  fetchStatus[tid] != IcacheWaitResponse &&
1015  fetchStatus[tid] != IcacheWaitRetry &&
1016  fetchStatus[tid] != ItlbWait &&
1017  fetchStatus[tid] != QuiescePending) {
1018  DPRINTF(Fetch, "[tid:%i] Setting to blocked\n",tid);
1019 
1020  fetchStatus[tid] = Blocked;
1021 
1022  return true;
1023  }
1024 
1025  if (fetchStatus[tid] == Blocked ||
1026  fetchStatus[tid] == Squashing) {
1027  // Switch status to running if fetch isn't being told to block or
1028  // squash this cycle.
1029  DPRINTF(Fetch, "[tid:%i] Done squashing, switching to running.\n",
1030  tid);
1031 
1032  fetchStatus[tid] = Running;
1033 
1034  return true;
1035  }
1036 
1037  // If we've reached this point, we have not gotten any signals that
1038  // cause fetch to change its status. Fetch remains the same as before.
1039  return false;
1040 }
1041 
1042 DynInstPtr
1044  StaticInstPtr curMacroop, const PCStateBase &this_pc,
1045  const PCStateBase &next_pc, bool trace)
1046 {
1047  // Get a sequence number.
1049 
1050  DynInst::Arrays arrays;
1051  arrays.numSrcs = staticInst->numSrcRegs();
1052  arrays.numDests = staticInst->numDestRegs();
1053 
1054  // Create a new DynInst from the instruction fetched.
1055  DynInstPtr instruction = new (arrays) DynInst(
1056  arrays, staticInst, curMacroop, this_pc, next_pc, seq, cpu);
1057  instruction->setTid(tid);
1058 
1059  instruction->setThreadState(cpu->thread[tid]);
1060 
1061  DPRINTF(Fetch, "[tid:%i] Instruction PC %s created [sn:%lli].\n",
1062  tid, this_pc, seq);
1063 
1064  DPRINTF(Fetch, "[tid:%i] Instruction is: %s\n", tid,
1065  instruction->staticInst->disassemble(this_pc.instAddr()));
1066 
1067 #if TRACING_ON
1068  if (trace) {
1069  instruction->traceData =
1070  cpu->getTracer()->getInstRecord(curTick(), cpu->tcBase(tid),
1071  instruction->staticInst, this_pc, curMacroop);
1072  }
1073 #else
1074  instruction->traceData = NULL;
1075 #endif
1076 
1077  // Add instruction to the CPU's list of instructions.
1078  instruction->setInstListIt(cpu->addInst(instruction));
1079 
1080  // Write the instruction to the first slot in the queue
1081  // that heads to decode.
1082  assert(numInst < fetchWidth);
1083  fetchQueue[tid].push_back(instruction);
1084  assert(fetchQueue[tid].size() <= fetchQueueSize);
1085  DPRINTF(Fetch, "[tid:%i] Fetch queue entry created (%i/%i).\n",
1086  tid, fetchQueue[tid].size(), fetchQueueSize);
1087  //toDecode->insts[toDecode->size++] = instruction;
1088 
1089  // Keep track of if we can take an interrupt at this boundary
1090  delayedCommit[tid] = instruction->isDelayedCommit();
1091 
1092  return instruction;
1093 }
1094 
1095 void
1096 Fetch::fetch(bool &status_change)
1097 {
1099  // Start actual fetch
1101  ThreadID tid = getFetchingThread();
1102 
1103  assert(!cpu->switchedOut());
1104 
1105  if (tid == InvalidThreadID) {
1106  // Breaks looping condition in tick()
1108 
1109  if (numThreads == 1) { // @todo Per-thread stats
1110  profileStall(0);
1111  }
1112 
1113  return;
1114  }
1115 
1116  DPRINTF(Fetch, "Attempting to fetch from [tid:%i]\n", tid);
1117 
1118  // The current PC.
1119  PCStateBase &this_pc = *pc[tid];
1120 
1121  Addr pcOffset = fetchOffset[tid];
1122  Addr fetchAddr = (this_pc.instAddr() + pcOffset) & decoder[tid]->pcMask();
1123 
1124  bool inRom = isRomMicroPC(this_pc.microPC());
1125 
1126  // If returning from the delay of a cache miss, then update the status
1127  // to running, otherwise do the cache access. Possibly move this up
1128  // to tick() function.
1129  if (fetchStatus[tid] == IcacheAccessComplete) {
1130  DPRINTF(Fetch, "[tid:%i] Icache miss is complete.\n", tid);
1131 
1132  fetchStatus[tid] = Running;
1133  status_change = true;
1134  } else if (fetchStatus[tid] == Running) {
1135  // Align the fetch PC so its at the start of a fetch buffer segment.
1136  Addr fetchBufferBlockPC = fetchBufferAlignPC(fetchAddr);
1137 
1138  // If buffer is no longer valid or fetchAddr has moved to point
1139  // to the next cache block, AND we have no remaining ucode
1140  // from a macro-op, then start fetch from icache.
1141  if (!(fetchBufferValid[tid] &&
1142  fetchBufferBlockPC == fetchBufferPC[tid]) && !inRom &&
1143  !macroop[tid]) {
1144  DPRINTF(Fetch, "[tid:%i] Attempting to translate and read "
1145  "instruction, starting at PC %s.\n", tid, this_pc);
1146 
1147  fetchCacheLine(fetchAddr, tid, this_pc.instAddr());
1148 
1149  if (fetchStatus[tid] == IcacheWaitResponse)
1151  else if (fetchStatus[tid] == ItlbWait)
1153  else
1155  return;
1156  } else if (checkInterrupt(this_pc.instAddr()) &&
1157  !delayedCommit[tid]) {
1158  // Stall CPU if an interrupt is posted and we're not issuing
1159  // an delayed commit micro-op currently (delayed commit
1160  // instructions are not interruptable by interrupts, only faults)
1162  DPRINTF(Fetch, "[tid:%i] Fetch is stalled!\n", tid);
1163  return;
1164  }
1165  } else {
1166  if (fetchStatus[tid] == Idle) {
1168  DPRINTF(Fetch, "[tid:%i] Fetch is idle!\n", tid);
1169  }
1170 
1171  // Status is Idle, so fetch should do nothing.
1172  return;
1173  }
1174 
1175  ++fetchStats.cycles;
1176 
1177  std::unique_ptr<PCStateBase> next_pc(this_pc.clone());
1178 
1179  StaticInstPtr staticInst = NULL;
1180  StaticInstPtr curMacroop = macroop[tid];
1181 
1182  // If the read of the first instruction was successful, then grab the
1183  // instructions from the rest of the cache line and put them into the
1184  // queue heading to decode.
1185 
1186  DPRINTF(Fetch, "[tid:%i] Adding instructions to queue to "
1187  "decode.\n", tid);
1188 
1189  // Need to keep track of whether or not a predicted branch
1190  // ended this fetch block.
1191  bool predictedBranch = false;
1192 
1193  // Need to halt fetch if quiesce instruction detected
1194  bool quiesce = false;
1195 
1196  const unsigned numInsts = fetchBufferSize / instSize;
1197  unsigned blkOffset = (fetchAddr - fetchBufferPC[tid]) / instSize;
1198 
1199  auto *dec_ptr = decoder[tid];
1200  const Addr pc_mask = dec_ptr->pcMask();
1201 
1202  // Loop through instruction memory from the cache.
1203  // Keep issuing while fetchWidth is available and branch is not
1204  // predicted taken
1205  while (numInst < fetchWidth && fetchQueue[tid].size() < fetchQueueSize
1206  && !predictedBranch && !quiesce) {
1207  // We need to process more memory if we aren't going to get a
1208  // StaticInst from the rom, the current macroop, or what's already
1209  // in the decoder.
1210  bool needMem = !inRom && !curMacroop && !dec_ptr->instReady();
1211  fetchAddr = (this_pc.instAddr() + pcOffset) & pc_mask;
1212  Addr fetchBufferBlockPC = fetchBufferAlignPC(fetchAddr);
1213 
1214  if (needMem) {
1215  // If buffer is no longer valid or fetchAddr has moved to point
1216  // to the next cache block then start fetch from icache.
1217  if (!fetchBufferValid[tid] ||
1218  fetchBufferBlockPC != fetchBufferPC[tid])
1219  break;
1220 
1221  if (blkOffset >= numInsts) {
1222  // We need to process more memory, but we've run out of the
1223  // current block.
1224  break;
1225  }
1226 
1227  memcpy(dec_ptr->moreBytesPtr(),
1228  fetchBuffer[tid] + blkOffset * instSize, instSize);
1229  decoder[tid]->moreBytes(this_pc, fetchAddr);
1230 
1231  if (dec_ptr->needMoreBytes()) {
1232  blkOffset++;
1233  fetchAddr += instSize;
1234  pcOffset += instSize;
1235  }
1236  }
1237 
1238  // Extract as many instructions and/or microops as we can from
1239  // the memory we've processed so far.
1240  do {
1241  if (!(curMacroop || inRom)) {
1242  if (dec_ptr->instReady()) {
1243  staticInst = dec_ptr->decode(this_pc);
1244 
1245  // Increment stat of fetched instructions.
1246  ++fetchStats.insts;
1247 
1248  if (staticInst->isMacroop()) {
1249  curMacroop = staticInst;
1250  } else {
1251  pcOffset = 0;
1252  }
1253  } else {
1254  // We need more bytes for this instruction so blkOffset and
1255  // pcOffset will be updated
1256  break;
1257  }
1258  }
1259  // Whether we're moving to a new macroop because we're at the
1260  // end of the current one, or the branch predictor incorrectly
1261  // thinks we are...
1262  bool newMacro = false;
1263  if (curMacroop || inRom) {
1264  if (inRom) {
1265  staticInst = dec_ptr->fetchRomMicroop(
1266  this_pc.microPC(), curMacroop);
1267  } else {
1268  staticInst = curMacroop->fetchMicroop(this_pc.microPC());
1269  }
1270  newMacro |= staticInst->isLastMicroop();
1271  }
1272 
1273  DynInstPtr instruction = buildInst(
1274  tid, staticInst, curMacroop, this_pc, *next_pc, true);
1275 
1276  ppFetch->notify(instruction);
1277  numInst++;
1278 
1279 #if TRACING_ON
1280  if (debug::O3PipeView) {
1281  instruction->fetchTick = curTick();
1282  }
1283 #endif
1284 
1285  set(next_pc, this_pc);
1286 
1287  // If we're branching after this instruction, quit fetching
1288  // from the same block.
1289  predictedBranch |= this_pc.branching();
1290  predictedBranch |= lookupAndUpdateNextPC(instruction, *next_pc);
1291  if (predictedBranch) {
1292  DPRINTF(Fetch, "Branch detected with PC = %s\n", this_pc);
1293  }
1294 
1295  newMacro |= this_pc.instAddr() != next_pc->instAddr();
1296 
1297  // Move to the next instruction, unless we have a branch.
1298  set(this_pc, *next_pc);
1299  inRom = isRomMicroPC(this_pc.microPC());
1300 
1301  if (newMacro) {
1302  fetchAddr = this_pc.instAddr() & pc_mask;
1303  blkOffset = (fetchAddr - fetchBufferPC[tid]) / instSize;
1304  pcOffset = 0;
1305  curMacroop = NULL;
1306  }
1307 
1308  if (instruction->isQuiesce()) {
1309  DPRINTF(Fetch,
1310  "Quiesce instruction encountered, halting fetch!\n");
1311  fetchStatus[tid] = QuiescePending;
1312  status_change = true;
1313  quiesce = true;
1314  break;
1315  }
1316  } while ((curMacroop || dec_ptr->instReady()) &&
1317  numInst < fetchWidth &&
1318  fetchQueue[tid].size() < fetchQueueSize);
1319 
1320  // Re-evaluate whether the next instruction to fetch is in micro-op ROM
1321  // or not.
1322  inRom = isRomMicroPC(this_pc.microPC());
1323  }
1324 
1325  if (predictedBranch) {
1326  DPRINTF(Fetch, "[tid:%i] Done fetching, predicted branch "
1327  "instruction encountered.\n", tid);
1328  } else if (numInst >= fetchWidth) {
1329  DPRINTF(Fetch, "[tid:%i] Done fetching, reached fetch bandwidth "
1330  "for this cycle.\n", tid);
1331  } else if (blkOffset >= fetchBufferSize) {
1332  DPRINTF(Fetch, "[tid:%i] Done fetching, reached the end of the"
1333  "fetch buffer.\n", tid);
1334  }
1335 
1336  macroop[tid] = curMacroop;
1337  fetchOffset[tid] = pcOffset;
1338 
1339  if (numInst > 0) {
1340  wroteToTimeBuffer = true;
1341  }
1342 
1343  // pipeline a fetch if we're crossing a fetch buffer boundary and not in
1344  // a state that would preclude fetching
1345  fetchAddr = (this_pc.instAddr() + pcOffset) & pc_mask;
1346  Addr fetchBufferBlockPC = fetchBufferAlignPC(fetchAddr);
1347  issuePipelinedIfetch[tid] = fetchBufferBlockPC != fetchBufferPC[tid] &&
1348  fetchStatus[tid] != IcacheWaitResponse &&
1349  fetchStatus[tid] != ItlbWait &&
1350  fetchStatus[tid] != IcacheWaitRetry &&
1351  fetchStatus[tid] != QuiescePending &&
1352  !curMacroop;
1353 }
1354 
1355 void
1357 {
1358  if (retryPkt != NULL) {
1359  assert(cacheBlocked);
1360  assert(retryTid != InvalidThreadID);
1361  assert(fetchStatus[retryTid] == IcacheWaitRetry);
1362 
1365  // Notify Fetch Request probe when a retryPkt is successfully sent.
1366  // Note that notify must be called before retryPkt is set to NULL.
1368  retryPkt = NULL;
1370  cacheBlocked = false;
1371  }
1372  } else {
1373  assert(retryTid == InvalidThreadID);
1374  // Access has been squashed since it was sent out. Just clear
1375  // the cache being blocked.
1376  cacheBlocked = false;
1377  }
1378 }
1379 
1381 // //
1382 // SMT FETCH POLICY MAINTAINED HERE //
1383 // //
1385 ThreadID
1387 {
1388  if (numThreads > 1) {
1389  switch (fetchPolicy) {
1390  case SMTFetchPolicy::RoundRobin:
1391  return roundRobin();
1392  case SMTFetchPolicy::IQCount:
1393  return iqCount();
1394  case SMTFetchPolicy::LSQCount:
1395  return lsqCount();
1396  case SMTFetchPolicy::Branch:
1397  return branchCount();
1398  default:
1399  return InvalidThreadID;
1400  }
1401  } else {
1402  std::list<ThreadID>::iterator thread = activeThreads->begin();
1403  if (thread == activeThreads->end()) {
1404  return InvalidThreadID;
1405  }
1406 
1407  ThreadID tid = *thread;
1408 
1409  if (fetchStatus[tid] == Running ||
1411  fetchStatus[tid] == Idle) {
1412  return tid;
1413  } else {
1414  return InvalidThreadID;
1415  }
1416  }
1417 }
1418 
1419 
1420 ThreadID
1422 {
1423  std::list<ThreadID>::iterator pri_iter = priorityList.begin();
1425 
1426  ThreadID high_pri;
1427 
1428  while (pri_iter != end) {
1429  high_pri = *pri_iter;
1430 
1431  assert(high_pri <= numThreads);
1432 
1433  if (fetchStatus[high_pri] == Running ||
1434  fetchStatus[high_pri] == IcacheAccessComplete ||
1435  fetchStatus[high_pri] == Idle) {
1436 
1437  priorityList.erase(pri_iter);
1438  priorityList.push_back(high_pri);
1439 
1440  return high_pri;
1441  }
1442 
1443  pri_iter++;
1444  }
1445 
1446  return InvalidThreadID;
1447 }
1448 
1449 ThreadID
1451 {
1452  //sorted from lowest->highest
1453  std::priority_queue<unsigned, std::vector<unsigned>,
1454  std::greater<unsigned> > PQ;
1455  std::map<unsigned, ThreadID> threadMap;
1456 
1457  std::list<ThreadID>::iterator threads = activeThreads->begin();
1459 
1460  while (threads != end) {
1461  ThreadID tid = *threads++;
1462  unsigned iqCount = fromIEW->iewInfo[tid].iqCount;
1463 
1464  //we can potentially get tid collisions if two threads
1465  //have the same iqCount, but this should be rare.
1466  PQ.push(iqCount);
1467  threadMap[iqCount] = tid;
1468  }
1469 
1470  while (!PQ.empty()) {
1471  ThreadID high_pri = threadMap[PQ.top()];
1472 
1473  if (fetchStatus[high_pri] == Running ||
1474  fetchStatus[high_pri] == IcacheAccessComplete ||
1475  fetchStatus[high_pri] == Idle)
1476  return high_pri;
1477  else
1478  PQ.pop();
1479 
1480  }
1481 
1482  return InvalidThreadID;
1483 }
1484 
1485 ThreadID
1487 {
1488  //sorted from lowest->highest
1489  std::priority_queue<unsigned, std::vector<unsigned>,
1490  std::greater<unsigned> > PQ;
1491  std::map<unsigned, ThreadID> threadMap;
1492 
1493  std::list<ThreadID>::iterator threads = activeThreads->begin();
1495 
1496  while (threads != end) {
1497  ThreadID tid = *threads++;
1498  unsigned ldstqCount = fromIEW->iewInfo[tid].ldstqCount;
1499 
1500  //we can potentially get tid collisions if two threads
1501  //have the same iqCount, but this should be rare.
1502  PQ.push(ldstqCount);
1503  threadMap[ldstqCount] = tid;
1504  }
1505 
1506  while (!PQ.empty()) {
1507  ThreadID high_pri = threadMap[PQ.top()];
1508 
1509  if (fetchStatus[high_pri] == Running ||
1510  fetchStatus[high_pri] == IcacheAccessComplete ||
1511  fetchStatus[high_pri] == Idle)
1512  return high_pri;
1513  else
1514  PQ.pop();
1515  }
1516 
1517  return InvalidThreadID;
1518 }
1519 
1520 ThreadID
1522 {
1523  panic("Branch Count Fetch policy unimplemented\n");
1524  return InvalidThreadID;
1525 }
1526 
1527 void
1529 {
1530  if (!issuePipelinedIfetch[tid]) {
1531  return;
1532  }
1533 
1534  // The next PC to access.
1535  const PCStateBase &this_pc = *pc[tid];
1536 
1537  if (isRomMicroPC(this_pc.microPC())) {
1538  return;
1539  }
1540 
1541  Addr pcOffset = fetchOffset[tid];
1542  Addr fetchAddr = (this_pc.instAddr() + pcOffset) & decoder[tid]->pcMask();
1543 
1544  // Align the fetch PC so its at the start of a fetch buffer segment.
1545  Addr fetchBufferBlockPC = fetchBufferAlignPC(fetchAddr);
1546 
1547  // Unless buffer already got the block, fetch it from icache.
1548  if (!(fetchBufferValid[tid] && fetchBufferBlockPC == fetchBufferPC[tid])) {
1549  DPRINTF(Fetch, "[tid:%i] Issuing a pipelined I-cache access, "
1550  "starting at PC %s.\n", tid, this_pc);
1551 
1552  fetchCacheLine(fetchAddr, tid, this_pc.instAddr());
1553  }
1554 }
1555 
1556 void
1558 {
1559  DPRINTF(Fetch,"There are no more threads available to fetch from.\n");
1560 
1561  // @todo Per-thread stats
1562 
1563  if (stalls[tid].drain) {
1565  DPRINTF(Fetch, "Fetch is waiting for a drain!\n");
1566  } else if (activeThreads->empty()) {
1568  DPRINTF(Fetch, "Fetch has no active thread!\n");
1569  } else if (fetchStatus[tid] == Blocked) {
1571  DPRINTF(Fetch, "[tid:%i] Fetch is blocked!\n", tid);
1572  } else if (fetchStatus[tid] == Squashing) {
1574  DPRINTF(Fetch, "[tid:%i] Fetch is squashing!\n", tid);
1575  } else if (fetchStatus[tid] == IcacheWaitResponse) {
1577  DPRINTF(Fetch, "[tid:%i] Fetch is waiting cache response!\n",
1578  tid);
1579  } else if (fetchStatus[tid] == ItlbWait) {
1581  DPRINTF(Fetch, "[tid:%i] Fetch is waiting ITLB walk to "
1582  "finish!\n", tid);
1583  } else if (fetchStatus[tid] == TrapPending) {
1585  DPRINTF(Fetch, "[tid:%i] Fetch is waiting for a pending trap!\n",
1586  tid);
1587  } else if (fetchStatus[tid] == QuiescePending) {
1589  DPRINTF(Fetch, "[tid:%i] Fetch is waiting for a pending quiesce "
1590  "instruction!\n", tid);
1591  } else if (fetchStatus[tid] == IcacheWaitRetry) {
1593  DPRINTF(Fetch, "[tid:%i] Fetch is waiting for an I-cache retry!\n",
1594  tid);
1595  } else if (fetchStatus[tid] == NoGoodAddr) {
1596  DPRINTF(Fetch, "[tid:%i] Fetch predicted non-executable address\n",
1597  tid);
1598  } else {
1599  DPRINTF(Fetch, "[tid:%i] Unexpected fetch stall reason "
1600  "(Status: %i)\n",
1601  tid, fetchStatus[tid]);
1602  }
1603 }
1604 
1605 bool
1607 {
1608  DPRINTF(O3CPU, "Fetch unit received timing\n");
1609  // We shouldn't ever get a cacheable block in Modified state
1610  assert(pkt->req->isUncacheable() ||
1611  !(pkt->cacheResponding() && !pkt->hasSharers()));
1612  fetch->processCacheCompletion(pkt);
1613 
1614  return true;
1615 }
1616 
1617 void
1619 {
1620  fetch->recvReqRetry();
1621 }
1622 
1623 } // namespace o3
1624 } // namespace gem5
gem5::InstDecoder::moreBytes
virtual void moreBytes(const PCStateBase &pc, Addr fetchPC)=0
Feed data to the decoder.
gem5::curTick
Tick curTick()
The universal simulation clock.
Definition: cur_tick.hh:46
fatal
#define fatal(...)
This implements a cprintf based fatal() function.
Definition: logging.hh:190
gem5::o3::Fetch::FetchStatGroup::pendingQuiesceStallCycles
statistics::Scalar pendingQuiesceStallCycles
Total number of stall cycles caused by pending quiesce instructions.
Definition: fetch.hh:568
gem5::o3::Fetch::FetchStatus
FetchStatus
Overall fetch status.
Definition: fetch.hh:163
gem5::branch_prediction::BPredUnit::update
void update(const InstSeqNum &done_sn, ThreadID tid)
Tells the branch predictor to commit any updates until the given sequence number.
Definition: bpred_unit.cc:304
gem5::o3::Fetch::numFetchingThreads
ThreadID numFetchingThreads
Number of threads that are actively fetching.
Definition: fetch.hh:512
gem5::o3::Fetch::lookupAndUpdateNextPC
bool lookupAndUpdateNextPC(const DynInstPtr &inst, PCStateBase &pc)
Looks up in the branch predictor to see if the next PC should be either next PC+=MachInst or a branch...
Definition: fetch.cc:510
gem5::o3::Fetch::_status
FetchStatus _status
Fetch status.
Definition: fetch.hh:188
gem5::PCStateBase::instAddr
Addr instAddr() const
Returns the memory address of the instruction this PC points to.
Definition: pcstate.hh:107
gem5::o3::Fetch::fetchCacheLine
bool fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc)
Fetches the cache line that contains the fetch PC.
Definition: fetch.cc:554
gem5::o3::DynInst::Arrays
Definition: dyn_inst.hh:86
gem5::o3::Fetch::switchToInactive
void switchToInactive()
Changes the status of this stage to inactive, and indicates this to the CPU.
Definition: fetch.cc:488
gem5::branch_prediction::BPredUnit::predict
bool predict(const StaticInstPtr &inst, const InstSeqNum &seqNum, PCStateBase &pc, ThreadID tid)
Predicts whether or not the instruction is a taken branch, and the target of the branch if it is take...
Definition: bpred_unit.cc:131
gem5::ProbePointArg::notify
void notify(const Arg &arg)
called at the ProbePoint call site, passes arg to each listener.
Definition: probe.hh:313
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:253
gem5::o3::Fetch::FetchStatGroup::insts
statistics::Scalar insts
Stat for total number of fetched instructions.
Definition: fetch.hh:540
gem5::RequestPort::sendTimingReq
bool sendTimingReq(PacketPtr pkt)
Attempt to send a timing request to the responder port by calling its corresponding receive function.
Definition: port.hh:495
warn
#define warn(...)
Definition: logging.hh:246
gem5::o3::Fetch::pc
std::unique_ptr< PCStateBase > pc[MaxThreads]
Definition: fetch.hh:416
gem5::o3::Fetch::Fetch
Fetch(CPU *_cpu, const BaseO3CPUParams &params)
Fetch constructor.
Definition: fetch.cc:84
gem5::o3::CPU::removeInstsUntil
void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
Remove all instructions younger than the given sequence number.
Definition: cpu.cc:1298
system.hh
gem5::o3::Fetch::FetchStatGroup::blockedCycles
statistics::Scalar blockedCycles
Total number of cycles spent blocked.
Definition: fetch.hh:557
gem5::o3::CPU::mmu
BaseMMU * mmu
Definition: cpu.hh:111
gem5::TimeBuffer::getWire
wire getWire(int idx)
Definition: timebuf.hh:232
gem5::o3::Fetch::fetchBuffer
uint8_t * fetchBuffer[MaxThreads]
The fetch data that is being fetched and buffered.
Definition: fetch.hh:485
gem5::o3::Fetch::FetchStatGroup::pendingDrainCycles
statistics::Scalar pendingDrainCycles
Total number of cycles spent in waiting for drains.
Definition: fetch.hh:561
gem5::o3::Fetch::squash
void squash(const PCStateBase &new_pc, const InstSeqNum seq_num, DynInstPtr squashInst, ThreadID tid)
Squashes a specific thread and resets the PC.
Definition: fetch.cc:827
gem5::o3::Fetch::FetchStatGroup::miscStallCycles
statistics::Scalar miscStallCycles
Total number of cycles spent in any other state.
Definition: fetch.hh:559
gem5::o3::Fetch::profileStall
void profileStall(ThreadID tid)
Profile the reasons of fetch stall.
Definition: fetch.cc:1557
gem5::o3::Fetch::pipelineIcacheAccesses
void pipelineIcacheAccesses(ThreadID tid)
Pipeline the next I-cache access to the current one.
Definition: fetch.cc:1528
gem5::isRomMicroPC
static bool isRomMicroPC(MicroPC upc)
Definition: types.hh:166
gem5::o3::Fetch::IcachePort::recvReqRetry
virtual void recvReqRetry()
Handles doing a retry of a failed fetch.
Definition: fetch.cc:1618
gem5::Packet::req
RequestPtr req
A pointer to the original request.
Definition: packet.hh:374
gem5::o3::Fetch::branchPred
branch_prediction::BPredUnit * branchPred
BPredUnit.
Definition: fetch.hh:414
gem5::o3::DynInst::Arrays::numSrcs
size_t numSrcs
Definition: dyn_inst.hh:88
gem5::o3::Fetch::drainStall
void drainStall(ThreadID tid)
Stall the fetch stage after reaching a safe drain point.
Definition: fetch.cc:458
gem5::o3::Fetch::checkInterrupt
bool checkInterrupt(Addr pc)
Check if an interrupt is pending and that we need to handle.
Definition: fetch.hh:306
gem5::o3::Fetch::retryPkt
PacketPtr retryPkt
The packet that is waiting to be retried.
Definition: fetch.hh:468
gem5::o3::Fetch::iewToFetchDelay
Cycles iewToFetchDelay
IEW to fetch delay.
Definition: fetch.hh:453
gem5::ArmISA::set
Bitfield< 12, 11 > set
Definition: misc_types.hh:703
gem5::Request::INST_FETCH
@ INST_FETCH
The request was an instruction fetch.
Definition: request.hh:115
gem5::o3::Fetch::wakeFromQuiesce
void wakeFromQuiesce()
Tells fetch to wake up from a quiesce instruction.
Definition: fetch.cc:467
gem5::o3::Fetch::name
std::string name() const
Returns the name of fetch.
Definition: fetch.cc:149
gem5::o3::Fetch::processCacheCompletion
void processCacheCompletion(PacketPtr pkt)
Processes cache completion event.
Definition: fetch.cc:351
random.hh
tlb.hh
gem5::Packet::cacheResponding
bool cacheResponding() const
Definition: packet.hh:655
exetrace.hh
gem5::o3::CPU::getAndIncrementInstSeq
InstSeqNum getAndIncrementInstSeq()
Get the current instruction sequence number, and increment it.
Definition: cpu.hh:282
gem5::o3::Fetch::setActiveThreads
void setActiveThreads(std::list< ThreadID > *at_ptr)
Sets pointer to list of active threads.
Definition: fetch.cc:274
gem5::Packet::hasSharers
bool hasSharers() const
Definition: packet.hh:682
gem5::o3::Fetch::FetchStatGroup::nisnDist
statistics::Distribution nisnDist
Distribution of number of instructions fetched each cycle.
Definition: fetch.hh:582
gem5::o3::Fetch::delayedCommit
bool delayedCommit[MaxThreads]
Can the fetch stage redirect from an interrupt on this instruction?
Definition: fetch.hh:423
gem5::o3::Fetch::FetchStatGroup::cacheLines
statistics::Scalar cacheLines
Stat for total number of fetched cache lines.
Definition: fetch.hh:572
gem5::o3::Fetch::Idle
@ Idle
Definition: fetch.hh:173
gem5::o3::Fetch::FetchTranslation
Definition: fetch.hh:105
gem5::PCStateBase::microPC
MicroPC microPC() const
Returns the current micropc.
Definition: pcstate.hh:118
gem5::o3::Fetch::fetchWidth
unsigned fetchWidth
The width of fetch in instructions.
Definition: fetch.hh:459
dyn_inst.hh
gem5::o3::Fetch::clearStates
void clearStates(ThreadID tid)
Clear all thread-specific states.
Definition: fetch.cc:298
gem5::o3::Fetch
Fetch class handles both single threaded and SMT fetch.
Definition: fetch.hh:79
gem5::pseudo_inst::quiesce
void quiesce(ThreadContext *tc)
Definition: pseudo_inst.cc:118
gem5::o3::Fetch::numInst
int numInst
Tracks how many instructions has been fetched this cycle.
Definition: fetch.hh:434
gem5::o3::Fetch::retryTid
ThreadID retryTid
The thread that is waiting on the cache to tell fetch to retry.
Definition: fetch.hh:471
gem5::o3::Fetch::isDrained
bool isDrained() const
Has the stage drained?
Definition: fetch.cc:420
gem5::o3::Fetch::macroop
StaticInstPtr macroop[MaxThreads]
Definition: fetch.hh:420
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:67
gem5::o3::Fetch::getFetchingThread
ThreadID getFetchingThread()
Returns the appropriate thread to fetch, given the fetch policy.
Definition: fetch.cc:1386
gem5::statistics::DistBase::sample
void sample(const U &v, int n=1)
Add a value to the distribtion n times.
Definition: statistics.hh:1328
gem5::o3::Fetch::fetchStats
gem5::o3::Fetch::FetchStatGroup fetchStats
gem5::o3::Fetch::Blocked
@ Blocked
Definition: fetch.hh:175
gem5::o3::Fetch::decoder
InstDecoder * decoder[MaxThreads]
The decoder.
Definition: fetch.hh:359
gem5::o3::Fetch::Active
@ Active
Definition: fetch.hh:165
gem5::o3::Fetch::FetchStatGroup::idleCycles
statistics::Scalar idleCycles
Stat for total number of cycles spent blocked due to other stages in the pipeline.
Definition: fetch.hh:555
gem5::o3::CPU::ppInstAccessComplete
ProbePointArg< PacketPtr > * ppInstAccessComplete
Definition: cpu.hh:174
gem5::BaseMMU::Execute
@ Execute
Definition: mmu.hh:56
gem5::o3::Fetch::Squashing
@ Squashing
Definition: fetch.hh:174
gem5::o3::Fetch::IcacheWaitRetry
@ IcacheWaitRetry
Definition: fetch.hh:181
gem5::o3::Fetch::FetchStatGroup::pendingTrapStallCycles
statistics::Scalar pendingTrapStallCycles
Total number of stall cycles caused by pending traps.
Definition: fetch.hh:565
gem5::RefCountingPtr< DynInst >
gem5::Random::random
std::enable_if_t< std::is_integral_v< T >, T > random()
Use the SFINAE idiom to choose an implementation based on whether the type is integral or floating po...
Definition: random.hh:90
gem5::o3::Fetch::ppFetchRequestSent
ProbePointArg< RequestPtr > * ppFetchRequestSent
To probe when a fetch request is successfully sent.
Definition: fetch.hh:202
gem5::TimeBuffer
Definition: timebuf.hh:40
packet.hh
gem5::RequestPort
A RequestPort is a specialisation of a Port, which implements the default protocol for the three diff...
Definition: port.hh:77
gem5::o3::Fetch::FinishTranslationEvent::setFault
void setFault(Fault _fault)
Definition: fetch.hh:141
gem5::o3::Fetch::FetchStatGroup::tlbCycles
statistics::Scalar tlbCycles
Stat for total number of cycles spent waiting for translation.
Definition: fetch.hh:550
gem5::StaticInst::fetchMicroop
virtual StaticInstPtr fetchMicroop(MicroPC upc) const
Return the microop that goes with a particular micropc.
Definition: static_inst.cc:39
gem5::Cycles
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:78
gem5::o3::CPU::deactivateStage
void deactivateStage(const StageIdx idx)
Changes a stage's status to inactive within the activity recorder.
Definition: cpu.hh:497
gem5::o3::Fetch::FetchStatGroup::icacheStallCycles
statistics::Scalar icacheStallCycles
Stat for total number of cycles stalled due to an icache miss.
Definition: fetch.hh:538
gem5::o3::Fetch::QuiescePending
@ QuiescePending
Definition: fetch.hh:178
gem5::statistics::pdf
const FlagsType pdf
Print the percent of the total that this entry represents.
Definition: info.hh:62
gem5::o3::Fetch::drainSanityCheck
void drainSanityCheck() const
Perform sanity checks after a drain.
Definition: fetch.cc:403
gem5::o3::Fetch::lastIcacheStall
Counter lastIcacheStall[MaxThreads]
Icache stall statistics.
Definition: fetch.hh:503
gem5::PCStateBase::branching
virtual bool branching() const =0
gem5::o3::Fetch::drainResume
void drainResume()
Resume after a drain.
Definition: fetch.cc:394
nop_static_inst.hh
gem5::o3::Fetch::fromDecode
TimeBuffer< TimeStruct >::wire fromDecode
Wire to get decode's information from backwards time buffer.
Definition: fetch.hh:398
gem5::o3::Fetch::fetchBufferSize
unsigned fetchBufferSize
The size of the fetch buffer in bytes.
Definition: fetch.hh:479
gem5::o3::Fetch::FetchStatGroup::tlbSquashes
statistics::Scalar tlbSquashes
Total number of outstanding tlb accesses that were dropped due to a squash.
Definition: fetch.hh:580
gem5::o3::Fetch::priorityList
std::list< ThreadID > priorityList
List that has the threads organized by priority.
Definition: fetch.hh:197
gem5::o3::Fetch::fromIEW
TimeBuffer< TimeStruct >::wire fromIEW
Wire to get iew's information from backwards time buffer.
Definition: fetch.hh:404
gem5::o3::Fetch::IcacheAccessComplete
@ IcacheAccessComplete
Definition: fetch.hh:182
gem5::o3::Fetch::commitToFetchDelay
Cycles commitToFetchDelay
Commit to fetch delay.
Definition: fetch.hh:456
gem5::o3::CPU
O3CPU class, has each of the stages (fetch through commit) within it, as well as all of the time buff...
Definition: cpu.hh:94
gem5::o3::Fetch::fetch
void fetch(bool &status_change)
Does the actual fetching of instructions and passing them on to the next stage.
Definition: fetch.cc:1096
gem5::o3::CPU::getInstPort
Port & getInstPort() override
Used by the fetch unit to get a hold of the instruction port.
Definition: cpu.hh:562
gem5::statistics::Distribution::init
Distribution & init(Counter min, Counter max, Counter bkt)
Set the parameters of this distribution.
Definition: statistics.hh:2113
gem5::o3::Fetch::FetchStatGroup::branches
statistics::Scalar branches
Total number of fetched branches.
Definition: fetch.hh:542
gem5::System::isMemAddr
bool isMemAddr(Addr addr) const
Check if a physical address is within a range of a memory that is part of the global address map.
Definition: system.cc:299
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:248
gem5::o3::Fetch::checkStall
bool checkStall(ThreadID tid) const
Checks if a thread is stalled.
Definition: fetch.cc:774
gem5::o3::Fetch::finishTranslationEvent
FinishTranslationEvent finishTranslationEvent
Event used to delay fault generation of translation faults.
Definition: fetch.hh:529
gem5::o3::Fetch::stalls
Stalls stalls[MaxThreads]
Tracks which stages are telling fetch to stall.
Definition: fetch.hh:444
gem5::o3::Fetch::wroteToTimeBuffer
bool wroteToTimeBuffer
Variable that tracks if fetch has written to the time buffer this cycle.
Definition: fetch.hh:431
gem5::o3::Fetch::recvReqRetry
void recvReqRetry()
Handles retrying the fetch access.
Definition: fetch.cc:1356
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::o3::Fetch::roundRobin
ThreadID roundRobin()
Returns the appropriate thread to fetch using a round robin policy.
Definition: fetch.cc:1421
gem5::o3::Fetch::fetchBufferAlignPC
Addr fetchBufferAlignPC(Addr addr)
Align a PC to the start of a fetch buffer block.
Definition: fetch.hh:353
ADD_STAT
#define ADD_STAT(n,...)
Convenience macro to add a stat to a statistics group.
Definition: group.hh:75
gem5::o3::Fetch::squashFromDecode
void squashFromDecode(const PCStateBase &new_pc, const DynInstPtr squashInst, const InstSeqNum seq_num, ThreadID tid)
Squashes a specific thread and resets the PC.
Definition: fetch.cc:761
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:291
gem5::o3::Fetch::lsqCount
ThreadID lsqCount()
Returns the appropriate thread to fetch using the LSQ count policy.
Definition: fetch.cc:1486
gem5::probing::Packet
ProbePointArg< PacketInfo > Packet
Packet probe point.
Definition: mem.hh:109
gem5::o3::CPU::pcState
void pcState(const PCStateBase &new_pc_state, ThreadID tid)
Sets the commit PC state of a specific thread.
Definition: cpu.cc:1201
gem5::o3::Fetch::setTimeBuffer
void setTimeBuffer(TimeBuffer< TimeStruct > *time_buffer)
Sets the main backwards communication time buffer pointer.
Definition: fetch.cc:262
gem5::o3::CPU::FetchIdx
@ FetchIdx
Definition: cpu.hh:454
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::o3::Fetch::FinishTranslationEvent::setReq
void setReq(const RequestPtr &_req)
Definition: fetch.hh:142
gem5::Packet::getConstPtr
const T * getConstPtr() const
Definition: packet.hh:1206
gem5::MemCmd::ReadReq
@ ReadReq
Definition: packet.hh:86
gem5::o3::CPU::activateStage
void activateStage(const StageIdx idx)
Changes a stage's status to active within the activity recorder.
Definition: cpu.hh:490
gem5::o3::CPU::tcBase
gem5::ThreadContext * tcBase(ThreadID tid)
Returns a pointer to a thread context.
Definition: cpu.hh:513
gem5::o3::Fetch::fetchBufferValid
bool fetchBufferValid[MaxThreads]
Whether or not the fetch buffer data is valid.
Definition: fetch.hh:497
gem5::o3::Fetch::threadFetched
ThreadID threadFetched
Thread ID being fetched.
Definition: fetch.hh:515
gem5::o3::CPU::thread
std::vector< ThreadState * > thread
Pointers to all of the threads in the CPU.
Definition: cpu.hh:531
gem5::o3::Fetch::deactivateThread
void deactivateThread(ThreadID tid)
For priority-based fetch policies, need to keep update priorityList.
Definition: fetch.cc:500
gem5::branch_prediction::BPredUnit::drainSanityCheck
void drainSanityCheck() const
Perform sanity checks after a drain.
Definition: bpred_unit.cc:122
gem5::o3::Fetch::ItlbWait
@ ItlbWait
Definition: fetch.hh:179
gem5::InvalidThreadID
const ThreadID InvalidThreadID
Definition: types.hh:236
gem5::o3::CPU::wakeCPU
void wakeCPU()
Wakes the CPU, rescheduling the CPU if it's not already active.
Definition: cpu.cc:1397
gem5::o3::Fetch::cpu
CPU * cpu
Pointer to the O3CPU.
Definition: fetch.hh:392
gem5::o3::Fetch::FetchStatGroup::cycles
statistics::Scalar cycles
Stat for total number of cycles spent fetching.
Definition: fetch.hh:546
gem5::Port::isConnected
bool isConnected() const
Is this port currently connected to a peer?
Definition: port.hh:133
gem5::o3::MaxWidth
static constexpr int MaxWidth
Definition: limits.hh:37
gem5::o3::Fetch::FetchStatGroup::squashCycles
statistics::Scalar squashCycles
Stat for total number of cycles spent squashing.
Definition: fetch.hh:548
gem5::o3::Fetch::switchToActive
void switchToActive()
Changes the status of this stage to active, and indicates this to the CPU.
Definition: fetch.cc:476
gem5::o3::Fetch::Running
@ Running
Definition: fetch.hh:172
gem5::InstDecoder::reset
virtual void reset()
Definition: decoder.hh:63
gem5::o3::Fetch::FetchStatGroup::rate
statistics::Formula rate
Number of instruction fetched per cycle.
Definition: fetch.hh:588
gem5::o3::Fetch::instSize
int instSize
Size of instructions.
Definition: fetch.hh:500
gem5::branch_prediction::BPredUnit::squash
void squash(const InstSeqNum &squashed_sn, ThreadID tid)
Squashes all outstanding updates until a given sequence number.
Definition: bpred_unit.cc:327
fetch.hh
gem5::o3::Fetch::timeBuffer
TimeBuffer< TimeStruct > * timeBuffer
Time buffer interface.
Definition: fetch.hh:395
gem5::o3::Fetch::fetchQueue
std::deque< DynInstPtr > fetchQueue[MaxThreads]
Queue of fetched instructions.
Definition: fetch.hh:494
gem5::o3::Fetch::tick
void tick()
Ticks the fetch stage, processing all inputs signals and fetching as many instructions as possible.
Definition: fetch.cc:839
gem5::o3::Fetch::interruptPending
bool interruptPending
Checks if there is an interrupt pending.
Definition: fetch.hh:520
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::o3::Fetch::FetchStatGroup::icacheSquashes
statistics::Scalar icacheSquashes
Total number of outstanding icache accesses that were dropped due to a squash.
Definition: fetch.hh:576
gem5::o3::Fetch::FetchStatGroup::branchRate
statistics::Formula branchRate
Number of branch fetches per cycle.
Definition: fetch.hh:586
name
const std::string & name()
Definition: trace.cc:49
gem5::StaticInst::isLastMicroop
bool isLastMicroop() const
Definition: static_inst.hh:188
gem5::o3::Fetch::resetStage
void resetStage()
Reset this pipeline stage.
Definition: fetch.cc:317
gem5::o3::Fetch::updateFetchStatus
FetchStatus updateFetchStatus()
Updates overall fetch stage status; to be called at the end of each cycle.
Definition: fetch.cc:788
gem5::BaseMMU::translateTiming
virtual void translateTiming(const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode)
Definition: mmu.cc:111
gem5::o3::Fetch::cacheBlocked
bool cacheBlocked
Is the cache blocked? If so no threads can access it.
Definition: fetch.hh:465
full_system.hh
gem5::o3::Fetch::decodeToFetchDelay
Cycles decodeToFetchDelay
Decode to fetch delay.
Definition: fetch.hh:447
gem5::o3::Fetch::checkSignalsAndUpdate
bool checkSignalsAndUpdate(ThreadID tid)
Checks all input signals and updates the status as necessary.
Definition: fetch.cc:941
gem5::o3::Fetch::startupStage
void startupStage()
Initialize stage.
Definition: fetch.cc:287
gem5::ProbePointArg
ProbePointArg generates a point for the class of Arg.
Definition: thermal_domain.hh:54
gem5::o3::CPU::system
System * system
Pointer to the system.
Definition: cpu.hh:528
gem5::FullSystem
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:220
gem5::InstDecoder::moreBytesSize
size_t moreBytesSize() const
Definition: decoder.hh:96
gem5::o3::Fetch::decodeWidth
unsigned decodeWidth
The width of decode in instructions.
Definition: fetch.hh:462
gem5::o3::MaxThreads
static constexpr int MaxThreads
Definition: limits.hh:38
gem5::o3::Fetch::ppFetch
ProbePointArg< DynInstPtr > * ppFetch
Probe points.
Definition: fetch.hh:200
gem5::InstDecoder::pcMask
Addr pcMask() const
Definition: decoder.hh:97
gem5::o3::CPU::activityThisCycle
void activityThisCycle()
Records that there was time buffer activity this cycle.
Definition: cpu.hh:486
gem5::o3::CPU::removeInstsNotInROB
void removeInstsNotInROB(ThreadID tid)
Remove all instructions that are not currently in the ROB.
Definition: cpu.cc:1254
gem5::o3::Fetch::toDecode
TimeBuffer< FetchStruct >::wire toDecode
Wire used to write any information heading to decode.
Definition: fetch.hh:411
gem5::o3::Fetch::iqCount
ThreadID iqCount()
Returns the appropriate thread to fetch using the IQ count policy.
Definition: fetch.cc:1450
gem5::nopStaticInstPtr
StaticInstPtr nopStaticInstPtr
Pointer to a statically allocated generic "nop" instruction object.
Definition: nop_static_inst.cc:67
base.hh
gem5::statistics::DataWrap::prereq
Derived & prereq(const Stat &prereq)
Set the prerequisite stat and marks this stat to print at the end of simulation.
Definition: statistics.hh:372
types.hh
gem5::o3::Fetch::FetchStatGroup::noActiveThreadStallCycles
statistics::Scalar noActiveThreadStallCycles
Total number of stall cycles caused by no active threads to run.
Definition: fetch.hh:563
gem5::o3::Fetch::issuePipelinedIfetch
bool issuePipelinedIfetch[MaxThreads]
Set to true if a pipelined I-cache request should be issued.
Definition: fetch.hh:526
gem5::o3::Fetch::fetchPolicy
SMTFetchPolicy fetchPolicy
Fetch policy.
Definition: fetch.hh:194
gem5::o3::Fetch::fromRename
TimeBuffer< TimeStruct >::wire fromRename
Wire to get rename's information from backwards time buffer.
Definition: fetch.hh:401
gem5::o3::Fetch::takeOverFrom
void takeOverFrom()
Takes over from another CPU's thread.
Definition: fetch.cc:450
core.hh
gem5::StaticInst::isMacroop
bool isMacroop() const
Definition: static_inst.hh:185
gem5::o3::CPU::addInst
ListIt addInst(const DynInstPtr &inst)
Function to add instruction onto the head of the list of the instructions.
Definition: cpu.cc:1214
gem5::Packet::dataDynamic
void dataDynamic(T *p)
Set the data pointer to a value that should have delete [] called on it.
Definition: packet.hh:1185
gem5::o3::Fetch::activeThreads
std::list< ThreadID > * activeThreads
List of Active Threads.
Definition: fetch.hh:506
gem5::StaticInst::numDestRegs
uint8_t numDestRegs() const
Number of destination registers.
Definition: static_inst.hh:125
gem5::o3::Fetch::fetchBufferPC
Addr fetchBufferPC[MaxThreads]
The PC of the first instruction loaded into the fetch buffer.
Definition: fetch.hh:488
gem5::o3::CPU::isDraining
bool isDraining() const
Is the CPU draining?
Definition: cpu.hh:236
gem5::statistics::Group
Statistics container.
Definition: group.hh:93
gem5::o3::Fetch::NoGoodAddr
@ NoGoodAddr
Definition: fetch.hh:183
gem5::InstSeqNum
uint64_t InstSeqNum
Definition: inst_seq.hh:40
gem5::o3::Fetch::fromCommit
TimeBuffer< TimeStruct >::wire fromCommit
Wire to get commit's information from backwards time buffer.
Definition: fetch.hh:407
gem5::o3::Fetch::finishTranslation
void finishTranslation(const Fault &fault, const RequestPtr &mem_req)
Definition: fetch.cc:603
gem5::StaticInst::numSrcRegs
uint8_t numSrcRegs() const
Number of source registers.
Definition: static_inst.hh:123
gem5::o3::Fetch::Stalls::decode
bool decode
Definition: fetch.hh:439
gem5::o3::Fetch::fetchBufferMask
Addr fetchBufferMask
Mask to align a fetch address to a fetch buffer boundary.
Definition: fetch.hh:482
gem5::o3::Fetch::IcachePort::IcachePort
IcachePort(Fetch *_fetch, CPU *_cpu)
Default constructor.
Definition: fetch.cc:79
gem5::o3::Fetch::FetchStatGroup::icacheWaitRetryStallCycles
statistics::Scalar icacheWaitRetryStallCycles
Total number of stall cycles caused by I-cache wait retrys.
Definition: fetch.hh:570
gem5::o3::Fetch::regProbePoints
void regProbePoints()
Registers probes.
Definition: fetch.cc:152
gem5::o3::Fetch::buildInst
DynInstPtr buildInst(ThreadID tid, StaticInstPtr staticInst, StaticInstPtr curMacroop, const PCStateBase &this_pc, const PCStateBase &next_pc, bool trace)
Definition: fetch.cc:1043
gem5::o3::Fetch::Inactive
@ Inactive
Definition: fetch.hh:166
gem5::o3::Fetch::icachePort
IcachePort icachePort
Instruction port.
Definition: fetch.hh:523
gem5::statistics::DataWrap::flags
Derived & flags(Flags _flags)
Set the flags and marks this stat to print at the end of simulation.
Definition: statistics.hh:358
gem5::MipsISA::vaddr
vaddr
Definition: pra_constants.hh:278
gem5::PCStateBase
Definition: pcstate.hh:57
cpu.hh
std::list< ThreadID >
gem5::o3::Fetch::setFetchQueue
void setFetchQueue(TimeBuffer< FetchStruct > *fq_ptr)
Sets pointer to time buffer used to communicate to the next stage.
Definition: fetch.cc:280
gem5::o3::Fetch::Stalls::drain
bool drain
Definition: fetch.hh:440
gem5::o3::Fetch::fetchQueueSize
unsigned fetchQueueSize
The size of the fetch queue in micro-ops.
Definition: fetch.hh:491
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::o3::Fetch::branchCount
ThreadID branchCount()
Returns the appropriate thread to fetch using the branch count policy.
Definition: fetch.cc:1521
gem5::statistics::total
const FlagsType total
Print the total.
Definition: info.hh:60
limits.hh
gem5::o3::Fetch::TrapPending
@ TrapPending
Definition: fetch.hh:177
gem5::o3::Fetch::fetchOffset
Addr fetchOffset[MaxThreads]
Definition: fetch.hh:418
gem5::o3::DynInst::Arrays::numDests
size_t numDests
Definition: dyn_inst.hh:89
gem5::o3::Fetch::FetchStatGroup::idleRate
statistics::Formula idleRate
Rate of how often fetch was idle.
Definition: fetch.hh:584
gem5::o3::Fetch::FetchStatGroup::predictedBranches
statistics::Scalar predictedBranches
Stat for total number of predicted branches.
Definition: fetch.hh:544
gem5::random_mt
Random random_mt
Definition: random.cc:99
gem5::o3::Fetch::memReq
RequestPtr memReq[MaxThreads]
Memory request used to access cache.
Definition: fetch.hh:426
gem5::o3::Fetch::doSquash
void doSquash(const PCStateBase &new_pc, const DynInstPtr squashInst, ThreadID tid)
Squashes a specific thread and resets the PC.
Definition: fetch.cc:710
gem5::o3::Fetch::numThreads
ThreadID numThreads
Number of threads.
Definition: fetch.hh:509
gem5::o3::Fetch::cacheBlkSize
unsigned int cacheBlkSize
Cache block size.
Definition: fetch.hh:474
gem5::o3::Fetch::FetchStatGroup::FetchStatGroup
FetchStatGroup(CPU *cpu, Fetch *fetch)
Definition: fetch.cc:160
gem5::o3::Fetch::fetchStatus
ThreadStatus fetchStatus[MaxThreads]
Per-thread status.
Definition: fetch.hh:191
gem5::PCStateBase::clone
virtual PCStateBase * clone() const =0
gem5::o3::Fetch::renameToFetchDelay
Cycles renameToFetchDelay
Rename to fetch delay.
Definition: fetch.hh:450
gem5::Event::scheduled
bool scheduled() const
Determine if the current event is scheduled.
Definition: eventq.hh:465
gem5::ThreadID
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:235
gem5::o3::DynInst
Definition: dyn_inst.hh:76
byteswap.hh
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
gem5::o3::Fetch::IcacheWaitResponse
@ IcacheWaitResponse
Definition: fetch.hh:180
gem5::o3::Fetch::IcachePort::recvTimingResp
virtual bool recvTimingResp(PacketPtr pkt)
Timing version of receive.
Definition: fetch.cc:1606
eventq.hh

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