58#include "debug/Activity.hh"
59#include "debug/Drain.hh"
60#include "debug/Fetch.hh"
61#include "debug/O3CPU.hh"
62#include "debug/O3PipeView.hh"
64#include "params/BaseO3CPU.hh"
104 fatal(
"numThreads (%d) is larger than compiled limit (%d),\n"
105 "\tincrease MaxThreads in src/cpu/o3/limits.hh\n",
108 fatal(
"fetchWidth (%d) is larger than compiled limit (%d),\n"
109 "\tincrease MaxWidth in src/cpu/o3/limits.hh\n",
112 fatal(
"fetch buffer size (%u bytes) is greater than the cache "
115 fatal(
"cache block (%u bytes) is not a multiple of the "
121 pc[
i].
reset(params.isa[0]->newPCState());
137 decoder[tid] = params.decoder[tid];
159 : statistics::
Group(cpu,
"fetch"),
160 ADD_STAT(predictedBranches, statistics::units::Count::get(),
161 "Number of branches that fetch has predicted taken"),
162 ADD_STAT(cycles, statistics::units::Cycle::get(),
163 "Number of cycles fetch has run and was not squashing or "
165 ADD_STAT(squashCycles, statistics::units::Cycle::get(),
166 "Number of cycles fetch has spent squashing"),
167 ADD_STAT(tlbCycles, statistics::units::Cycle::get(),
168 "Number of cycles fetch has spent waiting for tlb"),
169 ADD_STAT(idleCycles, statistics::units::Cycle::get(),
170 "Number of cycles fetch was idle"),
171 ADD_STAT(blockedCycles, statistics::units::Cycle::get(),
172 "Number of cycles fetch has spent blocked"),
173 ADD_STAT(miscStallCycles, statistics::units::Cycle::get(),
174 "Number of cycles fetch has spent waiting on interrupts, or bad "
175 "addresses, or out of MSHRs"),
176 ADD_STAT(pendingDrainCycles, statistics::units::Cycle::get(),
177 "Number of cycles fetch has spent waiting on pipes to drain"),
178 ADD_STAT(noActiveThreadStallCycles, statistics::units::Cycle::get(),
179 "Number of stall cycles due to no active thread to fetch from"),
180 ADD_STAT(pendingTrapStallCycles, statistics::units::Cycle::get(),
181 "Number of stall cycles due to pending traps"),
182 ADD_STAT(pendingQuiesceStallCycles, statistics::units::Cycle::get(),
183 "Number of stall cycles due to pending quiesce instructions"),
184 ADD_STAT(icacheWaitRetryStallCycles, statistics::units::Cycle::get(),
185 "Number of stall cycles due to full MSHR"),
186 ADD_STAT(cacheLines, statistics::units::Count::get(),
187 "Number of cache lines fetched"),
188 ADD_STAT(icacheSquashes, statistics::units::Count::get(),
189 "Number of outstanding Icache misses that were squashed"),
190 ADD_STAT(tlbSquashes, statistics::units::Count::get(),
191 "Number of outstanding ITLB misses that were squashed"),
192 ADD_STAT(nisnDist, statistics::units::Count::get(),
193 "Number of instructions fetched each cycle (Total)"),
194 ADD_STAT(idleRate, statistics::units::Ratio::get(),
195 "Ratio of cycles fetch was idle",
196 idleCycles / cpu->baseStats.numCycles)
330 DPRINTF(
Fetch,
"[tid:%i] Waking up from cache miss.\n", tid);
349 DPRINTF(Activity,
"[tid:%i] Activating fetch due to cache completion\n",
361 pkt->
req->setAccessLatency();
436 assert(!
stalls[tid].drain);
437 DPRINTF(Drain,
"%i: Thread drained.\n", tid);
454 DPRINTF(Activity,
"Activating stage.\n");
466 DPRINTF(Activity,
"Deactivating stage.\n");
492 if (!inst->isControl()) {
493 inst->staticInst->advancePC(next_pc);
494 inst->setPredTarg(next_pc);
495 inst->setPredTaken(
false);
505 "predicted to be taken to %s\n",
506 tid, inst->seqNum, inst->pcState().instAddr(), next_pc);
509 "predicted to be not taken\n",
510 tid, inst->seqNum, inst->pcState().instAddr());
514 "predicted to go to %s\n",
515 tid, inst->seqNum, inst->pcState().instAddr(), next_pc);
516 inst->setPredTarg(next_pc);
517 inst->setPredTaken(predict_taken);
525 return predict_taken;
538 DPRINTF(
Fetch,
"[tid:%i] Can't fetch cache line, cache blocked\n",
546 DPRINTF(
Fetch,
"[tid:%i] Can't fetch cache line, interrupt pending\n",
554 DPRINTF(
Fetch,
"[tid:%i] Fetching cache line %#x for addr %#x\n",
555 tid, fetchBufferBlockPC,
vaddr);
560 RequestPtr mem_req = std::make_shared<Request>(
581 Addr fetchBufferBlockPC = mem_req->getVaddr();
589 mem_req->getVaddr() !=
memReq[tid]->getVaddr()) {
590 DPRINTF(
Fetch,
"[tid:%i] Ignoring itlb completed after squash\n",
603 warn(
"Address %#x is outside of physical memory, stopping fetch\n",
604 mem_req->getPaddr());
632 DPRINTF(Activity,
"[tid:%i] Activity: Waiting on I-cache "
652 "[tid:%i] Got back req with addr %#x but expected %#x\n",
653 tid, mem_req->getVaddr(),
memReq[tid]->getVaddr());
662 DPRINTF(
Fetch,
"[tid:%i] Translation faulted, building noop.\n", tid);
665 fetch_pc, fetch_pc,
false);
666 instruction->setNotAnInst();
668 instruction->setPredTarg(fetch_pc);
669 instruction->fault = fault;
672 DPRINTF(Activity,
"Activity this cycle.\n");
677 DPRINTF(
Fetch,
"[tid:%i] Blocked, need to handle the trap.\n", tid);
678 DPRINTF(
Fetch,
"[tid:%i] fault (%s) detected @ PC %s.\n",
679 tid, fault->
name(), *
pc[tid]);
688 DPRINTF(
Fetch,
"[tid:%i] Squashing, setting PC to: %s.\n",
691 set(
pc[tid], new_pc);
693 if (squashInst && squashInst->pcState().instAddr() == new_pc.
instAddr() &&
694 !squashInst->isLastMicroop())
695 macroop[tid] = squashInst->macroop;
702 DPRINTF(
Fetch,
"[tid:%i] Squashing outstanding Icache miss.\n",
706 DPRINTF(
Fetch,
"[tid:%i] Squashing outstanding ITLB miss.\n",
740 DPRINTF(
Fetch,
"[tid:%i] Squashing from decode.\n", tid);
752 bool ret_val =
false;
770 while (threads != end) {
778 DPRINTF(Activity,
"[tid:%i] Activating stage.\n",tid);
781 DPRINTF(Activity,
"[tid:%i] Activating fetch due to cache"
794 DPRINTF(Activity,
"Deactivating stage.\n");
819 bool status_change =
false;
827 while (threads != end) {
833 status_change = status_change || updated_status;
839 if (
fromCommit->commitInfo[0].interruptPending) {
843 if (
fromCommit->commitInfo[0].clearInterrupt) {
851 fetch(status_change);
871 unsigned insts_to_decode = 0;
872 unsigned available_insts = 0;
875 if (!
stalls[tid].decode) {
882 std::advance(tid_itr,
885 while (available_insts != 0 && insts_to_decode <
decodeWidth) {
890 DPRINTF(
Fetch,
"[tid:%i] [sn:%llu] Sending instruction to decode "
891 "from fetch queue. Fetch queue size: %i.\n",
908 DPRINTF(Activity,
"Activity this cycle.\n");
925 assert(
stalls[tid].decode);
933 DPRINTF(
Fetch,
"[tid:%i] Squashing instructions due to squash "
934 "from commit.\n",tid);
943 if (
fromCommit->commitInfo[tid].mispredictInst &&
944 fromCommit->commitInfo[tid].mispredictInst->isControl()) {
947 fromCommit->commitInfo[tid].branchTaken, tid);
954 }
else if (
fromCommit->commitInfo[tid].doneSeqNum) {
962 DPRINTF(
Fetch,
"[tid:%i] Squashing instructions due to squash "
963 "from decode.\n",tid);
966 if (
fromDecode->decodeInfo[tid].branchMispredict) {
969 fromDecode->decodeInfo[tid].branchTaken, tid);
1005 DPRINTF(
Fetch,
"[tid:%i] Done squashing, switching to running.\n",
1032 arrays, staticInst, curMacroop, this_pc, next_pc, seq,
cpu);
1033 instruction->setTid(tid);
1035 instruction->setThreadState(
cpu->
thread[tid]);
1037 DPRINTF(
Fetch,
"[tid:%i] Instruction PC %s created [sn:%lli].\n",
1041 instruction->staticInst->disassemble(this_pc.
instAddr()));
1045 instruction->traceData =
1047 instruction->staticInst, this_pc, curMacroop);
1050 instruction->traceData = NULL;
1054 instruction->setInstListIt(
cpu->
addInst(instruction));
1061 DPRINTF(
Fetch,
"[tid:%i] Fetch queue entry created (%i/%i).\n",
1092 DPRINTF(
Fetch,
"Attempting to fetch from [tid:%i]\n", tid);
1106 DPRINTF(
Fetch,
"[tid:%i] Icache miss is complete.\n", tid);
1109 status_change =
true;
1120 DPRINTF(
Fetch,
"[tid:%i] Attempting to translate and read "
1121 "instruction, starting at PC %s.\n", tid, this_pc);
1154 std::unique_ptr<PCStateBase> next_pc(this_pc.
clone());
1163 DPRINTF(
Fetch,
"[tid:%i] Adding instructions to queue to "
1168 bool predictedBranch =
false;
1171 bool quiesce =
false;
1183 && !predictedBranch && !quiesce) {
1187 bool needMem = !inRom && !curMacroop && !dec_ptr->instReady();
1188 fetchAddr = (this_pc.
instAddr() + pcOffset) & pc_mask;
1198 if (blkOffset >= numInsts) {
1204 memcpy(dec_ptr->moreBytesPtr(),
1208 if (dec_ptr->needMoreBytes()) {
1218 if (!(curMacroop || inRom)) {
1219 if (dec_ptr->instReady()) {
1220 staticInst = dec_ptr->decode(this_pc);
1226 curMacroop = staticInst;
1239 bool newMacro =
false;
1240 if (curMacroop || inRom) {
1242 staticInst = dec_ptr->fetchRomMicroop(
1243 this_pc.
microPC(), curMacroop);
1251 tid, staticInst, curMacroop, this_pc, *next_pc,
true);
1257 if (debug::O3PipeView) {
1258 instruction->fetchTick =
curTick();
1262 set(next_pc, this_pc);
1268 if (predictedBranch) {
1269 DPRINTF(
Fetch,
"Branch detected with PC = %s\n", this_pc);
1272 newMacro |= this_pc.
instAddr() != next_pc->instAddr();
1275 set(this_pc, *next_pc);
1279 fetchAddr = this_pc.
instAddr() & pc_mask;
1285 if (instruction->isQuiesce()) {
1287 "Quiesce instruction encountered, halting fetch!\n");
1289 status_change =
true;
1293 }
while ((curMacroop || dec_ptr->instReady()) &&
1302 if (predictedBranch) {
1303 DPRINTF(
Fetch,
"[tid:%i] Done fetching, predicted branch "
1304 "instruction encountered.\n", tid);
1306 DPRINTF(
Fetch,
"[tid:%i] Done fetching, reached fetch bandwidth "
1307 "for this cycle.\n", tid);
1309 DPRINTF(
Fetch,
"[tid:%i] Done fetching, reached the end of the"
1310 "fetch buffer.\n", tid);
1322 fetchAddr = (this_pc.
instAddr() + pcOffset) & pc_mask;
1367 case SMTFetchPolicy::RoundRobin:
1369 case SMTFetchPolicy::IQCount:
1371 case SMTFetchPolicy::LSQCount:
1373 case SMTFetchPolicy::Branch:
1405 while (pri_iter != end) {
1406 high_pri = *pri_iter;
1430 std::priority_queue<unsigned, std::vector<unsigned>,
1431 std::greater<unsigned> > PQ;
1432 std::map<unsigned, ThreadID> threadMap;
1437 while (threads != end) {
1447 while (!PQ.empty()) {
1448 ThreadID high_pri = threadMap[PQ.top()];
1466 std::priority_queue<unsigned, std::vector<unsigned>,
1467 std::greater<unsigned> > PQ;
1468 std::map<unsigned, ThreadID> threadMap;
1473 while (threads != end) {
1475 unsigned ldstqCount =
fromIEW->iewInfo[tid].ldstqCount;
1479 PQ.push(ldstqCount);
1480 threadMap[ldstqCount] = tid;
1483 while (!PQ.empty()) {
1484 ThreadID high_pri = threadMap[PQ.top()];
1500 panic(
"Branch Count Fetch policy unimplemented\n");
1526 DPRINTF(
Fetch,
"[tid:%i] Issuing a pipelined I-cache access, "
1527 "starting at PC %s.\n", tid, this_pc);
1536 DPRINTF(
Fetch,
"There are no more threads available to fetch from.\n");
1554 DPRINTF(
Fetch,
"[tid:%i] Fetch is waiting cache response!\n",
1558 DPRINTF(
Fetch,
"[tid:%i] Fetch is waiting ITLB walk to "
1562 DPRINTF(
Fetch,
"[tid:%i] Fetch is waiting for a pending trap!\n",
1566 DPRINTF(
Fetch,
"[tid:%i] Fetch is waiting for a pending quiesce "
1567 "instruction!\n", tid);
1570 DPRINTF(
Fetch,
"[tid:%i] Fetch is waiting for an I-cache retry!\n",
1573 DPRINTF(
Fetch,
"[tid:%i] Fetch predicted non-executable address\n",
1576 DPRINTF(
Fetch,
"[tid:%i] Unexpected fetch stall reason "
1585 DPRINTF(O3CPU,
"Fetch unit received timing\n");
1587 assert(pkt->
req->isUncacheable() ||
1589 fetch->processCacheCompletion(pkt);
1597 fetch->recvReqRetry();
Defines global host-dependent types: Counter, Tick, and (indirectly) {int,uint}{8,...
RequestorID instRequestorId() const
Reads this CPU's unique instruction requestor ID.
uint32_t taskId() const
Get cpu task id.
trace::InstTracer * getTracer()
Provide access to the tracer pointer.
std::vector< std::unique_ptr< FetchCPUStats > > fetchStats
ThreadID contextToThread(ContextID cid)
Convert ContextID to threadID.
bool switchedOut() const
Determine if the CPU is switched out.
virtual void translateTiming(const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode)
Tick clockEdge(Cycles cycles=Cycles(0)) const
Determine the tick when a cycle begins, by default the current one, but the argument also enables the...
Cycles is a wrapper class for representing cycle counts, i.e.
size_t moreBytesSize() const
virtual void moreBytes(const PCStateBase &pc, Addr fetchPC)=0
Feed data to the decoder.
virtual std::string name() const
virtual bool branching() const =0
MicroPC microPC() const
Returns the current micropc.
Addr instAddr() const
Returns the memory address of the instruction this PC points to.
virtual PCStateBase * clone() const =0
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
RequestPtr req
A pointer to the original request.
const T * getConstPtr() const
void dataDynamic(T *p)
Set the data pointer to a value that should have delete [] called on it.
bool cacheResponding() const
bool isConnected() const
Is this port currently connected to a peer?
ProbePointArg generates a point for the class of Arg.
void notify(const Arg &arg)
called at the ProbePoint call site, passes arg to each listener.
A RequestPort is a specialisation of a Port, which implements the default protocol for the three diff...
bool sendTimingReq(PacketPtr pkt)
Attempt to send a timing request to the responder port by calling its corresponding receive function.
@ INST_FETCH
The request was an instruction fetch.
uint8_t numSrcRegs() const
Number of source registers.
virtual StaticInstPtr fetchMicroop(MicroPC upc) const
Return the microop that goes with a particular micropc.
uint8_t numDestRegs() const
Number of destination registers.
bool isLastMicroop() const
bool isMemAddr(Addr addr) const
Check if a physical address is within a range of a memory that is part of the global address map.
void update(const InstSeqNum &done_sn, ThreadID tid)
Tells the branch predictor to commit any updates until the given sequence number.
bool predict(const StaticInstPtr &inst, const InstSeqNum &seqNum, PCStateBase &pc, ThreadID tid)
Predicts whether or not the instruction is a taken branch, and the target of the branch if it is take...
void drainSanityCheck() const
Perform sanity checks after a drain.
void squash(const InstSeqNum &squashed_sn, ThreadID tid)
Squashes all outstanding updates until a given sequence number.
O3CPU class, has each of the stages (fetch through commit) within it, as well as all of the time buff...
ListIt addInst(const DynInstPtr &inst)
Function to add instruction onto the head of the list of the instructions.
ProbePointArg< PacketPtr > * ppInstAccessComplete
std::vector< ThreadState * > thread
Pointers to all of the threads in the CPU.
void activityThisCycle()
Records that there was time buffer activity this cycle.
Port & getInstPort() override
Used by the fetch unit to get a hold of the instruction port.
void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
Remove all instructions younger than the given sequence number.
bool isDraining() const
Is the CPU draining?
void removeInstsNotInROB(ThreadID tid)
Remove all instructions that are not currently in the ROB.
void deactivateStage(const StageIdx idx)
Changes a stage's status to inactive within the activity recorder.
System * system
Pointer to the system.
InstSeqNum getAndIncrementInstSeq()
Get the current instruction sequence number, and increment it.
void pcState(const PCStateBase &new_pc_state, ThreadID tid)
Sets the commit PC state of a specific thread.
gem5::ThreadContext * tcBase(ThreadID tid)
Returns a pointer to a thread context.
void activateStage(const StageIdx idx)
Changes a stage's status to active within the activity recorder.
void wakeCPU()
Wakes the CPU, rescheduling the CPU if it's not already active.
void setReq(const RequestPtr &_req)
void setFault(Fault _fault)
virtual bool recvTimingResp(PacketPtr pkt)
Timing version of receive.
IcachePort(Fetch *_fetch, CPU *_cpu)
Default constructor.
virtual void recvReqRetry()
Handles doing a retry of a failed fetch.
Fetch class handles both single threaded and SMT fetch.
gem5::o3::Fetch::FetchStatGroup fetchStats
bool wroteToTimeBuffer
Variable that tracks if fetch has written to the time buffer this cycle.
void deactivateThread(ThreadID tid)
For priority-based fetch policies, need to keep update priorityList.
FetchStatus
Overall fetch status.
std::list< ThreadID > * activeThreads
List of Active Threads.
TimeBuffer< TimeStruct >::wire fromCommit
Wire to get commit's information from backwards time buffer.
Cycles renameToFetchDelay
Rename to fetch delay.
StaticInstPtr macroop[MaxThreads]
void fetch(bool &status_change)
Does the actual fetching of instructions and passing them on to the next stage.
void takeOverFrom()
Takes over from another CPU's thread.
uint8_t * fetchBuffer[MaxThreads]
The fetch data that is being fetched and buffered.
void doSquash(const PCStateBase &new_pc, const DynInstPtr squashInst, ThreadID tid)
Squashes a specific thread and resets the PC.
TimeBuffer< FetchStruct >::wire toDecode
Wire used to write any information heading to decode.
void setActiveThreads(std::list< ThreadID > *at_ptr)
Sets pointer to list of active threads.
bool lookupAndUpdateNextPC(const DynInstPtr &inst, PCStateBase &pc)
Looks up in the branch predictor to see if the next PC should be either next PC+=MachInst or a branch...
ThreadStatus fetchStatus[MaxThreads]
Per-thread status.
ThreadID numThreads
Number of threads.
TimeBuffer< TimeStruct >::wire fromDecode
Wire to get decode's information from backwards time buffer.
ProbePointArg< DynInstPtr > * ppFetch
Probe points.
TimeBuffer< TimeStruct >::wire fromRename
Wire to get rename's information from backwards time buffer.
void squash(const PCStateBase &new_pc, const InstSeqNum seq_num, DynInstPtr squashInst, ThreadID tid)
Squashes a specific thread and resets the PC.
void squashFromDecode(const PCStateBase &new_pc, const DynInstPtr squashInst, const InstSeqNum seq_num, ThreadID tid)
Squashes a specific thread and resets the PC.
FetchStatus updateFetchStatus()
Updates overall fetch stage status; to be called at the end of each cycle.
ThreadID getFetchingThread()
Returns the appropriate thread to fetch, given the fetch policy.
bool fetchBufferValid[MaxThreads]
Whether or not the fetch buffer data is valid.
void startupStage()
Initialize stage.
void pipelineIcacheAccesses(ThreadID tid)
Pipeline the next I-cache access to the current one.
std::string name() const
Returns the name of fetch.
void wakeFromQuiesce()
Tells fetch to wake up from a quiesce instruction.
void switchToActive()
Changes the status of this stage to active, and indicates this to the CPU.
void switchToInactive()
Changes the status of this stage to inactive, and indicates this to the CPU.
int numInst
Tracks how many instructions has been fetched this cycle.
bool fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc)
Fetches the cache line that contains the fetch PC.
Cycles decodeToFetchDelay
Decode to fetch delay.
bool issuePipelinedIfetch[MaxThreads]
Set to true if a pipelined I-cache request should be issued.
Addr fetchBufferAlignPC(Addr addr)
Align a PC to the start of a fetch buffer block.
FetchStatus _status
Fetch status.
bool delayedCommit[MaxThreads]
Can the fetch stage redirect from an interrupt on this instruction?
ThreadID threadFetched
Thread ID being fetched.
SMTFetchPolicy fetchPolicy
Fetch policy.
Addr cacheBlkSize
Cache block size.
branch_prediction::BPredUnit * branchPred
BPredUnit.
void drainSanityCheck() const
Perform sanity checks after a drain.
unsigned fetchWidth
The width of fetch in instructions.
unsigned fetchQueueSize
The size of the fetch queue in micro-ops.
InstDecoder * decoder[MaxThreads]
The decoder.
TimeBuffer< TimeStruct >::wire fromIEW
Wire to get iew's information from backwards time buffer.
void regProbePoints()
Registers probes.
bool checkSignalsAndUpdate(ThreadID tid)
Checks all input signals and updates the status as necessary.
bool checkStall(ThreadID tid) const
Checks if a thread is stalled.
IcachePort icachePort
Instruction port.
void setTimeBuffer(TimeBuffer< TimeStruct > *time_buffer)
Sets the main backwards communication time buffer pointer.
void processCacheCompletion(PacketPtr pkt)
Processes cache completion event.
ThreadID iqCount()
Returns the appropriate thread to fetch using the IQ count policy.
Addr fetchBufferMask
Mask to align a fetch address to a fetch buffer boundary.
void recvReqRetry()
Handles retrying the fetch access.
bool checkInterrupt(Addr pc)
Check if an interrupt is pending and that we need to handle.
Cycles iewToFetchDelay
IEW to fetch delay.
void resetStage()
Reset this pipeline stage.
Fetch(CPU *_cpu, const BaseO3CPUParams ¶ms)
Fetch constructor.
void drainStall(ThreadID tid)
Stall the fetch stage after reaching a safe drain point.
Counter lastIcacheStall[MaxThreads]
Icache stall statistics.
int instSize
Size of instructions.
ProbePointArg< RequestPtr > * ppFetchRequestSent
To probe when a fetch request is successfully sent.
Cycles commitToFetchDelay
Commit to fetch delay.
RequestPtr memReq[MaxThreads]
Memory request used to access cache.
TimeBuffer< TimeStruct > * timeBuffer
Time buffer interface.
void profileStall(ThreadID tid)
Profile the reasons of fetch stall.
ThreadID roundRobin()
Returns the appropriate thread to fetch using a round robin policy.
Addr fetchBufferPC[MaxThreads]
The PC of the first instruction loaded into the fetch buffer.
void drainResume()
Resume after a drain.
void clearStates(ThreadID tid)
Clear all thread-specific states.
void finishTranslation(const Fault &fault, const RequestPtr &mem_req)
bool interruptPending
Checks if there is an interrupt pending.
std::unique_ptr< PCStateBase > pc[MaxThreads]
ThreadID lsqCount()
Returns the appropriate thread to fetch using the LSQ count policy.
Stalls stalls[MaxThreads]
Tracks which stages are telling fetch to stall.
DynInstPtr buildInst(ThreadID tid, StaticInstPtr staticInst, StaticInstPtr curMacroop, const PCStateBase &this_pc, const PCStateBase &next_pc, bool trace)
bool isDrained() const
Has the stage drained?
Addr fetchOffset[MaxThreads]
std::deque< DynInstPtr > fetchQueue[MaxThreads]
Queue of fetched instructions.
PacketPtr retryPkt
The packet that is waiting to be retried.
std::list< ThreadID > priorityList
List that has the threads organized by priority.
FinishTranslationEvent finishTranslationEvent
Event used to delay fault generation of translation faults.
ThreadID retryTid
The thread that is waiting on the cache to tell fetch to retry.
void tick()
Ticks the fetch stage, processing all inputs signals and fetching as many instructions as possible.
ThreadID numFetchingThreads
Number of threads that are actively fetching.
unsigned fetchBufferSize
The size of the fetch buffer in bytes.
void setFetchQueue(TimeBuffer< FetchStruct > *fq_ptr)
Sets pointer to time buffer used to communicate to the next stage.
CPU * cpu
Pointer to the O3CPU.
unsigned decodeWidth
The width of decode in instructions.
bool cacheBlocked
Is the cache blocked? If so no threads can access it.
ThreadID branchCount()
Returns the appropriate thread to fetch using the branch count policy.
Derived & flags(Flags _flags)
Set the flags and marks this stat to print at the end of simulation.
Derived & prereq(const Stat &prereq)
Set the prerequisite stat and marks this stat to print at the end of simulation.
void sample(const U &v, int n=1)
Add a value to the distribtion n times.
Distribution & init(Counter min, Counter max, Counter bkt)
Set the parameters of this distribution.
virtual InstRecord * getInstRecord(Tick when, ThreadContext *tc, const StaticInstPtr staticInst, const PCStateBase &pc, const StaticInstPtr macroStaticInst=nullptr)=0
#define ADD_STAT(n,...)
Convenience macro to add a stat to a statistics group.
bool scheduled() const
Determine if the current event is scheduled.
void schedule(Event &event, Tick when)
#define panic(...)
This implements a cprintf based panic() function.
#define fatal(...)
This implements a cprintf based fatal() function.
ProbeManager * getProbeManager()
Get the probe manager for this object.
static constexpr int MaxThreads
static constexpr int MaxWidth
const FlagsType pdf
Print the percent of the total that this entry represents.
Copyright (c) 2024 Arm Limited All rights reserved.
std::shared_ptr< FaultBase > Fault
int16_t ThreadID
Thread index/ID type.
std::shared_ptr< Request > RequestPtr
const ThreadID InvalidThreadID
Tick curTick()
The universal simulation clock.
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
static bool isRomMicroPC(MicroPC upc)
StaticInstPtr nopStaticInstPtr
Pointer to a statically allocated generic "nop" instruction object.
constexpr decltype(nullptr) NoFault
Declaration of the Packet class.
statistics::Scalar icacheSquashes
Total number of outstanding icache accesses that were dropped due to a squash.
statistics::Scalar pendingDrainCycles
Total number of cycles spent in waiting for drains.
statistics::Scalar cacheLines
Stat for total number of fetched cache lines.
statistics::Scalar blockedCycles
Total number of cycles spent blocked.
statistics::Scalar idleCycles
Stat for total number of cycles spent blocked due to other stages in the pipeline.
statistics::Scalar predictedBranches
Stat for total number of predicted branches.
statistics::Scalar noActiveThreadStallCycles
Total number of stall cycles caused by no active threads to run.
statistics::Scalar pendingQuiesceStallCycles
Total number of stall cycles caused by pending quiesce instructions.
statistics::Scalar icacheWaitRetryStallCycles
Total number of stall cycles caused by I-cache wait retrys.
statistics::Scalar pendingTrapStallCycles
Total number of stall cycles caused by pending traps.
statistics::Scalar cycles
Stat for total number of cycles spent fetching.
statistics::Scalar miscStallCycles
Total number of cycles spent in any other state.
statistics::Scalar tlbCycles
Stat for total number of cycles spent waiting for translation.
statistics::Scalar squashCycles
Stat for total number of cycles spent squashing.
FetchStatGroup(CPU *cpu, Fetch *fetch)
statistics::Formula idleRate
Rate of how often fetch was idle.
statistics::Scalar tlbSquashes
Total number of outstanding tlb accesses that were dropped due to a squash.
statistics::Distribution nisnDist
Distribution of number of instructions fetched each cycle.
const std::string & name()