gem5  v21.1.0.2
scalar_memory_pipeline.cc
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33 
35 
36 #include "debug/GPUMem.hh"
37 #include "debug/GPUReg.hh"
41 #include "gpu-compute/shader.hh"
42 #include "gpu-compute/wavefront.hh"
43 
44 namespace gem5
45 {
46 
47 ScalarMemPipeline::ScalarMemPipeline(const ComputeUnitParams &p,
48  ComputeUnit &cu)
49  : computeUnit(cu), _name(cu.name() + ".ScalarMemPipeline"),
50  queueSize(p.scalar_mem_queue_size),
51  inflightStores(0), inflightLoads(0)
52 {
53 }
54 
55 void
57 {
58  // afind oldest scalar request whose data has arrived
59  GPUDynInstPtr m = !returnedLoads.empty() ? returnedLoads.front() :
60  !returnedStores.empty() ? returnedStores.front() : nullptr;
61 
62  Wavefront *w = nullptr;
63 
64  bool accessSrf = true;
65  // check the SRF to see if the operands of a load (or load component
66  // of an atomic) are accessible
67  if ((m) && (m->isLoad() || m->isAtomicRet())) {
68  w = m->wavefront();
69 
70  accessSrf =
71  w->computeUnit->srf[w->simdId]->
72  canScheduleWriteOperandsFromLoad(w, m);
73  }
74 
75  if ((!returnedStores.empty() || !returnedLoads.empty()) &&
76  m->latency.rdy() && computeUnit.scalarMemToSrfBus.rdy() &&
77  accessSrf &&
80 
81  w = m->wavefront();
82 
83  if (m->isLoad() || m->isAtomicRet()) {
84  w->computeUnit->srf[w->simdId]->
85  scheduleWriteOperandsFromLoad(w, m);
86  }
87 
88  m->completeAcc(m);
89  w->decLGKMInstsIssued();
90 
91  if (m->isLoad() || m->isAtomic()) {
92  returnedLoads.pop();
93  assert(inflightLoads > 0);
94  --inflightLoads;
95  } else {
96  returnedStores.pop();
97  assert(inflightStores > 0);
99  }
100 
101  // Decrement outstanding register count
102  computeUnit.shader->ScheduleAdd(&w->outstandingReqs, m->time, -1);
103 
104  if (m->isStore() || m->isAtomic()) {
105  computeUnit.shader->ScheduleAdd(&w->scalarOutstandingReqsWrGm,
106  m->time, -1);
107  }
108 
109  if (m->isLoad() || m->isAtomic()) {
110  computeUnit.shader->ScheduleAdd(&w->scalarOutstandingReqsRdGm,
111  m->time, -1);
112  }
113 
114  // Mark write bus busy for appropriate amount of time
117  w->computeUnit->scalarMemUnit.set(m->time);
118  }
119 
120  // If pipeline has executed a global memory instruction
121  // execute global memory packets and issue global
122  // memory packets to DTLB
123  if (!issuedRequests.empty()) {
124  GPUDynInstPtr mp = issuedRequests.front();
125  if (mp->isLoad() || mp->isAtomic()) {
126 
127  if (inflightLoads >= queueSize) {
128  return;
129  } else {
130  ++inflightLoads;
131  }
132  } else {
133  if (inflightStores >= queueSize) {
134  return;
135  } else {
136  ++inflightStores;
137  }
138  }
139  mp->initiateAcc(mp);
140  issuedRequests.pop();
141 
142  DPRINTF(GPUMem, "CU%d: WF[%d][%d] Popping scalar mem_op\n",
143  computeUnit.cu_id, mp->simdId, mp->wfSlotId);
144  }
145 }
146 
147 void
149 {
150  Wavefront *wf = gpuDynInst->wavefront();
151  if (gpuDynInst->isLoad()) {
152  wf->scalarRdGmReqsInPipe--;
154  } else if (gpuDynInst->isStore()) {
155  wf->scalarWrGmReqsInPipe--;
157  }
158 
159  wf->outstandingReqs++;
161 
162  issuedRequests.push(gpuDynInst);
163 }
164 
165 } // namespace gem5
gem5::ScalarMemPipeline::returnedStores
std::queue< GPUDynInstPtr > returnedStores
Definition: scalar_memory_pipeline.hh:108
gem5::ScalarMemPipeline::issuedRequests
std::queue< GPUDynInstPtr > issuedRequests
Definition: scalar_memory_pipeline.hh:104
gem5::ScalarMemPipeline::exec
void exec()
Definition: scalar_memory_pipeline.cc:56
gem5::MipsISA::w
Bitfield< 0 > w
Definition: pra_constants.hh:281
shader.hh
gem5::Wavefront
Definition: wavefront.hh:62
compute_unit.hh
gem5::ScalarMemPipeline::queueSize
int queueSize
Definition: scalar_memory_pipeline.hh:95
gem5::ArmISA::mp
Bitfield< 11 > mp
Definition: misc_types.hh:768
gem5::Wavefront::scalarRdGmReqsInPipe
int scalarRdGmReqsInPipe
Definition: wavefront.hh:190
gem5::ComputeUnit::shader
Shader * shader
Definition: compute_unit.hh:355
gem5::ComputeUnit::cu_id
int cu_id
Definition: compute_unit.hh:294
wavefront.hh
gem5::ComputeUnit
Definition: compute_unit.hh:203
gem5::Wavefront::validateRequestCounters
void validateRequestCounters()
Definition: wavefront.cc:748
gem5::Wavefront::outstandingReqs
int outstandingReqs
Definition: wavefront.hh:173
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::ComputeUnit::scalarMemUnit
WaitClass scalarMemUnit
Definition: compute_unit.hh:243
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::Wavefront::scalarWrGmReqsInPipe
int scalarWrGmReqsInPipe
Definition: wavefront.hh:191
gem5::Wavefront::scalarOutstandingReqsRdGm
int scalarOutstandingReqsRdGm
Definition: wavefront.hh:183
gem5::Wavefront::scalarOutstandingReqsWrGm
int scalarOutstandingReqsWrGm
Definition: wavefront.hh:185
scalar_register_file.hh
gpu_dyn_inst.hh
gem5::ScalarMemPipeline::issueRequest
void issueRequest(GPUDynInstPtr gpuDynInst)
Definition: scalar_memory_pipeline.cc:148
scalar_memory_pipeline.hh
name
const std::string & name()
Definition: trace.cc:49
gem5::ScalarMemPipeline::computeUnit
ComputeUnit & computeUnit
Definition: scalar_memory_pipeline.hh:93
gem5::ScalarMemPipeline::inflightStores
int inflightStores
Definition: scalar_memory_pipeline.hh:99
gem5::GPUDynInstPtr
std::shared_ptr< GPUDynInst > GPUDynInstPtr
Definition: misc.hh:51
gem5::ScalarMemPipeline::returnedLoads
std::queue< GPUDynInstPtr > returnedLoads
Definition: scalar_memory_pipeline.hh:112
gem5::Shader::coissue_return
int coissue_return
Definition: shader.hh:199
gem5::WaitClass::set
void set(uint64_t i)
Definition: misc.hh:84
gem5::ArmISA::m
Bitfield< 0 > m
Definition: misc_types.hh:394
gem5::Shader::ScheduleAdd
void ScheduleAdd(int *val, Tick when, int x)
Definition: shader.cc:359
gem5::ComputeUnit::scalarMemToSrfBus
WaitClass scalarMemToSrfBus
Definition: compute_unit.hh:239
gem5::ScalarMemPipeline::inflightLoads
int inflightLoads
Definition: scalar_memory_pipeline.hh:100
gem5::ScalarMemPipeline::ScalarMemPipeline
ScalarMemPipeline(const ComputeUnitParams &p, ComputeUnit &cu)
Definition: scalar_memory_pipeline.cc:47
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::WaitClass::rdy
bool rdy(Cycles cycles=Cycles(0)) const
Definition: misc.hh:95

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