gem5  v21.2.1.1
scalar_memory_pipeline.cc
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31 
33 
34 #include "debug/GPUMem.hh"
35 #include "debug/GPUReg.hh"
39 #include "gpu-compute/shader.hh"
40 #include "gpu-compute/wavefront.hh"
41 
42 namespace gem5
43 {
44 
45 ScalarMemPipeline::ScalarMemPipeline(const ComputeUnitParams &p,
46  ComputeUnit &cu)
47  : computeUnit(cu), _name(cu.name() + ".ScalarMemPipeline"),
48  queueSize(p.scalar_mem_queue_size),
49  inflightStores(0), inflightLoads(0)
50 {
51 }
52 
53 void
55 {
56  // afind oldest scalar request whose data has arrived
57  GPUDynInstPtr m = !returnedLoads.empty() ? returnedLoads.front() :
58  !returnedStores.empty() ? returnedStores.front() : nullptr;
59 
60  Wavefront *w = nullptr;
61 
62  bool accessSrf = true;
63  // check the SRF to see if the operands of a load (or load component
64  // of an atomic) are accessible
65  if ((m) && (m->isLoad() || m->isAtomicRet())) {
66  w = m->wavefront();
67 
68  accessSrf =
69  w->computeUnit->srf[w->simdId]->
70  canScheduleWriteOperandsFromLoad(w, m);
71  }
72 
73  if ((!returnedStores.empty() || !returnedLoads.empty()) &&
74  m->latency.rdy() && computeUnit.scalarMemToSrfBus.rdy() &&
75  accessSrf &&
78 
79  w = m->wavefront();
80 
81  if (m->isLoad() || m->isAtomicRet()) {
82  w->computeUnit->srf[w->simdId]->
83  scheduleWriteOperandsFromLoad(w, m);
84  }
85 
86  m->completeAcc(m);
87  w->decLGKMInstsIssued();
88 
89  if (m->isLoad() || m->isAtomic()) {
90  returnedLoads.pop();
91  assert(inflightLoads > 0);
92  --inflightLoads;
93  } else {
94  returnedStores.pop();
95  assert(inflightStores > 0);
97  }
98 
99  // Decrement outstanding register count
100  computeUnit.shader->ScheduleAdd(&w->outstandingReqs, m->time, -1);
101 
102  if (m->isStore() || m->isAtomic()) {
103  computeUnit.shader->ScheduleAdd(&w->scalarOutstandingReqsWrGm,
104  m->time, -1);
105  }
106 
107  if (m->isLoad() || m->isAtomic()) {
108  computeUnit.shader->ScheduleAdd(&w->scalarOutstandingReqsRdGm,
109  m->time, -1);
110  }
111 
112  // Mark write bus busy for appropriate amount of time
115  w->computeUnit->scalarMemUnit.set(m->time);
116  }
117 
118  // If pipeline has executed a global memory instruction
119  // execute global memory packets and issue global
120  // memory packets to DTLB
121  if (!issuedRequests.empty()) {
122  GPUDynInstPtr mp = issuedRequests.front();
123  if (mp->isLoad() || mp->isAtomic()) {
124 
125  if (inflightLoads >= queueSize) {
126  return;
127  } else {
128  ++inflightLoads;
129  }
130  } else {
131  if (inflightStores >= queueSize) {
132  return;
133  } else {
134  ++inflightStores;
135  }
136  }
137  mp->initiateAcc(mp);
138  issuedRequests.pop();
139 
140  DPRINTF(GPUMem, "CU%d: WF[%d][%d] Popping scalar mem_op\n",
141  computeUnit.cu_id, mp->simdId, mp->wfSlotId);
142  }
143 }
144 
145 void
147 {
148  Wavefront *wf = gpuDynInst->wavefront();
149  if (gpuDynInst->isLoad()) {
150  wf->scalarRdGmReqsInPipe--;
152  } else if (gpuDynInst->isStore()) {
153  wf->scalarWrGmReqsInPipe--;
155  }
156 
157  wf->outstandingReqs++;
159 
160  issuedRequests.push(gpuDynInst);
161 }
162 
163 } // namespace gem5
gem5::ScalarMemPipeline::returnedStores
std::queue< GPUDynInstPtr > returnedStores
Definition: scalar_memory_pipeline.hh:106
gem5::ScalarMemPipeline::issuedRequests
std::queue< GPUDynInstPtr > issuedRequests
Definition: scalar_memory_pipeline.hh:102
gem5::ScalarMemPipeline::exec
void exec()
Definition: scalar_memory_pipeline.cc:54
gem5::MipsISA::w
Bitfield< 0 > w
Definition: pra_constants.hh:281
shader.hh
gem5::Wavefront
Definition: wavefront.hh:60
compute_unit.hh
gem5::ScalarMemPipeline::queueSize
int queueSize
Definition: scalar_memory_pipeline.hh:93
gem5::ArmISA::mp
Bitfield< 11 > mp
Definition: misc_types.hh:769
gem5::Wavefront::scalarRdGmReqsInPipe
int scalarRdGmReqsInPipe
Definition: wavefront.hh:188
gem5::ComputeUnit::shader
Shader * shader
Definition: compute_unit.hh:353
gem5::ComputeUnit::cu_id
int cu_id
Definition: compute_unit.hh:292
wavefront.hh
gem5::ComputeUnit
Definition: compute_unit.hh:201
gem5::Wavefront::validateRequestCounters
void validateRequestCounters()
Definition: wavefront.cc:746
gem5::Wavefront::outstandingReqs
int outstandingReqs
Definition: wavefront.hh:171
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::ComputeUnit::scalarMemUnit
WaitClass scalarMemUnit
Definition: compute_unit.hh:241
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::Wavefront::scalarWrGmReqsInPipe
int scalarWrGmReqsInPipe
Definition: wavefront.hh:189
gem5::Wavefront::scalarOutstandingReqsRdGm
int scalarOutstandingReqsRdGm
Definition: wavefront.hh:181
gem5::Wavefront::scalarOutstandingReqsWrGm
int scalarOutstandingReqsWrGm
Definition: wavefront.hh:183
scalar_register_file.hh
gpu_dyn_inst.hh
gem5::ScalarMemPipeline::issueRequest
void issueRequest(GPUDynInstPtr gpuDynInst)
Definition: scalar_memory_pipeline.cc:146
scalar_memory_pipeline.hh
name
const std::string & name()
Definition: trace.cc:49
gem5::ScalarMemPipeline::computeUnit
ComputeUnit & computeUnit
Definition: scalar_memory_pipeline.hh:91
gem5::ScalarMemPipeline::inflightStores
int inflightStores
Definition: scalar_memory_pipeline.hh:97
gem5::GPUDynInstPtr
std::shared_ptr< GPUDynInst > GPUDynInstPtr
Definition: misc.hh:49
gem5::ScalarMemPipeline::returnedLoads
std::queue< GPUDynInstPtr > returnedLoads
Definition: scalar_memory_pipeline.hh:110
gem5::Shader::coissue_return
int coissue_return
Definition: shader.hh:197
gem5::WaitClass::set
void set(uint64_t i)
Definition: misc.hh:82
gem5::ArmISA::m
Bitfield< 0 > m
Definition: misc_types.hh:395
gem5::Shader::ScheduleAdd
void ScheduleAdd(int *val, Tick when, int x)
Definition: shader.cc:356
gem5::ComputeUnit::scalarMemToSrfBus
WaitClass scalarMemToSrfBus
Definition: compute_unit.hh:237
gem5::ScalarMemPipeline::inflightLoads
int inflightLoads
Definition: scalar_memory_pipeline.hh:98
gem5::ScalarMemPipeline::ScalarMemPipeline
ScalarMemPipeline(const ComputeUnitParams &p, ComputeUnit &cu)
Definition: scalar_memory_pipeline.cc:45
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::WaitClass::rdy
bool rdy(Cycles cycles=Cycles(0)) const
Definition: misc.hh:93

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