gem5 v24.1.0.1
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RubyPrefetcherProxy.cc
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1/*
2 * Copyright (c) 2023 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 */
37
39
40#include "debug/HWPrefetch.hh"
42
43namespace gem5
44{
45
46namespace ruby
47{
48
50 prefetch::Base* _prefetcher,
51 MessageBuffer *_pf_queue)
52 :Named(_parent->name()),
53 prefetcher(_prefetcher),
54 cacheCntrl(_parent),
55 pfQueue(_pf_queue),
56 pfEvent([this]{ issuePrefetch(); }, name()),
57 ppHit(nullptr), ppMiss(nullptr),
58 ppFill(nullptr), ppDataUpdate(nullptr)
59{
60 fatal_if(!cacheCntrl,
61 "initializing a RubyPrefetcherProxy without a parent");
62 if (prefetcher) {
63 fatal_if(!pfQueue,
64 "%s initializing a RubyPrefetcherProxy without a prefetch queue",
65 name());
66 prefetcher->setParentInfo(
67 cacheCntrl->params().system,
68 cacheCntrl->getProbeManager(),
69 cacheCntrl->m_ruby_system->getBlockSizeBytes());
70 }
71}
72
73void
75{
76 if (pfEvent.scheduled())
77 return;
78
79 Tick next_pf_time = std::max(prefetcher->nextPrefetchReadyTime(),
81 if (next_pf_time != MaxTick) {
82 DPRINTF(HWPrefetch, "Next prefetch ready at %d\n", next_pf_time);
83 cacheCntrl->schedule(&pfEvent, next_pf_time);
84 }
85}
86
87void
93
94void
96{
97 assert(makeLineAddress(addr) == addr);
98 assert(issuedPfPkts.count(addr) == 1);
99 DPRINTF(HWPrefetch, "Prefetch request for addr %#x completed\n", addr);
100 delete issuedPfPkts[addr];
101 issuedPfPkts.erase(addr);
102}
103
104void
106{
107 assert(prefetcher);
108 assert(pfQueue);
109
112
113 if (pkt) {
114 DPRINTF(HWPrefetch, "Next prefetch ready %s\n", pkt->print());
115 unsigned blk_size = cacheCntrl->m_ruby_system->getBlockSizeBytes();
116 Addr line_addr = pkt->getBlockAddr(blk_size);
117
118 if (issuedPfPkts.count(line_addr) == 0) {
119 DPRINTF(HWPrefetch, "Issued PF request for paddr=%#x, "
120 "line_addr=%#x, is_write=%d\n",
121 pkt->getAddr(), line_addr,
122 pkt->needsWritable());
123
124 RubyRequestType req_type = pkt->needsWritable() ?
125 RubyRequestType_ST : RubyRequestType_LD;
126
127 std::shared_ptr<RubyRequest> msg =
128 std::make_shared<RubyRequest>(cacheCntrl->clockEdge(),
129 blk_size,
131 pkt->getAddr(),
132 blk_size,
133 0, // pc
134 req_type,
135 RubyAccessMode_Supervisor,
136 pkt,
137 PrefetchBit_Yes);
138
139 // enqueue request into prefetch queue to the cache
144 );
145
146 // track all pending PF requests
147 issuedPfPkts[line_addr] = pkt;
148 } else {
149 DPRINTF(HWPrefetch, "Aborted PF request for address being "
150 "prefetched\n");
151 delete pkt;
152 }
153 }
154 } else {
155 DPRINTF(HWPrefetch, "No prefetch slots are available\n");
156 }
157
159}
160
161void
163 const DataBlock& data_blk)
164{
165 assert(ppHit);
166 assert(req);
167 Packet pkt(req, is_read ? Packet::makeReadCmd(req) :
169 // NOTE: for now we only communicate physical address with prefetchers
170 pkt.dataStaticConst<uint8_t>(data_blk.getData(getOffset(req->getPaddr()),
171 pkt.getSize()));
172 DPRINTF(HWPrefetch, "notify hit: %s\n", pkt.print());
173 ppHit->notify(CacheAccessProbeArg(&pkt, *this));
175}
176
177void
179 const DataBlock& data_blk)
180{
181 assert(ppMiss);
182 assert(req);
183 Packet pkt(req, is_read ? Packet::makeReadCmd(req) :
185 // NOTE: for now we only communicate physical address with prefetchers
186 pkt.dataStaticConst<uint8_t>(data_blk.getData(getOffset(req->getPaddr()),
187 pkt.getSize()));
188 DPRINTF(HWPrefetch, "notify miss: %s\n", pkt.print());
189 ppMiss->notify(CacheAccessProbeArg(&pkt, *this));
191}
192
193void
195 const DataBlock& data_blk,
196 bool from_pf)
197{
198 assert(ppFill);
199 assert(req);
200 Packet pkt(req, Packet::makeReadCmd(req));
201 if (from_pf)
202 pkt.cmd = Packet::Command::HardPFReq;
203 // NOTE: for now we only communicate physical address with prefetchers
204 pkt.dataStaticConst<uint8_t>(data_blk.getData(getOffset(req->getPaddr()),
205 pkt.getSize()));
206 DPRINTF(HWPrefetch, "notify fill: %s\n", pkt.print());
207 ppFill->notify(CacheAccessProbeArg(&pkt, *this));
209}
210
211void
212RubyPrefetcherProxy::notifyPfEvict(Addr blkAddr, bool hwPrefetched,
213 RequestorID requestorID)
214{
215 DPRINTF(HWPrefetch, "notify evict: %#x hw_pf=%d\n", blkAddr, hwPrefetched);
216 CacheDataUpdateProbeArg data_update(
217 blkAddr, false, requestorID, *this);
218 data_update.hwPrefetched = hwPrefetched;
219 ppDataUpdate->notify(data_update);
221}
222
223void
237
238Addr
244
245Addr
251
252} // namespace ruby
253} // namespace gem5
#define DPRINTF(x,...)
Definition trace.hh:209
Information provided to probes on a cache event.
Tick clockEdge(Cycles cycles=Cycles(0)) const
Determine the tick when a cycle begins, by default the current one, but the argument also enables the...
Tick cyclesToTicks(Cycles c) const
Cycles is a wrapper class for representing cycle counts, i.e.
Definition types.hh:79
Interface for things with names.
Definition named.hh:39
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition packet.hh:295
Addr getAddr() const
Definition packet.hh:807
bool needsWritable() const
Definition packet.hh:599
void print(std::ostream &o, int verbosity=0, const std::string &prefix="") const
Definition packet.cc:368
static MemCmd makeWriteCmd(const RequestPtr &req)
Generate the appropriate write MemCmd based on the Request flags.
Definition packet.hh:1016
Addr getBlockAddr(unsigned int blk_size) const
Definition packet.hh:831
unsigned getSize() const
Definition packet.hh:817
void dataStaticConst(const T *p)
Set the data pointer to the following value that should not be freed.
Definition packet.hh:1192
static MemCmd makeReadCmd(const RequestPtr &req)
Generate the appropriate read MemCmd based on the Request flags.
Definition packet.hh:993
MemCmd cmd
The command field of the packet.
Definition packet.hh:372
ProbePointArg generates a point for the class of Arg.
Definition probe.hh:264
virtual PacketPtr getPacket()=0
virtual Tick nextPrefetchReadyTime() const =0
const uint8_t * getData(int offset, int len) const
Definition DataBlock.cc:191
bool areNSlotsAvailable(unsigned int n, Tick curTime)
void enqueue(MsgPtr message, Tick curTime, Tick delta, bool ruby_is_random, bool ruby_warmup, bool bypassStrictFIFO=false)
void regProbePoints()
Registers probes.
void issuePrefetch()
Issue prefetch to the contoller prefetch queue.
void notifyPfEvict(Addr blkAddr, bool hwPrefetched, RequestorID requestorID)
prefetch::Base * prefetcher
Prefetcher from classic memory.
ProbePointArg< CacheAccessProbeArg > * ppMiss
To probe when a cache miss occurs.
EventFunctionWrapper pfEvent
Prefetch event.
void notifyPfMiss(const RequestPtr &req, bool is_read, const DataBlock &data_blk)
ProbePointArg< CacheAccessProbeArg > * ppFill
To probe when a cache fill occurs.
void scheduleNextPrefetch()
Schedule the next ready prefetch.
void notifyPfHit(const RequestPtr &req, bool is_read, const DataBlock &data_blk)
Notify PF probes hit/miss/fill.
void completePrefetch(Addr addr)
Notifies a completed prefetch request.
AbstractController * cacheCntrl
Ruby cache controller.
void deschedulePrefetch()
Deschedled the ready prefetch event.
void notifyPfFill(const RequestPtr &req, const DataBlock &data_blk, bool from_pf)
ProbePointArg< CacheAccessProbeArg > * ppHit
To probe when a cache hit occurs.
MessageBuffer * pfQueue
Prefetch queue to the cache controller.
ProbePointArg< CacheDataUpdateProbeArg > * ppDataUpdate
To probe when the contents of a block are updated.
std::unordered_map< Addr, PacketPtr > issuedPfPkts
List of issued prefetch request packets.
RubyPrefetcherProxy(AbstractController *parent, prefetch::Base *prefetcher, MessageBuffer *pf_queue)
uint32_t getBlockSizeBits()
Definition RubySystem.hh:74
uint32_t getBlockSizeBytes()
Definition RubySystem.hh:73
void deschedule(Event &event)
Definition eventq.hh:1021
bool scheduled() const
Determine if the current event is scheduled.
Definition eventq.hh:458
void schedule(Event &event, Tick when)
Definition eventq.hh:1012
#define fatal_if(cond,...)
Conditional fatal macro that checks the supplied condition and only causes a fatal error if the condi...
Definition logging.hh:236
ProbeManager * getProbeManager()
Get the probe manager for this object.
Bitfield< 3 > addr
Definition types.hh:84
Addr makeLineAddress(Addr addr, int cacheLineBits)
Definition Address.cc:61
Addr getOffset(Addr addr, int cacheLineBits)
Definition Address.cc:54
Copyright (c) 2024 Arm Limited All rights reserved.
Definition binary32.hh:36
std::shared_ptr< Request > RequestPtr
Definition request.hh:94
Tick curTick()
The universal simulation clock.
Definition cur_tick.hh:46
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition types.hh:147
uint64_t Tick
Tick count type.
Definition types.hh:58
const Tick MaxTick
Definition types.hh:60
uint16_t RequestorID
Definition request.hh:95
A data contents update is composed of the updated block's address, the old contents,...
bool hwPrefetched
Set if the update is from a prefetch or evicting a prefetched block that was never used.
const std::string & name()
Definition trace.cc:48

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