gem5  v21.2.0.0
thread_context.hh
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27 
28 #ifndef __ARCH_ARM_FASTMODEL_CORTEXR52_THREAD_CONTEXT_HH__
29 #define __ARCH_ARM_FASTMODEL_CORTEXR52_THREAD_CONTEXT_HH__
30 
32 
33 namespace gem5
34 {
35 
36 GEM5_DEPRECATED_NAMESPACE(FastModel, fastmodel);
37 namespace fastmodel
38 {
39 
40 // This ThreadContext class translates accesses to state using gem5's native
41 // to the Iris API. This includes extracting and translating register indices.
43 {
44  protected:
49 
50  public:
51  CortexR52TC(gem5::BaseCPU *cpu, int id, System *system,
52  gem5::BaseMMU *mmu, gem5::BaseISA *isa,
53  iris::IrisConnectionInterface *iris_if,
54  const std::string &iris_path);
55 
56  bool translateAddress(Addr &paddr, Addr vaddr) override;
57 
58  void initFromIrisInstance(const ResourceMap &resources) override;
59  void sendFunctional(PacketPtr pkt) override;
60 
61  // Since this CPU doesn't support aarch64, we override these two methods
62  // and always assume we're 32 bit. More than likely we could be more
63  // general than that, but that would require letting the default
64  // implementation read the CPSR, and that's not currently implemented.
65  RegVal readIntReg(RegIndex reg_idx) const override;
66  void setIntReg(RegIndex reg_idx, RegVal val) override;
67 
68  RegVal readCCRegFlat(RegIndex idx) const override;
69  void setCCRegFlat(RegIndex idx, RegVal val) override;
70 
71  const std::vector<iris::MemorySpaceId> &getBpSpaceIds() const override;
72 
73  // The map from gem5 indexes to IRIS resource names is not currently set
74  // up. It will be a little more complicated for R52, since it won't have
75  // many of the registers since it doesn't support aarch64. We may need to
76  // just return dummy values on reads and throw away writes, throw an
77  // error, or some combination of the two.
78  RegVal
79  readMiscRegNoEffect(RegIndex idx) const override
80  {
81  panic_if(miscRegIdxNameMap.find(idx) == miscRegIdxNameMap.end(),
82  "No mapping for index %#x.", idx);
84  }
85 
86  void
87  setMiscRegNoEffect(RegIndex idx, const RegVal val) override
88  {
89  panic_if(miscRegIdxNameMap.find(idx) == miscRegIdxNameMap.end(),
90  "No mapping for index %#x.", idx);
92  }
93 
94  // Like the Misc regs, not currently supported and a little complicated.
95  RegVal
96  readIntRegFlat(RegIndex idx) const override
97  {
98  panic("%s not implemented.", __FUNCTION__);
99  }
100 
101  void
103  {
104  panic("%s not implemented.", __FUNCTION__);
105  }
106 
107  // Not supported by the CPU. There isn't anything to set up here as far
108  // as mapping, but the question still remains what to do about registers
109  // that don't exist in the CPU.
111  readVecReg(const RegId &) const override
112  {
113  panic("%s not implemented.", __FUNCTION__);
114  }
115 };
116 
117 } // namespace fastmodel
118 } // namespace gem5
119 
120 #endif // __ARCH_ARM_FASTMODEL_CORTEXR52_THREAD_CONTEXT_HH__
gem5::fastmodel::CortexR52TC::intReg32IdxNameMap
static IdxNameMap intReg32IdxNameMap
Definition: thread_context.hh:46
gem5::Iris::ThreadContext::IdxNameMap
std::map< int, std::string > IdxNameMap
Definition: thread_context.hh:59
gem5::fastmodel::CortexR52TC::readIntReg
RegVal readIntReg(RegIndex reg_idx) const override
Definition: thread_context.cc:88
gem5::fastmodel::CortexR52TC::sendFunctional
void sendFunctional(PacketPtr pkt) override
Definition: thread_context.cc:71
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::fastmodel::CortexR52TC::translateAddress
bool translateAddress(Addr &paddr, Addr vaddr) override
Definition: thread_context.cc:50
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
gem5::fastmodel::CortexR52TC::ccRegIdxNameMap
static IdxNameMap ccRegIdxNameMap
Definition: thread_context.hh:47
gem5::X86ISA::system
Bitfield< 15 > system
Definition: misc.hh:1003
std::vector< iris::MemorySpaceId >
gem5::fastmodel::CortexR52TC::CortexR52TC
CortexR52TC(gem5::BaseCPU *cpu, int id, System *system, gem5::BaseMMU *mmu, gem5::BaseISA *isa, iris::IrisConnectionInterface *iris_if, const std::string &iris_path)
Definition: thread_context.cc:42
gem5::fastmodel::CortexR52TC::miscRegIdxNameMap
static IdxNameMap miscRegIdxNameMap
Definition: thread_context.hh:45
gem5::BaseMMU
Definition: mmu.hh:53
gem5::fastmodel::CortexR52TC::readVecReg
const ArmISA::VecRegContainer & readVecReg(const RegId &) const override
Definition: thread_context.hh:111
gem5::System
Definition: system.hh:75
gem5::VecRegContainer
Vector Register Abstraction This generic class is the model in a particularization of MVC,...
Definition: vec_reg.hh:121
gem5::fastmodel::CortexR52TC::bpSpaceIds
static std::vector< iris::MemorySpaceId > bpSpaceIds
Definition: thread_context.hh:48
gem5::fastmodel::CortexR52TC::readIntRegFlat
RegVal readIntRegFlat(RegIndex idx) const override
Flat register interfaces.
Definition: thread_context.hh:96
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::Iris::ThreadContext
Definition: thread_context.hh:53
gem5::Iris::ThreadContext::setMiscRegNoEffect
void setMiscRegNoEffect(RegIndex misc_reg, const RegVal val) override
Definition: thread_context.cc:602
gem5::fastmodel::CortexR52TC::readCCRegFlat
RegVal readCCRegFlat(RegIndex idx) const override
Definition: thread_context.cc:103
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::GEM5_DEPRECATED_NAMESPACE
GEM5_DEPRECATED_NAMESPACE(GuestABI, guest_abi)
gem5::fastmodel::CortexR52TC::getBpSpaceIds
const std::vector< iris::MemorySpaceId > & getBpSpaceIds() const override
Definition: thread_context.cc:143
gem5::fastmodel::CortexR52TC
Definition: thread_context.hh:42
gem5::Iris::ThreadContext::readMiscRegNoEffect
RegVal readMiscRegNoEffect(RegIndex misc_reg) const override
Definition: thread_context.cc:594
gem5::fastmodel::CortexR52TC::setIntReg
void setIntReg(RegIndex reg_idx, RegVal val) override
Definition: thread_context.cc:96
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:204
gem5::fastmodel::CortexR52TC::initFromIrisInstance
void initFromIrisInstance(const ResourceMap &resources) override
Definition: thread_context.cc:58
gem5::fastmodel::CortexR52TC::setIntRegFlat
void setIntRegFlat(RegIndex idx, RegVal val) override
Definition: thread_context.hh:102
gem5::Iris::ThreadContext::ResourceMap
std::map< std::string, iris::ResourceInfo > ResourceMap
Definition: thread_context.hh:56
gem5::fastmodel::CortexR52TC::setMiscRegNoEffect
void setMiscRegNoEffect(RegIndex idx, const RegVal val) override
Definition: thread_context.hh:87
gem5::fastmodel::CortexR52TC::readMiscRegNoEffect
RegVal readMiscRegNoEffect(RegIndex idx) const override
Definition: thread_context.hh:79
gem5::fastmodel::CortexR52TC::setCCRegFlat
void setCCRegFlat(RegIndex idx, RegVal val) override
Definition: thread_context.cc:120
gem5::MipsISA::vaddr
vaddr
Definition: pra_constants.hh:278
gem5::BaseISA
Definition: isa.hh:57
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
thread_context.hh
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:113
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178

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