gem5  v22.0.0.2
thread_context.cc
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39 
41 
42 #include <cstdint>
43 #include <cstring>
44 #include <utility>
45 #include <vector>
46 
49 #include "arch/arm/system.hh"
50 #include "arch/arm/utility.hh"
51 #include "base/logging.hh"
52 #include "iris/detail/IrisCppAdapter.h"
53 #include "iris/detail/IrisObjects.h"
56 #include "sim/pseudo_inst.hh"
57 
58 namespace gem5
59 {
60 
61 namespace Iris
62 {
63 
64 void
66 {
67  bool enabled = false;
68  call().perInstanceExecution_getState(_instId, enabled);
70 
71  suspend();
72 
73  call().memory_getMemorySpaces(_instId, memorySpaces);
74  for (const auto &space: memorySpaces) {
75  memorySpaceIds.emplace(
76  Iris::CanonicalMsn(space.canonicalMsn), space.spaceId);
77  }
78  call().memory_getUsefulAddressTranslations(_instId, translations);
79 
80  typedef ThreadContext Self;
81  iris::EventSourceInfo evSrcInfo;
82 
83  client.registerEventCallback<Self, &Self::breakpointHit>(
84  this, "ec_IRIS_BREAKPOINT_HIT",
85  "Handle hitting a breakpoint", "Iris::ThreadContext");
86  call().event_getEventSource(_instId, evSrcInfo, "IRIS_BREAKPOINT_HIT");
87  call().eventStream_create(_instId, breakpointEventStreamId,
88  evSrcInfo.evSrcId, client.getInstId());
89 
90  for (auto it = bps.begin(); it != bps.end(); it++)
91  installBp(it);
92 
93  client.registerEventCallback<Self, &Self::semihostingEvent>(
94  this, "ec_IRIS_SEMIHOSTING_CALL_EXTENSION",
95  "Handle a semihosting call", "Iris::ThreadContext");
96  call().event_getEventSource(_instId, evSrcInfo,
97  "IRIS_SEMIHOSTING_CALL_EXTENSION");
98  call().eventStream_create(_instId, semihostingEventStreamId,
99  evSrcInfo.evSrcId, client.getInstId(),
100  // Set all arguments to their defaults, except syncEc which is
101  // changed to true.
102  nullptr, "", false, 0, nullptr, false, false, true);
103 }
104 
105 iris::ResourceId
107  const ResourceMap &resources, const std::string &name)
108 {
109  return resources.at(name).rscId;
110 }
111 
112 void
114  ResourceIds &ids, const ResourceMap &resources,
115  const IdxNameMap &idx_names)
116 {
117  for (const auto &idx_name: idx_names) {
118  int idx = idx_name.first;
119  const std::string &name = idx_name.second;
120 
121  if (idx >= ids.size())
122  ids.resize(idx + 1, iris::IRIS_UINT64_MAX);
123 
124  ids[idx] = extractResourceId(resources, name);
125  }
126 }
127 
128 iris::MemorySpaceId
130 {
131  auto it = memorySpaceIds.find(msn);
132  return it == memorySpaceIds.end() ? iris::IRIS_UINT64_MAX : it->second;
133 }
134 
135 void
137 {
138  Tick now = 0;
139 
140  while (true) {
141  if (comInstEventQueue.empty()) {
142  // Set to 0 to deactivate stepping.
143  call().step_setup(_instId, 0, "instruction");
144  break;
145  }
146 
148  if (!now)
149  now = getCurrentInstCount();
150 
151  if (next <= now) {
153  // Start over now that comInstEventQueue has likely changed.
154  continue;
155  }
156 
157  // Set to the number of instructions still to step through.
158  Tick remaining = next - now;
159  call().step_setup(_instId, remaining, "instruction");
160  break;
161  }
162 }
163 
166 {
167  auto pc_it = bps.find(pc);
168 
169  if (pc_it != bps.end())
170  return pc_it;
171 
172  auto res = bps.emplace(std::make_pair(pc, new BpInfo(pc)));
173  panic_if(!res.second, "Inserting breakpoint failed.");
174  return res.first;
175 }
176 
177 void
179 {
180  Addr pc = it->second->pc;
181  const auto &space_ids = getBpSpaceIds();
182  for (auto sid: space_ids) {
183  BpId id;
184  call().breakpoint_set_code(_instId, id, pc, sid, 0);
185  it->second->ids.push_back(id);
186  }
187 }
188 
189 void
191 {
192  for (auto id: it->second->ids)
193  call().breakpoint_delete(_instId, id);
194  it->second->clearIds();
195 }
196 
197 void
199 {
200  panic_if(!it->second->empty(),
201  "BP info still had events associated with it.");
202 
203  if (it->second->validIds())
204  uninstallBp(it);
205 
206  bps.erase(it);
207 }
208 
209 iris::IrisErrorCode
211  uint64_t esId, const iris::IrisValueMap &fields, uint64_t time,
212  uint64_t sInstId, bool syncEc, std::string &error_message_out)
213 {
214  const std::string &event = fields.at("EVENT").getString();
215  const iris::InstanceId id = fields.at("INST_ID").getU64();
216  const std::string &name = fields.at("INST_NAME").getString();
217 
218  if (name != "component." + _irisPath)
219  return iris::E_ok;
220 
221  if (event == "added")
222  _instId = id;
223  else if (event == "removed")
224  _instId = iris::IRIS_UINT64_MAX;
225  else
226  panic("Unrecognized event type %s", event);
227 
228  return iris::E_ok;
229 }
230 
231 iris::IrisErrorCode
233  uint64_t esId, const iris::IrisValueMap &fields, uint64_t time,
234  uint64_t sInstId, bool syncEc, std::string &error_message_out)
235 {
237  call().resource_getList(_instId, resources);
238 
239  std::map<iris::ResourceId, const iris::ResourceInfo *>
240  idToResource;
241  for (const auto &resource: resources) {
242  idToResource[resource.rscId] = &resource;
243  }
244  ResourceMap resourceMap;
245  for (const auto &resource: resources) {
246  std::string name = resource.name;
247  iris::ResourceId parentId = resource.parentRscId;
248  while (parentId != iris::IRIS_UINT64_MAX) {
249  const auto *parent = idToResource[parentId];
250  name = parent->name + "." + name;
251  parentId = parent->parentRscId;
252  }
253  resourceMap[name] = resource;
254  }
255 
256  initFromIrisInstance(resourceMap);
257 
258  return iris::E_ok;
259 }
260 
261 iris::IrisErrorCode
263  uint64_t esId, const iris::IrisValueMap &fields, uint64_t time,
264  uint64_t sInstId, bool syncEc, std::string &error_message_out)
265 {
266  if (fields.at("RUNNING").getAsBool()) {
267  // If this is just simulation time starting up, don't do anything.
268  return iris::E_ok;
269  }
270 
271  // If simulation time has stopped for any reason, IRIS helpfully clears
272  // all stepping counters and we need to set them back. We might also need
273  // to service events based on the current number of executed instructions.
275 
276  // Restart simulation time to make sure things progress once we give
277  // control back.
278  call().simulationTime_run(iris::IrisInstIdSimulationEngine);
279 
280  return iris::E_ok;
281 }
282 
283 iris::IrisErrorCode
285  uint64_t esId, const iris::IrisValueMap &fields, uint64_t time,
286  uint64_t sInstId, bool syncEc, std::string &error_message_out)
287 {
288  Addr pc = fields.at("PC").getU64();
289 
290  auto it = getOrAllocBp(pc);
291 
292  std::shared_ptr<BpInfo::EventList> events = it->second->events;
293  auto e_it = events->begin();
294  while (e_it != events->end()) {
295  PCEvent *e = *e_it;
296  // Advance e_it here since e might remove itself from the list.
297  e_it++;
298  e->process(this);
299  }
300 
301  return iris::E_ok;
302 }
303 
304 iris::IrisErrorCode
306  uint64_t esId, const iris::IrisValueMap &fields, uint64_t time,
307  uint64_t sInstId, bool syncEc, std::string &error_message_out)
308 {
309  if (ArmSystem::callSemihosting(this, true)) {
310  // Stop execution in case an exit of the sim loop was scheduled. We
311  // don't want to keep executing instructions in the mean time.
312  call().perInstanceExecution_setState(_instId, false);
313 
314  // Schedule an event to resume execution right after any exit has
315  // had a chance to happen.
317  getCpuPtr()->schedule(enableAfterPseudoEvent, curTick());
318 
319  call().semihosting_return(_instId, readIntReg(0));
320  } else {
321  call().semihosting_notImplemented(_instId);
322  }
323  return iris::E_ok;
324 }
325 
327  gem5::BaseCPU *cpu, int id, System *system, gem5::BaseMMU *mmu,
328  BaseISA *isa, iris::IrisConnectionInterface *iris_if,
329  const std::string &iris_path) :
330  _cpu(cpu), _threadId(id), _system(system), _mmu(mmu), _isa(isa),
331  _irisPath(iris_path), vecRegs(ArmISA::NumVecRegs),
332  vecPredRegs(ArmISA::NumVecPredRegs),
333  comInstEventQueue("instruction-based event queue"),
334  client(iris_if, "client." + iris_path)
335 {
336  iris::InstanceInfo info;
337  auto ret_code = noThrow().instanceRegistry_getInstanceInfoByName(
338  info, "component." + iris_path);
339  if (ret_code == iris::E_ok) {
340  // The iris instance registry already new about this path.
341  _instId = info.instId;
342  } else {
343  // This path doesn't (yet) exist. Set the ID to something invalid.
344  _instId = iris::IRIS_UINT64_MAX;
345  }
346 
347  typedef ThreadContext Self;
348  iris::EventSourceInfo evSrcInfo;
349 
350  client.registerEventCallback<Self, &Self::instanceRegistryChanged>(
351  this, "ec_IRIS_INSTANCE_REGISTRY_CHANGED",
352  "Install the iris instance ID", "Iris::ThreadContext");
353  call().event_getEventSource(iris::IrisInstIdGlobalInstance, evSrcInfo,
354  "IRIS_INSTANCE_REGISTRY_CHANGED");
355  regEventStreamId = iris::IRIS_UINT64_MAX;
356  static const std::vector<std::string> fields =
357  { "EVENT", "INST_ID", "INST_NAME" };
358  call().eventStream_create(iris::IrisInstIdGlobalInstance, regEventStreamId,
359  evSrcInfo.evSrcId, client.getInstId(), &fields);
360 
361  client.registerEventCallback<Self, &Self::phaseInitLeave>(
362  this, "ec_IRIS_SIM_PHASE_INIT_LEAVE",
363  "Initialize register contexts", "Iris::ThreadContext");
364  call().event_getEventSource(iris::IrisInstIdSimulationEngine, evSrcInfo,
365  "IRIS_SIM_PHASE_INIT_LEAVE");
366  initEventStreamId = iris::IRIS_UINT64_MAX;
367  call().eventStream_create(
368  iris::IrisInstIdSimulationEngine, initEventStreamId,
369  evSrcInfo.evSrcId, client.getInstId());
370 
371  client.registerEventCallback<Self, &Self::simulationTimeEvent>(
372  this, "ec_IRIS_SIMULATION_TIME_EVENT",
373  "Handle simulation time stopping for breakpoints or stepping",
374  "Iris::ThreadContext");
375  call().event_getEventSource(iris::IrisInstIdSimulationEngine, evSrcInfo,
376  "IRIS_SIMULATION_TIME_EVENT");
377  timeEventStreamId = iris::IRIS_UINT64_MAX;
378  call().eventStream_create(
379  iris::IrisInstIdSimulationEngine, timeEventStreamId,
380  evSrcInfo.evSrcId, client.getInstId());
381 
382  breakpointEventStreamId = iris::IRIS_UINT64_MAX;
383  semihostingEventStreamId = iris::IRIS_UINT64_MAX;
384 
385  auto enable_lambda = [this]{
386  call().perInstanceExecution_setState(_instId, true);
387  };
389  enable_lambda, "resume after pseudo inst",
390  false, Event::Sim_Exit_Pri + 1);
391 }
392 
394 {
395  call().eventStream_destroy(
396  iris::IrisInstIdSimulationEngine, initEventStreamId);
397  initEventStreamId = iris::IRIS_UINT64_MAX;
398  client.unregisterEventCallback("ec_IRIS_SIM_PHASE_INIT_LEAVE");
399 
400  call().eventStream_destroy(
401  iris::IrisInstIdGlobalInstance, regEventStreamId);
402  regEventStreamId = iris::IRIS_UINT64_MAX;
403  client.unregisterEventCallback("ec_IRIS_INSTANCE_REGISTRY_CHANGED");
404 
405  call().eventStream_destroy(
406  iris::IrisInstIdGlobalInstance, timeEventStreamId);
407  timeEventStreamId = iris::IRIS_UINT64_MAX;
408  client.unregisterEventCallback("ec_IRIS_SIMULATION_TIME_EVENT");
409 
411  getCpuPtr()->deschedule(enableAfterPseudoEvent);
412  delete enableAfterPseudoEvent;
413 }
414 
415 bool
417 {
418  auto it = getOrAllocBp(e->pc());
419  it->second->events->push_back(e);
420 
421  if (_instId != iris::IRIS_UINT64_MAX && !it->second->validIds())
422  installBp(it);
423 
424  return true;
425 }
426 
427 bool
429 {
430  auto it = getOrAllocBp(e->pc());
431  it->second->events->remove(e);
432 
433  if (it->second->empty())
434  delBp(it);
435 
436  return true;
437 }
438 
439 void
441  iris::MemorySpaceId space, Addr addr, void *p, size_t size)
442 {
443  iris::r0master::MemoryReadResult r;
444  auto err = call().memory_read(_instId, r, space, addr, 1, size);
445  panic_if(err != iris::r0master::E_ok, "readMem failed.");
446  std::memcpy(p, r.data.data(), size);
447 }
448 
449 void
451  iris::MemorySpaceId space, Addr addr, const void *p, size_t size)
452 {
453  std::vector<uint64_t> data((size + 7) / 8);
454  std::memcpy(data.data(), p, size);
455  iris::MemoryWriteResult r;
456  auto err = call().memory_write(_instId, r, space, addr, 1, size, data);
457  panic_if(err != iris::r0master::E_ok, "writeMem failed.");
458 }
459 
460 bool
461 ThreadContext::translateAddress(Addr &paddr, iris::MemorySpaceId p_space,
462  Addr vaddr, iris::MemorySpaceId v_space)
463 {
464  iris::MemoryAddressTranslationResult result;
465  auto ret = noThrow().memory_translateAddress(
466  _instId, result, v_space, vaddr, p_space);
467 
468  if (ret != iris::E_ok) {
469  // Check if there was a legal translation between these two spaces.
470  // If so, something else went wrong.
471  for (auto &trans: translations)
472  if (trans.inSpaceId == v_space && trans.outSpaceId == p_space)
473  return false;
474 
475  panic("No legal translation IRIS address translation found.");
476  }
477 
478  if (result.address.empty())
479  return false;
480 
481  if (result.address.size() > 1) {
482  warn("Multiple mappings for address %#x.", vaddr);
483  return false;
484  }
485 
486  paddr = result.address[0];
487  return true;
488 }
489 
490 void
492 {
493  Tick now = getCurrentInstCount();
495  if (count <= now)
496  call().simulationTime_stop(iris::IrisInstIdSimulationEngine);
497  else
499 }
500 
501 void
503 {
506 }
507 
508 Tick
510 {
511  uint64_t count;
512  auto ret = call().step_getStepCounterValue(_instId, count, "instruction");
513  panic_if(ret != iris::E_ok, "Failed to get instruction count.");
514  return count;
515 }
516 
517 void
519 {
520  auto msn = ArmISA::isSecure(this) ?
522  auto id = getMemorySpaceId(msn);
523 
524  auto addr = pkt->getAddr();
525  auto size = pkt->getSize();
526  auto data = pkt->getPtr<uint8_t>();
527 
528  pkt->makeResponse();
529  if (pkt->isRead())
530  readMem(id, addr, data, size);
531  else
532  writeMem(id, addr, data, size);
533 }
534 
537 {
538  return _status;
539 }
540 
541 void
543 {
545  getCpuPtr()->deschedule(enableAfterPseudoEvent);
546  if (new_status == Active) {
547  if (_status != Active)
548  call().perInstanceExecution_setState(_instId, true);
549  } else {
550  if (_status == Active)
551  call().perInstanceExecution_setState(_instId, false);
552  }
553  _status = new_status;
554 }
555 
556 const PCStateBase &
558 {
559  ArmISA::CPSR cpsr = readMiscRegNoEffect(ArmISA::MISCREG_CPSR);
560 
561  pc.thumb(cpsr.t);
562  pc.nextThumb(pc.thumb());
563  pc.jazelle(cpsr.j);
564  pc.nextJazelle(cpsr.j);
565  pc.aarch64(!cpsr.width);
566  pc.nextAArch64(!cpsr.width);
567  pc.illegalExec(false);
568  pc.itstate(ArmISA::itState(cpsr));
569  pc.nextItstate(0);
570 
571  iris::ResourceReadResult result;
572  call().resource_read(_instId, result, pcRscId);
573  Addr addr = result.data.at(0);
574  if (cpsr.width && cpsr.t)
575  addr = addr & ~0x1;
576  pc.set(addr);
577 
578  return pc;
579 }
580 void
582 {
583  Addr pc = val.instAddr();
584 
585  ArmISA::CPSR cpsr = readMiscRegNoEffect(ArmISA::MISCREG_CPSR);
586  if (cpsr.width && cpsr.t)
587  pc = pc | 0x1;
588 
589  iris::ResourceWriteResult result;
590  call().resource_write(_instId, result, pcRscId, pc);
591 }
592 
593 RegVal
595 {
596  iris::ResourceReadResult result;
597  call().resource_read(_instId, result, miscRegIds.at(misc_reg));
598  return result.data.at(0);
599 }
600 
601 void
603 {
604  iris::ResourceWriteResult result;
605  call().resource_write(_instId, result, miscRegIds.at(misc_reg), val);
606 }
607 
608 RegVal
610 {
611  RegVal val;
612  getReg(reg, &val);
613  return val;
614 }
615 
616 void
618 {
619  setReg(reg, &val);
620 }
621 
622 void
623 ThreadContext::getReg(const RegId &reg, void *val) const
624 {
625  const RegIndex idx = reg.index();
626  const RegClassType type = reg.classValue();
627  switch (type) {
628  case IntRegClass:
629  *(RegVal *)val = readIntReg(idx);
630  break;
631  case FloatRegClass:
632  *(RegVal *)val = readFloatReg(idx);
633  break;
634  case VecRegClass:
636  break;
637  case VecElemClass:
638  *(RegVal *)val = readVecElem(reg);
639  break;
640  case VecPredRegClass:
642  break;
643  case CCRegClass:
644  *(RegVal *)val = readCCReg(idx);
645  break;
646  case MiscRegClass:
647  panic("MiscRegs should not be read with getReg.");
648  default:
649  panic("Unrecognized register class type %d.", type);
650  }
651 }
652 
653 void
654 ThreadContext::setReg(const RegId &reg, const void *val)
655 {
656  const RegIndex idx = reg.index();
657  const RegClassType type = reg.classValue();
658  switch (type) {
659  case IntRegClass:
660  setIntReg(idx, *(RegVal *)val);
661  break;
662  case FloatRegClass:
663  setFloatReg(idx, *(RegVal *)val);
664  break;
665  case VecRegClass:
667  break;
668  case VecElemClass:
669  setVecElem(reg, *(RegVal *)val);
670  break;
671  case VecPredRegClass:
673  break;
674  case CCRegClass:
675  setCCReg(idx, *(RegVal *)val);
676  break;
677  case MiscRegClass:
678  panic("MiscRegs should not be read with getReg.");
679  default:
680  panic("Unrecognized register class type %d.", type);
681  }
682 }
683 
684 void *
686 {
687  const RegClassType type = reg.classValue();
688  switch (type) {
689  case VecRegClass:
690  return &getWritableVecReg(reg);
691  case VecPredRegClass:
692  return &getWritableVecPredReg(reg);
693  default:
694  panic("Unrecognized register class type %d.", type);
695  }
696 }
697 
698 RegVal
700 {
701  RegVal val;
702  getRegFlat(reg, &val);
703  return val;
704 }
705 
706 void
708 {
709  setRegFlat(reg, &val);
710 }
711 
712 void
714 {
715  const RegIndex idx = reg.index();
716  const RegClassType type = reg.classValue();
717  switch (type) {
718  case IntRegClass:
719  *(RegVal *)val = readIntRegFlat(idx);
720  break;
721  case VecRegClass:
723  break;
724  case VecElemClass:
725  *(RegVal *)val = readVecElemFlat(idx);
726  break;
727  case VecPredRegClass:
729  break;
730  case CCRegClass:
731  *(RegVal *)val = readCCRegFlat(idx);
732  break;
733  case MiscRegClass:
734  panic("MiscRegs should not be read with getReg.");
735  default:
736  panic("Unrecognized register class type %d.", type);
737  }
738 }
739 
740 void
742 {
743  const RegIndex idx = reg.index();
744  const RegClassType type = reg.classValue();
745  switch (type) {
746  case IntRegClass:
747  setIntRegFlat(idx, *(RegVal *)val);
748  break;
749  case VecRegClass:
751  break;
752  case VecElemClass:
753  setVecElemFlat(idx, *(RegVal *)val);
754  break;
755  case VecPredRegClass:
757  break;
758  case CCRegClass:
759  setCCRegFlat(idx, *(RegVal *)val);
760  break;
761  case MiscRegClass:
762  panic("MiscRegs should not be read with getReg.");
763  default:
764  panic("Unrecognized register class type %d.", type);
765  }
766 }
767 
768 void *
770 {
771  const RegIndex idx = reg.index();
772  const RegClassType type = reg.classValue();
773  switch (type) {
774  case VecRegClass:
775  return &getWritableVecRegFlat(idx);
776  case VecPredRegClass:
777  return &getWritableVecPredRegFlat(idx);
778  default:
779  panic("Unrecognized register class type %d.", type);
780  }
781 }
782 
783 RegVal
785 {
786  ArmISA::CPSR cpsr = readMiscRegNoEffect(ArmISA::MISCREG_CPSR);
787 
788  iris::ResourceReadResult result;
789  if (cpsr.width)
790  call().resource_read(_instId, result, intReg32Ids.at(reg_idx));
791  else
792  call().resource_read(_instId, result, intReg64Ids.at(reg_idx));
793  return result.data.at(0);
794 }
795 
796 void
798 {
799  ArmISA::CPSR cpsr = readMiscRegNoEffect(ArmISA::MISCREG_CPSR);
800 
801  iris::ResourceWriteResult result;
802  if (cpsr.width)
803  call().resource_write(_instId, result, intReg32Ids.at(reg_idx), val);
804  else
805  call().resource_write(_instId, result, intReg64Ids.at(reg_idx), val);
806 }
807 
808 /*
809  * The 64 bit version of registers gives us a pre-flattened view of the reg
810  * file, no matter what mode we're in or if we're currently 32 or 64 bit.
811  */
812 RegVal
814 {
815  if (idx >= flattenedIntIds.size())
816  return 0;
817  iris::ResourceId res_id = flattenedIntIds.at(idx);
818  if (res_id == iris::IRIS_UINT64_MAX)
819  return 0;
820  iris::ResourceReadResult result;
821  call().resource_read(_instId, result, res_id);
822  return result.data.at(0);
823 }
824 
825 void
827 {
828  iris::ResourceId res_id =
829  (idx >= flattenedIntIds.size()) ? iris::IRIS_UINT64_MAX :
830  flattenedIntIds.at(idx);
831  panic_if(res_id == iris::IRIS_UINT64_MAX,
832  "Int reg %d is not supported by fast model.", idx);
833  iris::ResourceWriteResult result;
834  call().resource_write(_instId, result, flattenedIntIds.at(idx), val);
835 }
836 
837 RegVal
839 {
840  if (idx >= ccRegIds.size())
841  return 0;
842  iris::ResourceReadResult result;
843  call().resource_read(_instId, result, ccRegIds.at(idx));
844  return result.data.at(0);
845 }
846 
847 void
849 {
850  panic_if(idx >= ccRegIds.size(),
851  "CC reg %d is not supported by fast model.", idx);
852  iris::ResourceWriteResult result;
853  call().resource_write(_instId, result, ccRegIds.at(idx), val);
854 }
855 
857 ThreadContext::readVecReg(const RegId &reg_id) const
858 {
859  const RegIndex idx = reg_id.index();
861  reg.zero();
862 
863  // Ignore accesses to registers which aren't architected. gem5 defines a
864  // few extra registers which it uses internally in the implementation of
865  // some instructions.
866  if (idx >= vecRegIds.size())
867  return reg;
868 
869  iris::ResourceReadResult result;
870  call().resource_read(_instId, result, vecRegIds.at(idx));
871  size_t data_size = result.data.size() * (sizeof(*result.data.data()));
872  size_t size = std::min(data_size, reg.size());
873  memcpy(reg.as<uint8_t>(), (void *)result.data.data(), size);
874 
875  return reg;
876 }
877 
880 {
881  return readVecReg(RegId(VecRegClass, idx));
882 }
883 
886 {
887  RegIndex idx = reg_id.index();
888 
890  reg.reset();
891 
892  if (idx >= vecPredRegIds.size())
893  return reg;
894 
895  iris::ResourceReadResult result;
896  call().resource_read(_instId, result, vecPredRegIds.at(idx));
897 
898  size_t offset = 0;
899  size_t num_bits = reg.NUM_BITS;
900  uint8_t *bytes = (uint8_t *)result.data.data();
901  while (num_bits > 8) {
902  reg.setBits(offset, 8, *bytes);
903  offset += 8;
904  num_bits -= 8;
905  bytes++;
906  }
907  if (num_bits)
908  reg.setBits(offset, num_bits, *bytes);
909 
910  return reg;
911 }
912 
915 {
916  return readVecPredReg(RegId(VecPredRegClass, idx));
917 }
918 
919 } // namespace Iris
920 } // namespace gem5
gem5::curTick
Tick curTick()
The universal simulation clock.
Definition: cur_tick.hh:46
gem5::ArmISA::MISCREG_CPSR
@ MISCREG_CPSR
Definition: misc.hh:61
gem5::Iris::ThreadContext::IdxNameMap
std::map< int, std::string > IdxNameMap
Definition: thread_context.hh:59
gem5::Iris::PhysicalMemoryNonSecureMsn
@ PhysicalMemoryNonSecureMsn
Definition: memory_spaces.hh:48
gem5::ThreadContext::Active
@ Active
Running.
Definition: thread_context.hh:109
gem5::Iris::PhysicalMemorySecureMsn
@ PhysicalMemorySecureMsn
Definition: memory_spaces.hh:47
gem5::ThreadContext::readFloatReg
RegVal readFloatReg(RegIndex reg_idx) const
Definition: thread_context.hh:210
warn
#define warn(...)
Definition: logging.hh:246
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::ArmISA::VecPredRegContainer
VecPredReg::Container VecPredRegContainer
Definition: vec.hh:68
gem5::Iris::ThreadContext::readVecRegFlat
virtual const ArmISA::VecRegContainer & readVecRegFlat(RegIndex idx) const
Definition: thread_context.cc:879
memory_spaces.hh
data
const char data[]
Definition: circlebuf.test.cc:48
gem5::Iris::ThreadContext::vecRegIds
ResourceIds vecRegIds
Definition: thread_context.hh:101
gem5::Iris::ThreadContext::pc
ArmISA::PCState pc
Definition: thread_context.hh:172
gem5::ArmISA::NumVecRegs
const int NumVecRegs
Definition: vec.hh:80
gem5::VecElemClass
@ VecElemClass
Vector Register Native Elem lane.
Definition: reg_class.hh:63
gem5::Iris::ThreadContext::regEventStreamId
iris::EventStreamId regEventStreamId
Definition: thread_context.hh:162
gem5::Iris::ThreadContext::readVecPredReg
virtual const ArmISA::VecPredRegContainer & readVecPredReg(const RegId &reg) const
Definition: thread_context.cc:885
pseudo_inst.hh
gem5::Iris::ThreadContext::getWritableRegFlat
void * getWritableRegFlat(const RegId &reg) override
Definition: thread_context.cc:769
gem5::Iris::ThreadContext::setReg
void setReg(const RegId &reg, RegVal val) override
Definition: thread_context.cc:617
gem5::Iris::ThreadContext::setRegFlat
void setRegFlat(const RegId &reg, RegVal val) override
Definition: thread_context.cc:707
gem5::CCRegClass
@ CCRegClass
Condition-code register.
Definition: reg_class.hh:65
gem5::Iris::ThreadContext::pcState
const PCStateBase & pcState() const override
Definition: thread_context.cc:557
gem5::MipsISA::event
Bitfield< 10, 5 > event
Definition: pra_constants.hh:300
gem5::Iris::ThreadContext::setCCRegFlat
virtual void setCCRegFlat(RegIndex idx, RegVal val)
Definition: thread_context.cc:848
gem5::ArmISA::err
Bitfield< 6 > err
Definition: misc_types.hh:803
gem5::Iris::ThreadContext::call
iris::IrisCppAdapter & call() const
Definition: thread_context.hh:169
translating_port_proxy.hh
gem5::ArmISA::e
Bitfield< 9 > e
Definition: misc_types.hh:65
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:769
gem5::ThreadContext::Status
Status
Definition: thread_context.hh:105
gem5::X86ISA::system
Bitfield< 15 > system
Definition: misc.hh:997
gem5::ArmSystem::callSemihosting
static bool callSemihosting(ThreadContext *tc, bool gem5_ops=false)
Make a Semihosting call from either aarch64 or aarch32.
Definition: system.cc:190
std::vector< iris::ResourceId >
gem5::ArmISA::ids
Bitfield< 39, 36 > ids
Definition: misc_types.hh:154
gem5::Iris::ThreadContext::readIntReg
virtual RegVal readIntReg(RegIndex reg_idx) const
Definition: thread_context.cc:784
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Bitfield< 5 > r
Definition: pagetable.hh:60
gem5::Iris::ThreadContext::breakpointHit
iris::IrisErrorCode breakpointHit(uint64_t esId, const iris::IrisValueMap &fields, uint64_t time, uint64_t sInstId, bool syncEc, std::string &error_message_out)
Definition: thread_context.cc:284
gem5::Iris::ThreadContext::sendFunctional
void sendFunctional(PacketPtr pkt) override
Definition: thread_context.cc:518
gem5::Iris::ThreadContext::descheduleInstCountEvent
void descheduleInstCountEvent(Event *event) override
Definition: thread_context.cc:502
gem5::Iris::ThreadContext::installBp
void installBp(BpInfoIt it)
Definition: thread_context.cc:178
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gem5::Iris::ThreadContext::initFromIrisInstance
virtual void initFromIrisInstance(const ResourceMap &resources)
Definition: thread_context.cc:65
gem5::Iris::ThreadContext::getOrAllocBp
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Definition: thread_context.cc:165
gem5::Iris::ThreadContext::uninstallBp
void uninstallBp(BpInfoIt it)
Definition: thread_context.cc:190
gem5::Iris::ThreadContext::getCpuPtr
gem5::BaseCPU * getCpuPtr() override
Definition: thread_context.hh:197
gem5::EventQueue::serviceEvents
void serviceEvents(Tick when)
process all events up to the given timestamp.
Definition: eventq.hh:876
gem5::Iris::ThreadContext::maintainStepping
void maintainStepping()
Definition: thread_context.cc:136
gem5::Iris::ThreadContext::setVecPredRegFlat
virtual void setVecPredRegFlat(RegIndex idx, const ArmISA::VecPredRegContainer &val)
Definition: thread_context.hh:436
cpu.hh
gem5::Iris::ThreadContext::enableAfterPseudoEvent
Event * enableAfterPseudoEvent
Definition: thread_context.hh:81
gem5::Iris::ThreadContext::breakpointEventStreamId
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Definition: thread_context.hh:165
gem5::VecPredRegClass
@ VecPredRegClass
Definition: reg_class.hh:64
gem5::Iris::ThreadContext::memorySpaces
std::vector< iris::MemorySpaceInfo > memorySpaces
Definition: thread_context.hh:104
gem5::BaseMMU
Definition: mmu.hh:53
gem5::Iris::ThreadContext::_status
Status _status
Definition: thread_context.hh:80
gem5::Iris::ThreadContext::vecPredRegs
std::vector< ArmISA::VecPredRegContainer > vecPredRegs
Definition: thread_context.hh:78
gem5::Iris::ThreadContext::suspend
void suspend() override
Set the status to Suspended.
Definition: thread_context.hh:244
gem5::Iris::ThreadContext::getWritableVecReg
virtual ArmISA::VecRegContainer & getWritableVecReg(const RegId &reg)
Definition: thread_context.hh:293
gem5::Iris::ThreadContext::memorySpaceIds
MemorySpaceMap memorySpaceIds
Definition: thread_context.hh:106
gem5::Iris::ThreadContext::noThrow
iris::IrisCppAdapter & noThrow() const
Definition: thread_context.hh:170
gem5::Iris::ThreadContext::setVecRegFlat
virtual void setVecRegFlat(RegIndex idx, const ArmISA::VecRegContainer &val)
Definition: thread_context.hh:413
gem5::FloatRegClass
@ FloatRegClass
Floating-point register.
Definition: reg_class.hh:59
gem5::Iris::ThreadContext::simulationTimeEvent
iris::IrisErrorCode simulationTimeEvent(uint64_t esId, const iris::IrisValueMap &fields, uint64_t time, uint64_t sInstId, bool syncEc, std::string &error_message_out)
Definition: thread_context.cc:262
gem5::Iris::ThreadContext::readCCRegFlat
virtual RegVal readCCRegFlat(RegIndex idx) const
Definition: thread_context.cc:838
gem5::Iris::ThreadContext::setVecElemFlat
virtual void setVecElemFlat(RegIndex idx, RegVal val)
Definition: thread_context.hh:424
gem5::ArmISA::NumVecPredRegs
const int NumVecPredRegs
Definition: vec.hh:81
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bool isRead() const
Definition: packet.hh:590
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Definition: system.hh:75
gem5::VecRegContainer
Vector Register Abstraction This generic class is the model in a particularization of MVC,...
Definition: vec_reg.hh:123
gem5::Iris::ThreadContext::getReg
RegVal getReg(const RegId &reg) const override
Definition: thread_context.cc:609
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Bitfield< 54 > p
Definition: pagetable.hh:70
gem5::Iris::ThreadContext::~ThreadContext
virtual ~ThreadContext()
Definition: thread_context.cc:393
gem5::ThreadContext::Suspended
@ Suspended
Temporarily inactive.
Definition: thread_context.hh:113
gem5::Event
Definition: eventq.hh:251
gem5::Iris::ThreadContext::BpInfoIt
BpInfoMap::iterator BpInfoIt
Definition: thread_context.hh:133
gem5::X86ISA::count
count
Definition: misc.hh:703
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:291
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void deschedule(Event *event)
Deschedule the specified event.
Definition: eventq.hh:797
gem5::Iris::ThreadContext::_irisPath
std::string _irisPath
Definition: thread_context.hh:72
gem5::Iris::ThreadContext::readMem
void readMem(iris::MemorySpaceId space, Addr addr, void *p, size_t size)
Definition: thread_context.cc:440
gem5::Iris::ThreadContext::miscRegIds
ResourceIds miscRegIds
Definition: thread_context.hh:92
gem5::Iris::ThreadContext
Definition: thread_context.hh:53
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::Iris::ThreadContext::setMiscRegNoEffect
void setMiscRegNoEffect(RegIndex misc_reg, const RegVal val) override
Definition: thread_context.cc:602
gem5::PCEvent
Definition: pc_event.hh:45
gem5::X86ISA::type
type
Definition: misc.hh:727
gem5::EventQueue::nextTick
Tick nextTick() const
Definition: eventq.hh:843
gem5::Iris::ThreadContext::ThreadContext
ThreadContext(gem5::BaseCPU *cpu, int id, System *system, gem5::BaseMMU *mmu, gem5::BaseISA *isa, iris::IrisConnectionInterface *iris_if, const std::string &iris_path)
Definition: thread_context.cc:326
gem5::Iris::ThreadContext::phaseInitLeave
iris::IrisErrorCode phaseInitLeave(uint64_t esId, const iris::IrisValueMap &fields, uint64_t time, uint64_t sInstId, bool syncEc, std::string &error_message_out)
Definition: thread_context.cc:232
gem5::Iris::ThreadContext::translations
std::vector< iris::MemorySupportedAddressTranslationResult > translations
Definition: thread_context.hh:105
gem5::EventQueue::empty
bool empty() const
Returns true if no events are queued.
Definition: eventq.hh:898
gem5::ArmISA::offset
Bitfield< 23, 0 > offset
Definition: types.hh:144
gem5::Iris::ThreadContext::extractResourceMap
void extractResourceMap(ResourceIds &ids, const ResourceMap &resources, const IdxNameMap &idx_names)
Definition: thread_context.cc:113
gem5::Iris::ThreadContext::ccRegIds
ResourceIds ccRegIds
Definition: thread_context.hh:96
gem5::Iris::ThreadContext::readVecReg
virtual const ArmISA::VecRegContainer & readVecReg(const RegId &reg) const
Definition: thread_context.cc:857
gem5::Iris::ThreadContext::flattenedIntIds
ResourceIds flattenedIntIds
Definition: thread_context.hh:95
gem5::Iris::ThreadContext::setIntRegFlat
virtual void setIntRegFlat(RegIndex idx, uint64_t val)
Definition: thread_context.cc:826
gem5::Iris::ThreadContext::readIntRegFlat
virtual RegVal readIntRegFlat(RegIndex idx) const
Definition: thread_context.cc:813
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::Iris::ThreadContext::delBp
void delBp(BpInfoIt it)
Definition: thread_context.cc:198
gem5::Iris::ThreadContext::vecRegs
std::vector< ArmISA::VecRegContainer > vecRegs
Definition: thread_context.hh:77
name
const std::string & name()
Definition: trace.cc:49
gem5::Iris::ThreadContext::extractResourceId
iris::ResourceId extractResourceId(const ResourceMap &resources, const std::string &name)
Definition: thread_context.cc:106
gem5::Iris::ThreadContext::getWritableVecPredRegFlat
virtual ArmISA::VecPredRegContainer & getWritableVecPredRegFlat(RegIndex idx)
Definition: thread_context.hh:431
gem5::ArmISA::isSecure
bool isSecure(ThreadContext *tc)
Definition: utility.cc:73
gem5::Iris::ThreadContext::vecPredRegIds
ResourceIds vecPredRegIds
Definition: thread_context.hh:102
utility.hh
gem5::Iris::ThreadContext::getWritableReg
void * getWritableReg(const RegId &reg) override
Definition: thread_context.cc:685
gem5::Iris::ThreadContext::timeEventStreamId
iris::EventStreamId timeEventStreamId
Definition: thread_context.hh:164
gem5::Iris::ThreadContext::semihostingEvent
iris::IrisErrorCode semihostingEvent(uint64_t esId, const iris::IrisValueMap &fields, uint64_t time, uint64_t sInstId, bool syncEc, std::string &error_message_out)
Definition: thread_context.cc:305
gem5::Iris::ThreadContext::readMiscRegNoEffect
RegVal readMiscRegNoEffect(RegIndex misc_reg) const override
Definition: thread_context.cc:594
gem5::statistics::enabled
bool enabled()
Definition: statistics.cc:286
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::EventFunctionWrapper
Definition: eventq.hh:1115
gem5::Iris::ThreadContext::scheduleInstCountEvent
void scheduleInstCountEvent(Event *event, Tick count) override
Definition: thread_context.cc:491
gem5::Iris::ThreadContext::bps
BpInfoMap bps
Definition: thread_context.hh:135
gem5::IntRegClass
@ IntRegClass
Integer register.
Definition: reg_class.hh:58
gem5::Iris::ThreadContext::instanceRegistryChanged
iris::IrisErrorCode instanceRegistryChanged(uint64_t esId, const iris::IrisValueMap &fields, uint64_t time, uint64_t sInstId, bool syncEc, std::string &error_message_out)
Definition: thread_context.cc:210
gem5::Iris::ThreadContext::getCurrentInstCount
Tick getCurrentInstCount() override
Definition: thread_context.cc:509
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:204
gem5::Iris::ThreadContext::comInstEventQueue
EventQueue comInstEventQueue
Definition: thread_context.hh:109
gem5::Iris::ThreadContext::setCCReg
virtual void setCCReg(RegIndex reg_idx, RegVal val)
Definition: thread_context.hh:340
gem5::Iris::ThreadContext::readVecPredRegFlat
virtual ArmISA::VecPredRegContainer readVecPredRegFlat(RegIndex idx) const
Definition: thread_context.cc:914
gem5::Iris::ThreadContext::intReg32Ids
ResourceIds intReg32Ids
Definition: thread_context.hh:93
gem5::Iris::ThreadContext::intReg64Ids
ResourceIds intReg64Ids
Definition: thread_context.hh:94
gem5::RegClassType
RegClassType
Enumerate the classes of registers.
Definition: reg_class.hh:56
gem5::Iris::ThreadContext::ResourceMap
std::map< std::string, iris::ResourceInfo > ResourceMap
Definition: thread_context.hh:56
gem5::MiscRegClass
@ MiscRegClass
Control (misc) register.
Definition: reg_class.hh:66
gem5::Iris::ThreadContext::translateAddress
bool translateAddress(Addr &paddr, iris::MemorySpaceId p_space, Addr vaddr, iris::MemorySpaceId v_space)
Definition: thread_context.cc:461
gem5::Iris::ThreadContext::getWritableVecPredReg
virtual ArmISA::VecPredRegContainer & getWritableVecPredReg(const RegId &reg)
Definition: thread_context.hh:307
gem5::Iris::ThreadContext::getBpSpaceIds
virtual const std::vector< iris::MemorySpaceId > & getBpSpaceIds() const =0
gem5::Iris::ThreadContext::readVecElem
virtual RegVal readVecElem(const RegId &reg) const
Definition: thread_context.hh:299
gem5::Iris::ThreadContext::readCCReg
virtual RegVal readCCReg(RegIndex reg_idx) const
Definition: thread_context.hh:313
gem5::Packet::makeResponse
void makeResponse()
Take a request packet and modify it in place to be suitable for returning as a response to that reque...
Definition: packet.hh:1044
gem5::Iris::ThreadContext::BpInfo
Definition: thread_context.hh:117
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::Iris::ThreadContext::setIntReg
virtual void setIntReg(RegIndex reg_idx, RegVal val)
Definition: thread_context.cc:797
logging.hh
gem5::ArmISA::id
Bitfield< 33 > id
Definition: misc_types.hh:251
gem5::EventQueue::schedule
void schedule(Event *event, Tick when, bool global=false)
Schedule the given event on this queue.
Definition: eventq.hh:764
gem5::Iris::ThreadContext::semihostingEventStreamId
iris::EventStreamId semihostingEventStreamId
Definition: thread_context.hh:166
se_translating_port_proxy.hh
gem5::Iris::ThreadContext::pcRscId
iris::ResourceId pcRscId
Definition: thread_context.hh:98
gem5::Iris::ThreadContext::getMemorySpaceId
iris::MemorySpaceId getMemorySpaceId(const Iris::CanonicalMsn &msn) const
Definition: thread_context.cc:129
gem5::Iris::ThreadContext::setStatus
void setStatus(Status new_status) override
Definition: thread_context.cc:542
gem5::ThreadContext::setFloatReg
void setFloatReg(RegIndex reg_idx, RegVal val)
Definition: thread_context.hh:247
gem5::Iris::ThreadContext::remove
bool remove(PCEvent *e) override
Definition: thread_context.cc:428
gem5::Iris::ThreadContext::status
Status status() const override
Definition: thread_context.cc:536
gem5::VecRegClass
@ VecRegClass
Vector Register.
Definition: reg_class.hh:61
gem5::MipsISA::vaddr
vaddr
Definition: pra_constants.hh:278
gem5::PCStateBase
Definition: pcstate.hh:57
gem5::RegId::index
constexpr RegIndex index() const
Index accessors.
Definition: reg_class.hh:188
gem5::Iris::ThreadContext::setVecElem
virtual void setVecElem(const RegId &reg, RegVal val)
Definition: thread_context.hh:327
gem5::BaseISA
Definition: isa.hh:57
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
gem5::Iris::ThreadContext::initEventStreamId
iris::EventStreamId initEventStreamId
Definition: thread_context.hh:163
gem5::Packet::getAddr
Addr getAddr() const
Definition: packet.hh:790
gem5::ArmISA::itState
static uint8_t itState(CPSR psr)
Definition: utility.hh:191
gem5::Iris::ThreadContext::getRegFlat
RegVal getRegFlat(const RegId &reg) const override
Flat register interfaces.
Definition: thread_context.cc:699
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
thread_context.hh
gem5::Iris::ThreadContext::schedule
bool schedule(PCEvent *e) override
Definition: thread_context.cc:416
gem5::Iris::ThreadContext::client
iris::IrisInstance client
Definition: thread_context.hh:168
gem5::Iris::ThreadContext::getWritableVecRegFlat
virtual ArmISA::VecRegContainer & getWritableVecRegFlat(RegIndex idx)
Definition: thread_context.hh:408
gem5::Iris::CanonicalMsn
CanonicalMsn
Definition: memory_spaces.hh:37
gem5::Iris::ThreadContext::readVecElemFlat
virtual RegVal readVecElemFlat(RegIndex idx) const
Definition: thread_context.hh:419
gem5::Packet::getSize
unsigned getSize() const
Definition: packet.hh:800
gem5::Event::scheduled
bool scheduled() const
Determine if the current event is scheduled.
Definition: eventq.hh:465
gem5::Iris::ThreadContext::BpId
uint64_t BpId
Definition: thread_context.hh:116
gem5::EventBase::Sim_Exit_Pri
static const Priority Sim_Exit_Pri
If we want to exit on this cycle, it's the very last thing we do.
Definition: eventq.hh:234
gem5::Iris::ThreadContext::setVecReg
virtual void setVecReg(const RegId &reg, const ArmISA::VecRegContainer &val)
Definition: thread_context.hh:321
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:126
gem5::Iris::ThreadContext::writeMem
void writeMem(iris::MemorySpaceId space, Addr addr, const void *p, size_t size)
Definition: thread_context.cc:450
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
gem5::Iris::ThreadContext::_instId
iris::InstanceId _instId
Definition: thread_context.hh:73
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::Packet::getPtr
T * getPtr()
get a pointer to the data ptr.
Definition: packet.hh:1197
gem5::Iris::ThreadContext::setVecPredReg
virtual void setVecPredReg(const RegId &reg, const ArmISA::VecPredRegContainer &val)
Definition: thread_context.hh:333

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