53 #include "iris/detail/IrisCppAdapter.h"
54 #include "iris/detail/IrisObjects.h"
82 iris::EventSourceInfo evSrcInfo;
84 client.registerEventCallback<Self, &Self::breakpointHit>(
85 this,
"ec_IRIS_BREAKPOINT_HIT",
86 "Handle hitting a breakpoint",
"Iris::ThreadContext");
87 call().event_getEventSource(
_instId, evSrcInfo,
"IRIS_BREAKPOINT_HIT");
89 evSrcInfo.evSrcId,
client.getInstId());
91 for (
auto it =
bps.begin(); it !=
bps.end(); it++)
94 client.registerEventCallback<Self, &Self::semihostingEvent>(
95 this,
"ec_IRIS_SEMIHOSTING_CALL_EXTENSION",
96 "Handle a semihosting call",
"Iris::ThreadContext");
98 "IRIS_SEMIHOSTING_CALL_EXTENSION");
100 evSrcInfo.evSrcId,
client.getInstId(),
103 nullptr,
"",
false, 0,
nullptr,
false,
false,
true);
110 return resources.at(
name).rscId;
118 for (
const auto &idx_name: idx_names) {
119 int idx = idx_name.first;
120 const std::string &
name = idx_name.second;
122 if (idx >=
ids.size())
123 ids.resize(idx + 1, iris::IRIS_UINT64_MAX);
133 return it ==
memorySpaceIds.end() ? iris::IRIS_UINT64_MAX : it->second;
159 Tick remaining = next - now;
160 call().step_setup(
_instId, remaining,
"instruction");
168 auto pc_it =
bps.find(
pc);
170 if (pc_it !=
bps.end())
174 panic_if(!res.second,
"Inserting breakpoint failed.");
183 for (
auto sid: space_ids) {
186 it->second->ids.push_back(
id);
193 for (
auto id: it->second->ids)
195 it->second->clearIds();
202 "BP info still had events associated with it.");
204 if (it->second->validIds())
212 uint64_t esId,
const iris::IrisValueMap &fields, uint64_t time,
213 uint64_t sInstId,
bool syncEc, std::string &error_message_out)
215 const std::string &
event = fields.at(
"EVENT").getString();
216 const iris::InstanceId
id = fields.at(
"INST_ID").getU64();
217 const std::string &
name = fields.at(
"INST_NAME").getString();
222 if (
event ==
"added")
224 else if (
event ==
"removed")
225 _instId = iris::IRIS_UINT64_MAX;
234 uint64_t esId,
const iris::IrisValueMap &fields, uint64_t time,
235 uint64_t sInstId,
bool syncEc, std::string &error_message_out)
240 std::map<iris::ResourceId, const iris::ResourceInfo *>
242 for (
const auto &resource: resources) {
243 idToResource[resource.rscId] = &resource;
246 for (
const auto &resource: resources) {
247 std::string
name = resource.name;
248 iris::ResourceId parentId = resource.parentRscId;
249 while (parentId != iris::IRIS_UINT64_MAX) {
250 const auto *parent = idToResource[parentId];
252 parentId = parent->parentRscId;
254 resourceMap[
name] = resource;
264 uint64_t esId,
const iris::IrisValueMap &fields, uint64_t time,
265 uint64_t sInstId,
bool syncEc, std::string &error_message_out)
267 if (fields.at(
"RUNNING").getAsBool()) {
279 call().simulationTime_run(iris::IrisInstIdSimulationEngine);
286 uint64_t esId,
const iris::IrisValueMap &fields, uint64_t time,
287 uint64_t sInstId,
bool syncEc, std::string &error_message_out)
289 Addr pc = fields.at(
"PC").getU64();
293 std::shared_ptr<BpInfo::EventList> events = it->second->events;
294 auto e_it = events->begin();
295 while (e_it != events->end()) {
307 uint64_t esId,
const iris::IrisValueMap &fields, uint64_t time,
308 uint64_t sInstId,
bool syncEc, std::string &error_message_out)
313 call().perInstanceExecution_setState(
_instId,
false);
329 BaseISA *isa, iris::IrisConnectionInterface *iris_if,
330 const std::string &iris_path) :
331 _cpu(cpu), _threadId(
id), _system(
system), _mmu(mmu), _isa(isa),
332 _irisPath(iris_path), vecRegs(ArmISA::
NumVecRegs),
334 comInstEventQueue(
"instruction-based event queue"),
335 client(iris_if,
"client." + iris_path)
337 iris::InstanceInfo info;
338 auto ret_code =
noThrow().instanceRegistry_getInstanceInfoByName(
339 info,
"component." + iris_path);
340 if (ret_code == iris::E_ok) {
345 _instId = iris::IRIS_UINT64_MAX;
349 iris::EventSourceInfo evSrcInfo;
351 client.registerEventCallback<Self, &Self::instanceRegistryChanged>(
352 this,
"ec_IRIS_INSTANCE_REGISTRY_CHANGED",
353 "Install the iris instance ID",
"Iris::ThreadContext");
354 call().event_getEventSource(iris::IrisInstIdGlobalInstance, evSrcInfo,
355 "IRIS_INSTANCE_REGISTRY_CHANGED");
358 {
"EVENT",
"INST_ID",
"INST_NAME" };
360 evSrcInfo.evSrcId,
client.getInstId(), &fields);
362 client.registerEventCallback<Self, &Self::phaseInitLeave>(
363 this,
"ec_IRIS_SIM_PHASE_INIT_LEAVE",
364 "Initialize register contexts",
"Iris::ThreadContext");
365 call().event_getEventSource(iris::IrisInstIdSimulationEngine, evSrcInfo,
366 "IRIS_SIM_PHASE_INIT_LEAVE");
368 call().eventStream_create(
370 evSrcInfo.evSrcId,
client.getInstId());
372 client.registerEventCallback<Self, &Self::simulationTimeEvent>(
373 this,
"ec_IRIS_SIMULATION_TIME_EVENT",
374 "Handle simulation time stopping for breakpoints or stepping",
375 "Iris::ThreadContext");
376 call().event_getEventSource(iris::IrisInstIdSimulationEngine, evSrcInfo,
377 "IRIS_SIMULATION_TIME_EVENT");
379 call().eventStream_create(
381 evSrcInfo.evSrcId,
client.getInstId());
386 auto enable_lambda = [
this]{
387 call().perInstanceExecution_setState(
_instId,
true);
390 enable_lambda,
"resume after pseudo inst",
396 call().eventStream_destroy(
399 client.unregisterEventCallback(
"ec_IRIS_SIM_PHASE_INIT_LEAVE");
401 call().eventStream_destroy(
404 client.unregisterEventCallback(
"ec_IRIS_INSTANCE_REGISTRY_CHANGED");
406 call().eventStream_destroy(
409 client.unregisterEventCallback(
"ec_IRIS_SIMULATION_TIME_EVENT");
420 it->second->events->push_back(
e);
422 if (
_instId != iris::IRIS_UINT64_MAX && !it->second->validIds())
432 it->second->events->remove(
e);
434 if (it->second->empty())
442 iris::MemorySpaceId space,
Addr addr,
void *
p,
size_t size)
444 iris::r0master::MemoryReadResult
r;
446 panic_if(
err != iris::r0master::E_ok,
"readMem failed.");
447 std::memcpy(
p,
r.data.data(), size);
452 iris::MemorySpaceId space,
Addr addr,
const void *
p,
size_t size)
455 std::memcpy(
data.data(),
p, size);
456 iris::MemoryWriteResult
r;
458 panic_if(
err != iris::r0master::E_ok,
"writeMem failed.");
465 iris::MemoryAddressTranslationResult result;
466 auto ret =
noThrow().memory_translateAddress(
469 if (ret != iris::E_ok) {
473 if (trans.inSpaceId == v_space && trans.outSpaceId == p_space)
476 panic(
"No legal translation IRIS address translation found.");
479 if (result.address.empty())
482 if (result.address.size() > 1) {
483 warn(
"Multiple mappings for address %#x.",
vaddr);
487 paddr = result.address[0];
497 call().simulationTime_stop(iris::IrisInstIdSimulationEngine);
514 panic_if(ret != iris::E_ok,
"Failed to get instruction count.");
560 if (new_status ==
Active) {
562 call().perInstanceExecution_setState(
_instId,
true);
565 call().perInstanceExecution_setState(
_instId,
false);
576 pc.nextThumb(
pc.thumb());
578 pc.nextJazelle(cpsr.j);
579 pc.aarch64(!cpsr.width);
580 pc.nextAArch64(!cpsr.width);
581 pc.illegalExec(
false);
585 iris::ResourceReadResult result;
588 if (cpsr.width && cpsr.t)
600 if (cpsr.width && cpsr.t)
603 iris::ResourceWriteResult result;
610 iris::ResourceId rsc_id = iris::IRIS_UINT64_MAX;
614 panic_if(rsc_id == iris::IRIS_UINT64_MAX,
615 "Misc reg %s is not supported by fast model.",
623 iris::ResourceReadResult result;
625 return result.data.at(0);
631 iris::ResourceWriteResult result;
653 const bool flat =
reg.regClass().isFlat();
673 panic(
"MiscRegs should not be read with getReg.");
675 panic(
"Unrecognized register class type %d.",
type);
695 panic(
"MiscRegs should not be read with getReg.");
697 panic(
"Unrecognized register class type %d.",
type);
706 const bool flat =
reg.regClass().isFlat();
726 panic(
"MiscRegs should not be read with getReg.");
728 panic(
"Unrecognized register class type %d.",
type);
748 panic(
"MiscRegs should not be read with getReg.");
750 panic(
"Unrecognized register class type %d.",
type);
759 const bool flat =
reg.regClass().isFlat();
768 panic(
"Unrecognized register class type %d.",
type);
777 panic(
"Unrecognized register class type %d.",
type);
787 iris::ResourceId rsc_id = iris::IRIS_UINT64_MAX;
788 if (int_reg < regIds.size())
789 rsc_id = regIds.at(int_reg);
791 panic_if(rsc_id == iris::IRIS_UINT64_MAX,
792 "Int reg %s is not supported by fast model.",
800 iris::ResourceReadResult result;
802 return result.data.at(0);
808 iris::ResourceWriteResult result;
815 iris::ResourceId rsc_id = iris::IRIS_UINT64_MAX;
829 if (rsc_id == iris::IRIS_UINT64_MAX)
831 iris::ResourceReadResult result;
833 return result.data.at(0);
840 panic_if(rsc_id == iris::IRIS_UINT64_MAX,
841 "Int reg %s is not supported by fast model.",
843 iris::ResourceWriteResult result;
850 iris::ResourceId rsc_id = iris::IRIS_UINT64_MAX;
860 if (rsc_id == iris::IRIS_UINT64_MAX)
862 iris::ResourceReadResult result;
864 return result.data.at(0);
871 panic_if(rsc_id == iris::IRIS_UINT64_MAX,
872 "CC reg %s is not supported by fast model.",
874 iris::ResourceWriteResult result;
881 iris::ResourceId rsc_id = iris::IRIS_UINT64_MAX;
898 if (rsc_id == iris::IRIS_UINT64_MAX)
901 iris::ResourceReadResult result;
903 size_t data_size = result.data.size() * (
sizeof(*result.data.data()));
904 size_t size = std::min(data_size,
reg.size());
905 memcpy(
reg.as<uint8_t>(), (
void *)result.data.data(), size);
919 iris::ResourceId rsc_id = iris::IRIS_UINT64_MAX;
934 if (rsc_id == iris::IRIS_UINT64_MAX)
937 iris::ResourceReadResult result;
941 size_t num_bits =
reg.NUM_BITS;
942 uint8_t *bytes = (uint8_t *)result.data.data();
943 while (num_bits > 8) {
static bool callSemihosting(ThreadContext *tc, bool gem5_ops=false)
Make a Semihosting call from either aarch64 or aarch32.
EventQueue comInstEventQueue
virtual void initFromIrisInstance(const ResourceMap &resources)
virtual void setVecPredReg(const RegId ®, const ArmISA::VecPredRegContainer &val)
void * getWritableReg(const RegId ®) override
ThreadContext(gem5::BaseCPU *cpu, int id, System *system, gem5::BaseMMU *mmu, gem5::BaseISA *isa, iris::IrisConnectionInterface *iris_if, const std::string &iris_path)
iris::ResourceId getMiscRegRscId(RegIndex misc_reg) const
bool remove(PCEvent *e) override
void uninstallBp(BpInfoIt it)
void setStatus(Status new_status) override
void readMemWithCurrentMsn(Addr vaddr, size_t size, char *data)
virtual RegVal readVecElemFlat(RegIndex idx) const
virtual void setCCReg(RegIndex reg_idx, RegVal val)
virtual void setVecReg(const RegId ®, const ArmISA::VecRegContainer &val)
MemorySpaceMap memorySpaceIds
std::vector< iris::MemorySupportedAddressTranslationResult > translations
virtual const std::vector< iris::MemorySpaceId > & getBpSpaceIds() const =0
ResourceIds vecPredRegIds
virtual RegVal readCCRegFlat(RegIndex idx) const
iris::IrisCppAdapter & noThrow() const
void installBp(BpInfoIt it)
iris::ResourceId getIntRegFlatRscId(RegIndex int_reg) const
Flat register interfaces.
ResourceIds flattenedIntIds
void descheduleInstCountEvent(Event *event) override
virtual RegVal readCCReg(RegIndex reg_idx) const
virtual ArmISA::VecRegContainer & getWritableVecRegFlat(RegIndex idx)
Status status() const override
void sendFunctional(PacketPtr pkt) override
void extractResourceMap(ResourceIds &ids, const ResourceMap &resources, const IdxNameMap &idx_names)
iris::ResourceId getVecPredRegRscId(RegIndex vec_reg) const
bool translateAddress(Addr &paddr, iris::MemorySpaceId p_space, Addr vaddr, iris::MemorySpaceId v_space)
iris::ResourceId getVecRegRscId(RegIndex vec_reg) const
void writeMem(iris::MemorySpaceId space, Addr addr, const void *p, size_t size)
iris::IrisErrorCode phaseInitLeave(uint64_t esId, const iris::IrisValueMap &fields, uint64_t time, uint64_t sInstId, bool syncEc, std::string &error_message_out)
virtual RegVal readIntRegFlat(RegIndex idx) const
iris::IrisCppAdapter & call() const
Tick getCurrentInstCount() override
const PCStateBase & pcState() const override
virtual const ArmISA::VecPredRegContainer & readVecPredReg(const RegId ®) const
virtual void setVecPredRegFlat(RegIndex idx, const ArmISA::VecPredRegContainer &val)
iris::IrisErrorCode semihostingEvent(uint64_t esId, const iris::IrisValueMap &fields, uint64_t time, uint64_t sInstId, bool syncEc, std::string &error_message_out)
virtual RegVal readVecElem(const RegId ®) const
iris::IrisErrorCode simulationTimeEvent(uint64_t esId, const iris::IrisValueMap &fields, uint64_t time, uint64_t sInstId, bool syncEc, std::string &error_message_out)
virtual const ArmISA::VecRegContainer & readVecReg(const RegId ®) const
iris::ResourceId getCCRegFlatRscId(RegIndex cc_reg) const
RegVal getReg(const RegId ®) const override
iris::EventStreamId regEventStreamId
virtual void setVecRegFlat(RegIndex idx, const ArmISA::VecRegContainer &val)
iris::EventStreamId initEventStreamId
iris::EventStreamId semihostingEventStreamId
void readMem(iris::MemorySpaceId space, Addr addr, void *p, size_t size)
BpInfoIt getOrAllocBp(Addr pc)
virtual ArmISA::VecPredRegContainer & getWritableVecPredReg(const RegId ®)
gem5::BaseCPU * getCpuPtr() override
std::vector< ArmISA::VecRegContainer > vecRegs
std::map< std::string, iris::ResourceInfo > ResourceMap
std::map< int, std::string > IdxNameMap
virtual void setVecElemFlat(RegIndex idx, RegVal val)
iris::MemorySpaceId getMemorySpaceId(const Iris::CanonicalMsn &msn) const
virtual ArmISA::VecRegContainer & getWritableVecReg(const RegId ®)
RegVal readMiscRegNoEffect(RegIndex misc_reg) const override
void suspend() override
Set the status to Suspended.
iris::IrisErrorCode breakpointHit(uint64_t esId, const iris::IrisValueMap &fields, uint64_t time, uint64_t sInstId, bool syncEc, std::string &error_message_out)
std::vector< ArmISA::VecPredRegContainer > vecPredRegs
virtual void setIntRegFlat(RegIndex idx, uint64_t val)
virtual ArmISA::VecPredRegContainer readVecPredRegFlat(RegIndex idx) const
BpInfoMap::iterator BpInfoIt
iris::ResourceId extractResourceId(const ResourceMap &resources, const std::string &name)
void writeMemWithCurrentMsn(Addr vaddr, size_t size, const char *data)
virtual RegVal readIntReg(RegIndex reg_idx) const
std::vector< iris::MemorySpaceInfo > memorySpaces
virtual void setVecElem(const RegId ®, RegVal val)
virtual void setIntReg(RegIndex reg_idx, RegVal val)
iris::EventStreamId timeEventStreamId
bool schedule(PCEvent *e) override
iris::ResourceId getIntRegRscId(RegIndex int_reg) const
iris::EventStreamId breakpointEventStreamId
virtual void setCCRegFlat(RegIndex idx, RegVal val)
void scheduleInstCountEvent(Event *event, Tick count) override
virtual const ArmISA::VecRegContainer & readVecRegFlat(RegIndex idx) const
virtual ArmISA::VecPredRegContainer & getWritableVecPredRegFlat(RegIndex idx)
iris::IrisErrorCode instanceRegistryChanged(uint64_t esId, const iris::IrisValueMap &fields, uint64_t time, uint64_t sInstId, bool syncEc, std::string &error_message_out)
void setReg(const RegId ®, RegVal val) override
iris::IrisInstance client
void setMiscRegNoEffect(RegIndex misc_reg, const RegVal val) override
Event * enableAfterPseudoEvent
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
T * getPtr()
get a pointer to the data ptr.
void makeResponse()
Take a request packet and modify it in place to be suitable for returning as a response to that reque...
Register ID: describe an architectural register with its class and index.
constexpr RegIndex index() const
Index accessors.
@ Suspended
Temporarily inactive.
Vector Register Abstraction This generic class is the model in a particularization of MVC,...
void schedule(Event *event, Tick when, bool global=false)
Schedule the given event on this queue.
void deschedule(Event *event)
Deschedule the specified event.
void deschedule(Event &event)
void serviceEvents(Tick when)
process all events up to the given timestamp.
bool scheduled() const
Determine if the current event is scheduled.
void schedule(Event &event, Tick when)
static const Priority Sim_Exit_Pri
If we want to exit on this cycle, it's the very last thing we do.
bool empty() const
Returns true if no events are queued.
#define panic(...)
This implements a cprintf based panic() function.
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
constexpr RegClass ccRegClass(CCRegClass, CCRegClassName, cc_reg::NumRegs, debug::CCRegs)
bool isSecure(ThreadContext *tc)
VecPredReg::Container VecPredRegContainer
constexpr RegClass intRegClass
constexpr RegClass vecPredRegClass
constexpr RegClass miscRegClass
static uint8_t itState(CPSR psr)
constexpr RegClass vecRegClass
@ PhysicalMemorySecureMsn
@ PhysicalMemoryNonSecureMsn
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Tick curTick()
The universal simulation clock.
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
uint64_t Tick
Tick count type.
RegClassType
Enumerate the classes of registers.
@ CCRegClass
Condition-code register.
@ VecRegClass
Vector Register.
@ IntRegClass
Integer register.
@ MiscRegClass
Control (misc) register.
@ VecElemClass
Vector Register Native Elem lane.
const std::string & name()