gem5  v21.1.0.2
thread_context.cc
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39 
41 
42 #include <utility>
43 
45 #include "arch/arm/system.hh"
46 #include "arch/arm/utility.hh"
47 #include "iris/detail/IrisCppAdapter.h"
48 #include "iris/detail/IrisObjects.h"
51 #include "sim/pseudo_inst.hh"
52 
53 namespace gem5
54 {
55 
56 namespace Iris
57 {
58 
59 void
61 {
62  bool enabled = false;
63  call().perInstanceExecution_getState(_instId, enabled);
65 
66  suspend();
67 
68  call().memory_getMemorySpaces(_instId, memorySpaces);
69  call().memory_getUsefulAddressTranslations(_instId, translations);
70 
71  typedef ThreadContext Self;
72  iris::EventSourceInfo evSrcInfo;
73 
74  client.registerEventCallback<Self, &Self::breakpointHit>(
75  this, "ec_IRIS_BREAKPOINT_HIT",
76  "Handle hitting a breakpoint", "Iris::ThreadContext");
77  call().event_getEventSource(_instId, evSrcInfo, "IRIS_BREAKPOINT_HIT");
78  call().eventStream_create(_instId, breakpointEventStreamId,
79  evSrcInfo.evSrcId, client.getInstId());
80 
81  for (auto it = bps.begin(); it != bps.end(); it++)
82  installBp(it);
83 
84  client.registerEventCallback<Self, &Self::semihostingEvent>(
85  this, "ec_IRIS_SEMIHOSTING_CALL_EXTENSION",
86  "Handle a semihosting call", "Iris::ThreadContext");
87  call().event_getEventSource(_instId, evSrcInfo,
88  "IRIS_SEMIHOSTING_CALL_EXTENSION");
89  call().eventStream_create(_instId, semihostingEventStreamId,
90  evSrcInfo.evSrcId, client.getInstId(),
91  // Set all arguments to their defaults, except syncEc which is
92  // changed to true.
93  nullptr, "", false, 0, nullptr, false, false, true);
94 }
95 
96 iris::ResourceId
98  const ResourceMap &resources, const std::string &name)
99 {
100  return resources.at(name).rscId;
101 }
102 
103 void
105  ResourceIds &ids, const ResourceMap &resources,
106  const IdxNameMap &idx_names)
107 {
108  for (const auto &idx_name: idx_names) {
109  int idx = idx_name.first;
110  const std::string &name = idx_name.second;
111 
112  if (idx >= ids.size())
113  ids.resize(idx + 1, iris::IRIS_UINT64_MAX);
114 
115  ids[idx] = extractResourceId(resources, name);
116  }
117 }
118 
119 void
121 {
122  Tick now = 0;
123 
124  while (true) {
125  if (comInstEventQueue.empty()) {
126  // Set to 0 to deactivate stepping.
127  call().step_setup(_instId, 0, "instruction");
128  break;
129  }
130 
132  if (!now)
133  now = getCurrentInstCount();
134 
135  if (next <= now) {
137  // Start over now that comInstEventQueue has likely changed.
138  continue;
139  }
140 
141  // Set to the number of instructions still to step through.
142  Tick remaining = next - now;
143  call().step_setup(_instId, remaining, "instruction");
144  break;
145  }
146 }
147 
150 {
151  auto pc_it = bps.find(pc);
152 
153  if (pc_it != bps.end())
154  return pc_it;
155 
156  auto res = bps.emplace(std::make_pair(pc, new BpInfo(pc)));
157  panic_if(!res.second, "Inserting breakpoint failed.");
158  return res.first;
159 }
160 
161 void
163 {
164  Addr pc = it->second->pc;
165  const auto &space_ids = getBpSpaceIds();
166  for (auto sid: space_ids) {
167  BpId id;
168  call().breakpoint_set_code(_instId, id, pc, sid, 0, true);
169  it->second->ids.push_back(id);
170  }
171 }
172 
173 void
175 {
176  for (auto id: it->second->ids)
177  call().breakpoint_delete(_instId, id);
178  it->second->clearIds();
179 }
180 
181 void
183 {
184  panic_if(!it->second->empty(),
185  "BP info still had events associated with it.");
186 
187  if (it->second->validIds())
188  uninstallBp(it);
189 
190  bps.erase(it);
191 }
192 
193 iris::IrisErrorCode
195  uint64_t esId, const iris::IrisValueMap &fields, uint64_t time,
196  uint64_t sInstId, bool syncEc, std::string &error_message_out)
197 {
198  const std::string &event = fields.at("EVENT").getString();
199  const iris::InstanceId id = fields.at("INST_ID").getU64();
200  const std::string &name = fields.at("INST_NAME").getString();
201 
202  if (name != "component." + _irisPath)
203  return iris::E_ok;
204 
205  if (event == "added")
206  _instId = id;
207  else if (event == "removed")
208  _instId = iris::IRIS_UINT64_MAX;
209  else
210  panic("Unrecognized event type %s", event);
211 
212  return iris::E_ok;
213 }
214 
215 iris::IrisErrorCode
217  uint64_t esId, const iris::IrisValueMap &fields, uint64_t time,
218  uint64_t sInstId, bool syncEc, std::string &error_message_out)
219 {
221  call().resource_getList(_instId, resources);
222 
223  std::map<iris::ResourceId, const iris::ResourceInfo *>
224  idToResource;
225  for (const auto &resource: resources) {
226  idToResource[resource.rscId] = &resource;
227  }
228  ResourceMap resourceMap;
229  for (const auto &resource: resources) {
230  std::string name = resource.name;
231  iris::ResourceId parentId = resource.parentRscId;
232  while (parentId != iris::IRIS_UINT64_MAX) {
233  const auto *parent = idToResource[parentId];
234  name = parent->name + "." + name;
235  parentId = parent->parentRscId;
236  }
237  resourceMap[name] = resource;
238  }
239 
240  initFromIrisInstance(resourceMap);
241 
242  return iris::E_ok;
243 }
244 
245 iris::IrisErrorCode
247  uint64_t esId, const iris::IrisValueMap &fields, uint64_t time,
248  uint64_t sInstId, bool syncEc, std::string &error_message_out)
249 {
250  if (fields.at("RUNNING").getAsBool()) {
251  // If this is just simulation time starting up, don't do anything.
252  return iris::E_ok;
253  }
254 
255  // If simulation time has stopped for any reason, IRIS helpfully clears
256  // all stepping counters and we need to set them back. We might also need
257  // to service events based on the current number of executed instructions.
259 
260  // Restart simulation time to make sure things progress once we give
261  // control back.
262  call().simulationTime_run(iris::IrisInstIdSimulationEngine);
263 
264  return iris::E_ok;
265 }
266 
267 iris::IrisErrorCode
269  uint64_t esId, const iris::IrisValueMap &fields, uint64_t time,
270  uint64_t sInstId, bool syncEc, std::string &error_message_out)
271 {
272  Addr pc = fields.at("PC").getU64();
273 
274  auto it = getOrAllocBp(pc);
275 
276  std::shared_ptr<BpInfo::EventList> events = it->second->events;
277  auto e_it = events->begin();
278  while (e_it != events->end()) {
279  PCEvent *e = *e_it;
280  // Advance e_it here since e might remove itself from the list.
281  e_it++;
282  e->process(this);
283  }
284 
285  return iris::E_ok;
286 }
287 
288 iris::IrisErrorCode
290  uint64_t esId, const iris::IrisValueMap &fields, uint64_t time,
291  uint64_t sInstId, bool syncEc, std::string &error_message_out)
292 {
293  if (ArmSystem::callSemihosting(this, true)) {
294  // Stop execution in case an exit of the sim loop was scheduled. We
295  // don't want to keep executing instructions in the mean time.
296  call().perInstanceExecution_setState(_instId, false);
297 
298  // Schedule an event to resume execution right after any exit has
299  // had a chance to happen.
302 
303  call().semihosting_return(_instId, readIntReg(0));
304  } else {
305  call().semihosting_notImplemented(_instId);
306  }
307  return iris::E_ok;
308 }
309 
311  gem5::BaseCPU *cpu, int id, System *system, gem5::BaseMMU *mmu,
312  BaseISA *isa, iris::IrisConnectionInterface *iris_if,
313  const std::string &iris_path) :
314  _cpu(cpu), _threadId(id), _system(system), _mmu(mmu), _isa(isa),
315  _irisPath(iris_path), vecRegs(ArmISA::NumVecRegs),
316  vecPredRegs(ArmISA::NumVecPredRegs),
317  comInstEventQueue("instruction-based event queue"),
318  client(iris_if, "client." + iris_path)
319 {
320  iris::InstanceInfo info;
321  auto ret_code = noThrow().instanceRegistry_getInstanceInfoByName(
322  info, "component." + iris_path);
323  if (ret_code == iris::E_ok) {
324  // The iris instance registry already new about this path.
325  _instId = info.instId;
326  } else {
327  // This path doesn't (yet) exist. Set the ID to something invalid.
328  _instId = iris::IRIS_UINT64_MAX;
329  }
330 
331  typedef ThreadContext Self;
332  iris::EventSourceInfo evSrcInfo;
333 
334  client.registerEventCallback<Self, &Self::instanceRegistryChanged>(
335  this, "ec_IRIS_INSTANCE_REGISTRY_CHANGED",
336  "Install the iris instance ID", "Iris::ThreadContext");
337  call().event_getEventSource(iris::IrisInstIdGlobalInstance, evSrcInfo,
338  "IRIS_INSTANCE_REGISTRY_CHANGED");
339  regEventStreamId = iris::IRIS_UINT64_MAX;
340  static const std::vector<std::string> fields =
341  { "EVENT", "INST_ID", "INST_NAME" };
342  call().eventStream_create(iris::IrisInstIdGlobalInstance, regEventStreamId,
343  evSrcInfo.evSrcId, client.getInstId(), &fields);
344 
345  client.registerEventCallback<Self, &Self::phaseInitLeave>(
346  this, "ec_IRIS_SIM_PHASE_INIT_LEAVE",
347  "Initialize register contexts", "Iris::ThreadContext");
348  call().event_getEventSource(iris::IrisInstIdSimulationEngine, evSrcInfo,
349  "IRIS_SIM_PHASE_INIT_LEAVE");
350  initEventStreamId = iris::IRIS_UINT64_MAX;
351  call().eventStream_create(
352  iris::IrisInstIdSimulationEngine, initEventStreamId,
353  evSrcInfo.evSrcId, client.getInstId());
354 
355  client.registerEventCallback<Self, &Self::simulationTimeEvent>(
356  this, "ec_IRIS_SIMULATION_TIME_EVENT",
357  "Handle simulation time stopping for breakpoints or stepping",
358  "Iris::ThreadContext");
359  call().event_getEventSource(iris::IrisInstIdSimulationEngine, evSrcInfo,
360  "IRIS_SIMULATION_TIME_EVENT");
361  timeEventStreamId = iris::IRIS_UINT64_MAX;
362  call().eventStream_create(
363  iris::IrisInstIdSimulationEngine, timeEventStreamId,
364  evSrcInfo.evSrcId, client.getInstId());
365 
366  breakpointEventStreamId = iris::IRIS_UINT64_MAX;
367  semihostingEventStreamId = iris::IRIS_UINT64_MAX;
368 
369  auto enable_lambda = [this]{
370  call().perInstanceExecution_setState(_instId, true);
371  };
373  enable_lambda, "resume after pseudo inst",
374  false, Event::Sim_Exit_Pri + 1);
375 }
376 
378 {
379  call().eventStream_destroy(
380  iris::IrisInstIdSimulationEngine, initEventStreamId);
381  initEventStreamId = iris::IRIS_UINT64_MAX;
382  client.unregisterEventCallback("ec_IRIS_SIM_PHASE_INIT_LEAVE");
383 
384  call().eventStream_destroy(
385  iris::IrisInstIdGlobalInstance, regEventStreamId);
386  regEventStreamId = iris::IRIS_UINT64_MAX;
387  client.unregisterEventCallback("ec_IRIS_INSTANCE_REGISTRY_CHANGED");
388 
389  call().eventStream_destroy(
390  iris::IrisInstIdGlobalInstance, timeEventStreamId);
391  timeEventStreamId = iris::IRIS_UINT64_MAX;
392  client.unregisterEventCallback("ec_IRIS_SIMULATION_TIME_EVENT");
393 
396  delete enableAfterPseudoEvent;
397 }
398 
399 bool
401 {
402  auto it = getOrAllocBp(e->pc());
403  it->second->events->push_back(e);
404 
405  if (_instId != iris::IRIS_UINT64_MAX && !it->second->validIds())
406  installBp(it);
407 
408  return true;
409 }
410 
411 bool
413 {
414  auto it = getOrAllocBp(e->pc());
415  it->second->events->remove(e);
416 
417  if (it->second->empty())
418  delBp(it);
419 
420  return true;
421 }
422 
423 bool
424 ThreadContext::translateAddress(Addr &paddr, iris::MemorySpaceId p_space,
425  Addr vaddr, iris::MemorySpaceId v_space)
426 {
427  iris::MemoryAddressTranslationResult result;
428  auto ret = noThrow().memory_translateAddress(
429  _instId, result, v_space, vaddr, p_space);
430 
431  if (ret != iris::E_ok) {
432  // Check if there was a legal translation between these two spaces.
433  // If so, something else went wrong.
434  for (auto &trans: translations)
435  if (trans.inSpaceId == v_space && trans.outSpaceId == p_space)
436  return false;
437 
438  panic("No legal translation IRIS address translation found.");
439  }
440 
441  if (result.address.empty())
442  return false;
443 
444  if (result.address.size() > 1) {
445  warn("Multiple mappings for address %#x.", vaddr);
446  return false;
447  }
448 
449  paddr = result.address[0];
450  return true;
451 }
452 
453 void
455 {
456  Tick now = getCurrentInstCount();
458  if (count <= now)
459  call().simulationTime_stop(iris::IrisInstIdSimulationEngine);
460  else
462 }
463 
464 void
466 {
469 }
470 
471 Tick
473 {
474  uint64_t count;
475  auto ret = call().step_getStepCounterValue(_instId, count, "instruction");
476  panic_if(ret != iris::E_ok, "Failed to get instruction count.");
477  return count;
478 }
479 
480 void
482 {
483  assert(!virtProxy);
484  if (FullSystem) {
485  virtProxy.reset(new TranslatingPortProxy(tc));
486  } else {
487  virtProxy.reset(new SETranslatingPortProxy(this,
489  }
490 }
491 
492 void
494 {
495  auto *iris_cpu = dynamic_cast<Iris::BaseCPU *>(getCpuPtr());
496  assert(iris_cpu);
497  iris_cpu->evs_base_cpu->sendFunc(pkt);
498 }
499 
502 {
503  return _status;
504 }
505 
506 void
508 {
511  if (new_status == Active) {
512  if (_status != Active)
513  call().perInstanceExecution_setState(_instId, true);
514  } else {
515  if (_status == Active)
516  call().perInstanceExecution_setState(_instId, false);
517  }
518  _status = new_status;
519 }
520 
523 {
524  ArmISA::CPSR cpsr = readMiscRegNoEffect(ArmISA::MISCREG_CPSR);
526 
527  pc.thumb(cpsr.t);
528  pc.nextThumb(pc.thumb());
529  pc.jazelle(cpsr.j);
530  pc.nextJazelle(cpsr.j);
531  pc.aarch64(!cpsr.width);
532  pc.nextAArch64(!cpsr.width);
533  pc.illegalExec(false);
534  pc.itstate(ArmISA::itState(cpsr));
535  pc.nextItstate(0);
536 
537  iris::ResourceReadResult result;
538  call().resource_read(_instId, result, pcRscId);
539  Addr addr = result.data.at(0);
540  if (cpsr.width && cpsr.t)
541  addr = addr & ~0x1;
542  pc.set(addr);
543 
544  return pc;
545 }
546 void
548 {
549  Addr pc = val.pc();
550 
551  ArmISA::CPSR cpsr = readMiscRegNoEffect(ArmISA::MISCREG_CPSR);
552  if (cpsr.width && cpsr.t)
553  pc = pc | 0x1;
554 
555  iris::ResourceWriteResult result;
556  call().resource_write(_instId, result, pcRscId, pc);
557 }
558 
559 Addr
561 {
562  return pcState().instAddr();
563 }
564 
565 Addr
567 {
568  return pcState().nextInstAddr();
569 }
570 
571 RegVal
573 {
574  iris::ResourceReadResult result;
575  call().resource_read(_instId, result, miscRegIds.at(misc_reg));
576  return result.data.at(0);
577 }
578 
579 void
581 {
582  iris::ResourceWriteResult result;
583  call().resource_write(_instId, result, miscRegIds.at(misc_reg), val);
584 }
585 
586 RegVal
588 {
589  ArmISA::CPSR cpsr = readMiscRegNoEffect(ArmISA::MISCREG_CPSR);
590 
591  iris::ResourceReadResult result;
592  if (cpsr.width)
593  call().resource_read(_instId, result, intReg32Ids.at(reg_idx));
594  else
595  call().resource_read(_instId, result, intReg64Ids.at(reg_idx));
596  return result.data.at(0);
597 }
598 
599 void
601 {
602  ArmISA::CPSR cpsr = readMiscRegNoEffect(ArmISA::MISCREG_CPSR);
603 
604  iris::ResourceWriteResult result;
605  if (cpsr.width)
606  call().resource_write(_instId, result, intReg32Ids.at(reg_idx), val);
607  else
608  call().resource_write(_instId, result, intReg64Ids.at(reg_idx), val);
609 }
610 
611 /*
612  * The 64 bit version of registers gives us a pre-flattened view of the reg
613  * file, no matter what mode we're in or if we're currently 32 or 64 bit.
614  */
615 RegVal
617 {
618  if (idx >= flattenedIntIds.size())
619  return 0;
620  iris::ResourceId res_id = flattenedIntIds.at(idx);
621  if (res_id == iris::IRIS_UINT64_MAX)
622  return 0;
623  iris::ResourceReadResult result;
624  call().resource_read(_instId, result, res_id);
625  return result.data.at(0);
626 }
627 
628 void
630 {
631  iris::ResourceId res_id =
632  (idx >= flattenedIntIds.size()) ? iris::IRIS_UINT64_MAX :
633  flattenedIntIds.at(idx);
634  panic_if(res_id == iris::IRIS_UINT64_MAX,
635  "Int reg %d is not supported by fast model.", idx);
636  iris::ResourceWriteResult result;
637  call().resource_write(_instId, result, flattenedIntIds.at(idx), val);
638 }
639 
640 RegVal
642 {
643  if (idx >= ccRegIds.size())
644  return 0;
645  iris::ResourceReadResult result;
646  call().resource_read(_instId, result, ccRegIds.at(idx));
647  return result.data.at(0);
648 }
649 
650 void
652 {
653  panic_if(idx >= ccRegIds.size(),
654  "CC reg %d is not supported by fast model.", idx);
655  iris::ResourceWriteResult result;
656  call().resource_write(_instId, result, ccRegIds.at(idx), val);
657 }
658 
660 ThreadContext::readVecReg(const RegId &reg_id) const
661 {
662  const RegIndex idx = reg_id.index();
664  reg.zero();
665 
666  // Ignore accesses to registers which aren't architected. gem5 defines a
667  // few extra registers which it uses internally in the implementation of
668  // some instructions.
669  if (idx >= vecRegIds.size())
670  return reg;
671 
672  iris::ResourceReadResult result;
673  call().resource_read(_instId, result, vecRegIds.at(idx));
674  size_t data_size = result.data.size() * (sizeof(*result.data.data()));
675  size_t size = std::min(data_size, reg.size());
676  memcpy(reg.as<uint8_t>(), (void *)result.data.data(), size);
677 
678  return reg;
679 }
680 
683 {
684  return readVecReg(RegId(VecRegClass, idx));
685 }
686 
689 {
690  RegIndex idx = reg_id.index();
691 
693  reg.reset();
694 
695  if (idx >= vecPredRegIds.size())
696  return reg;
697 
698  iris::ResourceReadResult result;
699  call().resource_read(_instId, result, vecPredRegIds.at(idx));
700 
701  size_t offset = 0;
702  size_t num_bits = reg.NUM_BITS;
703  uint8_t *bytes = (uint8_t *)result.data.data();
704  while (num_bits > 8) {
705  reg.setBits(offset, 8, *bytes);
706  offset += 8;
707  num_bits -= 8;
708  bytes++;
709  }
710  if (num_bits)
711  reg.setBits(offset, num_bits, *bytes);
712 
713  return reg;
714 }
715 
718 {
719  return readVecPredReg(RegId(VecPredRegClass, idx));
720 }
721 
722 } // namespace Iris
723 } // namespace gem5
gem5::curTick
Tick curTick()
The universal simulation clock.
Definition: cur_tick.hh:46
gem5::ArmISA::MISCREG_CPSR
@ MISCREG_CPSR
Definition: misc.hh:61
gem5::SETranslatingPortProxy
Definition: se_translating_port_proxy.hh:49
gem5::Iris::ThreadContext::IdxNameMap
std::map< int, std::string > IdxNameMap
Definition: thread_context.hh:57
gem5::ThreadContext::Active
@ Active
Running.
Definition: thread_context.hh:108
warn
#define warn(...)
Definition: logging.hh:245
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::Iris::ThreadContext::readIntRegFlat
RegVal readIntRegFlat(RegIndex idx) const override
Flat register interfaces.
Definition: thread_context.cc:616
gem5::Iris::ThreadContext::pcState
ArmISA::PCState pcState() const override
Definition: thread_context.cc:522
gem5::ArmISA::VecPredRegContainer
VecPredReg::Container VecPredRegContainer
Definition: vec.hh:68
gem5::Iris::ThreadContext::vecRegIds
ResourceIds vecRegIds
Definition: thread_context.hh:95
gem5::ArmISA::NumVecRegs
const int NumVecRegs
Definition: vec.hh:80
gem5::Iris::ThreadContext::readVecPredReg
const ArmISA::VecPredRegContainer & readVecPredReg(const RegId &reg) const override
Definition: thread_context.cc:688
gem5::SETranslatingPortProxy::NextPage
@ NextPage
Definition: se_translating_port_proxy.hh:57
gem5::Iris::ThreadContext::regEventStreamId
iris::EventStreamId regEventStreamId
Definition: thread_context.hh:158
pseudo_inst.hh
gem5::Iris::BaseCPU
Definition: cpu.hh:60
gem5::MipsISA::event
Bitfield< 10, 5 > event
Definition: pra_constants.hh:300
gem5::Iris::ThreadContext::nextInstAddr
Addr nextInstAddr() const override
Definition: thread_context.cc:566
gem5::Iris::ThreadContext::call
iris::IrisCppAdapter & call() const
Definition: thread_context.hh:165
translating_port_proxy.hh
gem5::ArmISA::e
Bitfield< 9 > e
Definition: misc_types.hh:64
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
gem5::ThreadContext::Status
Status
Definition: thread_context.hh:104
gem5::VecPredRegClass
@ VecPredRegClass
Definition: reg_class.hh:63
gem5::Iris::ThreadContext::setIntReg
void setIntReg(RegIndex reg_idx, RegVal val) override
Definition: thread_context.cc:600
gem5::X86ISA::system
Bitfield< 15 > system
Definition: misc.hh:1003
gem5::ArmSystem::callSemihosting
static bool callSemihosting(ThreadContext *tc, bool gem5_ops=false)
Make a Semihosting call from either aarch64 or aarch32.
Definition: system.cc:203
gem5::EventManager::schedule
void schedule(Event &event, Tick when)
Definition: eventq.hh:1019
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gem5::ArmISA::ids
Bitfield< 39, 36 > ids
Definition: misc_types.hh:153
gem5::Iris::ThreadContext::breakpointHit
iris::IrisErrorCode breakpointHit(uint64_t esId, const iris::IrisValueMap &fields, uint64_t time, uint64_t sInstId, bool syncEc, std::string &error_message_out)
Definition: thread_context.cc:268
gem5::Iris::ThreadContext::sendFunctional
void sendFunctional(PacketPtr pkt) override
Definition: thread_context.cc:493
gem5::Iris::ThreadContext::descheduleInstCountEvent
void descheduleInstCountEvent(Event *event) override
Definition: thread_context.cc:465
gem5::Iris::ThreadContext::installBp
void installBp(BpInfoIt it)
Definition: thread_context.cc:162
system.hh
gem5::Iris::ThreadContext::initFromIrisInstance
virtual void initFromIrisInstance(const ResourceMap &resources)
Definition: thread_context.cc:60
gem5::Iris::ThreadContext::getOrAllocBp
BpInfoIt getOrAllocBp(Addr pc)
Definition: thread_context.cc:149
gem5::Iris::ThreadContext::uninstallBp
void uninstallBp(BpInfoIt it)
Definition: thread_context.cc:174
gem5::Iris::ThreadContext::getCpuPtr
gem5::BaseCPU * getCpuPtr() override
Definition: thread_context.hh:187
gem5::RegId::index
RegIndex index() const
Index accessors.
Definition: reg_class.hh:154
gem5::EventQueue::serviceEvents
void serviceEvents(Tick when)
process all events up to the given timestamp.
Definition: eventq.hh:876
gem5::Iris::ThreadContext::maintainStepping
void maintainStepping()
Definition: thread_context.cc:120
cpu.hh
gem5::Iris::ThreadContext::enableAfterPseudoEvent
Event * enableAfterPseudoEvent
Definition: thread_context.hh:76
gem5::Iris::ThreadContext::breakpointEventStreamId
iris::EventStreamId breakpointEventStreamId
Definition: thread_context.hh:161
gem5::Iris::ThreadContext::memorySpaces
std::vector< iris::MemorySpaceInfo > memorySpaces
Definition: thread_context.hh:98
gem5::BaseMMU
Definition: mmu.hh:50
gem5::Iris::ThreadContext::_status
Status _status
Definition: thread_context.hh:75
gem5::TranslatingPortProxy
This proxy attempts to translate virtual addresses using the TLBs.
Definition: translating_port_proxy.hh:58
gem5::Iris::ThreadContext::vecPredRegs
std::vector< ArmISA::VecPredRegContainer > vecPredRegs
Definition: thread_context.hh:73
gem5::Iris::ThreadContext::suspend
void suspend() override
Set the status to Suspended.
Definition: thread_context.hh:237
gem5::Iris::ThreadContext::noThrow
iris::IrisCppAdapter & noThrow() const
Definition: thread_context.hh:166
gem5::Iris::ThreadContext::simulationTimeEvent
iris::IrisErrorCode simulationTimeEvent(uint64_t esId, const iris::IrisValueMap &fields, uint64_t time, uint64_t sInstId, bool syncEc, std::string &error_message_out)
Definition: thread_context.cc:246
gem5::ArmISA::NumVecPredRegs
const int NumVecPredRegs
Definition: vec.hh:81
gem5::System
Definition: system.hh:77
gem5::VecRegContainer< NumVecElemPerVecReg *sizeof(VecElem)>
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::Iris::ThreadContext::~ThreadContext
virtual ~ThreadContext()
Definition: thread_context.cc:377
gem5::ThreadContext::Suspended
@ Suspended
Temporarily inactive.
Definition: thread_context.hh:112
gem5::Event
Definition: eventq.hh:251
gem5::Iris::ThreadContext::BpInfoIt
BpInfoMap::iterator BpInfoIt
Definition: thread_context.hh:129
gem5::X86ISA::count
count
Definition: misc.hh:709
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::EventQueue::deschedule
void deschedule(Event *event)
Deschedule the specified event.
Definition: eventq.hh:797
gem5::Iris::ThreadContext::_irisPath
std::string _irisPath
Definition: thread_context.hh:67
gem5::Iris::ThreadContext::miscRegIds
ResourceIds miscRegIds
Definition: thread_context.hh:86
gem5::Iris::ThreadContext
Definition: thread_context.hh:51
gem5::MipsISA::PCState
GenericISA::DelaySlotPCState< 4 > PCState
Definition: pcstate.hh:40
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::Iris::ThreadContext::setMiscRegNoEffect
void setMiscRegNoEffect(RegIndex misc_reg, const RegVal val) override
Definition: thread_context.cc:580
gem5::PCEvent
Definition: pc_event.hh:45
gem5::Iris::ThreadContext::virtProxy
std::unique_ptr< PortProxy > virtProxy
Definition: thread_context.hh:101
gem5::EventQueue::nextTick
Tick nextTick() const
Definition: eventq.hh:843
gem5::Iris::ThreadContext::readCCRegFlat
RegVal readCCRegFlat(RegIndex idx) const override
Definition: thread_context.cc:641
gem5::Iris::ThreadContext::ThreadContext
ThreadContext(gem5::BaseCPU *cpu, int id, System *system, gem5::BaseMMU *mmu, gem5::BaseISA *isa, iris::IrisConnectionInterface *iris_if, const std::string &iris_path)
Definition: thread_context.cc:310
gem5::Iris::ThreadContext::readVecPredRegFlat
const ArmISA::VecPredRegContainer & readVecPredRegFlat(RegIndex idx) const override
Definition: thread_context.cc:717
gem5::Iris::ThreadContext::phaseInitLeave
iris::IrisErrorCode phaseInitLeave(uint64_t esId, const iris::IrisValueMap &fields, uint64_t time, uint64_t sInstId, bool syncEc, std::string &error_message_out)
Definition: thread_context.cc:216
gem5::Iris::ThreadContext::readVecRegFlat
const ArmISA::VecRegContainer & readVecRegFlat(RegIndex idx) const override
Definition: thread_context.cc:682
gem5::Iris::ThreadContext::translations
std::vector< iris::MemorySupportedAddressTranslationResult > translations
Definition: thread_context.hh:99
gem5::EventQueue::empty
bool empty() const
Returns true if no events are queued.
Definition: eventq.hh:898
gem5::ArmISA::offset
Bitfield< 23, 0 > offset
Definition: types.hh:144
gem5::BaseCPU
Definition: base.hh:107
gem5::Iris::ThreadContext::extractResourceMap
void extractResourceMap(ResourceIds &ids, const ResourceMap &resources, const IdxNameMap &idx_names)
Definition: thread_context.cc:104
gem5::Iris::ThreadContext::ccRegIds
ResourceIds ccRegIds
Definition: thread_context.hh:90
gem5::Iris::ThreadContext::flattenedIntIds
ResourceIds flattenedIntIds
Definition: thread_context.hh:89
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::Iris::ThreadContext::delBp
void delBp(BpInfoIt it)
Definition: thread_context.cc:182
gem5::Iris::ThreadContext::vecRegs
std::vector< ArmISA::VecRegContainer > vecRegs
Definition: thread_context.hh:72
name
const std::string & name()
Definition: trace.cc:49
gem5::Iris::ThreadContext::extractResourceId
iris::ResourceId extractResourceId(const ResourceMap &resources, const std::string &name)
Definition: thread_context.cc:97
gem5::Iris::ThreadContext::vecPredRegIds
ResourceIds vecPredRegIds
Definition: thread_context.hh:96
utility.hh
gem5::EventManager::deschedule
void deschedule(Event &event)
Definition: eventq.hh:1028
gem5::Iris::ThreadContext::timeEventStreamId
iris::EventStreamId timeEventStreamId
Definition: thread_context.hh:160
gem5::Iris::ThreadContext::semihostingEvent
iris::IrisErrorCode semihostingEvent(uint64_t esId, const iris::IrisValueMap &fields, uint64_t time, uint64_t sInstId, bool syncEc, std::string &error_message_out)
Definition: thread_context.cc:289
gem5::Iris::ThreadContext::readMiscRegNoEffect
RegVal readMiscRegNoEffect(RegIndex misc_reg) const override
Definition: thread_context.cc:572
gem5::statistics::enabled
bool enabled()
Definition: statistics.cc:280
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::EventFunctionWrapper
Definition: eventq.hh:1115
gem5::FullSystem
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:223
gem5::Iris::ThreadContext::setCCRegFlat
void setCCRegFlat(RegIndex idx, RegVal val) override
Definition: thread_context.cc:651
gem5::Iris::ThreadContext::scheduleInstCountEvent
void scheduleInstCountEvent(Event *event, Tick count) override
Definition: thread_context.cc:454
gem5::Iris::ThreadContext::bps
BpInfoMap bps
Definition: thread_context.hh:131
gem5::Iris::ThreadContext::instanceRegistryChanged
iris::IrisErrorCode instanceRegistryChanged(uint64_t esId, const iris::IrisValueMap &fields, uint64_t time, uint64_t sInstId, bool syncEc, std::string &error_message_out)
Definition: thread_context.cc:194
gem5::VecRegClass
@ VecRegClass
Vector Register.
Definition: reg_class.hh:60
gem5::Iris::ThreadContext::getCurrentInstCount
Tick getCurrentInstCount() override
Definition: thread_context.cc:472
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:203
gem5::Iris::ThreadContext::comInstEventQueue
EventQueue comInstEventQueue
Definition: thread_context.hh:105
gem5::Iris::ThreadContext::intReg32Ids
ResourceIds intReg32Ids
Definition: thread_context.hh:87
gem5::Iris::ThreadContext::intReg64Ids
ResourceIds intReg64Ids
Definition: thread_context.hh:88
gem5::Iris::ThreadContext::initMemProxies
void initMemProxies(gem5::ThreadContext *tc) override
Initialise the physical and virtual port proxies and tie them to the data port of the CPU.
Definition: thread_context.cc:481
gem5::Iris::ThreadContext::ResourceMap
std::map< std::string, iris::ResourceInfo > ResourceMap
Definition: thread_context.hh:54
gem5::Iris::ThreadContext::translateAddress
bool translateAddress(Addr &paddr, iris::MemorySpaceId p_space, Addr vaddr, iris::MemorySpaceId v_space)
Definition: thread_context.cc:424
gem5::Iris::ThreadContext::getBpSpaceIds
virtual const std::vector< iris::MemorySpaceId > & getBpSpaceIds() const =0
gem5::Iris::ThreadContext::BpInfo
Definition: thread_context.hh:113
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::ArmISA::id
Bitfield< 33 > id
Definition: misc_types.hh:250
gem5::EventQueue::schedule
void schedule(Event *event, Tick when, bool global=false)
Schedule the given event on this queue.
Definition: eventq.hh:764
gem5::Iris::ThreadContext::semihostingEventStreamId
iris::EventStreamId semihostingEventStreamId
Definition: thread_context.hh:162
se_translating_port_proxy.hh
gem5::Iris::ThreadContext::pcRscId
iris::ResourceId pcRscId
Definition: thread_context.hh:92
gem5::Iris::ThreadContext::setStatus
void setStatus(Status new_status) override
Definition: thread_context.cc:507
gem5::Iris::ThreadContext::remove
bool remove(PCEvent *e) override
Definition: thread_context.cc:412
gem5::Iris::ThreadContext::status
Status status() const override
Definition: thread_context.cc:501
gem5::MipsISA::vaddr
vaddr
Definition: pra_constants.hh:278
gem5::BaseISA
Definition: isa.hh:54
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
gem5::Iris::ThreadContext::initEventStreamId
iris::EventStreamId initEventStreamId
Definition: thread_context.hh:159
gem5::ArmISA::itState
static uint8_t itState(CPSR psr)
Definition: utility.hh:197
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
thread_context.hh
gem5::Iris::ThreadContext::schedule
bool schedule(PCEvent *e) override
Definition: thread_context.cc:400
gem5::Iris::ThreadContext::client
iris::IrisInstance client
Definition: thread_context.hh:164
gem5::Iris::ThreadContext::readIntReg
RegVal readIntReg(RegIndex reg_idx) const override
Definition: thread_context.cc:587
gem5::Iris::ThreadContext::setIntRegFlat
void setIntRegFlat(RegIndex idx, uint64_t val) override
Definition: thread_context.cc:629
gem5::Iris::ThreadContext::readVecReg
const ArmISA::VecRegContainer & readVecReg(const RegId &reg) const override
Definition: thread_context.cc:660
gem5::Event::scheduled
bool scheduled() const
Determine if the current event is scheduled.
Definition: eventq.hh:465
gem5::Iris::ThreadContext::instAddr
Addr instAddr() const override
Definition: thread_context.cc:560
gem5::Iris::ThreadContext::BpId
uint64_t BpId
Definition: thread_context.hh:112
gem5::EventBase::Sim_Exit_Pri
static const Priority Sim_Exit_Pri
If we want to exit on this cycle, it's the very last thing we do.
Definition: eventq.hh:234
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:88
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::Iris::ThreadContext::_instId
iris::InstanceId _instId
Definition: thread_context.hh:68
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84

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