gem5  v21.1.0.2
pmu.hh
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37 
38 #ifndef __ARCH_ARM_PMU_HH__
39 #define __ARCH_ARM_PMU_HH__
40 
41 #include <map>
42 #include <memory>
43 #include <vector>
44 
45 #include "arch/arm/isa_device.hh"
46 #include "arch/arm/system.hh"
47 #include "base/cprintf.hh"
48 #include "cpu/base.hh"
49 #include "debug/PMUVerbose.hh"
50 #include "sim/eventq.hh"
51 #include "sim/sim_object.hh"
52 #include "sim/system.hh"
53 
54 namespace gem5
55 {
56 
57 struct ArmPMUParams;
58 class Platform;
59 class ThreadContext;
60 class ArmInterruptPin;
61 
62 namespace ArmISA {
63 
64 
96 class PMU : public SimObject, public ArmISA::BaseISADevice
97 {
98  public:
99  PMU(const ArmPMUParams &p);
100  ~PMU();
101 
102  void addEventProbe(unsigned int id, SimObject *obj, const char *name);
103  void addSoftwareIncrementEvent(unsigned int id);
104 
105  void registerEvent(uint32_t id);
106 
107  public: // SimObject and related interfaces
108  void serialize(CheckpointOut &cp) const override;
109  void unserialize(CheckpointIn &cp) override;
110 
111  void drainResume() override;
112 
113  void regProbeListeners() override;
114 
115  public: // ISA Device interface
116  void setThreadContext(ThreadContext *tc) override;
117 
124  void setMiscReg(int misc_reg, RegVal val) override;
131  RegVal readMiscReg(int misc_reg) override;
132 
133  protected: // PMU register types and constants
134  BitUnion32(PMCR_t)
135  // PMU Enable
136  Bitfield<0> e;
137  // Event counter reset
138  Bitfield<1> p;
139  // Cycle counter reset
140  Bitfield<2> c;
141  // Cycle counter divider enable
142  Bitfield<3> d;
143  // Export enable
144  Bitfield<4> x;
145  // Disable PMCCNTR when event counting is prohibited
146  Bitfield<5> dp;
147  // Long Cycle counter enable
148  Bitfield<6> lc;
149  // Number of event counters implemented
150  Bitfield<15, 11> n;
151  // Implementation ID
152  Bitfield<23, 16> idcode;
153  // Implementer code
154  Bitfield<31, 24> imp;
155  EndBitUnion(PMCR_t)
156 
157  BitUnion32(PMSELR_t)
158  // Performance counter selector
159  Bitfield<4, 0> sel;
160  EndBitUnion(PMSELR_t)
161 
162  BitUnion32(PMEVTYPER_t)
163  Bitfield<15, 0> evtCount;
164 
165  // Secure EL3 filtering
166  Bitfield<26> m;
167  // Non-secure EL2 mode filtering
168  Bitfield<27> nsh;
169  // Non-secure EL0 mode filtering
170  Bitfield<28> nsu;
171  // Non-secure EL1 mode filtering
172  Bitfield<29> nsk;
173  // EL0 filtering
174  Bitfield<30> u;
175  // EL1 filtering
176  Bitfield<31> p;
177  EndBitUnion(PMEVTYPER_t)
178 
186  typedef unsigned int CounterId;
187 
189  static const CounterId PMCCNTR = 31;
190 
196  typedef unsigned int EventTypeId;
197 
198  protected: /* High-level register and interrupt handling */
199  RegVal readMiscRegInt(int misc_reg);
200 
209  void setControlReg(PMCR_t val);
210 
214  void resetEventCounts();
215 
219  void raiseInterrupt();
220 
224  void clearInterrupt();
225 
236  uint64_t getCounterValue(CounterId id) const {
237  return isValidCounter(id) ? getCounter(id).getValue() : 0;
238  }
239 
247  void setCounterValue(CounterId id, uint64_t val);
248 
260  PMEVTYPER_t getCounterTypeRegister(CounterId id) const;
261 
275  void setCounterTypeRegister(CounterId id, PMEVTYPER_t type);
276 
287  void setOverflowStatus(RegVal new_val);
288 
289  protected: /* Probe handling and counter state */
290  struct CounterState;
291 
295  struct PMUEvent
296  {
297 
298  PMUEvent() {}
299 
300  virtual ~PMUEvent() {}
301 
307  void attachEvent(PMU::CounterState *user);
308 
314  void detachEvent(PMU::CounterState *user);
315 
323  virtual void increment(const uint64_t val);
324 
328  virtual void enable() = 0;
329 
333  virtual void disable() = 0;
334 
339  virtual void updateAttachedCounters() {}
340 
341  protected:
342 
344  std::set<PMU::CounterState*> userCounters;
345  };
346 
347  struct RegularEvent : public PMUEvent
348  {
350 
352  std::string name) {
353 
354  panic_if(!object,"malformed probe-point"
355  " definition with name %s\n", name);
356 
357  microArchitectureEventSet.emplace(object, name);
358  }
359 
360  protected:
361  struct RegularProbe: public ProbeListenerArgBase<uint64_t>
362  {
364  std::string name)
366  parentEvent(parent) {}
367 
368  RegularProbe() = delete;
369 
370  void notify(const uint64_t &val);
371 
372  protected:
374  };
375 
377  std::set<EventTypeEntry> microArchitectureEventSet;
378 
383 
384  void enable() override;
385 
386  void disable() override;
387  };
388 
389  class SWIncrementEvent : public PMUEvent
390  {
391  void enable() override {}
392  void disable() override {}
393 
394  public:
395 
402  void write(uint64_t val);
403  };
404 
411  PMUEvent* getEvent(uint64_t eventId);
412 
414  struct CounterState : public Serializable
415  {
416  CounterState(PMU &pmuReference, uint64_t counter_id)
417  : eventId(0), filter(0), enabled(false),
418  overflow64(false), sourceEvent(nullptr),
419  counterId(counter_id), value(0), resetValue(false),
420  pmu(pmuReference) {}
421 
422  void serialize(CheckpointOut &cp) const override;
423  void unserialize(CheckpointIn &cp) override;
424 
431  uint64_t add(uint64_t delta);
432 
433  bool isFiltered() const;
434 
438  void detach();
439 
445  void attach(PMUEvent* event);
446 
452  uint64_t getCounterId() const{
453  return counterId;
454  }
455 
461  uint64_t getValue() const;
462 
468  void setValue(uint64_t val);
469 
470  public: /* Serializable state */
473 
475  PMEVTYPER_t filter;
476 
478  bool enabled;
479 
482 
483  protected: /* Configuration */
486 
488  uint64_t counterId;
489 
491  uint64_t value;
492 
495 
497 
498  template <typename ...Args>
499  void debugCounter(const char* mainString, Args &...args) const {
500 
501  std::string userString = csprintf(mainString, args...);
502 
503  warn("[counterId = %d, eventId = %d, sourceEvent = 0x%x] %s",
504  counterId, eventId, sourceEvent, userString.c_str());
505 
506  }
507  };
508 
517  bool isValidCounter(CounterId id) const {
518  return id < counters.size() || id == PMCCNTR;
519  }
520 
528  CounterState &getCounter(CounterId id) {
529  assert(isValidCounter(id));
530  return id == PMCCNTR ? cycleCounter : counters[id];
531  }
532 
540  const CounterState &getCounter(CounterId id) const {
541  assert(isValidCounter(id));
542  return id == PMCCNTR ? cycleCounter : counters[id];
543  }
544 
556  void updateCounter(CounterState &ctr);
557 
564  bool isFiltered(const CounterState &ctr) const;
565 
572  void updateAllCounters();
573 
574  protected: /* State that needs to be serialized */
577 
579  PMCR_t reg_pmcr;
580 
582  PMSELR_t reg_pmselr;
583 
586 
589 
596  uint64_t reg_pmceid0;
597  uint64_t reg_pmceid1;
598 
600  unsigned clock_remainder;
601 
604 
607 
610 
612  const uint64_t cycleCounterEventId;
613 
616 
617  protected: /* Configuration and constants */
620 
622  static const RegVal reg_pmcr_wr_mask;
623 
626 
630  std::map<EventTypeId, PMUEvent*> eventMap;
631 };
632 
633 } // namespace ArmISA
634 } // namespace gem5
635 
636 #endif
gem5::ArmISA::PMU::SWIncrementEvent::enable
void enable() override
Enable the current event.
Definition: pmu.hh:391
isa_device.hh
gem5::ArmISA::PMU::p
Bitfield< 1 > p
Definition: pmu.hh:138
gem5::ArmISA::PMU::addEventProbe
void addEventProbe(unsigned int id, SimObject *obj, const char *name)
Definition: pmu.cc:127
gem5::ArmISA::PMU::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: pmu.cc:690
gem5::ArmISA::PMU::PMUEvent::enable
virtual void enable()=0
Enable the current event.
gem5::ArmISA::PMU::dp
Bitfield< 5 > dp
Definition: pmu.hh:146
gem5::auxv::Platform
@ Platform
Definition: aux_vector.hh:84
gem5::ArmISA::PMU::CounterState::isFiltered
bool isFiltered() const
Definition: pmu.cc:493
gem5::ArmISA::PMU::u
Bitfield< 30 > u
Definition: pmu.hh:174
gem5::ArmISA::PMU::setCounterValue
void setCounterValue(CounterId id, uint64_t val)
Set the value of a performance counter.
Definition: pmu.cc:601
gem5::ArmISA::PMU::raiseInterrupt
void raiseInterrupt()
Deliver a PMU interrupt to the GIC.
Definition: pmu.cc:666
gem5::ArmISA::PMU::RegularEvent::addMicroarchitectureProbe
void addMicroarchitectureProbe(SimObject *object, std::string name)
Definition: pmu.hh:351
warn
#define warn(...)
Definition: logging.hh:245
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
system.hh
gem5::ArmISA::PMU::setMiscReg
void setMiscReg(int misc_reg, RegVal val) override
Set a register within the PMU.
Definition: pmu.cc:192
gem5::ArmISA::PMU::maximumCounterCount
uint64_t maximumCounterCount
The number of regular event counters.
Definition: pmu.hh:603
gem5::ArmISA::PMU::RegularEvent::RegularProbe::notify
void notify(const uint64_t &val)
Definition: pmu.cc:472
gem5::ArmISA::PMU::CounterState
State of a counter within the PMU.
Definition: pmu.hh:414
gem5::ArmISA::PMU::imp
Bitfield< 31, 24 > imp
Definition: pmu.hh:154
gem5::ArmISA::PMU::CounterState::getCounterId
uint64_t getCounterId() const
Obtain the counter id.
Definition: pmu.hh:452
gem5::ArmISA::PMU::cycleCounter
CounterState cycleCounter
State of the cycle counter.
Definition: pmu.hh:609
gem5::ArmISA::PMU::SWIncrementEvent::disable
void disable() override
Disable the current event.
Definition: pmu.hh:392
gem5::ArmISA::PMU::PMUEvent::detachEvent
void detachEvent(PMU::CounterState *user)
detach this event from a given counter
Definition: pmu.cc:462
gem5::ArmISA::PMU::nsk
Bitfield< 29 > nsk
Definition: pmu.hh:172
gem5::ArmISA::PMU::RegularEvent::disable
void disable() override
Disable the current event.
Definition: pmu.cc:487
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::ArmISA::PMU::getCounterTypeRegister
PMEVTYPER_t getCounterTypeRegister(CounterId id) const
Get the type and filter settings of a counter (PMEVTYPER)
Definition: pmu.cc:614
gem5::MipsISA::event
Bitfield< 10, 5 > event
Definition: pra_constants.hh:300
gem5::ArmISA::PMU::RegularEvent::RegularProbe
Definition: pmu.hh:361
gem5::ArmISA::PMU::isFiltered
bool isFiltered(const CounterState &ctr) const
Check if a counter's settings allow it to be counted.
gem5::ArmISA::PMU::updateCounter
void updateCounter(CounterState &ctr)
Depending on counter configuration, add or remove the probes driving the counter.
Definition: pmu.cc:571
gem5::ArmISA::PMU::getEvent
PMUEvent * getEvent(uint64_t eventId)
Obtain the event of a given id.
Definition: pmu.cc:738
gem5::ArmISA::e
Bitfield< 9 > e
Definition: misc_types.hh:64
gem5::ArmISA::PMU::SWIncrementEvent
Definition: pmu.hh:389
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
gem5::ArmISA::PMU::reg_pmceid0
uint64_t reg_pmceid0
Performance counter ID register.
Definition: pmu.hh:596
gem5::ArmISA::PMU::CounterState::eventId
EventTypeId eventId
Counter event ID.
Definition: pmu.hh:472
gem5::ArmISA::PMU::setOverflowStatus
void setOverflowStatus(RegVal new_val)
Used for writing the Overflow Flag Status Register (SET/CLR)
Definition: pmu.cc:652
gem5::ArmISA::PMU::CounterState::setValue
void setValue(uint64_t val)
overwrite the value of the counter
Definition: pmu.cc:557
std::vector
STL vector class.
Definition: stl.hh:37
gem5::ArmISA::PMU::CounterState::add
uint64_t add(uint64_t delta)
Add an event count to the counter and check for overflow.
Definition: pmu.cc:767
gem5::csprintf
std::string csprintf(const char *format, const Args &...args)
Definition: cprintf.hh:161
system.hh
gem5::ArmISA::PMU::PMUEvent::attachEvent
void attachEvent(PMU::CounterState *user)
attach this event to a given counter
Definition: pmu.cc:444
gem5::ArmISA::PMU::eventMap
std::map< EventTypeId, PMUEvent * > eventMap
List of event types supported by this PMU.
Definition: pmu.hh:630
gem5::ArmISA::PMU::CounterState::sourceEvent
PMUEvent * sourceEvent
PmuEvent currently in use (if any)
Definition: pmu.hh:485
gem5::ArmISA::PMU::RegularEvent::microArchitectureEventSet
std::set< EventTypeEntry > microArchitectureEventSet
The set of events driving the event value.
Definition: pmu.hh:377
gem5::ArmISA::PMU::CounterState::getValue
uint64_t getValue() const
rReturn the counter value
Definition: pmu.cc:545
gem5::ArmISA::PMU::counters
std::vector< CounterState > counters
State of all general-purpose counters supported by PMU.
Definition: pmu.hh:606
gem5::ArmISA::PMU::resetEventCounts
void resetEventCounts()
Reset all event counters excluding the cycle counter to zero.
Definition: pmu.cc:594
gem5::ArmISA::PMU::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: pmu.cc:710
gem5::ArmISA::PMU::RegularEvent::RegularProbe::RegularProbe
RegularProbe()=delete
gem5::ArmISA::PMU::CounterState::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: pmu.cc:759
gem5::ArmISA::PMU::c
Bitfield< 2 > c
Definition: pmu.hh:140
gem5::ArmISA::PMU::RegularEvent::attachedProbePointList
std::vector< std::unique_ptr< RegularProbe > > attachedProbePointList
Set of probe listeners tapping onto each of the input micro-arch events which compose this pmu event.
Definition: pmu.hh:382
gem5::ArmISA::PMU::BitUnion32
BitUnion32(PMCR_t) Bitfield< 0 > e
gem5::ArmISA::PMU::nsu
Bitfield< 28 > nsu
Definition: pmu.hh:170
gem5::ArmISA::PMU::CounterState::pmu
PMU & pmu
Definition: pmu.hh:496
gem5::ArmISA::PMU::lc
Bitfield< 6 > lc
Definition: pmu.hh:148
gem5::Serializable
Basic support for object serialization.
Definition: serialize.hh:169
gem5::ArmISA::PMU::EndBitUnion
EndBitUnion(PMCR_t) BitUnion32(PMSELR_t) Bitfield< 4
gem5::ArmISA::PMU::CounterState::debugCounter
void debugCounter(const char *mainString, Args &...args) const
Definition: pmu.hh:499
gem5::ArmISA::PMU::CounterState::attach
void attach(PMUEvent *event)
Attach this counter to an event.
Definition: pmu.cc:534
gem5::ArmISA::PMU::PMCCNTR
static const CounterId PMCCNTR
Cycle Count Register Number.
Definition: pmu.hh:189
gem5::ArmISA::PMU::getCounter
CounterState & getCounter(CounterId id)
Return the state of a counter.
Definition: pmu.hh:528
gem5::ArmISA::PMU::PMUEvent::updateAttachedCounters
virtual void updateAttachedCounters()
Method called immediately before a counter access in order for the associated event to update its sta...
Definition: pmu.hh:339
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::Named::name
virtual std::string name() const
Definition: named.hh:47
sim_object.hh
gem5::ArmISA::PMU::RegularEvent::RegularProbe::parentEvent
RegularEvent * parentEvent
Definition: pmu.hh:373
gem5::ArmISA::PMU::x
Bitfield< 4 > x
Definition: pmu.hh:144
gem5::ArmISA::PMU::PMUEvent::~PMUEvent
virtual ~PMUEvent()
Definition: pmu.hh:300
gem5::ArmISA::PMU::clearInterrupt
void clearInterrupt()
Clear a PMU interrupt.
Definition: pmu.cc:678
gem5::ArmISA::PMU::CounterState::enabled
bool enabled
Is the counter enabled?
Definition: pmu.hh:478
gem5::ArmISA::PMU::CounterState::filter
PMEVTYPER_t filter
Filtering settings (evtCount is unused)
Definition: pmu.hh:475
gem5::ArmISA::PMU::n
Bitfield< 15, 11 > n
Definition: pmu.hh:150
gem5::X86ISA::type
type
Definition: misc.hh:733
gem5::ArmISA::PMU::reg_pmcr
PMCR_t reg_pmcr
Performance Monitor Control Register.
Definition: pmu.hh:579
gem5::ArmISA::PMU::drainResume
void drainResume() override
Resume execution after a successful drain.
Definition: pmu.cc:169
gem5::ArmISA::PMU::idcode
Bitfield< 23, 16 > idcode
Definition: pmu.hh:152
gem5::ArmISA::PMU::regProbeListeners
void regProbeListeners() override
Register probe listeners for this object.
Definition: pmu.cc:176
cprintf.hh
gem5::ArmISA::PMU::reg_pmovsr
RegVal reg_pmovsr
Performance Monitor Overflow Status Register.
Definition: pmu.hh:588
gem5::ArmISA::PMU::cycleCounterEventId
const uint64_t cycleCounterEventId
The id of the counter hardwired to the cpu cycle counter.
Definition: pmu.hh:612
gem5::ArmISA::PMU::PMUEvent::increment
virtual void increment(const uint64_t val)
notify an event increment of val units, all the attached counters' value is incremented by val units.
Definition: pmu.cc:454
gem5::ArmISA::PMU::sel
sel
Definition: pmu.hh:159
gem5::ArmISA::PMU::reg_pmselr
PMSELR_t reg_pmselr
Performance Monitor Selection Register.
Definition: pmu.hh:582
gem5::SimObject
Abstract superclass for simulation objects.
Definition: sim_object.hh:146
gem5::ArmISA::PMU::isValidCounter
bool isValidCounter(CounterId id) const
Is this a valid counter ID?
Definition: pmu.hh:517
gem5::ArmISA::PMU::CounterState::detach
void detach()
Detach the counter from its event.
Definition: pmu.cc:522
gem5::ArmISA::PMU::setCounterTypeRegister
void setCounterTypeRegister(CounterId id, PMEVTYPER_t type)
Set the type and filter settings of a performance counter (PMEVTYPER)
Definition: pmu.cc:628
std::pair
STL pair class.
Definition: stl.hh:58
gem5::ArmISA::PMU::reg_pmcnten
RegVal reg_pmcnten
Performance Monitor Count Enable Register.
Definition: pmu.hh:576
gem5::ArmISA::PMU::getCounterValue
uint64_t getCounterValue(CounterId id) const
Get the value of a performance counter.
Definition: pmu.hh:236
gem5::ArmISA::PMU::m
Bitfield< 26 > m
Definition: pmu.hh:166
gem5::ArmISA::PMU::RegularEvent
Definition: pmu.hh:347
gem5::ArmISA::PMU::getCounter
const CounterState & getCounter(CounterId id) const
Return the state of a counter.
Definition: pmu.hh:540
gem5::ArmISA::PMU::reg_pmcr_conf
PMCR_t reg_pmcr_conf
Constant (configuration-dependent) part of the PMCR.
Definition: pmu.hh:619
gem5::ArmISA::PMU::updateAllCounters
void updateAllCounters()
Call updateCounter() for each counter in the PMU if the counter's state has changed.
Definition: pmu.cc:423
gem5::ArmISA::PMU::PMUEvent
Event definition base class.
Definition: pmu.hh:295
gem5::ArmISA::PMU::SWIncrementEvent::write
void write(uint64_t val)
write on the sw increment register inducing an increment of the counters with this event selected acc...
Definition: pmu.cc:803
gem5::ArmISA::PMU::CounterState::counterId
uint64_t counterId
id of the counter instance
Definition: pmu.hh:488
gem5::ArmISA::PMU::RegularEvent::RegularProbe::RegularProbe
RegularProbe(RegularEvent *parent, SimObject *obj, std::string name)
Definition: pmu.hh:363
gem5::ArmISA::PMU::CounterState::overflow64
bool overflow64
Is this a 64-bit counter?
Definition: pmu.hh:481
gem5::ArmISA::PMU::CounterState::value
uint64_t value
Current value of the counter.
Definition: pmu.hh:491
gem5::SimObject::getProbeManager
ProbeManager * getProbeManager()
Get the probe manager for this object.
Definition: sim_object.cc:120
gem5::ArmISA::PMU::nsh
Bitfield< 27 > nsh
Definition: pmu.hh:168
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:203
gem5::ArmISA::PMU::RegularEvent::EventTypeEntry
std::pair< SimObject *, std::string > EventTypeEntry
Definition: pmu.hh:349
gem5::ArmISA::PMU::evtCount
evtCount
Definition: pmu.hh:163
base.hh
gem5::ProbeListenerArgBase
ProbeListenerArgBase is used to define the base interface to a ProbeListenerArg (i....
Definition: probe.hh:211
gem5::ArmISA::PMU::addSoftwareIncrementEvent
void addSoftwareIncrementEvent(unsigned int id)
Definition: pmu.cc:105
gem5::ArmISA::PMU::RegularEvent::enable
void enable() override
Enable the current event.
Definition: pmu.cc:478
gem5::ArmISA::PMU::CounterState::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: pmu.cc:751
gem5::ArmISA::PMU::clock_remainder
unsigned clock_remainder
Remainder part when the clock counter is divided by 64.
Definition: pmu.hh:600
gem5::ArmISA::PMU::setControlReg
void setControlReg(PMCR_t val)
PMCR write handling.
Definition: pmu.cc:400
gem5::ArmISA::PMU::d
Bitfield< 3 > d
Definition: pmu.hh:142
gem5::ArmISA::PMU::swIncrementEvent
SWIncrementEvent * swIncrementEvent
The event that implements the software increment.
Definition: pmu.hh:615
gem5::ArmISA::PMU::setThreadContext
void setThreadContext(ThreadContext *tc) override
Definition: pmu.cc:95
gem5::ArmISA::PMU::PMUEvent::PMUEvent
PMUEvent()
Definition: pmu.hh:298
gem5::ArmISA::PMU::reg_pmceid1
uint64_t reg_pmceid1
Definition: pmu.hh:597
gem5::ArmISA::id
Bitfield< 33 > id
Definition: misc_types.hh:250
gem5::ArmISA::PMU::reg_pmcr_wr_mask
static const RegVal reg_pmcr_wr_mask
PMCR write mask when accessed from the guest.
Definition: pmu.hh:622
gem5::ArmInterruptPin
Generic representation of an Arm interrupt pin.
Definition: base_gic.hh:200
gem5::ArmISA::PMU::interrupt
ArmInterruptPin * interrupt
Performance monitor interrupt number.
Definition: pmu.hh:625
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::ProbeListener::name
const std::string name
Definition: probe.hh:138
gem5::ArmISA::PMU::PMUEvent::userCounters
std::set< PMU::CounterState * > userCounters
set of counters using this event
Definition: pmu.hh:344
gem5::ArmISA::PMU::readMiscRegInt
RegVal readMiscRegInt(int misc_reg)
Definition: pmu.cc:310
gem5::ArmISA::PMU::EventTypeId
unsigned int EventTypeId
Event type ID.
Definition: pmu.hh:196
gem5::ArmISA::PMU::PMUEvent::disable
virtual void disable()=0
Disable the current event.
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::ArmISA::PMU
Model of an ARM PMU version 3.
Definition: pmu.hh:96
gem5::ArmISA::PMU::reg_pminten
RegVal reg_pminten
Performance Monitor Interrupt Enable Register.
Definition: pmu.hh:585
gem5::ArmISA::PMU::CounterState::resetValue
bool resetValue
Flag keeping track if the counter has been reset.
Definition: pmu.hh:494
gem5::ArmISA::PMU::PMU
PMU(const ArmPMUParams &p)
Definition: pmu.cc:57
gem5::ArmISA::PMU::registerEvent
void registerEvent(uint32_t id)
Definition: pmu.cc:153
gem5::ArmISA::PMU::~PMU
~PMU()
Definition: pmu.cc:90
gem5::ArmISA::PMU::CounterState::CounterState
CounterState(PMU &pmuReference, uint64_t counter_id)
Definition: pmu.hh:416
gem5::ArmISA::PMU::readMiscReg
RegVal readMiscReg(int misc_reg) override
Read a register within the PMU.
Definition: pmu.cc:301
gem5::ArmISA::BaseISADevice
Base class for devices that use the MiscReg interfaces.
Definition: isa_device.hh:61
eventq.hh

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