gem5  v21.1.0.2
pmu.cc
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37 
38 #include "arch/arm/pmu.hh"
39 
40 #include "arch/arm/isa.hh"
41 #include "arch/arm/utility.hh"
42 #include "base/trace.hh"
43 #include "cpu/base.hh"
44 #include "debug/Checkpoint.hh"
45 #include "debug/PMUVerbose.hh"
46 #include "dev/arm/base_gic.hh"
47 #include "dev/arm/generic_timer.hh"
48 #include "params/ArmPMU.hh"
49 
50 namespace gem5
51 {
52 
53 namespace ArmISA {
54 
55 const RegVal PMU::reg_pmcr_wr_mask = 0x39;
56 
57 PMU::PMU(const ArmPMUParams &p)
59  reg_pmcnten(0), reg_pmcr(0),
60  reg_pmselr(0), reg_pminten(0), reg_pmovsr(0),
61  reg_pmceid0(0),reg_pmceid1(0),
62  clock_remainder(0),
63  maximumCounterCount(p.eventCounters),
64  cycleCounter(*this, maximumCounterCount),
65  cycleCounterEventId(p.cycleEventId),
66  swIncrementEvent(nullptr),
67  reg_pmcr_conf(0),
68  interrupt(nullptr)
69 {
70  DPRINTF(PMUVerbose, "Initializing the PMU.\n");
71 
72  if (maximumCounterCount > 31) {
73  fatal("The PMU can only accept 31 counters, %d counters requested.\n",
75  }
76 
77  warn_if(!p.interrupt, "ARM PMU: No interrupt specified, interrupt " \
78  "delivery disabled.\n");
79 
80  /* Setup the performance counter ID registers */
81  reg_pmcr_conf.imp = 0x41; // ARM Ltd.
82  reg_pmcr_conf.idcode = 0x00;
83  reg_pmcr_conf.n = p.eventCounters;
84 
85  // Setup the hard-coded cycle counter, which is equivalent to
86  // architected counter event type 0x11.
87  cycleCounter.eventId = 0x11;
88 }
89 
91 {
92 }
93 
94 void
96 {
97  DPRINTF(PMUVerbose, "Assigning PMU to ContextID %i.\n", tc->contextId());
98  const auto &pmu_params = static_cast<const ArmPMUParams &>(params());
99 
100  if (pmu_params.interrupt)
101  interrupt = pmu_params.interrupt->get(tc);
102 }
103 
104 void
106 {
107  auto old_event = eventMap.find(id);
108  DPRINTF(PMUVerbose, "PMU: Adding SW increment event with id '0x%x'\n", id);
109 
110  if (swIncrementEvent) {
111  fatal_if(old_event == eventMap.end() ||
112  old_event->second != swIncrementEvent,
113  "Trying to add a software increment event with multiple"
114  "IDs. This is not supported.\n");
115  return;
116  }
117 
118  fatal_if(old_event != eventMap.end(), "An event with id %d has "
119  "been previously defined\n", id);
120 
123  registerEvent(id);
124 }
125 
126 void
127 PMU::addEventProbe(unsigned int id, SimObject *obj, const char *probe_name)
128 {
129 
130  DPRINTF(PMUVerbose, "PMU: Adding Probe Driven event with id '0x%x'"
131  "as probe %s:%s\n",id, obj->name(), probe_name);
132 
133  RegularEvent *event = nullptr;
134  auto event_entry = eventMap.find(id);
135  if (event_entry == eventMap.end()) {
136 
137  event = new RegularEvent();
138  eventMap[id] = event;
139 
140  } else {
141  event = dynamic_cast<RegularEvent*>(event_entry->second);
142  if (!event) {
143  fatal("Event with id %d is not probe driven\n", id);
144  }
145  }
146  event->addMicroarchitectureProbe(obj, probe_name);
147 
148  registerEvent(id);
149 
150 }
151 
152 void
153 PMU::registerEvent(uint32_t id)
154 {
155  // Flag the event as available in the corresponding PMCEID register if it
156  // is an architected event.
157  if (id < 0x20) {
158  reg_pmceid0 |= ((uint64_t)1) << id;
159  } else if (id > 0x20 && id < 0x40) {
160  reg_pmceid1 |= ((uint64_t)1) << (id - 0x20);
161  } else if (id >= 0x4000 && id < 0x4020) {
162  reg_pmceid0 |= ((uint64_t)1) << (id - 0x4000 + 32);
163  } else if (id >= 0x4020 && id < 0x4040) {
164  reg_pmceid1 |= ((uint64_t)1) << (id - 0x4020 + 32);
165  }
166 }
167 
168 void
170 {
171  // Re-attach enabled counters after a resume in case they changed.
173 }
174 
175 void
177 {
178 
179  // at this stage all probe configurations are done
180  // counters can be configured
181  for (uint32_t index = 0; index < maximumCounterCount-1; index++) {
182  counters.emplace_back(*this, index);
183  }
184 
186  panic_if(!event, "core cycle event is not present\n");
187  cycleCounter.enabled = true;
189 }
190 
191 void
192 PMU::setMiscReg(int misc_reg, RegVal val)
193 {
194  DPRINTF(PMUVerbose, "setMiscReg(%s, 0x%x)\n",
195  miscRegName[unflattenMiscReg(misc_reg)], val);
196 
197  switch (unflattenMiscReg(misc_reg)) {
198  case MISCREG_PMCR_EL0:
199  case MISCREG_PMCR:
201  return;
202 
204  case MISCREG_PMCNTENSET:
205  reg_pmcnten |= val;
207  return;
208 
210  case MISCREG_PMCNTENCLR:
211  reg_pmcnten &= ~val;
213  return;
214 
216  case MISCREG_PMOVSR:
218  return;
219 
220  case MISCREG_PMSWINC_EL0:
221  case MISCREG_PMSWINC:
222  if (swIncrementEvent) {
224  }
225  return;
226 
227  case MISCREG_PMCCNTR_EL0:
228  case MISCREG_PMCCNTR:
230  return;
231 
232  case MISCREG_PMSELR_EL0:
233  case MISCREG_PMSELR:
234  reg_pmselr = val;
235  return;
236  //TODO: implement MISCREF_PMCEID{2,3}
237  case MISCREG_PMCEID0_EL0:
238  case MISCREG_PMCEID0:
239  case MISCREG_PMCEID1_EL0:
240  case MISCREG_PMCEID1:
241  // Ignore writes
242  return;
243 
244  case MISCREG_PMEVTYPER0_EL0...MISCREG_PMEVTYPER5_EL0:
246  return;
247 
248  case MISCREG_PMCCFILTR:
250  DPRINTF(PMUVerbose, "Setting PMCCFILTR: 0x%x\n", val);
252  return;
253 
256  case MISCREG_PMXEVTYPER:
257  DPRINTF(PMUVerbose, "Setting counter type: "
258  "[PMSELR: 0x%x, PMSELER.sel: 0x%x, EVTYPER: 0x%x]\n",
259  reg_pmselr, reg_pmselr.sel, val);
261  return;
262 
263  case MISCREG_PMEVCNTR0_EL0...MISCREG_PMEVCNTR5_EL0:
265  return;
266 
268  case MISCREG_PMXEVCNTR:
270  return;
271 
273  case MISCREG_PMUSERENR:
274  // TODO
275  break;
276 
278  case MISCREG_PMINTENSET:
279  reg_pminten |= val;
280  return;
281 
283  case MISCREG_PMINTENCLR:
284  reg_pminten &= ~val;
285  return;
286 
288  case MISCREG_PMOVSSET:
290  return;
291 
292  default:
293  panic("Unexpected PMU register: %i\n", miscRegName[misc_reg]);
294  }
295 
296  warn("Not doing anything for write to miscreg %s\n",
297  miscRegName[misc_reg]);
298 }
299 
300 RegVal
301 PMU::readMiscReg(int misc_reg)
302 {
303  RegVal val(readMiscRegInt(misc_reg));
304  DPRINTF(PMUVerbose, "readMiscReg(%s): 0x%x\n",
305  miscRegName[unflattenMiscReg(misc_reg)], val);
306  return val;
307 }
308 
309 RegVal
310 PMU::readMiscRegInt(int misc_reg)
311 {
312  misc_reg = unflattenMiscReg(misc_reg);
313  switch (misc_reg) {
314  case MISCREG_PMCR_EL0:
315  case MISCREG_PMCR:
317 
320  case MISCREG_PMCNTENSET:
321  case MISCREG_PMCNTENCLR:
322  return reg_pmcnten;
323 
326  case MISCREG_PMOVSR: // Overflow Status Register
327  case MISCREG_PMOVSSET:
328  return reg_pmovsr;
329 
330  case MISCREG_PMSWINC_EL0:
331  case MISCREG_PMSWINC: // Software Increment Register (RAZ)
332  return 0;
333 
334  case MISCREG_PMSELR_EL0:
335  case MISCREG_PMSELR:
336  return reg_pmselr;
337 
338  case MISCREG_PMCEID0_EL0:
339  return reg_pmceid0;
340 
341  case MISCREG_PMCEID1_EL0:
342  return reg_pmceid1;
343 
344  //TODO: implement MISCREF_PMCEID{2,3}
345  case MISCREG_PMCEID0: // Common Event ID register
346  return reg_pmceid0 & 0xFFFFFFFF;
347 
348  case MISCREG_PMCEID1: // Common Event ID register
349  return reg_pmceid1 & 0xFFFFFFFF;
350 
351  case MISCREG_PMCCNTR_EL0:
352  return cycleCounter.getValue();
353 
354  case MISCREG_PMCCNTR:
355  return cycleCounter.getValue() & 0xFFFFFFFF;
356 
357  case MISCREG_PMEVTYPER0_EL0...MISCREG_PMEVTYPER5_EL0:
359 
360  case MISCREG_PMCCFILTR:
363 
366  case MISCREG_PMXEVTYPER:
368 
369  case MISCREG_PMEVCNTR0_EL0...MISCREG_PMEVCNTR5_EL0: {
370  return getCounterValue(misc_reg - MISCREG_PMEVCNTR0_EL0) &
371  0xFFFFFFFF;
372 
373  }
374 
376  case MISCREG_PMXEVCNTR:
377  return getCounterValue(reg_pmselr.sel) & 0xFFFFFFFF;
378 
380  case MISCREG_PMUSERENR:
381  // TODO
382  return 0;
383 
386  case MISCREG_PMINTENSET:
387  case MISCREG_PMINTENCLR:
388  return reg_pminten;
389 
390  default:
391  panic("Unexpected PMU register: %i\n", miscRegName[misc_reg]);
392  }
393 
394  warn("Not doing anything for read from miscreg %s\n",
395  miscRegName[misc_reg]);
396  return 0;
397 }
398 
399 void
401 {
402  DPRINTF(PMUVerbose, "Set Control Reg 0x%08x.\n", val);
403 
404  if (val.p) {
405  DPRINTF(PMUVerbose, "PMU reset all events to zero.\n");
407  }
408 
409  if (val.c) {
410  DPRINTF(PMUVerbose, "PMU reset cycle counter to zero.\n");
412  }
413 
414  // Reset the clock remainder if divide by 64-mode is toggled.
415  if (reg_pmcr.d != val.d)
416  clock_remainder = 0;
417 
420 }
421 
422 void
424 {
425  const bool global_enable(reg_pmcr.e);
426 
427  for (int i = 0; i < counters.size(); ++i) {
428  CounterState &ctr(counters[i]);
429  const bool enable(global_enable && (reg_pmcnten & (1 << i)));
430  if (ctr.enabled != enable) {
431  ctr.enabled = enable;
432  updateCounter(ctr);
433  }
434  }
435 
436  const bool ccntr_enable(global_enable && (reg_pmcnten & (1 << PMCCNTR)));
437  if (cycleCounter.enabled != ccntr_enable) {
438  cycleCounter.enabled = ccntr_enable;
440  }
441 }
442 
443 void
445 {
446  if (userCounters.empty()) {
447  enable();
448  }
449  userCounters.insert(user);
451 }
452 
453 void
455 {
456  for (auto& counter: userCounters) {
457  counter->add(val);
458  }
459 }
460 
461 void
463 {
464  userCounters.erase(user);
465 
466  if (userCounters.empty()) {
467  disable();
468  }
469 }
470 
471 void
473 {
474  parentEvent->increment(val);
475 }
476 
477 void
479 {
480  for (auto& subEvents: microArchitectureEventSet) {
481  attachedProbePointList.emplace_back(
482  new RegularProbe(this, subEvents.first, subEvents.second));
483  }
484 }
485 
486 void
488 {
489  attachedProbePointList.clear();
490 }
491 
492 bool
494 {
495  assert(pmu.isa);
496 
497  const PMEVTYPER_t filter(this->filter);
498  const SCR scr(pmu.isa->readMiscRegNoEffect(MISCREG_SCR));
499  const CPSR cpsr(pmu.isa->readMiscRegNoEffect(MISCREG_CPSR));
500  const ExceptionLevel el(currEL(cpsr));
501  const bool secure(inSecureState(scr, cpsr));
502 
503  switch (el) {
504  case EL0:
505  return secure ? filter.u : (filter.u != filter.nsu);
506 
507  case EL1:
508  return secure ? filter.p : (filter.p != filter.nsk);
509 
510  case EL2:
511  return !filter.nsh;
512 
513  case EL3:
514  return filter.p != filter.m;
515 
516  default:
517  panic("Unexpected execution level in PMU::isFiltered.\n");
518  }
519 }
520 
521 void
523 {
524  if (sourceEvent) {
525  sourceEvent->detachEvent(this);
526  sourceEvent = nullptr;
527  } else {
528  debugCounter("detaching event not currently attached"
529  " to any event\n");
530  }
531 }
532 
533 void
535 {
536  if (!resetValue) {
537  value = 0;
538  resetValue = true;
539  }
540  sourceEvent = event;
541  sourceEvent->attachEvent(this);
542 }
543 
544 uint64_t
546 {
547  if (sourceEvent) {
548  sourceEvent->updateAttachedCounters();
549  } else {
550  debugCounter("attempted to get value from a counter without"
551  " an associated event\n");
552  }
553  return value;
554 }
555 
556 void
558 {
559  value = val;
560  resetValue = true;
561 
562  if (sourceEvent) {
563  sourceEvent->updateAttachedCounters();
564  } else {
565  debugCounter("attempted to set value from a counter without"
566  " an associated event\n");
567  }
568 }
569 
570 void
572 {
573  if (!ctr.enabled) {
574  DPRINTF(PMUVerbose, "updateCounter(%i): Disabling counter\n",
575  ctr.getCounterId());
576  ctr.detach();
577 
578  } else {
579  DPRINTF(PMUVerbose, "updateCounter(%i): Enable event id 0x%x\n",
580  ctr.getCounterId(), ctr.eventId);
581 
582  auto sourceEvent = eventMap.find(ctr.eventId);
583  if (sourceEvent == eventMap.end()) {
584  warn("Can't enable PMU counter of type '0x%x': "
585  "No such event type.\n", ctr.eventId);
586  } else {
587  ctr.attach(sourceEvent->second);
588  }
589  }
590 }
591 
592 
593 void
595 {
596  for (CounterState &ctr : counters)
597  ctr.setValue(0);
598 }
599 
600 void
601 PMU::setCounterValue(CounterId id, uint64_t val)
602 {
603  if (!isValidCounter(id)) {
604  warn_once("Can't change counter value: Counter %i does not exist.\n",
605  id);
606  return;
607  }
608 
609  CounterState &ctr(getCounter(id));
610  ctr.setValue(val);
611 }
612 
613 PMU::PMEVTYPER_t
614 PMU::getCounterTypeRegister(CounterId id) const
615 {
616  if (!isValidCounter(id))
617  return 0;
618 
619  const CounterState &cs(getCounter(id));
620  PMEVTYPER_t type(cs.filter);
621 
622  type.evtCount = cs.eventId;
623 
624  return type;
625 }
626 
627 void
628 PMU::setCounterTypeRegister(CounterId id, PMEVTYPER_t val)
629 {
630  DPRINTF(PMUVerbose, "Set Event [%d] = 0x%08x\n", id, val);
631  if (!isValidCounter(id)) {
632  warn_once("Can't change counter type: Counter %i does not exist.\n",
633  id);
634  return;
635  }
636 
637  CounterState &ctr(getCounter(id));
638  const EventTypeId old_event_id(ctr.eventId);
639 
640  ctr.filter = val;
641 
642  // If PMCCNTR Register, do not change event type. PMCCNTR can
643  // count processor cycles only. If we change the event type, we
644  // need to update the probes the counter is using.
645  if (id != PMCCNTR && old_event_id != val.evtCount) {
646  ctr.eventId = val.evtCount;
647  updateCounter(ctr);
648  }
649 }
650 
651 void
653 {
654  const bool int_old = reg_pmovsr != 0;
655  const bool int_new = new_val != 0;
656 
657  reg_pmovsr = new_val;
658  if (int_old && !int_new) {
659  clearInterrupt();
660  } else if (!int_old && int_new && (reg_pminten & reg_pmovsr)) {
661  raiseInterrupt();
662  }
663 }
664 
665 void
667 {
668  if (interrupt) {
669  DPRINTF(PMUVerbose, "Delivering PMU interrupt.\n");
670  interrupt->raise();
671  } else {
672  warn_once("Dropping PMU interrupt as no interrupt has "
673  "been specified\n");
674  }
675 }
676 
677 void
679 {
680  if (interrupt) {
681  DPRINTF(PMUVerbose, "Clearing PMU interrupt.\n");
682  interrupt->clear();
683  } else {
684  warn_once("Dropping PMU interrupt as no interrupt has "
685  "been specified\n");
686  }
687 }
688 
689 void
691 {
692  DPRINTF(Checkpoint, "Serializing Arm PMU\n");
693 
702 
703  for (size_t i = 0; i < counters.size(); ++i)
704  counters[i].serializeSection(cp, csprintf("counters.%i", i));
705 
706  cycleCounter.serializeSection(cp, "cycleCounter");
707 }
708 
709 void
711 {
712  DPRINTF(Checkpoint, "Unserializing Arm PMU\n");
713 
719 
720  // Old checkpoints used to store the entire PMCEID value in a
721  // single 64-bit entry (reg_pmceid). The register was extended in
722  // ARMv8.1, so we now need to store it as two 64-bit registers.
724  paramIn(cp, "reg_pmceid", reg_pmceid0);
725 
727  reg_pmceid1 = 0;
728 
730 
731  for (size_t i = 0; i < counters.size(); ++i)
732  counters[i].unserializeSection(cp, csprintf("counters.%i", i));
733 
734  cycleCounter.unserializeSection(cp, "cycleCounter");
735 }
736 
738 PMU::getEvent(uint64_t eventId)
739 {
740  auto entry = eventMap.find(eventId);
741 
742  if (entry == eventMap.end()) {
743  warn("event %d does not exist\n", eventId);
744  return nullptr;
745  } else {
746  return entry->second;
747  }
748 }
749 
750 void
752 {
753  SERIALIZE_SCALAR(eventId);
754  SERIALIZE_SCALAR(value);
755  SERIALIZE_SCALAR(overflow64);
756 }
757 
758 void
760 {
761  UNSERIALIZE_SCALAR(eventId);
762  UNSERIALIZE_SCALAR(value);
763  UNSERIALIZE_SCALAR(overflow64);
764 }
765 
766 uint64_t
767 PMU::CounterState::add(uint64_t delta)
768 {
769  uint64_t value_until_overflow;
770  if (overflow64) {
771  value_until_overflow = UINT64_MAX - value;
772  } else {
773  value_until_overflow = UINT32_MAX - (uint32_t)value;
774  }
775 
776  if (isFiltered())
777  return value_until_overflow;
778 
779  if (resetValue) {
780  delta = 0;
781  resetValue = false;
782  } else {
783  value += delta;
784  }
785 
786  if (delta > value_until_overflow) {
787 
788  // overflow situation detected
789  // flag the overflow occurence
790  pmu.reg_pmovsr |= (1 << counterId);
791 
792  // Deliver a PMU interrupt if interrupt delivery is enabled
793  // for this counter.
794  if (pmu.reg_pminten & (1 << counterId)) {
795  pmu.raiseInterrupt();
796  }
797  return overflow64 ? UINT64_MAX : UINT32_MAX;
798  }
799  return value_until_overflow - delta + 1;
800 }
801 
802 void
804 {
805  for (auto& counter: userCounters) {
806  if (val & (0x1 << counter->getCounterId())) {
807  counter->add(1);
808  }
809  }
810 }
811 
812 } // namespace ArmISA
813 } // namespace gem5
gem5::ArmISA::PMU::p
Bitfield< 1 > p
Definition: pmu.hh:138
gem5::ArmISA::PMU::addEventProbe
void addEventProbe(unsigned int id, SimObject *obj, const char *name)
Definition: pmu.cc:127
gem5::ArmISA::MISCREG_PMSWINC
@ MISCREG_PMSWINC
Definition: misc.hh:355
fatal
#define fatal(...)
This implements a cprintf based fatal() function.
Definition: logging.hh:189
gem5::ArmISA::PMU::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: pmu.cc:690
gem5::ArmISA::MISCREG_CPSR
@ MISCREG_CPSR
Definition: misc.hh:61
gem5::ArmISA::PMU::PMUEvent::enable
virtual void enable()=0
Enable the current event.
gem5::ArmISA::MISCREG_PMCCFILTR
@ MISCREG_PMCCFILTR
Definition: misc.hh:361
gem5::ArmISA::MISCREG_PMCEID1
@ MISCREG_PMCEID1
Definition: misc.hh:358
gem5::ArmISA::MISCREG_PMCR
@ MISCREG_PMCR
Definition: misc.hh:351
gem5::ArmISA::PMU::CounterState::isFiltered
bool isFiltered() const
Definition: pmu.cc:493
gem5::ArmISA::PMU::setCounterValue
void setCounterValue(CounterId id, uint64_t val)
Set the value of a performance counter.
Definition: pmu.cc:601
gem5::Trace::disable
void disable()
Definition: trace.cc:100
gem5::ArmISA::MISCREG_PMCCFILTR_EL0
@ MISCREG_PMCCFILTR_EL0
Definition: misc.hh:722
gem5::ArmISA::MISCREG_PMXEVTYPER_EL0
@ MISCREG_PMXEVTYPER_EL0
Definition: misc.hh:721
gem5::ArmISA::PMU::raiseInterrupt
void raiseInterrupt()
Deliver a PMU interrupt to the GIC.
Definition: pmu.cc:666
gem5::ArmISA::MISCREG_PMOVSCLR_EL0
@ MISCREG_PMOVSCLR_EL0
Definition: misc.hh:715
gem5::ArmISA::MISCREG_PMOVSR
@ MISCREG_PMOVSR
Definition: misc.hh:354
warn
#define warn(...)
Definition: logging.hh:245
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::ArmISA::MISCREG_PMCNTENCLR
@ MISCREG_PMCNTENCLR
Definition: misc.hh:353
gem5::ArmISA::PMU::setMiscReg
void setMiscReg(int misc_reg, RegVal val) override
Set a register within the PMU.
Definition: pmu.cc:192
gem5::ArmISA::PMU::maximumCounterCount
uint64_t maximumCounterCount
The number of regular event counters.
Definition: pmu.hh:603
gem5::ArmISA::PMU::RegularEvent::RegularProbe::notify
void notify(const uint64_t &val)
Definition: pmu.cc:472
gem5::ArmISA::PMU::CounterState
State of a counter within the PMU.
Definition: pmu.hh:414
UNSERIALIZE_SCALAR
#define UNSERIALIZE_SCALAR(scalar)
Definition: serialize.hh:575
gem5::ArmISA::PMU::CounterState::getCounterId
uint64_t getCounterId() const
Obtain the counter id.
Definition: pmu.hh:452
gem5::ArmISA::PMU::cycleCounter
CounterState cycleCounter
State of the cycle counter.
Definition: pmu.hh:609
gem5::ArmISA::el
Bitfield< 3, 2 > el
Definition: misc_types.hh:72
gem5::ArmISA::MISCREG_PMINTENCLR_EL1
@ MISCREG_PMINTENCLR_EL1
Definition: misc.hh:711
gem5::MipsISA::index
Bitfield< 30, 0 > index
Definition: pra_constants.hh:47
gem5::ArmISA::PMU::PMUEvent::detachEvent
void detachEvent(PMU::CounterState *user)
detach this event from a given counter
Definition: pmu.cc:462
warn_once
#define warn_once(...)
Definition: logging.hh:249
gem5::ArmISA::MISCREG_PMSELR_EL0
@ MISCREG_PMSELR_EL0
Definition: misc.hh:717
gem5::ArmISA::PMU::RegularEvent::disable
void disable() override
Disable the current event.
Definition: pmu.cc:487
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::ArmISA::PMU::getCounterTypeRegister
PMEVTYPER_t getCounterTypeRegister(CounterId id) const
Get the type and filter settings of a counter (PMEVTYPER)
Definition: pmu.cc:614
gem5::MipsISA::event
Bitfield< 10, 5 > event
Definition: pra_constants.hh:300
base_gic.hh
gem5::Serializable::serializeSection
void serializeSection(CheckpointOut &cp, const char *name) const
Serialize an object into a new section.
Definition: serialize.cc:74
gem5::ArmISA::PMU::RegularEvent::RegularProbe
Definition: pmu.hh:361
gem5::ArmISA::currEL
static ExceptionLevel currEL(const ThreadContext *tc)
Definition: utility.hh:119
gem5::ArmISA::PMU::isFiltered
bool isFiltered(const CounterState &ctr) const
Check if a counter's settings allow it to be counted.
gem5::ArmISA::PMU::updateCounter
void updateCounter(CounterState &ctr)
Depending on counter configuration, add or remove the probes driving the counter.
Definition: pmu.cc:571
gem5::ArmISA::PMU::getEvent
PMUEvent * getEvent(uint64_t eventId)
Obtain the event of a given id.
Definition: pmu.cc:738
gem5::ArmISA::PMU::SWIncrementEvent
Definition: pmu.hh:389
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
gem5::ArmISA::PMU::reg_pmceid0
uint64_t reg_pmceid0
Performance counter ID register.
Definition: pmu.hh:596
gem5::ArmISA::PMU::CounterState::eventId
EventTypeId eventId
Counter event ID.
Definition: pmu.hh:472
gem5::ArmISA::MISCREG_PMINTENSET_EL1
@ MISCREG_PMINTENSET_EL1
Definition: misc.hh:710
gem5::ArmISA::PMU::setOverflowStatus
void setOverflowStatus(RegVal new_val)
Used for writing the Overflow Flag Status Register (SET/CLR)
Definition: pmu.cc:652
gem5::ArmISA::miscRegName
const char *const miscRegName[]
Definition: misc.hh:1172
gem5::ThreadContext::contextId
virtual ContextID contextId() const =0
gem5::ArmISA::EL1
@ EL1
Definition: types.hh:267
gem5::ArmISA::PMU::CounterState::setValue
void setValue(uint64_t val)
overwrite the value of the counter
Definition: pmu.cc:557
gem5::ArmISA::PMU::CounterState::add
uint64_t add(uint64_t delta)
Add an event count to the counter and check for overflow.
Definition: pmu.cc:767
gem5::csprintf
std::string csprintf(const char *format, const Args &...args)
Definition: cprintf.hh:161
gem5::ArmISA::MISCREG_PMOVSSET
@ MISCREG_PMOVSSET
Definition: misc.hh:366
gem5::ArmISA::MISCREG_PMUSERENR
@ MISCREG_PMUSERENR
Definition: misc.hh:363
gem5::ArmISA::MISCREG_PMSWINC_EL0
@ MISCREG_PMSWINC_EL0
Definition: misc.hh:716
gem5::ArmISA::MISCREG_PMCCNTR_EL0
@ MISCREG_PMCCNTR_EL0
Definition: misc.hh:720
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
gem5::ArmISA::PMU::PMUEvent::attachEvent
void attachEvent(PMU::CounterState *user)
attach this event to a given counter
Definition: pmu.cc:444
gem5::ArmISA::PMU::eventMap
std::map< EventTypeId, PMUEvent * > eventMap
List of event types supported by this PMU.
Definition: pmu.hh:630
gem5::ArmISA::PMU::CounterState::getValue
uint64_t getValue() const
rReturn the counter value
Definition: pmu.cc:545
gem5::ArmISA::PMU::counters
std::vector< CounterState > counters
State of all general-purpose counters supported by PMU.
Definition: pmu.hh:606
gem5::ArmISA::PMU::resetEventCounts
void resetEventCounts()
Reset all event counters excluding the cycle counter to zero.
Definition: pmu.cc:594
gem5::ArmISA::PMU::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: pmu.cc:710
gem5::ArmISA::PMU::CounterState::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: pmu.cc:759
gem5::ArmISA::PMU::CounterState::attach
void attach(PMUEvent *event)
Attach this counter to an event.
Definition: pmu.cc:534
gem5::ArmISA::PMU::PMCCNTR
static const CounterId PMCCNTR
Cycle Count Register Number.
Definition: pmu.hh:189
gem5::ArmISA::PMU::getCounter
CounterState & getCounter(CounterId id)
Return the state of a counter.
Definition: pmu.hh:528
gem5::ArmISA::PMU::PMUEvent::updateAttachedCounters
virtual void updateAttachedCounters()
Method called immediately before a counter access in order for the associated event to update its sta...
Definition: pmu.hh:339
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::Named::name
virtual std::string name() const
Definition: named.hh:47
gem5::Serializable::unserializeSection
void unserializeSection(CheckpointIn &cp, const char *name)
Unserialize an a child object.
Definition: serialize.cc:81
gem5::ArmISA::MISCREG_PMCNTENSET
@ MISCREG_PMCNTENSET
Definition: misc.hh:352
gem5::X86ISA::enable
Bitfield< 11 > enable
Definition: misc.hh:1057
gem5::SimObject::params
const Params & params() const
Definition: sim_object.hh:176
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::ArmISA::MISCREG_PMOVSSET_EL0
@ MISCREG_PMOVSSET_EL0
Definition: misc.hh:725
gem5::ArmISA::MISCREG_PMSELR
@ MISCREG_PMSELR
Definition: misc.hh:356
gem5::ArmISA::EL2
@ EL2
Definition: types.hh:268
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::ArmISA::PMU::clearInterrupt
void clearInterrupt()
Clear a PMU interrupt.
Definition: pmu.cc:678
isa.hh
gem5::ArmISA::PMU::CounterState::enabled
bool enabled
Is the counter enabled?
Definition: pmu.hh:478
gem5::ArmISA::PMU::CounterState::filter
PMEVTYPER_t filter
Filtering settings (evtCount is unused)
Definition: pmu.hh:475
gem5::ArmInterruptPin::clear
virtual void clear()=0
Clear a signalled interrupt.
gem5::X86ISA::type
type
Definition: misc.hh:733
gem5::ArmISA::PMU::reg_pmcr
PMCR_t reg_pmcr
Performance Monitor Control Register.
Definition: pmu.hh:579
gem5::ArmISA::MISCREG_PMXEVCNTR_EL0
@ MISCREG_PMXEVCNTR_EL0
Definition: misc.hh:723
gem5::ArmISA::PMU::drainResume
void drainResume() override
Resume execution after a successful drain.
Definition: pmu.cc:169
gem5::ArmISA::MISCREG_PMXEVTYPER_PMCCFILTR
@ MISCREG_PMXEVTYPER_PMCCFILTR
Definition: misc.hh:90
UNSERIALIZE_OPT_SCALAR
#define UNSERIALIZE_OPT_SCALAR(scalar)
Definition: serialize.hh:582
gem5::ArmISA::PMU::regProbeListeners
void regProbeListeners() override
Register probe listeners for this object.
Definition: pmu.cc:176
gem5::ArmISA::MISCREG_PMINTENSET
@ MISCREG_PMINTENSET
Definition: misc.hh:364
gem5::ArmISA::PMU::reg_pmovsr
RegVal reg_pmovsr
Performance Monitor Overflow Status Register.
Definition: pmu.hh:588
gem5::ArmISA::PMU::cycleCounterEventId
const uint64_t cycleCounterEventId
The id of the counter hardwired to the cpu cycle counter.
Definition: pmu.hh:612
gem5::ArmISA::EL3
@ EL3
Definition: types.hh:269
gem5::ArmISA::PMU::PMUEvent::increment
virtual void increment(const uint64_t val)
notify an event increment of val units, all the attached counters' value is incremented by val units.
Definition: pmu.cc:454
gem5::ArmISA::MISCREG_PMCNTENSET_EL0
@ MISCREG_PMCNTENSET_EL0
Definition: misc.hh:713
gem5::ArmISA::PMU::reg_pmselr
PMSELR_t reg_pmselr
Performance Monitor Selection Register.
Definition: pmu.hh:582
gem5::SimObject
Abstract superclass for simulation objects.
Definition: sim_object.hh:146
gem5::ArmISA::PMU::isValidCounter
bool isValidCounter(CounterId id) const
Is this a valid counter ID?
Definition: pmu.hh:517
gem5::ArmISA::PMU::CounterState::detach
void detach()
Detach the counter from its event.
Definition: pmu.cc:522
gem5::ArmISA::PMU::setCounterTypeRegister
void setCounterTypeRegister(CounterId id, PMEVTYPER_t type)
Set the type and filter settings of a performance counter (PMEVTYPER)
Definition: pmu.cc:628
gem5::ArmISA::PMU::reg_pmcnten
RegVal reg_pmcnten
Performance Monitor Count Enable Register.
Definition: pmu.hh:576
generic_timer.hh
gem5::ArmISA::PMU::getCounterValue
uint64_t getCounterValue(CounterId id) const
Get the value of a performance counter.
Definition: pmu.hh:236
gem5::ArmISA::PMU::RegularEvent
Definition: pmu.hh:347
gem5::ArmISA::PMU::reg_pmcr_conf
PMCR_t reg_pmcr_conf
Constant (configuration-dependent) part of the PMCR.
Definition: pmu.hh:619
gem5::ArmISA::PMU::updateAllCounters
void updateAllCounters()
Call updateCounter() for each counter in the PMU if the counter's state has changed.
Definition: pmu.cc:423
gem5::ArmISA::PMU::PMUEvent
Event definition base class.
Definition: pmu.hh:295
gem5::ArmISA::PMU::SWIncrementEvent::write
void write(uint64_t val)
write on the sw increment register inducing an increment of the counters with this event selected acc...
Definition: pmu.cc:803
gem5::ArmISA::MISCREG_PMCEID1_EL0
@ MISCREG_PMCEID1_EL0
Definition: misc.hh:719
SERIALIZE_SCALAR
#define SERIALIZE_SCALAR(scalar)
Definition: serialize.hh:568
utility.hh
gem5::ArmISA::MISCREG_PMINTENCLR
@ MISCREG_PMINTENCLR
Definition: misc.hh:365
warn_if
#define warn_if(cond,...)
Conditional warning macro that checks the supplied condition and only prints a warning if the conditi...
Definition: logging.hh:272
gem5::ArmISA::EL0
@ EL0
Definition: types.hh:266
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:203
gem5::ArmISA::MISCREG_PMXEVCNTR
@ MISCREG_PMXEVCNTR
Definition: misc.hh:362
base.hh
gem5::ArmISA::PMU::addSoftwareIncrementEvent
void addSoftwareIncrementEvent(unsigned int id)
Definition: pmu.cc:105
gem5::ArmISA::PMU::RegularEvent::enable
void enable() override
Enable the current event.
Definition: pmu.cc:478
gem5::ArmISA::PMU::CounterState::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: pmu.cc:751
gem5::ArmISA::PMU::clock_remainder
unsigned clock_remainder
Remainder part when the clock counter is divided by 64.
Definition: pmu.hh:600
gem5::ArmISA::PMU::setControlReg
void setControlReg(PMCR_t val)
PMCR write handling.
Definition: pmu.cc:400
gem5::paramIn
void paramIn(CheckpointIn &cp, const std::string &name, ExtMachInst &machInst)
Definition: types.cc:72
gem5::ArmISA::PMU::swIncrementEvent
SWIncrementEvent * swIncrementEvent
The event that implements the software increment.
Definition: pmu.hh:615
gem5::ArmISA::MISCREG_SCR
@ MISCREG_SCR
Definition: misc.hh:243
gem5::ArmISA::PMU::setThreadContext
void setThreadContext(ThreadContext *tc) override
Definition: pmu.cc:95
gem5::ArmISA::inSecureState
static bool inSecureState(SCR scr, CPSR cpsr)
Definition: utility.hh:223
gem5::ArmISA::PMU::reg_pmceid1
uint64_t reg_pmceid1
Definition: pmu.hh:597
gem5::ArmISA::id
Bitfield< 33 > id
Definition: misc_types.hh:250
gem5::ArmISA::MISCREG_PMEVCNTR0_EL0
@ MISCREG_PMEVCNTR0_EL0
Definition: misc.hh:790
gem5::ArmISA::PMU::reg_pmcr_wr_mask
static const RegVal reg_pmcr_wr_mask
PMCR write mask when accessed from the guest.
Definition: pmu.hh:622
pmu.hh
gem5::ArmISA::PMU::interrupt
ArmInterruptPin * interrupt
Performance monitor interrupt number.
Definition: pmu.hh:625
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::ArmInterruptPin::raise
virtual void raise()=0
Signal an interrupt.
gem5::ArmISA::MISCREG_PMXEVTYPER
@ MISCREG_PMXEVTYPER
Definition: misc.hh:360
trace.hh
gem5::ArmISA::PMU::PMUEvent::userCounters
std::set< PMU::CounterState * > userCounters
set of counters using this event
Definition: pmu.hh:344
gem5::ArmISA::PMU::readMiscRegInt
RegVal readMiscRegInt(int misc_reg)
Definition: pmu.cc:310
gem5::ArmISA::MISCREG_PMCEID0_EL0
@ MISCREG_PMCEID0_EL0
Definition: misc.hh:718
gem5::ArmISA::MISCREG_PMCEID0
@ MISCREG_PMCEID0
Definition: misc.hh:357
gem5::ArmISA::PMU::EventTypeId
unsigned int EventTypeId
Event type ID.
Definition: pmu.hh:196
fatal_if
#define fatal_if(cond,...)
Conditional fatal macro that checks the supplied condition and only causes a fatal error if the condi...
Definition: logging.hh:225
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::ArmISA::MISCREG_PMCCNTR
@ MISCREG_PMCCNTR
Definition: misc.hh:359
gem5::ArmISA::MISCREG_PMUSERENR_EL0
@ MISCREG_PMUSERENR_EL0
Definition: misc.hh:724
gem5::ArmISA::MISCREG_PMCNTENCLR_EL0
@ MISCREG_PMCNTENCLR_EL0
Definition: misc.hh:714
gem5::ArmISA::PMU::reg_pminten
RegVal reg_pminten
Performance Monitor Interrupt Enable Register.
Definition: pmu.hh:585
gem5::ArmISA::PMU::PMU
PMU(const ArmPMUParams &p)
Definition: pmu.cc:57
gem5::ArmISA::PMU::registerEvent
void registerEvent(uint32_t id)
Definition: pmu.cc:153
gem5::ArmISA::PMU::~PMU
~PMU()
Definition: pmu.cc:90
gem5::ArmISA::MISCREG_PMCR_EL0
@ MISCREG_PMCR_EL0
Definition: misc.hh:712
gem5::ArmISA::MISCREG_PMEVTYPER0_EL0
@ MISCREG_PMEVTYPER0_EL0
Definition: misc.hh:796
gem5::ArmISA::PMU::readMiscReg
RegVal readMiscReg(int misc_reg) override
Read a register within the PMU.
Definition: pmu.cc:301
gem5::ArmISA::unflattenMiscReg
int unflattenMiscReg(int reg)
Definition: misc.cc:1365
gem5::ArmISA::ExceptionLevel
ExceptionLevel
Definition: types.hh:264
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::ArmISA::BaseISADevice
Base class for devices that use the MiscReg interfaces.
Definition: isa_device.hh:61

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