gem5  v22.0.0.2
se_workload.cc
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27 
29 
30 #include "arch/sparc/process.hh"
31 #include "arch/sparc/regs/int.hh"
32 #include "arch/sparc/regs/misc.hh"
33 #include "arch/sparc/types.hh"
34 #include "base/logging.hh"
35 #include "cpu/thread_context.hh"
37 
38 namespace gem5
39 {
40 
41 namespace SparcISA
42 {
43 
46 };
47 
48 bool
50 {
51  return dynamic_cast<Sparc64Process *>(tc->getProcessPtr());
52 }
53 
54 void
56 {
57  auto &pc = tc->pcState().as<PCState>();
58  switch (trapNum) {
59  case 0x01: // Software breakpoint
60  warn("Software breakpoint encountered at pc %#x.", pc.pc());
61  break;
62  case 0x02: // Division by zero
63  warn("Software signaled a division by zero at pc %#x.", pc.pc());
64  break;
65  case 0x03: // Flush window trap
66  flushWindows(tc);
67  break;
68  case 0x04: // Clean windows
69  warn("Ignoring process request for clean register "
70  "windows at pc %#x.", pc.pc());
71  break;
72  case 0x05: // Range check
73  warn("Software signaled a range check at pc %#x.", pc.pc());
74  break;
75  case 0x06: // Fix alignment
76  warn("Ignoring process request for os assisted unaligned accesses "
77  "at pc %#x.", pc.pc());
78  break;
79  case 0x07: // Integer overflow
80  warn("Software signaled an integer overflow at pc %#x.", pc.pc());
81  break;
82  case 0x32: // Get integer condition codes
83  warn("Ignoring process request to get the integer condition codes "
84  "at pc %#x.", pc.pc());
85  break;
86  case 0x33: // Set integer condition codes
87  warn("Ignoring process request to set the integer condition codes "
88  "at pc %#x.", pc.pc());
89  break;
90  default:
91  panic("Unimplemented trap to operating system: trap number %#x.",
92  trapNum);
93  }
94 }
95 
96 void
98 {
99  RegVal Cansave = tc->readIntReg(INTREG_CANSAVE);
100  RegVal Canrestore = tc->readIntReg(INTREG_CANRESTORE);
101  RegVal Otherwin = tc->readIntReg(INTREG_OTHERWIN);
102  RegVal CWP = tc->readMiscReg(MISCREG_CWP);
103  RegVal origCWP = CWP;
104 
105  const bool is_64 = is64(tc);
106  const size_t reg_bytes = is_64 ? 8 : 4;
107  uint8_t bytes[8];
108 
109  SETranslatingPortProxy proxy(tc);
110 
111  CWP = (CWP + Cansave + 2) % NWindows;
112  while (NWindows - 2 - Cansave != 0) {
113  panic_if(Otherwin, "Otherwin non-zero.");
114 
115  tc->setMiscReg(MISCREG_CWP, CWP);
116  // Do the stores
118 
119  Addr addr = is_64 ? sp + 2047 : sp;
120  for (int index = 16; index < 32; index++) {
121  if (is_64) {
122  uint64_t regVal = htobe<uint64_t>(tc->readIntReg(index));
123  memcpy(bytes, &regVal, reg_bytes);
124  } else {
125  uint32_t regVal = htobe<uint32_t>(tc->readIntReg(index));
126  memcpy(bytes, &regVal, reg_bytes);
127  }
128  if (!proxy.tryWriteBlob(addr, bytes, reg_bytes)) {
129  warn("Failed to save register to the stack when "
130  "flushing windows.");
131  }
132  addr += reg_bytes;
133  }
134  Canrestore--;
135  Cansave++;
136  CWP = (CWP + 1) % NWindows;
137  }
138 
139  tc->setIntReg(INTREG_CANSAVE, Cansave);
140  tc->setIntReg(INTREG_CANRESTORE, Canrestore);
141  tc->setMiscReg(MISCREG_CWP, origCWP);
142 }
143 
144 } // namespace SparcISA
145 } // namespace gem5
gem5::SETranslatingPortProxy
Definition: se_translating_port_proxy.hh:49
gem5::ThreadContext::readMiscReg
virtual RegVal readMiscReg(RegIndex misc_reg)=0
misc.hh
warn
#define warn(...)
Definition: logging.hh:246
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
process.hh
gem5::SparcISA::INTREG_CANSAVE
@ INTREG_CANSAVE
Definition: int.hh:60
gem5::MipsISA::index
Bitfield< 30, 0 > index
Definition: pra_constants.hh:47
gem5::PCStateBase::as
Target & as()
Definition: pcstate.hh:72
gem5::ThreadContext::pcState
virtual const PCStateBase & pcState() const =0
std::vector< int >
gem5::SparcISA::INTREG_CANRESTORE
@ INTREG_CANRESTORE
Definition: int.hh:61
gem5::SparcISA::INTREG_O5
@ INTREG_O5
Definition: int.hh:47
gem5::SparcISA::INTREG_O2
@ INTREG_O2
Definition: int.hh:46
gem5::SparcISA::INTREG_O4
@ INTREG_O4
Definition: int.hh:47
gem5::SparcISA::INTREG_OTHERWIN
@ INTREG_OTHERWIN
Definition: int.hh:63
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::ThreadContext::readIntReg
RegVal readIntReg(RegIndex reg_idx) const
Definition: thread_context.hh:204
gem5::TranslatingPortProxy::tryWriteBlob
bool tryWriteBlob(Addr addr, const void *p, int size) const override
Version of tryWriteBlob that translates virt->phys and deals with page boundries.
Definition: translating_port_proxy.cc:101
int.hh
gem5::SparcISA::INTREG_O1
@ INTREG_O1
Definition: int.hh:46
gem5::SparcISA::INTREG_O0
@ INTREG_O0
Definition: int.hh:46
gem5::SparcISA::INTREG_O3
@ INTREG_O3
Definition: int.hh:46
types.hh
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ThreadContext::getProcessPtr
virtual Process * getProcessPtr()=0
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:204
gem5::SparcISA::NWindows
const int NWindows
Definition: sparc_traits.hh:44
gem5::ThreadContext::setMiscReg
virtual void setMiscReg(RegIndex misc_reg, RegVal val)=0
gem5::GenericISA::DelaySlotUPCState
Definition: pcstate.hh:530
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
logging.hh
se_workload.hh
gem5::SparcISA::StackPointerReg
const int StackPointerReg
Definition: int.hh:73
se_translating_port_proxy.hh
gem5::SparcISA::SEWorkload::flushWindows
virtual void flushWindows(ThreadContext *tc)
Definition: se_workload.cc:97
gem5::SparcISA::SEWorkload::handleTrap
virtual void handleTrap(ThreadContext *tc, int trapNum)
Definition: se_workload.cc:55
gem5::SparcISA::MISCREG_CWP
@ MISCREG_CWP
Definition: misc.hh:68
gem5::ArmISA::sp
Bitfield< 0 > sp
Definition: misc_types.hh:75
gem5::Sparc64Process
Definition: process.hh:103
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::SparcISA::SEWorkload::is64
bool is64(ThreadContext *tc)
Definition: se_workload.cc:49
gem5::SparcISA::SEWorkload::BaseSyscallABI::ArgumentRegs
static const std::vector< int > ArgumentRegs
Definition: se_workload.hh:66
thread_context.hh
gem5::ThreadContext::setIntReg
void setIntReg(RegIndex reg_idx, RegVal val)
Definition: thread_context.hh:241
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84

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