gem5  v21.1.0.2
se_workload.cc
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27 
29 
30 #include "arch/sparc/process.hh"
31 #include "arch/sparc/regs/int.hh"
32 #include "arch/sparc/regs/misc.hh"
33 #include "arch/sparc/types.hh"
34 #include "base/logging.hh"
35 #include "cpu/thread_context.hh"
36 
37 namespace gem5
38 {
39 
40 namespace SparcISA
41 {
42 
45 };
46 
47 bool
49 {
50  return dynamic_cast<Sparc64Process *>(tc->getProcessPtr());
51 }
52 
53 void
55 {
56  PCState pc = tc->pcState();
57  switch (trapNum) {
58  case 0x01: // Software breakpoint
59  warn("Software breakpoint encountered at pc %#x.", pc.pc());
60  break;
61  case 0x02: // Division by zero
62  warn("Software signaled a division by zero at pc %#x.", pc.pc());
63  break;
64  case 0x03: // Flush window trap
65  flushWindows(tc);
66  break;
67  case 0x04: // Clean windows
68  warn("Ignoring process request for clean register "
69  "windows at pc %#x.", pc.pc());
70  break;
71  case 0x05: // Range check
72  warn("Software signaled a range check at pc %#x.", pc.pc());
73  break;
74  case 0x06: // Fix alignment
75  warn("Ignoring process request for os assisted unaligned accesses "
76  "at pc %#x.", pc.pc());
77  break;
78  case 0x07: // Integer overflow
79  warn("Software signaled an integer overflow at pc %#x.", pc.pc());
80  break;
81  case 0x32: // Get integer condition codes
82  warn("Ignoring process request to get the integer condition codes "
83  "at pc %#x.", pc.pc());
84  break;
85  case 0x33: // Set integer condition codes
86  warn("Ignoring process request to set the integer condition codes "
87  "at pc %#x.", pc.pc());
88  break;
89  default:
90  panic("Unimplemented trap to operating system: trap number %#x.",
91  trapNum);
92  }
93 }
94 
95 void
97 {
98  RegVal Cansave = tc->readIntReg(INTREG_CANSAVE);
99  RegVal Canrestore = tc->readIntReg(INTREG_CANRESTORE);
100  RegVal Otherwin = tc->readIntReg(INTREG_OTHERWIN);
101  RegVal CWP = tc->readMiscReg(MISCREG_CWP);
102  RegVal origCWP = CWP;
103 
104  const bool is_64 = is64(tc);
105  const size_t reg_bytes = is_64 ? 8 : 4;
106  uint8_t bytes[8];
107 
108  CWP = (CWP + Cansave + 2) % NWindows;
109  while (NWindows - 2 - Cansave != 0) {
110  panic_if(Otherwin, "Otherwin non-zero.");
111 
112  tc->setMiscReg(MISCREG_CWP, CWP);
113  // Do the stores
115 
116  Addr addr = is_64 ? sp + 2047 : sp;
117  for (int index = 16; index < 32; index++) {
118  if (is_64) {
119  uint64_t regVal = htobe<uint64_t>(tc->readIntReg(index));
120  memcpy(bytes, &regVal, reg_bytes);
121  } else {
122  uint32_t regVal = htobe<uint32_t>(tc->readIntReg(index));
123  memcpy(bytes, &regVal, reg_bytes);
124  }
125  if (!tc->getVirtProxy().tryWriteBlob(addr, bytes, reg_bytes)) {
126  warn("Failed to save register to the stack when "
127  "flushing windows.");
128  }
129  addr += reg_bytes;
130  }
131  Canrestore--;
132  Cansave++;
133  CWP = (CWP + 1) % NWindows;
134  }
135 
136  tc->setIntReg(INTREG_CANSAVE, Cansave);
137  tc->setIntReg(INTREG_CANRESTORE, Canrestore);
138  tc->setMiscReg(MISCREG_CWP, origCWP);
139 }
140 
141 } // namespace SparcISA
142 } // namespace gem5
gem5::ThreadContext::setIntReg
virtual void setIntReg(RegIndex reg_idx, RegVal val)=0
gem5::PortProxy::tryWriteBlob
virtual bool tryWriteBlob(Addr addr, const void *p, int size) const
Write size bytes from p to address.
Definition: port_proxy.hh:157
gem5::ThreadContext::readMiscReg
virtual RegVal readMiscReg(RegIndex misc_reg)=0
misc.hh
warn
#define warn(...)
Definition: logging.hh:245
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
process.hh
gem5::MipsISA::index
Bitfield< 30, 0 > index
Definition: pra_constants.hh:47
gem5::SparcISA::INTREG_CANSAVE
@ INTREG_CANSAVE
Definition: int.hh:60
gem5::SparcISA::INTREG_O5
@ INTREG_O5
Definition: int.hh:47
gem5::SparcISA::INTREG_O3
@ INTREG_O3
Definition: int.hh:46
gem5::SparcISA::INTREG_O1
@ INTREG_O1
Definition: int.hh:46
std::vector< int >
gem5::SparcISA::INTREG_O2
@ INTREG_O2
Definition: int.hh:46
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::ThreadContext::getVirtProxy
virtual PortProxy & getVirtProxy()=0
gem5::SparcISA::INTREG_OTHERWIN
@ INTREG_OTHERWIN
Definition: int.hh:63
gem5::SparcISA::INTREG_CANRESTORE
@ INTREG_CANRESTORE
Definition: int.hh:61
int.hh
gem5::ThreadContext::pcState
virtual TheISA::PCState pcState() const =0
types.hh
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ThreadContext::readIntReg
virtual RegVal readIntReg(RegIndex reg_idx) const =0
gem5::ThreadContext::getProcessPtr
virtual Process * getProcessPtr()=0
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:203
gem5::SparcISA::NWindows
const int NWindows
Definition: sparc_traits.hh:44
gem5::SparcISA::INTREG_O0
@ INTREG_O0
Definition: int.hh:46
gem5::ThreadContext::setMiscReg
virtual void setMiscReg(RegIndex misc_reg, RegVal val)=0
gem5::GenericISA::DelaySlotUPCState
Definition: types.hh:384
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
logging.hh
se_workload.hh
gem5::SparcISA::StackPointerReg
const int StackPointerReg
Definition: int.hh:73
gem5::SparcISA::SEWorkload::flushWindows
virtual void flushWindows(ThreadContext *tc)
Definition: se_workload.cc:96
gem5::SparcISA::SEWorkload::handleTrap
virtual void handleTrap(ThreadContext *tc, int trapNum)
Definition: se_workload.cc:54
gem5::SparcISA::MISCREG_CWP
@ MISCREG_CWP
Definition: misc.hh:68
gem5::ArmISA::sp
Bitfield< 0 > sp
Definition: misc_types.hh:74
gem5::Sparc64Process
Definition: process.hh:103
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::SparcISA::SEWorkload::is64
bool is64(ThreadContext *tc)
Definition: se_workload.cc:48
gem5::SparcISA::INTREG_O4
@ INTREG_O4
Definition: int.hh:47
gem5::SparcISA::SEWorkload::BaseSyscallABI::ArgumentRegs
static const std::vector< int > ArgumentRegs
Definition: se_workload.hh:66
thread_context.hh
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84

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