gem5  v21.2.0.0
tlb.cc
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40 
41 #include "arch/arm/tlb.hh"
42 
43 #include <memory>
44 #include <string>
45 #include <vector>
46 
47 #include "arch/arm/table_walker.hh"
48 #include "arch/arm/tlbi_op.hh"
49 #include "arch/arm/utility.hh"
50 #include "base/trace.hh"
51 #include "cpu/thread_context.hh"
52 #include "debug/TLB.hh"
53 #include "debug/TLBVerbose.hh"
54 #include "params/ArmTLB.hh"
55 
56 namespace gem5
57 {
58 
59 using namespace ArmISA;
60 
61 TLB::TLB(const ArmTLBParams &p)
62  : BaseTLB(p), table(new TlbEntry[p.size]), size(p.size),
63  isStage2(p.is_stage2),
64  _walkCache(false),
65  tableWalker(nullptr),
66  stats(*this), rangeMRU(1), vmid(0)
67 {
68  for (int lvl = LookupLevel::L0;
69  lvl < LookupLevel::Num_ArmLookupLevel; lvl++) {
70 
71  auto it = std::find(
72  p.partial_levels.begin(),
73  p.partial_levels.end(),
74  lvl);
75 
76  auto lookup_lvl = static_cast<LookupLevel>(lvl);
77 
78  if (it != p.partial_levels.end()) {
79  // A partial entry from of the current LookupLevel can be
80  // cached within the TLB
81  partialLevels[lookup_lvl] = true;
82 
83  // Make sure this is not the last level (complete translation)
84  if (lvl != LookupLevel::Num_ArmLookupLevel - 1) {
85  _walkCache = true;
86  }
87  } else {
88  partialLevels[lookup_lvl] = false;
89  }
90  }
91 }
92 
94 {
95  delete[] table;
96 }
97 
98 void
100 {
101  tableWalker = table_walker;
102  tableWalker->setTlb(this);
103 }
104 
105 TlbEntry*
106 TLB::match(const Lookup &lookup_data)
107 {
108  // Vector of TLB entry candidates.
109  // Only one of them will be assigned to retval and will
110  // be returned to the MMU (in case of a hit)
111  // The vector has one entry per lookup level as it stores
112  // both complete and partial matches
114  LookupLevel::Num_ArmLookupLevel, {0, nullptr}};
115 
116  int x = 0;
117  while (x < size) {
118  if (table[x].match(lookup_data)) {
119  const TlbEntry &entry = table[x];
120  hits[entry.lookupLevel] = std::make_pair(x, &entry);
121 
122  // This is a complete translation, no need to loop further
123  if (!entry.partial)
124  break;
125  }
126  ++x;
127  }
128 
129  // Loop over the list of TLB entries matching our translation
130  // request, starting from the highest lookup level (complete
131  // translation) and iterating backwards (using reverse iterators)
132  for (auto it = hits.rbegin(); it != hits.rend(); it++) {
133  const auto& [idx, entry] = *it;
134  if (!entry) {
135  // No match for the current LookupLevel
136  continue;
137  }
138 
139  // Maintaining LRU array
140  // We only move the hit entry ahead when the position is higher
141  // than rangeMRU
142  if (idx > rangeMRU && !lookup_data.functional) {
143  TlbEntry tmp_entry = *entry;
144  for (int i = idx; i > 0; i--)
145  table[i] = table[i - 1];
146  table[0] = tmp_entry;
147  return &table[0];
148  } else {
149  return &table[idx];
150  }
151  }
152 
153  return nullptr;
154 }
155 
156 TlbEntry*
157 TLB::lookup(const Lookup &lookup_data)
158 {
159  const auto mode = lookup_data.mode;
160 
161  TlbEntry *retval = match(lookup_data);
162 
163  DPRINTF(TLBVerbose, "Lookup %#x, asn %#x -> %s vmn 0x%x hyp %d secure %d "
164  "ppn %#x size: %#x pa: %#x ap:%d ns:%d nstid:%d g:%d asid: %d "
165  "el: %d\n",
166  lookup_data.va, lookup_data.asn, retval ? "hit" : "miss",
167  lookup_data.vmid, lookup_data.hyp, lookup_data.secure,
168  retval ? retval->pfn : 0, retval ? retval->size : 0,
169  retval ? retval->pAddr(lookup_data.va) : 0,
170  retval ? retval->ap : 0,
171  retval ? retval->ns : 0, retval ? retval->nstid : 0,
172  retval ? retval->global : 0, retval ? retval->asid : 0,
173  retval ? retval->el : 0);
174 
175  // Updating stats if this was not a functional lookup
176  if (!lookup_data.functional) {
177  if (!retval) {
178  if (mode == BaseMMU::Execute) {
179  stats.instMisses++;
180  } else if (mode == BaseMMU::Write) {
181  stats.writeMisses++;
182  } else {
183  stats.readMisses++;
184  }
185  } else {
186  if (retval->partial) {
187  stats.partialHits++;
188  }
189 
190  if (mode == BaseMMU::Execute) {
191  stats.instHits++;
192  } else if (mode == BaseMMU::Write) {
193  stats.writeHits++;
194  } else {
195  stats.readHits++;
196  }
197  }
198  }
199 
200  return retval;
201 }
202 
203 TlbEntry*
204 TLB::multiLookup(const Lookup &lookup_data)
205 {
206  TlbEntry* te = lookup(lookup_data);
207 
208  if (te) {
209  checkPromotion(te, lookup_data.mode);
210  } else {
211  if (auto tlb = static_cast<TLB*>(nextLevel())) {
212  te = tlb->multiLookup(lookup_data);
213  if (te && !lookup_data.functional &&
214  (!te->partial || partialLevels[te->lookupLevel])) {
215  // Insert entry only if this is not a functional
216  // lookup and if the translation is complete (unless this
217  // TLB caches partial translations)
218  insert(*te);
219  }
220  }
221  }
222 
223  return te;
224 }
225 
226 void
228 {
229  TypeTLB acc_type = (mode == BaseMMU::Execute) ?
230  TypeTLB::instruction : TypeTLB::data;
231 
232  // Hitting an instruction TLB entry on a data access or
233  // a data TLB entry on an instruction access:
234  // promoting the entry to unified
235  if (!(entry->type & acc_type))
236  entry->type = TypeTLB::unified;
237 }
238 
239 // insert a new TLB entry
240 void
242 {
243  DPRINTF(TLB, "Inserting entry into TLB with pfn:%#x size:%#x vpn: %#x"
244  " asid:%d vmid:%d N:%d global:%d valid:%d nc:%d xn:%d"
245  " ap:%#x domain:%#x ns:%d nstid:%d isHyp:%d\n", entry.pfn,
246  entry.size, entry.vpn, entry.asid, entry.vmid, entry.N,
247  entry.global, entry.valid, entry.nonCacheable, entry.xn,
248  entry.ap, static_cast<uint8_t>(entry.domain), entry.ns, entry.nstid,
249  entry.isHyp);
250 
251  if (table[size - 1].valid)
252  DPRINTF(TLB, " - Replacing Valid entry %#x, asn %d vmn %d ppn %#x "
253  "size: %#x ap:%d ns:%d nstid:%d g:%d isHyp:%d el: %d\n",
254  table[size-1].vpn << table[size-1].N, table[size-1].asid,
255  table[size-1].vmid, table[size-1].pfn << table[size-1].N,
256  table[size-1].size, table[size-1].ap, table[size-1].ns,
257  table[size-1].nstid, table[size-1].global, table[size-1].isHyp,
258  table[size-1].el);
259 
260  // inserting to MRU position and evicting the LRU one
261  for (int i = size - 1; i > 0; --i)
262  table[i] = table[i-1];
263  table[0] = entry;
264 
265  stats.inserts++;
266  ppRefills->notify(1);
267 }
268 
269 void
271 {
272  // Insert a partial translation only if the TLB is configured
273  // as a walk cache
274  if (!entry.partial || partialLevels[entry.lookupLevel]) {
275  insert(entry);
276  }
277 
278  if (auto next_level = static_cast<TLB*>(nextLevel())) {
279  next_level->multiInsert(entry);
280  }
281 }
282 
283 void
285 {
286  int x = 0;
287  TlbEntry *te;
288  DPRINTF(TLB, "Current TLB contents:\n");
289  while (x < size) {
290  te = &table[x];
291  if (te->valid)
292  DPRINTF(TLB, " * %s\n", te->print());
293  ++x;
294  }
295 }
296 
297 void
299 {
300  DPRINTF(TLB, "Flushing all TLB entries\n");
301  int x = 0;
302  TlbEntry *te;
303  while (x < size) {
304  te = &table[x];
305 
306  if (te->valid) {
307  DPRINTF(TLB, " - %s\n", te->print());
308  te->valid = false;
310  }
311  ++x;
312  }
313 
314  stats.flushTlb++;
315 }
316 
317 void
318 TLB::flush(const TLBIALL& tlbi_op)
319 {
320  DPRINTF(TLB, "Flushing all TLB entries (%s lookup)\n",
321  (tlbi_op.secureLookup ? "secure" : "non-secure"));
322  int x = 0;
323  TlbEntry *te;
324  while (x < size) {
325  te = &table[x];
326  const bool el_match = te->checkELMatch(
327  tlbi_op.targetEL, tlbi_op.inHost);
328  if (te->valid && tlbi_op.secureLookup == !te->nstid &&
329  (te->vmid == vmid || tlbi_op.el2Enabled) && el_match) {
330 
331  DPRINTF(TLB, " - %s\n", te->print());
332  te->valid = false;
334  }
335  ++x;
336  }
337 
338  stats.flushTlb++;
339 }
340 
341 void
342 TLB::flush(const ITLBIALL& tlbi_op)
343 {
344  DPRINTF(TLB, "Flushing all ITLB entries (%s lookup)\n",
345  (tlbi_op.secureLookup ? "secure" : "non-secure"));
346  int x = 0;
347  TlbEntry *te;
348  while (x < size) {
349  te = &table[x];
350  const bool el_match = te->checkELMatch(
351  tlbi_op.targetEL, tlbi_op.inHost);
352  if (te->type & TypeTLB::instruction && te->valid &&
353  tlbi_op.secureLookup == !te->nstid &&
354  (te->vmid == vmid || tlbi_op.el2Enabled) && el_match) {
355 
356  DPRINTF(TLB, " - %s\n", te->print());
357  te->valid = false;
359  }
360  ++x;
361  }
362 
363  stats.flushTlb++;
364 }
365 
366 void
367 TLB::flush(const DTLBIALL& tlbi_op)
368 {
369  DPRINTF(TLB, "Flushing all DTLB entries (%s lookup)\n",
370  (tlbi_op.secureLookup ? "secure" : "non-secure"));
371  int x = 0;
372  TlbEntry *te;
373  while (x < size) {
374  te = &table[x];
375  const bool el_match = te->checkELMatch(
376  tlbi_op.targetEL, tlbi_op.inHost);
377  if (te->type & TypeTLB::data && te->valid &&
378  tlbi_op.secureLookup == !te->nstid &&
379  (te->vmid == vmid || tlbi_op.el2Enabled) && el_match) {
380 
381  DPRINTF(TLB, " - %s\n", te->print());
382  te->valid = false;
384  }
385  ++x;
386  }
387 
388  stats.flushTlb++;
389 }
390 
391 void
392 TLB::flush(const TLBIALLEL &tlbi_op)
393 {
394  DPRINTF(TLB, "Flushing all TLB entries (%s lookup)\n",
395  (tlbi_op.secureLookup ? "secure" : "non-secure"));
396  int x = 0;
397  TlbEntry *te;
398  while (x < size) {
399  te = &table[x];
400  const bool el_match = te->checkELMatch(
401  tlbi_op.targetEL, tlbi_op.inHost);
402  if (te->valid && tlbi_op.secureLookup == !te->nstid && el_match) {
403 
404  DPRINTF(TLB, " - %s\n", te->print());
405  te->valid = false;
407  }
408  ++x;
409  }
410 
411  stats.flushTlb++;
412 }
413 
414 void
415 TLB::flush(const TLBIVMALL &tlbi_op)
416 {
417  DPRINTF(TLB, "Flushing all TLB entries (%s lookup)\n",
418  (tlbi_op.secureLookup ? "secure" : "non-secure"));
419  int x = 0;
420  TlbEntry *te;
421  while (x < size) {
422  te = &table[x];
423  const bool el_match = te->checkELMatch(
424  tlbi_op.targetEL, tlbi_op.inHost);
425 
426  const bool vmid_match =
427  te->vmid == vmid ||
428  !tlbi_op.el2Enabled ||
429  (!tlbi_op.stage2Flush() && tlbi_op.inHost);
430 
431  if (te->valid && tlbi_op.secureLookup == !te->nstid &&
432  el_match && vmid_match) {
433 
434  DPRINTF(TLB, " - %s\n", te->print());
435  te->valid = false;
437  }
438  ++x;
439  }
440 
441  stats.flushTlb++;
442 }
443 
444 void
445 TLB::flush(const TLBIALLN &tlbi_op)
446 {
447  bool hyp = tlbi_op.targetEL == EL2;
448 
449  DPRINTF(TLB, "Flushing all NS TLB entries (%s lookup)\n",
450  (hyp ? "hyp" : "non-hyp"));
451  int x = 0;
452  TlbEntry *te;
453  while (x < size) {
454  te = &table[x];
455  const bool el_match = te->checkELMatch(tlbi_op.targetEL, false);
456 
457  if (te->valid && te->nstid && te->isHyp == hyp && el_match) {
458 
459  DPRINTF(TLB, " - %s\n", te->print());
461  te->valid = false;
462  }
463  ++x;
464  }
465 
466  stats.flushTlb++;
467 }
468 
469 void
470 TLB::flush(const TLBIMVA &tlbi_op)
471 {
472  DPRINTF(TLB, "Flushing TLB entries with mva: %#x, asid: %#x "
473  "(%s lookup)\n", tlbi_op.addr, tlbi_op.asid,
474  (tlbi_op.secureLookup ? "secure" : "non-secure"));
475  _flushMva(tlbi_op.addr, tlbi_op.asid, tlbi_op.secureLookup, false,
476  tlbi_op.targetEL, tlbi_op.inHost, TypeTLB::unified);
478 }
479 
480 void
481 TLB::flush(const ITLBIMVA &tlbi_op)
482 {
483  DPRINTF(TLB, "Flushing ITLB entries with mva: %#x, asid: %#x "
484  "(%s lookup)\n", tlbi_op.addr, tlbi_op.asid,
485  (tlbi_op.secureLookup ? "secure" : "non-secure"));
486  _flushMva(tlbi_op.addr, tlbi_op.asid, tlbi_op.secureLookup, false,
487  tlbi_op.targetEL, tlbi_op.inHost, TypeTLB::instruction);
489 }
490 
491 void
492 TLB::flush(const DTLBIMVA &tlbi_op)
493 {
494  DPRINTF(TLB, "Flushing DTLB entries with mva: %#x, asid: %#x "
495  "(%s lookup)\n", tlbi_op.addr, tlbi_op.asid,
496  (tlbi_op.secureLookup ? "secure" : "non-secure"));
497  _flushMva(tlbi_op.addr, tlbi_op.asid, tlbi_op.secureLookup, false,
498  tlbi_op.targetEL, tlbi_op.inHost, TypeTLB::data);
500 }
501 
502 void
503 TLB::flush(const TLBIASID &tlbi_op)
504 {
505  DPRINTF(TLB, "Flushing TLB entries with asid: %#x (%s lookup)\n",
506  tlbi_op.asid, (tlbi_op.secureLookup ? "secure" : "non-secure"));
507 
508  int x = 0 ;
509  TlbEntry *te;
510 
511  while (x < size) {
512  te = &table[x];
513 
514  const bool el_match = te->checkELMatch(
515  tlbi_op.targetEL, tlbi_op.inHost);
516 
517  const bool vmid_match =
518  te->vmid == vmid || !tlbi_op.el2Enabled || tlbi_op.inHost;
519 
520  if (te->valid && te->asid == tlbi_op.asid &&
521  tlbi_op.secureLookup == !te->nstid &&
522  vmid_match && el_match) {
523 
524  te->valid = false;
525  DPRINTF(TLB, " - %s\n", te->print());
527  }
528  ++x;
529  }
531 }
532 
533 void
534 TLB::flush(const ITLBIASID &tlbi_op)
535 {
536  DPRINTF(TLB, "Flushing ITLB entries with asid: %#x (%s lookup)\n",
537  tlbi_op.asid, (tlbi_op.secureLookup ? "secure" : "non-secure"));
538 
539  int x = 0 ;
540  TlbEntry *te;
541 
542  while (x < size) {
543  te = &table[x];
544  if (te->type & TypeTLB::instruction &&
545  te->valid && te->asid == tlbi_op.asid &&
546  tlbi_op.secureLookup == !te->nstid &&
547  (te->vmid == vmid || tlbi_op.el2Enabled) &&
548  te->checkELMatch(tlbi_op.targetEL, tlbi_op.inHost)) {
549 
550  te->valid = false;
551  DPRINTF(TLB, " - %s\n", te->print());
553  }
554  ++x;
555  }
557 }
558 
559 void
560 TLB::flush(const DTLBIASID &tlbi_op)
561 {
562  DPRINTF(TLB, "Flushing DTLB entries with asid: %#x (%s lookup)\n",
563  tlbi_op.asid, (tlbi_op.secureLookup ? "secure" : "non-secure"));
564 
565  int x = 0 ;
566  TlbEntry *te;
567 
568  while (x < size) {
569  te = &table[x];
570  if (te->type & TypeTLB::data &&
571  te->valid && te->asid == tlbi_op.asid &&
572  tlbi_op.secureLookup == !te->nstid &&
573  (te->vmid == vmid || tlbi_op.el2Enabled) &&
574  te->checkELMatch(tlbi_op.targetEL, tlbi_op.inHost)) {
575 
576  te->valid = false;
577  DPRINTF(TLB, " - %s\n", te->print());
579  }
580  ++x;
581  }
583 }
584 
585 void
586 TLB::flush(const TLBIMVAA &tlbi_op) {
587 
588  DPRINTF(TLB, "Flushing TLB entries with mva: %#x (%s lookup)\n",
589  tlbi_op.addr,
590  (tlbi_op.secureLookup ? "secure" : "non-secure"));
591  _flushMva(tlbi_op.addr, 0xbeef, tlbi_op.secureLookup, true,
592  tlbi_op.targetEL, tlbi_op.inHost, TypeTLB::unified);
593  stats.flushTlbMva++;
594 }
595 
596 void
597 TLB::_flushMva(Addr mva, uint64_t asn, bool secure_lookup,
598  bool ignore_asn, ExceptionLevel target_el, bool in_host,
599  TypeTLB entry_type)
600 {
601  TlbEntry *te;
602  Lookup lookup_data;
603 
604  lookup_data.va = sext<56>(mva);
605  lookup_data.asn = asn;
606  lookup_data.ignoreAsn = ignore_asn;
607  lookup_data.vmid = vmid;
608  lookup_data.hyp = target_el == EL2;
609  lookup_data.secure = secure_lookup;
610  lookup_data.functional = true;
611  lookup_data.targetEL = target_el;
612  lookup_data.inHost = in_host;
613  lookup_data.mode = BaseMMU::Read;
614 
615  te = lookup(lookup_data);
616  while (te != NULL) {
617  bool matching_type = (te->type & entry_type);
618  if (matching_type && secure_lookup == !te->nstid) {
619  DPRINTF(TLB, " - %s\n", te->print());
620  te->valid = false;
622  }
623  te = lookup(lookup_data);
624  }
625 }
626 
627 void
629 {
630 }
631 
633  : statistics::Group(&parent), tlb(parent),
634  ADD_STAT(partialHits, statistics::units::Count::get(),
635  "partial translation hits"),
636  ADD_STAT(instHits, statistics::units::Count::get(), "Inst hits"),
637  ADD_STAT(instMisses, statistics::units::Count::get(), "Inst misses"),
638  ADD_STAT(readHits, statistics::units::Count::get(), "Read hits"),
639  ADD_STAT(readMisses, statistics::units::Count::get(), "Read misses"),
640  ADD_STAT(writeHits, statistics::units::Count::get(), "Write hits"),
641  ADD_STAT(writeMisses, statistics::units::Count::get(), "Write misses"),
642  ADD_STAT(inserts, statistics::units::Count::get(),
643  "Number of times an entry is inserted into the TLB"),
644  ADD_STAT(flushTlb, statistics::units::Count::get(),
645  "Number of times complete TLB was flushed"),
646  ADD_STAT(flushTlbMva, statistics::units::Count::get(),
647  "Number of times TLB was flushed by MVA"),
648  ADD_STAT(flushTlbMvaAsid, statistics::units::Count::get(),
649  "Number of times TLB was flushed by MVA & ASID"),
650  ADD_STAT(flushTlbAsid, statistics::units::Count::get(),
651  "Number of times TLB was flushed by ASID"),
652  ADD_STAT(flushedEntries, statistics::units::Count::get(),
653  "Number of entries that have been flushed from TLB"),
654  ADD_STAT(readAccesses, statistics::units::Count::get(), "Read accesses",
655  readHits + readMisses),
656  ADD_STAT(writeAccesses, statistics::units::Count::get(), "Write accesses",
657  writeHits + writeMisses),
658  ADD_STAT(instAccesses, statistics::units::Count::get(), "Inst accesses",
659  instHits + instMisses),
660  ADD_STAT(hits, statistics::units::Count::get(),
661  "Total TLB (inst and data) hits",
662  readHits + writeHits + instHits),
663  ADD_STAT(misses, statistics::units::Count::get(),
664  "Total TLB (inst and data) misses",
665  readMisses + writeMisses + instMisses),
666  ADD_STAT(accesses, statistics::units::Count::get(),
667  "Total TLB (inst and data) accesses",
668  readAccesses + writeAccesses + instAccesses)
669 {
670  // If this is a pure Data TLB, mark the instruction
671  // stats as nozero, so that they won't make it in
672  // into the final stats file
673  if (tlb.type() == TypeTLB::data) {
676 
678  }
679 
680  // If this is a pure Instruction TLB, mark the data
681  // stats as nozero, so that they won't make it in
682  // into the final stats file
683  if (tlb.type() & TypeTLB::instruction) {
688 
691  }
692 
694 }
695 
696 void
698 {
699  ppRefills.reset(new probing::PMU(getProbeManager(), "Refills"));
700 }
701 
702 Port *
704 {
705  return &tableWalker->getTableWalkerPort();
706 }
707 
708 } // namespace gem5
gem5::ArmISA::ITLBIALL
Instruction TLB Invalidate All.
Definition: tlbi_op.hh:136
gem5::ArmISA::TLB::tableWalker
TableWalker * tableWalker
Definition: tlb.hh:138
gem5::ArmISA::tlb
Bitfield< 59, 56 > tlb
Definition: misc_types.hh:92
gem5::ArmISA::TlbEntry::Lookup::mode
BaseMMU::Mode mode
Definition: pagetable.hh:206
gem5::BaseMMU::Read
@ Read
Definition: mmu.hh:56
gem5::ArmISA::TLB::ppRefills
probing::PMUUPtr ppRefills
PMU probe for TLB refills.
Definition: tlb.hh:170
gem5::ArmISA::TLB::lookup
TlbEntry * lookup(const Lookup &lookup_data)
Lookup an entry in the TLB.
Definition: tlb.cc:157
gem5::ArmISA::TLBIALLEL
Implementaton of AArch64 TLBI ALLE(1,2,3)(IS) instructions.
Definition: tlbi_op.hh:162
gem5::ArmISA::TlbEntry::valid
bool valid
Definition: pagetable.hh:236
data
const char data[]
Definition: circlebuf.test.cc:48
gem5::ArmISA::TLBIASID
TLB Invalidate by ASID match.
Definition: tlbi_op.hh:216
gem5::ArmISA::TLBIALL
TLB Invalidate All.
Definition: tlbi_op.hh:106
gem5::ArmISA::TlbEntry::type
TypeTLB type
Definition: pagetable.hh:246
gem5::ArmISA::TLB::TlbStats::partialHits
statistics::Scalar partialHits
Definition: tlb.hh:147
gem5::ArmISA::el
Bitfield< 3, 2 > el
Definition: misc_types.hh:73
gem5::ArmISA::TlbEntry::ns
bool ns
Definition: pagetable.hh:239
gem5::ArmISA::TLB::table
TlbEntry * table
Definition: tlb.hh:118
gem5::ArmISA::TLBIMVA::asid
uint16_t asid
Definition: tlbi_op.hh:308
gem5::BaseTLB::nextLevel
BaseTLB * nextLevel() const
Definition: tlb.hh:127
gem5::ArmISA::TableWalker::getTableWalkerPort
Port & getTableWalkerPort()
Definition: table_walker.cc:104
gem5::ArmISA::TLB::size
int size
TLB Size.
Definition: tlb.hh:121
gem5::ArmISA::TLB::match
TlbEntry * match(const Lookup &lookup_data)
Helper function looking up for a matching TLB entry Does not update stats; see lookup method instead.
Definition: tlb.cc:106
gem5::ArmISA::TLB::TlbStats::readHits
statistics::Scalar readHits
Definition: tlb.hh:150
gem5::BaseMMU::Mode
Mode
Definition: mmu.hh:56
gem5::ArmISA::asid
asid
Definition: misc_types.hh:618
gem5::BaseMMU::Write
@ Write
Definition: mmu.hh:56
gem5::ArmISA::TlbEntry::pfn
Addr pfn
Definition: pagetable.hh:210
gem5::ArmISA::TLB::TLB
TLB(const Params &p)
Definition: tlb.cc:61
gem5::statistics::nozero
const FlagsType nozero
Don't print if this is zero.
Definition: info.hh:68
gem5::ArmISA::TlbEntry::isHyp
bool isHyp
Definition: pagetable.hh:234
gem5::ArmISA::TLB
Definition: tlb.hh:115
gem5::ArmISA::ns
Bitfield< 0 > ns
Definition: misc_types.hh:332
tlb.hh
std::vector
STL vector class.
Definition: stl.hh:37
gem5::ArmISA::TLB::multiInsert
void multiInsert(TlbEntry &pte)
Insert a PTE in the current TLB and in the higher levels.
Definition: tlb.cc:270
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:67
table_walker.hh
gem5::ArmISA::DTLBIASID
Data TLB Invalidate by ASID match.
Definition: tlbi_op.hh:245
gem5::ArmISA::TLBIALL::inHost
bool inHost
Definition: tlbi_op.hh:130
gem5::ArmISA::ITLBIASID
Instruction TLB Invalidate by ASID match.
Definition: tlbi_op.hh:232
gem5::ArmISA::TlbEntry
Definition: pagetable.hh:165
gem5::ArmISA::TLBIOp::secureLookup
bool secureLookup
Definition: tlbi_op.hh:101
gem5::ArmISA::ITLBIMVA
Instruction TLB Invalidate by VA.
Definition: tlbi_op.hh:313
gem5::ArmISA::TLBIVMALL::stage2Flush
bool stage2Flush() const override
Return true if the TLBI op needs to flush stage2 entries, Defaulting to false in the TLBIOp abstract ...
Definition: tlbi_op.hh:199
gem5::BaseMMU::Execute
@ Execute
Definition: mmu.hh:56
gem5::ArmISA::TlbEntry::size
Addr size
Definition: pagetable.hh:211
gem5::ArmISA::TLB::LookupLevel
enums::ArmLookupLevel LookupLevel
Definition: tlb.hh:178
gem5::ArmISA::TLBIASID::asid
uint16_t asid
Definition: tlbi_op.hh:226
gem5::ArmISA::TlbEntry::Lookup
Definition: pagetable.hh:185
gem5::ArmISA::TLB::checkPromotion
void checkPromotion(TlbEntry *entry, BaseMMU::Mode mode)
Check if the tlb entry passed as an argument needs to be "promoted" as a unified entry: this should h...
Definition: tlb.cc:227
gem5::ArmISA::TLBIALLN
TLB Invalidate All, Non-Secure.
Definition: tlbi_op.hh:258
gem5::ArmISA::TLBIASID::el2Enabled
bool el2Enabled
Definition: tlbi_op.hh:228
gem5::ArmISA::TLB::multiLookup
TlbEntry * multiLookup(const Lookup &lookup_data)
Lookup an entry in the TLB and in the next levels by following the nextLevel pointer.
Definition: tlb.cc:204
gem5::ArmISA::TLB::TlbStats::instHits
statistics::Scalar instHits
Definition: tlb.hh:148
gem5::ArmISA::TLB::printTlb
void printTlb() const
Definition: tlb.cc:284
gem5::ArmISA::TLB::TlbStats::tlb
const TLB & tlb
Definition: tlb.hh:144
gem5::ArmISA::TLB::TlbStats::writeHits
statistics::Scalar writeHits
Definition: tlb.hh:152
gem5::ArmISA::TLB::takeOverFrom
void takeOverFrom(BaseTLB *otlb) override
Take over from an old tlb context.
Definition: tlb.cc:628
gem5::BaseTLB::type
TypeTLB type() const
Definition: tlb.hh:125
gem5::ArmISA::TLB::getTableWalkerPort
Port * getTableWalkerPort() override
Get the table walker port.
Definition: tlb.cc:703
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
ADD_STAT
#define ADD_STAT(n,...)
Convenience macro to add a stat to a statistics group.
Definition: group.hh:75
gem5::ArmISA::TlbEntry::Lookup::functional
bool functional
Definition: pagetable.hh:200
gem5::ArmISA::TlbEntry::Lookup::secure
bool secure
Definition: pagetable.hh:198
gem5::ArmISA::TLB::TlbStats::readMisses
statistics::Scalar readMisses
Definition: tlb.hh:151
gem5::ArmISA::TLB::stats
gem5::ArmISA::TLB::TlbStats stats
gem5::ArmISA::TLB::TlbStats::TlbStats
TlbStats(TLB &parent)
Definition: tlb.cc:632
gem5::ArmISA::TlbEntry::domain
DomainType domain
Definition: pagetable.hh:227
gem5::ArmISA::EL2
@ EL2
Definition: types.hh:268
gem5::ArmISA::TLBIMVAA
TLB Invalidate by VA, All ASID.
Definition: tlbi_op.hh:281
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::ArmISA::TLB::flush
void flush(const TLBIALL &tlbi_op)
Reset the entire TLB.
Definition: tlb.cc:318
gem5::ArmISA::TableWalker::setTlb
void setTlb(TLB *_tlb)
Definition: table_walker.hh:1110
gem5::ArmISA::TlbEntry::el
ExceptionLevel el
Definition: pagetable.hh:243
gem5::MipsISA::pfn
Bitfield< 29, 6 > pfn
Definition: pra_constants.hh:58
gem5::ArmISA::TLB::_walkCache
bool _walkCache
True if the TLB caches partial translations.
Definition: tlb.hh:136
gem5::ArmISA::TLB::TlbStats::instAccesses
statistics::Formula instAccesses
Definition: tlb.hh:163
gem5::BaseTLB
Definition: tlb.hh:58
gem5::ArmISA::TlbEntry::N
uint8_t N
Definition: pagetable.hh:222
gem5::ArmISA::TlbEntry::Lookup::inHost
bool inHost
Definition: pagetable.hh:204
tlbi_op.hh
gem5::ArmISA::te
Bitfield< 30 > te
Definition: misc_types.hh:338
gem5::ArmISA::TLBIALL::el2Enabled
bool el2Enabled
Definition: tlbi_op.hh:131
gem5::ArmISA::TLBIASID::inHost
bool inHost
Definition: tlbi_op.hh:227
gem5::ArmISA::TLB::TlbStats::flushTlbMva
statistics::Scalar flushTlbMva
Definition: tlb.hh:156
gem5::ArmISA::TlbEntry::Lookup::va
Addr va
Definition: pagetable.hh:188
gem5::ArmISA::TlbEntry::Lookup::vmid
vmid_t vmid
Definition: pagetable.hh:194
gem5::ArmISA::TLBIVMALL::el2Enabled
bool el2Enabled
Definition: tlbi_op.hh:211
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ArmISA::TLB::flushAll
void flushAll() override
Reset the entire TLB.
Definition: tlb.cc:298
gem5::ArmISA::TlbEntry::global
bool global
Definition: pagetable.hh:235
gem5::ArmISA::TlbEntry::vpn
Addr vpn
Definition: pagetable.hh:212
gem5::ArmISA::TlbEntry::Lookup::targetEL
ExceptionLevel targetEL
Definition: pagetable.hh:202
gem5::ArmISA::TLB::TlbStats::writeAccesses
statistics::Formula writeAccesses
Definition: tlb.hh:162
gem5::ArmISA::TLBIMVAA::inHost
bool inHost
Definition: tlbi_op.hh:292
gem5::ArmISA::TLB::TlbStats::flushTlb
statistics::Scalar flushTlb
Definition: tlb.hh:155
utility.hh
gem5::ArmISA::TLB::TlbStats::flushTlbAsid
statistics::Scalar flushTlbAsid
Definition: tlb.hh:158
gem5::ArmISA::TLB::TlbStats::writeMisses
statistics::Scalar writeMisses
Definition: tlb.hh:153
gem5::ProbePointArg
ProbePointArg generates a point for the class of Arg.
Definition: thermal_domain.hh:54
gem5::ArmISA::TLBIMVA::inHost
bool inHost
Definition: tlbi_op.hh:309
gem5::ArmISA::TLBIALLEL::inHost
bool inHost
Definition: tlbi_op.hh:184
gem5::ArmISA::TLBIMVA::addr
Addr addr
Definition: tlbi_op.hh:307
gem5::SimObject::getProbeManager
ProbeManager * getProbeManager()
Get the probe manager for this object.
Definition: sim_object.cc:120
gem5::ArmISA::TlbEntry::vmid
vmid_t vmid
Definition: pagetable.hh:221
gem5::ArmISA::TLB::TlbStats::instMisses
statistics::Scalar instMisses
Definition: tlb.hh:149
gem5::ArmISA::TableWalker
Definition: table_walker.hh:66
gem5::RiscvISA::x
Bitfield< 3 > x
Definition: pagetable.hh:73
gem5::ArmISA::TlbEntry::asid
uint16_t asid
Definition: pagetable.hh:220
gem5::ArmISA::TLBIMVAA::addr
Addr addr
Definition: tlbi_op.hh:291
gem5::ArmISA::TLB::vmid
vmid_t vmid
Definition: tlb.hh:173
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
gem5::ArmISA::TlbEntry::xn
bool xn
Definition: pagetable.hh:258
gem5::ArmISA::TLB::regProbePoints
void regProbePoints() override
Register probe points for this object.
Definition: tlb.cc:697
gem5::ArmISA::TLB::partialLevels
std::unordered_map< enums::ArmLookupLevel, bool > partialLevels
Hash map containing one entry per lookup level The TLB is caching partial translations from the key l...
Definition: tlb.hh:131
gem5::ArmISA::DTLBIALL
Data TLB Invalidate All.
Definition: tlbi_op.hh:149
gem5::ArmISA::TlbEntry::Lookup::asn
uint16_t asn
Definition: pagetable.hh:190
gem5::ArmISA::TLB::setTableWalker
void setTableWalker(TableWalker *table_walker)
Definition: tlb.cc:99
gem5::ArmISA::TLBIMVA
TLB Invalidate by VA.
Definition: tlbi_op.hh:296
gem5::ArmISA::TLBIOp::targetEL
ExceptionLevel targetEL
Definition: tlbi_op.hh:102
gem5::ArmISA::TLBIVMALL
Implementaton of AArch64 TLBI VMALLE1(IS)/VMALLS112E1(IS) instructions.
Definition: tlbi_op.hh:188
gem5::ArmISA::TlbEntry::nstid
bool nstid
Definition: pagetable.hh:241
gem5::ArmISA::TlbEntry::Lookup::hyp
bool hyp
Definition: pagetable.hh:196
gem5::ArmISA::TLBIVMALL::inHost
bool inHost
Definition: tlbi_op.hh:210
gem5::ArmISA::TLB::insert
void insert(TlbEntry &pte)
Insert a PTE in the current TLB.
Definition: tlb.cc:241
gem5::statistics::Group
Statistics container.
Definition: group.hh:93
gem5::ArmISA::TLB::_flushMva
void _flushMva(Addr mva, uint64_t asn, bool secure_lookup, bool ignore_asn, ExceptionLevel target_el, bool in_host, TypeTLB entry_type)
Remove any entries that match both a va and asn.
Definition: tlb.cc:597
gem5::ArmISA::TLB::TlbStats::inserts
statistics::Scalar inserts
Definition: tlb.hh:154
gem5::ArmISA::TlbEntry::partial
bool partial
Definition: pagetable.hh:248
gem5::ArmISA::TLB::TlbStats::flushedEntries
statistics::Scalar flushedEntries
Definition: tlb.hh:159
trace.hh
gem5::statistics::DataWrap::flags
Derived & flags(Flags _flags)
Set the flags and marks this stat to print at the end of simulation.
Definition: statistics.hh:358
gem5::ArmISA::DTLBIMVA
Data TLB Invalidate by VA.
Definition: tlbi_op.hh:327
gem5::ArmISA::TLB::~TLB
virtual ~TLB()
Definition: tlb.cc:93
gem5::ArmISA::TlbEntry::nonCacheable
bool nonCacheable
Definition: pagetable.hh:251
gem5::ArmISA::TlbEntry::Lookup::ignoreAsn
bool ignoreAsn
Definition: pagetable.hh:192
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::ArmISA::TlbEntry::pAddr
Addr pAddr(Addr va) const
Definition: pagetable.hh:348
gem5::ArmISA::TLB::TlbStats::readAccesses
statistics::Formula readAccesses
Definition: tlb.hh:161
thread_context.hh
gem5::ArmISA::TLB::rangeMRU
int rangeMRU
Definition: tlb.hh:172
gem5::ArmISA::TLB::TlbStats::flushTlbMvaAsid
statistics::Scalar flushTlbMvaAsid
Definition: tlb.hh:157
gem5::ArmISA::TlbEntry::ap
uint8_t ap
Definition: pagetable.hh:225
gem5::ArmISA::ExceptionLevel
ExceptionLevel
Definition: types.hh:264
gem5::ArmISA::mode
Bitfield< 4, 0 > mode
Definition: misc_types.hh:74
gem5::ArmISA::TlbEntry::lookupLevel
LookupLevel lookupLevel
Definition: pagetable.hh:215

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