gem5  v22.0.0.2
gic_v3.cc
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1 /*
2  * Copyright (c) 2019-2022 Arm Limited
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14  * Copyright (c) 2018 Metempsy Technology Consulting
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40 
41 #include "dev/arm/gic_v3.hh"
42 
43 #include "cpu/base.hh"
44 #include "debug/GIC.hh"
45 #include "debug/Interrupt.hh"
48 #include "dev/arm/gic_v3_its.hh"
50 #include "dev/platform.hh"
51 #include "mem/packet.hh"
52 #include "mem/packet_access.hh"
53 
54 namespace gem5
55 {
56 
57 void
60  Addr daddr)
61 {
62  auto val = from->readDistributor(daddr);
63  DPRINTF(GIC, "copy dist 0x%x 0x%08x\n", daddr, val);
64  to->writeDistributor(daddr, val);
65 }
66 
67 void
70  const ArmISA::Affinity &aff, Addr daddr)
71 {
72  auto val = from->readRedistributor(aff, daddr);
73  DPRINTF(GIC,
74  "copy redist (aff3: %d, aff2: %d, aff1: %d, aff0: %d) "
75  "0x%x 0x%08x\n",
76  aff.aff3, aff.aff2, aff.aff1, aff.aff0, daddr, val);
77 
78  to->writeRedistributor(aff, daddr, val);
79 }
80 
81 void
84  const ArmISA::Affinity &aff,
85  ArmISA::MiscRegIndex misc_reg)
86 {
87  auto val = from->readCpu(aff, misc_reg);
88  DPRINTF(GIC,
89  "copy cpu (aff3: %d, aff2: %d, aff1: %d, aff0: %d) "
90  "%s 0x%08x\n",
91  aff.aff3, aff.aff2, aff.aff1, aff.aff0,
92  ArmISA::miscRegName[misc_reg], val);
93 
94  to->writeCpu(aff, misc_reg, val);
95 }
96 
97 void
99  const ArmISA::Affinity &aff, Addr daddr)
100 {
101  to->writeRedistributor(aff, daddr, 0xFFFFFFFF);
102 }
103 
104 void
107  const ArmISA::Affinity &aff,
108  Addr daddr, size_t size)
109 {
110  for (auto a = daddr; a < daddr + size; a += 4)
111  copyRedistRegister(from, to, aff, a);
112 }
113 
114 void
117  Addr daddr, size_t size)
118 {
119  for (auto a = daddr; a < daddr + size; a += 4)
120  copyDistRegister(from, to, a);
121 }
122 
123 void
125 {
126  for (auto a = daddr; a < daddr + size; a += 4)
127  to->writeDistributor(a, 0xFFFFFFFF);
128 }
129 
130 
132  : BaseGic(p)
133 {
134 }
135 
136 void
138 {
139  distributor = new Gicv3Distributor(this, params().it_lines);
140  int threads = sys->threads.size();
141  redistributors.resize(threads, nullptr);
142  cpuInterfaces.resize(threads, nullptr);
143 
144  panic_if(threads > params().cpu_max,
145  "Exceeding maximum number of PEs supported by GICv3: "
146  "using %u while maximum is %u.", threads, params().cpu_max);
147 
148  for (int i = 0; i < threads; i++) {
149  redistributors[i] = new Gicv3Redistributor(this, i);
150  cpuInterfaces[i] = new Gicv3CPUInterface(this, i);
151  }
152 
153  distRange = RangeSize(params().dist_addr,
155 
156  redistSize = redistributors[0]->addrRangeSize;
157  redistRange = RangeSize(params().redist_addr, redistSize * threads);
158 
160 
161  distributor->init();
162 
163  for (int i = 0; i < threads; i++) {
164  redistributors[i]->init();
165  cpuInterfaces[i]->init();
166  }
167 
168  Gicv3Its *its = params().its;
169  if (its)
170  its->setGIC(this);
171 
172  BaseGic::init();
173 }
174 
175 Tick
177 {
178  const Addr addr = pkt->getAddr();
179  const size_t size = pkt->getSize();
180  bool is_secure_access = pkt->isSecure();
181  uint64_t resp = 0;
182  Tick delay = 0;
183 
184  if (distRange.contains(addr)) {
185  const Addr daddr = addr - distRange.start();
186  panic_if(!distributor, "Distributor is null!");
187  resp = distributor->read(daddr, size, is_secure_access);
188  delay = params().dist_pio_delay;
189  DPRINTF(GIC, "Gicv3::read(): (distributor) context_id %d register %#x "
190  "size %d is_secure_access %d (value %#x)\n",
191  pkt->req->contextId(), daddr, size, is_secure_access, resp);
192  } else if (redistRange.contains(addr)) {
193  Addr daddr = (addr - redistRange.start()) % redistSize;
194 
196  resp = redist->read(daddr, size, is_secure_access);
197 
198  delay = params().redist_pio_delay;
199  DPRINTF(GIC, "Gicv3::read(): (redistributor %d) context_id %d "
200  "register %#x size %d is_secure_access %d (value %#x)\n",
201  redist->processorNumber(), pkt->req->contextId(), daddr, size,
202  is_secure_access, resp);
203  } else {
204  panic("Gicv3::read(): unknown address %#x\n", addr);
205  }
206 
207  pkt->setUintX(resp, ByteOrder::little);
208  pkt->makeAtomicResponse();
209  return delay;
210 }
211 
212 Tick
214 {
215  const size_t size = pkt->getSize();
216  uint64_t data = pkt->getUintX(ByteOrder::little);
217  const Addr addr = pkt->getAddr();
218  bool is_secure_access = pkt->isSecure();
219  Tick delay = 0;
220 
221  if (distRange.contains(addr)) {
222  const Addr daddr = addr - distRange.start();
223  panic_if(!distributor, "Distributor is null!");
224  DPRINTF(GIC, "Gicv3::write(): (distributor) context_id %d "
225  "register %#x size %d is_secure_access %d value %#x\n",
226  pkt->req->contextId(), daddr, size, is_secure_access, data);
227  distributor->write(daddr, data, size, is_secure_access);
228  delay = params().dist_pio_delay;
229  } else if (redistRange.contains(addr)) {
230  Addr daddr = (addr - redistRange.start()) % redistSize;
231 
233  DPRINTF(GIC, "Gicv3::write(): (redistributor %d) context_id %d "
234  "register %#x size %d is_secure_access %d value %#x\n",
235  redist->processorNumber(), pkt->req->contextId(), daddr, size,
236  is_secure_access, data);
237 
238  redist->write(daddr, data, size, is_secure_access);
239 
240  delay = params().redist_pio_delay;
241  } else {
242  panic("Gicv3::write(): unknown address %#x\n", addr);
243  }
244 
245  pkt->makeAtomicResponse();
246  return delay;
247 }
248 
249 void
250 Gicv3::sendInt(uint32_t int_id)
251 {
252  DPRINTF(Interrupt, "Gicv3::sendInt(): received SPI %d\n", int_id);
253  distributor->sendInt(int_id);
254 }
255 
256 void
257 Gicv3::clearInt(uint32_t int_id)
258 {
259  DPRINTF(Interrupt, "Gicv3::clearInt(): received SPI %d\n", int_id);
260  distributor->clearInt(int_id);
261 }
262 
263 void
264 Gicv3::sendPPInt(uint32_t int_id, uint32_t cpu)
265 {
266  panic_if(cpu >= redistributors.size(), "Invalid cpuID sending PPI!");
267  DPRINTF(Interrupt, "Gicv3::sendPPInt(): received PPI %d cpuTarget %#x\n",
268  int_id, cpu);
269  redistributors[cpu]->sendPPInt(int_id);
270 }
271 
272 void
273 Gicv3::clearPPInt(uint32_t int_id, uint32_t cpu)
274 {
275  panic_if(cpu >= redistributors.size(), "Invalid cpuID clearing PPI!");
276  DPRINTF(Interrupt, "Gicv3::clearPPInt(): received PPI %d cpuTarget %#x\n",
277  int_id, cpu);
278  redistributors[cpu]->clearPPInt(int_id);
279 }
280 
281 void
283 {
284  auto tc = sys->threads[cpu];
285  tc->getCpuPtr()->postInterrupt(tc->threadId(), int_type, 0);
287 }
288 
289 bool
291 {
292  return (version == GicVersion::GIC_V3) ||
293  (version == GicVersion::GIC_V4 && params().gicv4);
294 }
295 
296 void
298 {
299  auto tc = sys->threads[cpu];
300  tc->getCpuPtr()->clearInterrupt(tc->threadId(), int_type, 0);
301 }
302 
303 void
304 Gicv3::deassertAll(uint32_t cpu)
305 {
306  auto tc = sys->threads[cpu];
307  tc->getCpuPtr()->clearInterrupts(tc->threadId());
308 }
309 
310 bool
311 Gicv3::haveAsserted(uint32_t cpu) const
312 {
313  auto tc = sys->threads[cpu];
314  return tc->getCpuPtr()->checkInterrupts(tc->threadId());
315 }
316 
318 Gicv3::getCPUInterfaceByAffinity(const ArmISA::Affinity &aff) const
319 {
321 }
322 
324 Gicv3::getRedistributorByAffinity(const ArmISA::Affinity &aff) const
325 {
326  for (auto & redistributor : redistributors) {
327  if (redistributor->getAffinity() == aff) {
328  return redistributor;
329  }
330  }
331 
332  return nullptr;
333 }
334 
337 {
339  "Address not pointing to a valid redistributor\n");
340 
341  const Addr daddr = addr - redistRange.start();
342  const uint32_t redistributor_id = daddr / redistSize;
343 
344  panic_if(redistributor_id >= redistributors.size(),
345  "Invalid redistributor_id!");
346  panic_if(!redistributors[redistributor_id], "Redistributor is null!");
347 
348  return redistributors[redistributor_id];
349 }
350 
351 uint32_t
353 {
354  return distributor->read(daddr, 4, false);
355 }
356 
357 uint32_t
358 Gicv3::readRedistributor(const ArmISA::Affinity &aff, Addr daddr)
359 {
360  auto redistributor = getRedistributorByAffinity(aff);
361  assert(redistributor);
362  return redistributor->read(daddr, 4, false);
363 }
364 
365 RegVal
366 Gicv3::readCpu(const ArmISA::Affinity &aff, ArmISA::MiscRegIndex misc_reg)
367 {
368  auto cpu_interface = getCPUInterfaceByAffinity(aff);
369  assert(cpu_interface);
370  return cpu_interface->readMiscReg(misc_reg);
371 }
372 
373 void
375 {
376  distributor->write(daddr, data, sizeof(data), false);
377 }
378 
379 void
380 Gicv3::writeRedistributor(const ArmISA::Affinity &aff, Addr daddr, uint32_t data)
381 {
382  auto redistributor = getRedistributorByAffinity(aff);
383  assert(redistributor);
384  redistributor->write(daddr, data, sizeof(data), false);
385 }
386 
387 void
388 Gicv3::writeCpu(const ArmISA::Affinity &aff, ArmISA::MiscRegIndex misc_reg,
389  RegVal data)
390 {
391  auto cpu_interface = getCPUInterfaceByAffinity(aff);
392  assert(cpu_interface);
393  cpu_interface->setMiscReg(misc_reg, data);
394 }
395 
396 void
398 {
399  distributor->copy(from, to);
400  for (auto& redistributor : redistributors) {
401  redistributor->copy(from, to);
402  }
403  for (auto& cpu_interface : cpuInterfaces) {
404  cpu_interface->copy(from, to);
405  }
406 }
407 
408 void
410 {
411  distributor->serializeSection(cp, "distributor");
412 
413  for (uint32_t redistributor_id = 0;
414  redistributor_id < redistributors.size(); redistributor_id++)
415  redistributors[redistributor_id]->serializeSection(cp,
416  csprintf("redistributors.%i", redistributor_id));
417 
418  for (uint32_t cpu_interface_id = 0;
419  cpu_interface_id < cpuInterfaces.size(); cpu_interface_id++)
420  cpuInterfaces[cpu_interface_id]->serializeSection(cp,
421  csprintf("cpuInterface.%i", cpu_interface_id));
422 }
423 
424 void
426 {
427  getSystem()->setGIC(this);
428 
429  distributor->unserializeSection(cp, "distributor");
430 
431  for (uint32_t redistributor_id = 0;
432  redistributor_id < redistributors.size(); redistributor_id++)
433  redistributors[redistributor_id]->unserializeSection(cp,
434  csprintf("redistributors.%i", redistributor_id));
435 
436  for (uint32_t cpu_interface_id = 0;
437  cpu_interface_id < cpuInterfaces.size(); cpu_interface_id++)
438  cpuInterfaces[cpu_interface_id]->unserializeSection(cp,
439  csprintf("cpuInterface.%i", cpu_interface_id));
440 }
441 
442 } // namespace gem5
gem5::Gicv3::addrRanges
AddrRangeList addrRanges
Definition: gic_v3.hh:108
gem5::Gicv3::writeRedistributor
void writeRedistributor(const ArmISA::Affinity &aff, Addr daddr, uint32_t data) override
Definition: gic_v3.cc:380
gic_v3_cpu_interface.hh
gem5::BaseGic::getSystem
ArmSystem * getSystem() const
Definition: base_gic.hh:114
gem5::Gicv3Its::setGIC
void setGIC(Gicv3 *_gic)
Definition: gic_v3_its.cc:808
gic_v3_its.hh
gem5::AddrRange::start
Addr start() const
Get the start address of the range.
Definition: addr_range.hh:343
gem5::System::Threads::size
int size() const
Definition: system.hh:214
gem5::Gicv3Registers::copyDistRange
static void copyDistRange(Gicv3Registers *from, Gicv3Registers *to, Addr daddr, size_t size)
Definition: gic_v3.cc:115
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gic_v3_redistributor.hh
gem5::Packet::getUintX
uint64_t getUintX(ByteOrder endian) const
Get the data in the packet byte swapped from the specified endianness and zero-extended to 64 bits.
Definition: packet.cc:348
gem5::Gicv3Registers
Definition: gic_v3.hh:57
gem5::Gicv3::haveAsserted
bool haveAsserted(uint32_t cpu) const
Definition: gic_v3.cc:311
data
const char data[]
Definition: circlebuf.test.cc:48
gem5::Gicv3Registers::copyRedistRange
static void copyRedistRange(Gicv3Registers *from, Gicv3Registers *to, const ArmISA::Affinity &aff, Addr daddr, size_t size)
Definition: gic_v3.cc:105
gem5::RangeSize
AddrRange RangeSize(Addr start, Addr size)
Definition: addr_range.hh:815
gem5::Gicv3Redistributor::read
uint64_t read(Addr addr, size_t size, bool is_secure_access)
Definition: gic_v3_redistributor.cc:94
gem5::Gicv3Redistributor
Definition: gic_v3_redistributor.hh:55
gem5::Gicv3Distributor::init
void init()
Definition: gic_v3_distributor.cc:137
gem5::Gicv3::its
Gicv3Its * its
Definition: gic_v3.hh:105
gem5::Packet::req
RequestPtr req
A pointer to the original request.
Definition: packet.hh:374
gem5::AddrRange::contains
bool contains(const Addr &a) const
Determine if the range contains an address.
Definition: addr_range.hh:471
gem5::BaseGic::GicVersion::GIC_V3
@ GIC_V3
gem5::CheckpointIn
Definition: serialize.hh:68
sc_dt::int_type
int64 int_type
Definition: sc_nbdefs.hh:240
gem5::Serializable::serializeSection
void serializeSection(CheckpointOut &cp, const char *name) const
Serialize an object into a new section.
Definition: serialize.cc:74
gem5::Gicv3::getRedistributorByAddr
Gicv3Redistributor * getRedistributorByAddr(Addr address) const
Definition: gic_v3.cc:336
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:769
gem5::Gicv3::deassertAll
void deassertAll(uint32_t cpu)
Definition: gic_v3.cc:304
gem5::ArmISA::a
Bitfield< 8 > a
Definition: misc_types.hh:66
gem5::Gicv3::clearPPInt
void clearPPInt(uint32_t int_id, uint32_t cpu) override
Definition: gic_v3.cc:273
gem5::Packet::isSecure
bool isSecure() const
Definition: packet.hh:819
gem5::ArmISA::miscRegName
const char *const miscRegName[]
Definition: misc.hh:1273
gem5::Gicv3::Gicv3
Gicv3(const Params &p)
Definition: gic_v3.cc:131
gem5::csprintf
std::string csprintf(const char *format, const Args &...args)
Definition: cprintf.hh:161
gem5::Packet::makeAtomicResponse
void makeAtomicResponse()
Definition: packet.hh:1056
gem5::Gicv3Redistributor::write
void write(Addr addr, uint64_t data, size_t size, bool is_secure_access)
Definition: gic_v3_redistributor.cc:386
gem5::BaseGic::GicVersion::GIC_V4
@ GIC_V4
gem5::Gicv3::write
Tick write(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: gic_v3.cc:213
gem5::Gicv3::distRange
AddrRange distRange
Definition: gic_v3.hh:106
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:67
gem5::Gicv3::getRedistributorByAffinity
Gicv3Redistributor * getRedistributorByAffinity(const ArmISA::Affinity &aff) const
Definition: gic_v3.cc:324
gem5::Gicv3Registers::readRedistributor
virtual uint32_t readRedistributor(const ArmISA::Affinity &aff, Addr daddr)=0
gem5::Gicv3::read
Tick read(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: gic_v3.cc:176
gem5::Gicv3Registers::copyRedistRegister
static void copyRedistRegister(Gicv3Registers *from, Gicv3Registers *to, const ArmISA::Affinity &aff, Addr daddr)
Definition: gic_v3.cc:68
gem5::Gicv3Distributor::copy
void copy(Gicv3Registers *from, Gicv3Registers *to)
Definition: gic_v3_distributor.cc:1185
gem5::Gicv3::redistRange
AddrRange redistRange
Definition: gic_v3.hh:107
gem5::Gicv3::writeCpu
void writeCpu(const ArmISA::Affinity &aff, ArmISA::MiscRegIndex misc_reg, RegVal data) override
Definition: gic_v3.cc:388
gem5::Gicv3::sendPPInt
void sendPPInt(uint32_t int_id, uint32_t cpu) override
Interface call for private peripheral interrupts.
Definition: gic_v3.cc:264
packet.hh
gem5::Gicv3::readDistributor
uint32_t readDistributor(Addr daddr) override
Definition: gic_v3.cc:352
gem5::Gicv3::postInt
void postInt(uint32_t cpu, ArmISA::InterruptTypes int_type)
Definition: gic_v3.cc:282
gem5::Gicv3Distributor::write
void write(Addr addr, uint64_t data, size_t size, bool is_secure_access)
Definition: gic_v3_distributor.cc:514
gem5::Gicv3::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: gic_v3.cc:425
gem5::PowerISA::to
Bitfield< 25, 21 > to
Definition: types.hh:96
gem5::Gicv3::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: gic_v3.cc:409
gem5::Gicv3Redistributor::getCPUInterface
Gicv3CPUInterface * getCPUInterface() const
Definition: gic_v3_redistributor.hh:208
gem5::Gicv3Distributor::sendInt
void sendInt(uint32_t int_id)
Definition: gic_v3_distributor.cc:1008
gem5::BaseGic
Definition: base_gic.hh:72
gem5::Serializable::unserializeSection
void unserializeSection(CheckpointIn &cp, const char *name)
Unserialize an a child object.
Definition: serialize.cc:81
gem5::VegaISA::p
Bitfield< 54 > p
Definition: pagetable.hh:70
gem5::Gicv3::cpuInterfaces
std::vector< Gicv3CPUInterface * > cpuInterfaces
Definition: gic_v3.hh:104
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:291
gem5::Gicv3::init
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: gic_v3.cc:137
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::PioDevice::sys
System * sys
Definition: io_device.hh:105
gem5::Gicv3Redistributor::processorNumber
uint32_t processorNumber() const
Definition: gic_v3_redistributor.hh:214
gem5::Gicv3::distributor
Gicv3Distributor * distributor
Definition: gic_v3.hh:102
gem5::Gicv3Registers::readCpu
virtual RegVal readCpu(const ArmISA::Affinity &aff, ArmISA::MiscRegIndex misc_reg)=0
gem5::Gicv3::redistributors
std::vector< Gicv3Redistributor * > redistributors
Definition: gic_v3.hh:103
gem5::Gicv3::Gicv3Redistributor
friend class Gicv3Redistributor
Definition: gic_v3.hh:99
gem5::BaseGic::params
const Params & params() const
Definition: base_gic.cc:78
gem5::ArmISA::InterruptTypes
InterruptTypes
Definition: interrupts.hh:59
gem5::Gicv3Registers::copyCpuRegister
static void copyCpuRegister(Gicv3Registers *from, Gicv3Registers *to, const ArmISA::Affinity &aff, ArmISA::MiscRegIndex misc_reg)
Definition: gic_v3.cc:82
gem5::Gicv3::Gicv3CPUInterface
friend class Gicv3CPUInterface
Definition: gic_v3.hh:98
gem5::Gicv3Distributor::read
uint64_t read(Addr addr, size_t size, bool is_secure_access)
Definition: gic_v3_distributor.cc:142
gem5::BaseGic::init
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: base_gic.cc:71
gem5::BaseGic::Params
BaseGicParams Params
Definition: base_gic.hh:75
platform.hh
gem5::Gicv3::sendInt
void sendInt(uint32_t int_id) override
Post an interrupt from a device that is connected to the GIC.
Definition: gic_v3.cc:250
gem5::Gicv3::readCpu
RegVal readCpu(const ArmISA::Affinity &aff, ArmISA::MiscRegIndex misc_reg) override
Definition: gic_v3.cc:366
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ArmSystem::callClearStandByWfi
static void callClearStandByWfi(ThreadContext *tc)
Make a call to notify the power controller of STANDBYWFI deassertion.
Definition: system.cc:206
gem5::Gicv3Distributor::clearInt
void clearInt(uint32_t int_id)
Definition: gic_v3_distributor.cc:1020
gem5::ArmISA::MiscRegIndex
MiscRegIndex
Definition: misc.hh:59
packet_access.hh
gem5::BaseGic::GicVersion
GicVersion
Definition: base_gic.hh:76
gem5::Gicv3::getCPUInterfaceByAffinity
Gicv3CPUInterface * getCPUInterfaceByAffinity(const ArmISA::Affinity &aff) const
Definition: gic_v3.cc:318
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:204
gem5::Gicv3CPUInterface
Definition: gic_v3_cpu_interface.hh:58
base.hh
gem5::Gicv3Its
GICv3 ITS module.
Definition: gic_v3_its.hh:83
gem5::System::threads
Threads threads
Definition: system.hh:314
gem5::Gicv3::copyGicState
void copyGicState(Gicv3Registers *from, Gicv3Registers *to)
Definition: gic_v3.cc:397
gem5::Gicv3Registers::copyDistRegister
static void copyDistRegister(Gicv3Registers *from, Gicv3Registers *to, Addr daddr)
Definition: gic_v3.cc:58
gem5::Gicv3::Gicv3Distributor
friend class Gicv3Distributor
Definition: gic_v3.hh:100
gem5::ArmSystem::setGIC
void setGIC(BaseGic *gic)
Sets the pointer to the GIC.
Definition: system.hh:164
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::Gicv3::writeDistributor
void writeDistributor(Addr daddr, uint32_t data) override
Definition: gic_v3.cc:374
gem5::Gicv3::readRedistributor
uint32_t readRedistributor(const ArmISA::Affinity &aff, Addr daddr) override
Definition: gic_v3.cc:358
gem5::Gicv3::deassertInt
void deassertInt(uint32_t cpu, ArmISA::InterruptTypes int_type)
Definition: gic_v3.cc:297
gem5::Gicv3Registers::clearRedistRegister
static void clearRedistRegister(Gicv3Registers *to, const ArmISA::Affinity &aff, Addr daddr)
Definition: gic_v3.cc:98
gem5::Packet::getAddr
Addr getAddr() const
Definition: packet.hh:790
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::Gicv3Distributor::ADDR_RANGE_SIZE
static const uint32_t ADDR_RANGE_SIZE
Definition: gic_v3_distributor.hh:177
gem5::Gicv3::redistSize
uint64_t redistSize
Definition: gic_v3.hh:109
gem5::Packet::setUintX
void setUintX(uint64_t w, ByteOrder endian)
Set the value in the word w after truncating it to the length of the packet and then byteswapping it ...
Definition: packet.cc:357
gem5::Gicv3Registers::readDistributor
virtual uint32_t readDistributor(Addr daddr)=0
gic_v3_distributor.hh
gem5::ArmISA::Interrupt
Definition: faults.hh:594
gic_v3.hh
gem5::Packet::getSize
unsigned getSize() const
Definition: packet.hh:800
gem5::Gicv3::clearInt
void clearInt(uint32_t int_id) override
Clear an interrupt from a device that is connected to the GIC.
Definition: gic_v3.cc:257
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
gem5::Gicv3::supportsVersion
bool supportsVersion(GicVersion version) override
Check if version supported.
Definition: gic_v3.cc:290
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::Gicv3Registers::clearDistRange
static void clearDistRange(Gicv3Registers *to, Addr daddr, size_t size)
Definition: gic_v3.cc:124

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