gem5  v21.1.0.2
base.cc
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40 
47 
48 #include <cassert>
49 
50 #include "base/intmath.hh"
51 #include "mem/cache/base.hh"
52 #include "params/BasePrefetcher.hh"
53 #include "sim/system.hh"
54 
55 namespace gem5
56 {
57 
59 namespace prefetch
60 {
61 
63  : address(addr), pc(pkt->req->hasPC() ? pkt->req->getPC() : 0),
64  requestorId(pkt->req->requestorId()), validPC(pkt->req->hasPC()),
65  secure(pkt->isSecure()), size(pkt->req->getSize()), write(pkt->isWrite()),
66  paddress(pkt->req->getPaddr()), cacheMiss(miss)
67 {
68  unsigned int req_size = pkt->req->getSize();
69  if (!write && miss) {
70  data = nullptr;
71  } else {
72  data = new uint8_t[req_size];
73  Addr offset = pkt->req->getPaddr() - pkt->getAddr();
74  std::memcpy(data, &(pkt->getConstPtr<uint8_t>()[offset]), req_size);
75  }
76 }
77 
79  : address(addr), pc(pfi.pc), requestorId(pfi.requestorId),
80  validPC(pfi.validPC), secure(pfi.secure), size(pfi.size),
81  write(pfi.write), paddress(pfi.paddress), cacheMiss(pfi.cacheMiss),
82  data(nullptr)
83 {
84 }
85 
86 void
88 {
89  if (isFill) {
90  parent.notifyFill(pkt);
91  } else {
92  parent.probeNotify(pkt, miss);
93  }
94 }
95 
96 Base::Base(const BasePrefetcherParams &p)
97  : ClockedObject(p), listeners(), cache(nullptr), blkSize(p.block_size),
98  lBlkSize(floorLog2(blkSize)), onMiss(p.on_miss), onRead(p.on_read),
99  onWrite(p.on_write), onData(p.on_data), onInst(p.on_inst),
100  requestorId(p.sys->getRequestorId(this)),
101  pageBytes(p.sys->getPageBytes()),
102  prefetchOnAccess(p.prefetch_on_access),
103  prefetchOnPfHit(p.prefetch_on_pf_hit),
104  useVirtualAddresses(p.use_virtual_addresses),
106  usefulPrefetches(0), tlb(nullptr)
107 {
108 }
109 
110 void
112 {
113  assert(!cache);
114  cache = _cache;
115 
116  // If the cache has a different block size from the system's, save it
119 }
120 
122  : statistics::Group(parent),
123  ADD_STAT(demandMshrMisses, statistics::units::Count::get(),
124  "demands not covered by prefetchs"),
125  ADD_STAT(pfIssued, statistics::units::Count::get(),
126  "number of hwpf issued"),
127  ADD_STAT(pfUnused, statistics::units::Count::get(),
128  "number of HardPF blocks evicted w/o reference"),
129  ADD_STAT(pfUseful, statistics::units::Count::get(),
130  "number of useful prefetch"),
131  ADD_STAT(pfUsefulButMiss, statistics::units::Count::get(),
132  "number of hit on prefetch but cache block is not in an usable "
133  "state"),
134  ADD_STAT(accuracy, statistics::units::Count::get(),
135  "accuracy of the prefetcher"),
136  ADD_STAT(coverage, statistics::units::Count::get(),
137  "coverage brought by this prefetcher"),
138  ADD_STAT(pfHitInCache, statistics::units::Count::get(),
139  "number of prefetches hitting in cache"),
140  ADD_STAT(pfHitInMSHR, statistics::units::Count::get(),
141  "number of prefetches hitting in a MSHR"),
142  ADD_STAT(pfHitInWB, statistics::units::Count::get(),
143  "number of prefetches hit in the Write Buffer"),
144  ADD_STAT(pfLate, statistics::units::Count::get(),
145  "number of late prefetches (hitting in cache, MSHR or WB)")
146 {
147  using namespace statistics;
148 
150 
153 
156 
158 }
159 
160 bool
161 Base::observeAccess(const PacketPtr &pkt, bool miss) const
162 {
163  bool fetch = pkt->req->isInstFetch();
164  bool read = pkt->isRead();
165  bool inv = pkt->isInvalidate();
166 
167  if (!miss) {
168  if (prefetchOnPfHit)
169  return hasBeenPrefetched(pkt->getAddr(), pkt->isSecure());
170  if (!prefetchOnAccess)
171  return false;
172  }
173  if (pkt->req->isUncacheable()) return false;
174  if (fetch && !onInst) return false;
175  if (!fetch && !onData) return false;
176  if (!fetch && read && !onRead) return false;
177  if (!fetch && !read && !onWrite) return false;
178  if (!fetch && !read && inv) return false;
179  if (pkt->cmd == MemCmd::CleanEvict) return false;
180 
181  if (onMiss) {
182  return miss;
183  }
184 
185  return true;
186 }
187 
188 bool
189 Base::inCache(Addr addr, bool is_secure) const
190 {
191  return cache->inCache(addr, is_secure);
192 }
193 
194 bool
195 Base::inMissQueue(Addr addr, bool is_secure) const
196 {
197  return cache->inMissQueue(addr, is_secure);
198 }
199 
200 bool
201 Base::hasBeenPrefetched(Addr addr, bool is_secure) const
202 {
203  return cache->hasBeenPrefetched(addr, is_secure);
204 }
205 
206 bool
208 {
209  return roundDown(a, pageBytes) == roundDown(b, pageBytes);
210 }
211 
212 Addr
214 {
215  return a & ~((Addr)blkSize-1);
216 }
217 
218 Addr
220 {
221  return a >> lBlkSize;
222 }
223 
224 Addr
226 {
227  return roundDown(a, pageBytes);
228 }
229 
230 Addr
232 {
233  return a & (pageBytes - 1);
234 }
235 
236 Addr
238 {
239  return page + (blockIndex << lBlkSize);
240 }
241 
242 void
243 Base::probeNotify(const PacketPtr &pkt, bool miss)
244 {
245  // Don't notify prefetcher on SWPrefetch, cache maintenance
246  // operations or for writes that we are coaslescing.
247  if (pkt->cmd.isSWPrefetch()) return;
248  if (pkt->req->isCacheMaintenance()) return;
249  if (pkt->isWrite() && cache != nullptr && cache->coalesce()) return;
250  if (!pkt->req->hasPaddr()) {
251  panic("Request must have a physical address");
252  }
253 
254  if (hasBeenPrefetched(pkt->getAddr(), pkt->isSecure())) {
255  usefulPrefetches += 1;
257  if (miss)
258  // This case happens when a demand hits on a prefetched line
259  // that's not in the requested coherency state.
261  }
262 
263  // Verify this access type is observed by prefetcher
264  if (observeAccess(pkt, miss)) {
265  if (useVirtualAddresses && pkt->req->hasVaddr()) {
266  PrefetchInfo pfi(pkt, pkt->req->getVaddr(), miss);
267  notify(pkt, pfi);
268  } else if (!useVirtualAddresses) {
269  PrefetchInfo pfi(pkt, pkt->req->getPaddr(), miss);
270  notify(pkt, pfi);
271  }
272  }
273 }
274 
275 void
277 {
283  if (listeners.empty() && cache != nullptr) {
285  listeners.push_back(new PrefetchListener(*this, pm, "Miss", false,
286  true));
287  listeners.push_back(new PrefetchListener(*this, pm, "Fill", true,
288  false));
289  listeners.push_back(new PrefetchListener(*this, pm, "Hit", false,
290  false));
291  }
292 }
293 
294 void
296 {
297  ProbeManager *pm(obj->getProbeManager());
298  listeners.push_back(new PrefetchListener(*this, pm, name));
299 }
300 
301 void
303 {
304  fatal_if(tlb != nullptr, "Only one TLB can be registered");
305  tlb = t;
306 }
307 
308 } // namespace prefetch
309 } // namespace gem5
gem5::prefetch::Base::StatGroup::demandMshrMisses
statistics::Scalar demandMshrMisses
Definition: base.hh:334
gem5::prefetch::Base::prefetchOnAccess
const bool prefetchOnAccess
Prefetch on every access, not just misses.
Definition: base.hh:296
gem5::prefetch::Base::StatGroup::pfUsefulButMiss
statistics::Scalar pfUsefulButMiss
The number of times there is a hit on prefetch but cache block is not in an usable state.
Definition: base.hh:343
gem5::prefetch::Base::blockIndex
Addr blockIndex(Addr a) const
Determine the address of a at block granularity.
Definition: base.cc:219
gem5::prefetch::Base::useVirtualAddresses
const bool useVirtualAddresses
Use Virtual Addresses for prefetching.
Definition: base.hh:302
gem5::prefetch::Base::pageOffset
Addr pageOffset(Addr a) const
Determine the page-offset of a
Definition: base.cc:231
gem5::prefetch::Base::hasBeenPrefetched
bool hasBeenPrefetched(Addr addr, bool is_secure) const
Definition: base.cc:201
base.hh
gem5::prefetch::Base::PrefetchInfo::write
bool write
Whether this event comes from a write request.
Definition: base.hh:112
system.hh
gem5::MemCmd::CleanEvict
@ CleanEvict
Definition: packet.hh:95
data
const char data[]
Definition: circlebuf.test.cc:48
gem5::prefetch::Base::StatGroup::StatGroup
StatGroup(statistics::Group *parent)
Definition: base.cc:121
gem5::prefetch::Base::setCache
virtual void setCache(BaseCache *_cache)
Definition: base.cc:111
gem5::prefetch::Base::StatGroup::pfIssued
statistics::Scalar pfIssued
Definition: base.hh:335
gem5::Packet::req
RequestPtr req
A pointer to the original request.
Definition: packet.hh:366
gem5::BaseCache::coalesce
bool coalesce() const
Checks if the cache is coalescing writes.
Definition: base.cc:1731
gem5::prefetch::Base::PrefetchInfo::data
uint8_t * data
Pointer to the associated request data.
Definition: base.hh:118
gem5::statistics::nozero
const FlagsType nozero
Don't print if this is zero.
Definition: info.hh:68
gem5::prefetch::Base::addEventProbe
void addEventProbe(SimObject *obj, const char *name)
Add a SimObject and a probe name to listen events from.
Definition: base.cc:295
gem5::prefetch::Base::listeners
std::vector< PrefetchListener * > listeners
Definition: base.hh:89
gem5::ArmISA::a
Bitfield< 8 > a
Definition: misc_types.hh:65
gem5::Packet::isWrite
bool isWrite() const
Definition: packet.hh:583
gem5::prefetch::Base::pageAddress
Addr pageAddress(Addr a) const
Determine the address of the page in which a lays.
Definition: base.cc:225
gem5::Packet::isSecure
bool isSecure() const
Definition: packet.hh:810
gem5::prefetch::Base::inMissQueue
bool inMissQueue(Addr addr, bool is_secure) const
Determine if address is in cache miss queue.
Definition: base.cc:195
gem5::prefetch::Base::Base
Base(const BasePrefetcherParams &p)
Definition: base.cc:96
gem5::prefetch::Base::blockAddress
Addr blockAddress(Addr a) const
Determine the address of the block in which a lays.
Definition: base.cc:213
gem5::prefetch::Base::requestorId
const RequestorID requestorId
Request id for prefetches.
Definition: base.hh:291
gem5::prefetch::Base::onRead
const bool onRead
Consult prefetcher on reads?
Definition: base.hh:279
gem5::prefetch::Base::StatGroup::pfHitInWB
statistics::Scalar pfHitInWB
The number of times a HW-prefetch hits in the Write Buffer (WB).
Definition: base.hh:355
gem5::prefetch::Base::observeAccess
bool observeAccess(const PacketPtr &pkt, bool miss) const
Determine if this access should be observed.
Definition: base.cc:161
gem5::prefetch::Base::onInst
const bool onInst
Consult prefetcher on instruction accesses?
Definition: base.hh:288
gem5::prefetch::Base::StatGroup::pfUnused
statistics::Scalar pfUnused
The number of times a HW-prefetched block is evicted w/o reference.
Definition: base.hh:338
gem5::prefetch::Base::samePage
bool samePage(Addr a, Addr b) const
Determine if addresses are on the same page.
Definition: base.cc:207
gem5::Packet::isRead
bool isRead() const
Definition: packet.hh:582
gem5::prefetch::Base::onMiss
const bool onMiss
Only consult prefetcher on cache misses?
Definition: base.hh:276
base.hh
gem5::ArmISA::b
Bitfield< 7 > b
Definition: misc_types.hh:381
gem5::prefetch::Base::pageBytes
const Addr pageBytes
Definition: base.hh:293
gem5::Named::name
virtual std::string name() const
Definition: named.hh:47
gem5::BaseCache
A basic cache interface.
Definition: base.hh:95
ADD_STAT
#define ADD_STAT(n,...)
Convenience macro to add a stat to a statistics group.
Definition: group.hh:75
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::prefetch::Base::usefulPrefetches
uint64_t usefulPrefetches
Total prefetches that has been useful.
Definition: base.hh:365
gem5::BaseCache::hasBeenPrefetched
bool hasBeenPrefetched(Addr addr, bool is_secure) const
Definition: base.hh:1274
gem5::prefetch::Base::PrefetchInfo::PrefetchInfo
PrefetchInfo(PacketPtr pkt, Addr addr, bool miss)
Constructs a PrefetchInfo using a PacketPtr.
Definition: base.cc:62
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::prefetch::Base::StatGroup::pfLate
statistics::Formula pfLate
The number of times a HW-prefetch is late (hit in cache, MSHR, WB).
Definition: base.hh:359
gem5::Packet::getConstPtr
const T * getConstPtr() const
Definition: packet.hh:1193
gem5::BaseTLB
Definition: tlb.hh:54
gem5::ArmISA::offset
Bitfield< 23, 0 > offset
Definition: types.hh:144
gem5::prefetch::Base::probeNotify
void probeNotify(const PacketPtr &pkt, bool miss)
Process a notification event from the ProbeListener.
Definition: base.cc:243
gem5::prefetch::Base::onData
const bool onData
Consult prefetcher on data accesses?
Definition: base.hh:285
gem5::prefetch::Base::StatGroup::coverage
statistics::Formula coverage
Definition: base.hh:345
gem5::roundDown
static constexpr T roundDown(const T &val, const U &align)
This function is used to align addresses in memory.
Definition: intmath.hh:279
gem5::SimObject
Abstract superclass for simulation objects.
Definition: sim_object.hh:146
gem5::Packet::cmd
MemCmd cmd
The command field of the packet.
Definition: packet.hh:361
gem5::ArmISA::t
Bitfield< 5 > t
Definition: misc_types.hh:70
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::GEM5_DEPRECATED_NAMESPACE
GEM5_DEPRECATED_NAMESPACE(GuestABI, guest_abi)
gem5::BaseCache::getBlockSize
unsigned getBlockSize() const
Query block size of a cache.
Definition: base.hh:1157
gem5::BaseCache::inMissQueue
bool inMissQueue(Addr addr, bool is_secure) const
Definition: base.hh:1283
gem5::ArmISA::isSecure
bool isSecure(ThreadContext *tc)
Definition: utility.cc:72
gem5::ClockedObject
The ClockedObject class extends the SimObject with a clock and accessor functions to relate ticks to ...
Definition: clocked_object.hh:234
gem5::ProbeManager
ProbeManager is a conduit class that lives on each SimObject, and is used to match up probe listeners...
Definition: probe.hh:163
gem5::SimObject::getProbeManager
ProbeManager * getProbeManager()
Get the probe manager for this object.
Definition: sim_object.cc:120
gem5::prefetch::Base::prefetchStats
gem5::prefetch::Base::StatGroup prefetchStats
gem5::prefetch::Base::PrefetchListener::notify
void notify(const PacketPtr &pkt) override
Definition: base.cc:87
gem5::prefetch::Base::issuedPrefetches
uint64_t issuedPrefetches
Total prefetches issued.
Definition: base.hh:363
gem5::prefetch::Base::lBlkSize
unsigned lBlkSize
log_2(block size of the parent cache).
Definition: base.hh:273
gem5::prefetch::Base::regProbeListeners
void regProbeListeners() override
Register probe points for this object.
Definition: base.cc:276
gem5::MemCmd::isSWPrefetch
bool isSWPrefetch() const
Definition: packet.hh:242
gem5::prefetch::Base::StatGroup::pfUseful
statistics::Scalar pfUseful
The number of times a HW-prefetch is useful.
Definition: base.hh:340
gem5::X86ISA::inv
Bitfield< 23 > inv
Definition: misc.hh:814
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::floorLog2
static constexpr std::enable_if_t< std::is_integral< T >::value, int > floorLog2(T x)
Definition: intmath.hh:59
gem5::prefetch::Base::StatGroup::accuracy
statistics::Formula accuracy
Definition: base.hh:344
gem5::statistics::Group
Statistics container.
Definition: group.hh:93
gem5::prefetch::Base::cache
BaseCache * cache
Pointr to the parent cache.
Definition: base.hh:267
gem5::prefetch::Base::prefetchOnPfHit
const bool prefetchOnPfHit
Prefetch on hit on prefetched lines.
Definition: base.hh:299
gem5::BaseCache::inCache
bool inCache(Addr addr, bool is_secure) const
Definition: base.hh:1270
gem5::prefetch::Base::blkSize
unsigned blkSize
The block size of the parent cache.
Definition: base.hh:270
gem5::prefetch::Base::tlb
BaseTLB * tlb
Registered tlb for address translations.
Definition: base.hh:368
gem5::context_switch_task_id::Prefetcher
@ Prefetcher
Definition: request.hh:83
gem5::statistics::DataWrap::flags
Derived & flags(Flags _flags)
Set the flags and marks this stat to print at the end of simulation.
Definition: statistics.hh:355
gem5::prefetch::Base::inCache
bool inCache(Addr addr, bool is_secure) const
Determine if address is in cache.
Definition: base.cc:189
gem5::Packet::getAddr
Addr getAddr() const
Definition: packet.hh:781
intmath.hh
gem5::prefetch::Base::pageIthBlockAddress
Addr pageIthBlockAddress(Addr page, uint32_t i) const
Build the address of the i-th block inside the page.
Definition: base.cc:237
fatal_if
#define fatal_if(cond,...)
Conditional fatal macro that checks the supplied condition and only causes a fatal error if the condi...
Definition: logging.hh:225
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::statistics::total
const FlagsType total
Print the total.
Definition: info.hh:60
gem5::prefetch::Base::StatGroup::pfHitInMSHR
statistics::Scalar pfHitInMSHR
The number of times a HW-prefetch hits in a MSHR.
Definition: base.hh:351
gem5::prefetch::Base::PrefetchInfo
Class containing the information needed by the prefetch to train and generate new prefetch requests.
Definition: base.hh:97
gem5::prefetch::Base::onWrite
const bool onWrite
Consult prefetcher on reads?
Definition: base.hh:282
gem5::prefetch::Base::StatGroup::pfHitInCache
statistics::Scalar pfHitInCache
The number of times a HW-prefetch hits in cache.
Definition: base.hh:348
gem5::Packet::isInvalidate
bool isInvalidate() const
Definition: packet.hh:598
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::prefetch::Base::addTLB
void addTLB(BaseTLB *tlb)
Add a BaseTLB object to be used whenever a translation is needed.
Definition: base.cc:302
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::prefetch::Base::PrefetchListener
Definition: base.hh:74
gem5::prefetch::Base::notify
virtual void notify(const PacketPtr &pkt, const PrefetchInfo &pfi)=0
Notify prefetcher of cache access (may be any access or just misses, depending on cache parameters....

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