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52 #include "params/BasePrefetcher.hh"
63 : address(
addr),
pc(pkt->req->hasPC() ? pkt->req->getPC() : 0),
64 requestorId(pkt->req->requestorId()), validPC(pkt->req->hasPC()),
65 secure(pkt->
isSecure()), size(pkt->req->getSize()), write(pkt->isWrite()),
66 paddress(pkt->req->getPaddr()), cacheMiss(miss)
68 unsigned int req_size = pkt->
req->getSize();
72 data =
new uint8_t[req_size];
80 validPC(pfi.validPC), secure(pfi.secure), size(pfi.size),
81 write(pfi.write), paddress(pfi.paddress), cacheMiss(pfi.cacheMiss),
90 parent.notifyFill(pkt);
92 parent.probeNotify(pkt, miss);
122 : statistics::
Group(parent),
123 ADD_STAT(demandMshrMisses, statistics::units::Count::get(),
124 "demands not covered by prefetchs"),
125 ADD_STAT(pfIssued, statistics::units::Count::get(),
126 "number of hwpf issued"),
127 ADD_STAT(pfUnused, statistics::units::Count::get(),
128 "number of HardPF blocks evicted w/o reference"),
129 ADD_STAT(pfUseful, statistics::units::Count::get(),
130 "number of useful prefetch"),
131 ADD_STAT(pfUsefulButMiss, statistics::units::Count::get(),
132 "number of hit on prefetch but cache block is not in an usable "
134 ADD_STAT(accuracy, statistics::units::Count::get(),
135 "accuracy of the prefetcher"),
136 ADD_STAT(coverage, statistics::units::Count::get(),
137 "coverage brought by this prefetcher"),
138 ADD_STAT(pfHitInCache, statistics::units::Count::get(),
139 "number of prefetches hitting in cache"),
140 ADD_STAT(pfHitInMSHR, statistics::units::Count::get(),
141 "number of prefetches hitting in a MSHR"),
142 ADD_STAT(pfHitInWB, statistics::units::Count::get(),
143 "number of prefetches hit in the Write Buffer"),
144 ADD_STAT(pfLate, statistics::units::Count::get(),
145 "number of late prefetches (hitting in cache, MSHR or WB)")
147 using namespace statistics;
163 bool fetch = pkt->
req->isInstFetch();
164 bool read = pkt->
isRead();
173 if (pkt->
req->isUncacheable())
return false;
174 if (fetch && !
onInst)
return false;
175 if (!fetch && !
onData)
return false;
176 if (!fetch && read && !
onRead)
return false;
177 if (!fetch && !read && !
onWrite)
return false;
178 if (!fetch && !read &&
inv)
return false;
248 if (pkt->
req->isCacheMaintenance())
return;
250 if (!pkt->
req->hasPaddr()) {
251 panic(
"Request must have a physical address");
304 fatal_if(
tlb !=
nullptr,
"Only one TLB can be registered");
statistics::Scalar demandMshrMisses
const bool prefetchOnAccess
Prefetch on every access, not just misses.
statistics::Scalar pfUsefulButMiss
The number of times there is a hit on prefetch but cache block is not in an usable state.
Addr blockIndex(Addr a) const
Determine the address of a at block granularity.
const bool useVirtualAddresses
Use Virtual Addresses for prefetching.
Addr pageOffset(Addr a) const
Determine the page-offset of a
bool hasBeenPrefetched(Addr addr, bool is_secure) const
bool write
Whether this event comes from a write request.
StatGroup(statistics::Group *parent)
virtual void setCache(BaseCache *_cache)
statistics::Scalar pfIssued
RequestPtr req
A pointer to the original request.
bool coalesce() const
Checks if the cache is coalescing writes.
uint8_t * data
Pointer to the associated request data.
const FlagsType nozero
Don't print if this is zero.
void addEventProbe(SimObject *obj, const char *name)
Add a SimObject and a probe name to listen events from.
std::vector< PrefetchListener * > listeners
static constexpr std::enable_if_t< std::is_integral_v< T >, int > floorLog2(T x)
Addr pageAddress(Addr a) const
Determine the address of the page in which a lays.
bool inMissQueue(Addr addr, bool is_secure) const
Determine if address is in cache miss queue.
Base(const BasePrefetcherParams &p)
Addr blockAddress(Addr a) const
Determine the address of the block in which a lays.
const RequestorID requestorId
Request id for prefetches.
const bool onRead
Consult prefetcher on reads?
statistics::Scalar pfHitInWB
The number of times a HW-prefetch hits in the Write Buffer (WB).
bool observeAccess(const PacketPtr &pkt, bool miss) const
Determine if this access should be observed.
const bool onInst
Consult prefetcher on instruction accesses?
statistics::Scalar pfUnused
The number of times a HW-prefetched block is evicted w/o reference.
bool samePage(Addr a, Addr b) const
Determine if addresses are on the same page.
const bool onMiss
Only consult prefetcher on cache misses?
virtual std::string name() const
#define ADD_STAT(n,...)
Convenience macro to add a stat to a statistics group.
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
uint64_t usefulPrefetches
Total prefetches that has been useful.
bool hasBeenPrefetched(Addr addr, bool is_secure) const
PrefetchInfo(PacketPtr pkt, Addr addr, bool miss)
Constructs a PrefetchInfo using a PacketPtr.
statistics::Formula pfLate
The number of times a HW-prefetch is late (hit in cache, MSHR, WB).
const T * getConstPtr() const
void probeNotify(const PacketPtr &pkt, bool miss)
Process a notification event from the ProbeListener.
const bool onData
Consult prefetcher on data accesses?
statistics::Formula coverage
static constexpr T roundDown(const T &val, const U &align)
This function is used to align addresses in memory.
Abstract superclass for simulation objects.
MemCmd cmd
The command field of the packet.
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
GEM5_DEPRECATED_NAMESPACE(GuestABI, guest_abi)
unsigned getBlockSize() const
Query block size of a cache.
bool inMissQueue(Addr addr, bool is_secure) const
bool isSecure(ThreadContext *tc)
The ClockedObject class extends the SimObject with a clock and accessor functions to relate ticks to ...
ProbeManager is a conduit class that lives on each SimObject, and is used to match up probe listeners...
ProbeManager * getProbeManager()
Get the probe manager for this object.
gem5::prefetch::Base::StatGroup prefetchStats
void notify(const PacketPtr &pkt) override
uint64_t issuedPrefetches
Total prefetches issued.
unsigned lBlkSize
log_2(block size of the parent cache).
void regProbeListeners() override
Register probe points for this object.
bool isSWPrefetch() const
statistics::Scalar pfUseful
The number of times a HW-prefetch is useful.
statistics::Formula accuracy
BaseCache * cache
Pointr to the parent cache.
const bool prefetchOnPfHit
Prefetch on hit on prefetched lines.
bool inCache(Addr addr, bool is_secure) const
unsigned blkSize
The block size of the parent cache.
BaseTLB * tlb
Registered tlb for address translations.
Derived & flags(Flags _flags)
Set the flags and marks this stat to print at the end of simulation.
bool inCache(Addr addr, bool is_secure) const
Determine if address is in cache.
Addr pageIthBlockAddress(Addr page, uint32_t i) const
Build the address of the i-th block inside the page.
#define fatal_if(cond,...)
Conditional fatal macro that checks the supplied condition and only causes a fatal error if the condi...
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
const FlagsType total
Print the total.
statistics::Scalar pfHitInMSHR
The number of times a HW-prefetch hits in a MSHR.
Class containing the information needed by the prefetch to train and generate new prefetch requests.
const bool onWrite
Consult prefetcher on reads?
statistics::Scalar pfHitInCache
The number of times a HW-prefetch hits in cache.
bool isInvalidate() const
#define panic(...)
This implements a cprintf based panic() function.
void addTLB(BaseTLB *tlb)
Add a BaseTLB object to be used whenever a translation is needed.
virtual void notify(const PacketPtr &pkt, const PrefetchInfo &pfi)=0
Notify prefetcher of cache access (may be any access or just misses, depending on cache parameters....
Generated on Wed May 4 2022 12:13:52 for gem5 by doxygen 1.8.17