52 #include "params/BasePrefetcher.hh"
63 : address(
addr),
pc(pkt->req->hasPC() ? pkt->req->getPC() : 0),
64 requestorId(pkt->req->requestorId()), validPC(pkt->req->hasPC()),
65 secure(pkt->
isSecure()), size(pkt->req->getSize()), write(pkt->isWrite()),
66 paddress(pkt->req->getPaddr()), cacheMiss(miss)
68 unsigned int req_size = pkt->
req->getSize();
72 data =
new uint8_t[req_size];
80 validPC(pfi.validPC), secure(pfi.secure), size(pfi.size),
81 write(pfi.write), paddress(pfi.paddress), cacheMiss(pfi.cacheMiss),
90 parent.notifyFill(pkt);
92 parent.probeNotify(pkt, miss);
122 : statistics::
Group(parent),
124 "demands not covered by prefetchs"),
126 "number of hwpf issued"),
128 "number of HardPF blocks evicted w/o reference"),
130 "number of useful prefetch"),
132 "number of hit on prefetch but cache block is not in an usable "
135 "accuracy of the prefetcher"),
137 "coverage brought by this prefetcher"),
139 "number of prefetches hitting in cache"),
141 "number of prefetches hitting in a MSHR"),
143 "number of prefetches hit in the Write Buffer"),
145 "number of late prefetches (hitting in cache, MSHR or WB)")
147 using namespace statistics;
163 bool fetch = pkt->
req->isInstFetch();
164 bool read = pkt->
isRead();
173 if (pkt->
req->isUncacheable())
return false;
174 if (fetch && !
onInst)
return false;
175 if (!fetch && !
onData)
return false;
176 if (!fetch && read && !
onRead)
return false;
177 if (!fetch && !read && !
onWrite)
return false;
178 if (!fetch && !read &&
inv)
return false;
248 if (pkt->
req->isCacheMaintenance())
return;
250 if (!pkt->
req->hasPaddr()) {
251 panic(
"Request must have a physical address");
304 fatal_if(
tlb !=
nullptr,
"Only one TLB can be registered");
bool inMissQueue(Addr addr, bool is_secure) const
bool hasBeenPrefetched(Addr addr, bool is_secure) const
unsigned getBlockSize() const
Query block size of a cache.
bool inCache(Addr addr, bool is_secure) const
bool coalesce() const
Checks if the cache is coalescing writes.
The ClockedObject class extends the SimObject with a clock and accessor functions to relate ticks to ...
bool isSWPrefetch() const
virtual std::string name() const
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
RequestPtr req
A pointer to the original request.
const T * getConstPtr() const
MemCmd cmd
The command field of the packet.
bool isInvalidate() const
ProbeManager is a conduit class that lives on each SimObject, and is used to match up probe listeners...
Abstract superclass for simulation objects.
Class containing the information needed by the prefetch to train and generate new prefetch requests.
PrefetchInfo(PacketPtr pkt, Addr addr, bool miss)
Constructs a PrefetchInfo using a PacketPtr.
bool write
Whether this event comes from a write request.
uint8_t * data
Pointer to the associated request data.
void notify(const PacketPtr &pkt) override
Base(const BasePrefetcherParams &p)
const bool useVirtualAddresses
Use Virtual Addresses for prefetching.
void addTLB(BaseTLB *tlb)
Add a BaseTLB object to be used whenever a translation is needed.
const bool prefetchOnAccess
Prefetch on every access, not just misses.
const bool onRead
Consult prefetcher on reads?
unsigned blkSize
The block size of the parent cache.
uint64_t issuedPrefetches
Total prefetches issued.
bool observeAccess(const PacketPtr &pkt, bool miss) const
Determine if this access should be observed.
bool inCache(Addr addr, bool is_secure) const
Determine if address is in cache.
void addEventProbe(SimObject *obj, const char *name)
Add a SimObject and a probe name to listen events from.
const RequestorID requestorId
Request id for prefetches.
std::vector< PrefetchListener * > listeners
BaseTLB * tlb
Registered tlb for address translations.
void regProbeListeners() override
Register probe points for this object.
Addr pageAddress(Addr a) const
Determine the address of the page in which a lays.
bool inMissQueue(Addr addr, bool is_secure) const
Determine if address is in cache miss queue.
bool hasBeenPrefetched(Addr addr, bool is_secure) const
const bool onInst
Consult prefetcher on instruction accesses?
uint64_t usefulPrefetches
Total prefetches that has been useful.
gem5::prefetch::Base::StatGroup prefetchStats
Addr pageIthBlockAddress(Addr page, uint32_t i) const
Build the address of the i-th block inside the page.
BaseCache * cache
Pointr to the parent cache.
Addr pageOffset(Addr a) const
Determine the page-offset of a
virtual void setCache(BaseCache *_cache)
const bool onData
Consult prefetcher on data accesses?
const bool prefetchOnPfHit
Prefetch on hit on prefetched lines.
void probeNotify(const PacketPtr &pkt, bool miss)
Process a notification event from the ProbeListener.
const bool onWrite
Consult prefetcher on reads?
virtual void notify(const PacketPtr &pkt, const PrefetchInfo &pfi)=0
Notify prefetcher of cache access (may be any access or just misses, depending on cache parameters....
unsigned lBlkSize
log_2(block size of the parent cache).
Addr blockIndex(Addr a) const
Determine the address of a at block granularity.
Addr blockAddress(Addr a) const
Determine the address of the block in which a lays.
const bool onMiss
Only consult prefetcher on cache misses?
bool samePage(Addr a, Addr b) const
Determine if addresses are on the same page.
Derived & flags(Flags _flags)
Set the flags and marks this stat to print at the end of simulation.
#define ADD_STAT(n,...)
Convenience macro to add a stat to a statistics group.
static constexpr std::enable_if_t< std::is_integral_v< T >, int > floorLog2(T x)
static constexpr T roundDown(const T &val, const U &align)
This function is used to align addresses in memory.
#define panic(...)
This implements a cprintf based panic() function.
#define fatal_if(cond,...)
Conditional fatal macro that checks the supplied condition and only causes a fatal error if the condi...
ProbeManager * getProbeManager()
Get the probe manager for this object.
Declares a basic cache interface BaseCache.
Miss and writeback queue declarations.
bool isSecure(ThreadContext *tc)
const FlagsType nozero
Don't print if this is zero.
const FlagsType total
Print the total.
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
GEM5_DEPRECATED_NAMESPACE(GuestABI, guest_abi)
statistics::Formula accuracy
statistics::Scalar pfUsefulButMiss
The number of times there is a hit on prefetch but cache block is not in an usable state.
statistics::Scalar pfIssued
statistics::Scalar pfUseful
The number of times a HW-prefetch is useful.
statistics::Scalar pfHitInWB
The number of times a HW-prefetch hits in the Write Buffer (WB).
statistics::Scalar pfHitInMSHR
The number of times a HW-prefetch hits in a MSHR.
statistics::Formula pfLate
The number of times a HW-prefetch is late (hit in cache, MSHR, WB).
statistics::Scalar pfUnused
The number of times a HW-prefetched block is evicted w/o reference.
statistics::Scalar pfHitInCache
The number of times a HW-prefetch hits in cache.
statistics::Scalar demandMshrMisses
StatGroup(statistics::Group *parent)
statistics::Formula coverage