gem5  v21.1.0.2
sve_macromem.hh
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37 
38 #ifndef __ARCH_ARM_SVE_MACROMEM_HH__
39 #define __ARCH_ARM_SVE_MACROMEM_HH__
40 
41 #include "arch/arm/generated/decoder.hh"
43 
44 namespace gem5
45 {
46 
47 namespace ArmISA {
48 
49 template <typename Element,
50  template <typename> class MicroopLdMemType,
51  template <typename> class MicroopDeIntrlvType>
52 class SveLdStructSS : public PredMacroOp
53 {
54  protected:
55  IntRegIndex dest;
56  IntRegIndex gp;
57  IntRegIndex base;
58  IntRegIndex offset;
59  uint8_t numregs;
60 
61  public:
62  SveLdStructSS(const char* mnem, ExtMachInst machInst, OpClass __opClass,
63  IntRegIndex _dest, IntRegIndex _gp, IntRegIndex _base,
64  IntRegIndex _offset, uint8_t _numregs)
65  : PredMacroOp(mnem, machInst, __opClass),
66  dest(_dest), gp(_gp), base(_base), offset(_offset), numregs(_numregs)
67  {
68  numMicroops = numregs * 2;
69 
71 
72  for (int i = 0; i < numregs; ++i) {
73  microOps[i] = new MicroopLdMemType<Element>(
74  mnem, machInst, static_cast<IntRegIndex>(INTRLVREG0 + i),
75  _gp, _base, _offset, _numregs, i);
76  }
77  for (int i = 0; i < numregs; ++i) {
78  microOps[i + numregs] = new MicroopDeIntrlvType<Element>(
79  mnem, machInst, static_cast<IntRegIndex>((_dest + i) % 32),
80  _numregs, i, this);
81  }
82 
85 
86  for (StaticInstPtr *uop = microOps; !(*uop)->isLastMicroop(); uop++) {
87  (*uop)->setDelayedCommit();
88  }
89  }
90 
91  Fault
92  execute(ExecContext *, Trace::InstRecord *) const override
93  {
94  panic("Execute method called when it shouldn't!");
95  return NoFault;
96  }
97 
98  std::string
100  const loader::SymbolTable *symtab) const override
101  {
102  std::stringstream ss;
103  printMnemonic(ss, "", false);
104  ccprintf(ss, "{");
105  for (int i = 0; i < numregs; ++i) {
106  printVecReg(ss, (dest + i) % 32, true);
107  if (i < numregs - 1)
108  ccprintf(ss, ", ");
109  }
110  ccprintf(ss, "}, ");
112  ccprintf(ss, "/z, [");
113  printIntReg(ss, base);
114  ccprintf(ss, ", ");
116  ccprintf(ss, "]");
117  return ss.str();
118  }
119 };
120 
121 template <typename Element,
122  template <typename> class MicroopStMemType,
123  template <typename> class MicroopIntrlvType>
125 {
126  protected:
127  IntRegIndex dest;
128  IntRegIndex gp;
129  IntRegIndex base;
130  IntRegIndex offset;
131  uint8_t numregs;
132 
133  public:
134  SveStStructSS(const char* mnem, ExtMachInst machInst, OpClass __opClass,
135  IntRegIndex _dest, IntRegIndex _gp, IntRegIndex _base,
136  IntRegIndex _offset, uint8_t _numregs)
137  : PredMacroOp(mnem, machInst, __opClass),
138  dest(_dest), gp(_gp), base(_base), offset(_offset), numregs(_numregs)
139  {
140  numMicroops = numregs * 2;
141 
143 
144  for (int i = 0; i < numregs; ++i) {
145  microOps[i] = new MicroopIntrlvType<Element>(
146  mnem, machInst, static_cast<IntRegIndex>(INTRLVREG0 + i),
147  _dest, _numregs, i, this);
148  }
149 
150  for (int i = 0; i < numregs; ++i) {
151  microOps[i + numregs] = new MicroopStMemType<Element>(
152  mnem, machInst, static_cast<IntRegIndex>(INTRLVREG0 + i),
153  _gp, _base, _offset, _numregs, i);
154  }
155 
158 
159  for (StaticInstPtr *uop = microOps; !(*uop)->isLastMicroop(); uop++) {
160  (*uop)->setDelayedCommit();
161  }
162  }
163 
164  Fault
165  execute(ExecContext *, Trace::InstRecord *) const override
166  {
167  panic("Execute method called when it shouldn't!");
168  return NoFault;
169  }
170 
171  std::string
173  const loader::SymbolTable *symtab) const override
174  {
175  std::stringstream ss;
176  printMnemonic(ss, "", false);
177  ccprintf(ss, "{");
178  for (int i = 0; i < numregs; ++i) {
179  printVecReg(ss, (dest + i) % 32, true);
180  if (i < numregs - 1)
181  ccprintf(ss, ", ");
182  }
183  ccprintf(ss, "}, ");
185  ccprintf(ss, ", [");
186  printIntReg(ss, base);
187  ccprintf(ss, ", ");
189  ccprintf(ss, "]");
190  return ss.str();
191  }
192 };
193 
194 
195 template <typename Element,
196  template <typename> class MicroopLdMemType,
197  template <typename> class MicroopDeIntrlvType>
199 {
200  protected:
201  IntRegIndex dest;
202  IntRegIndex gp;
203  IntRegIndex base;
204  int64_t imm;
205  uint8_t numregs;
206 
207  public:
208  SveLdStructSI(const char* mnem, ExtMachInst machInst, OpClass __opClass,
209  IntRegIndex _dest, IntRegIndex _gp, IntRegIndex _base,
210  int64_t _imm, uint8_t _numregs)
211  : PredMacroOp(mnem, machInst, __opClass),
212  dest(_dest), gp(_gp), base(_base), imm(_imm), numregs(_numregs)
213  {
214  numMicroops = numregs * 2;
215 
217 
218  for (int i = 0; i < numregs; ++i) {
219  microOps[i] = new MicroopLdMemType<Element>(
220  mnem, machInst, static_cast<IntRegIndex>(INTRLVREG0 + i),
221  _gp, _base, _imm, _numregs, i);
222  }
223  for (int i = 0; i < numregs; ++i) {
224  microOps[i + numregs] = new MicroopDeIntrlvType<Element>(
225  mnem, machInst, static_cast<IntRegIndex>((_dest + i) % 32),
226  _numregs, i, this);
227  }
228 
231 
232  for (StaticInstPtr *uop = microOps; !(*uop)->isLastMicroop(); uop++) {
233  (*uop)->setDelayedCommit();
234  }
235  }
236 
237  Fault
238  execute(ExecContext *, Trace::InstRecord *) const override
239  {
240  panic("Execute method called when it shouldn't!");
241  return NoFault;
242  }
243 
244  std::string
246  const loader::SymbolTable *symtab) const override
247  {
248  std::stringstream ss;
249  printMnemonic(ss, "", false);
250  ccprintf(ss, "{");
251  for (int i = 0; i < numregs; ++i) {
252  printVecReg(ss, (dest + i) % 32, true);
253  if (i < numregs - 1)
254  ccprintf(ss, ", ");
255  }
256  ccprintf(ss, "}, ");
258  ccprintf(ss, "/z, [");
259  printIntReg(ss, base);
260  if (imm != 0) {
261  ccprintf(ss, ", #%d, MUL VL", imm);
262  }
263  ccprintf(ss, "]");
264  return ss.str();
265  }
266 };
267 
268 template <typename Element,
269  template <typename> class MicroopStMemType,
270  template <typename> class MicroopIntrlvType>
272 {
273  protected:
274  IntRegIndex dest;
275  IntRegIndex gp;
276  IntRegIndex base;
277  int64_t imm;
278  uint8_t numregs;
279 
280  public:
281  SveStStructSI(const char* mnem, ExtMachInst machInst, OpClass __opClass,
282  IntRegIndex _dest, IntRegIndex _gp, IntRegIndex _base,
283  int64_t _imm, uint8_t _numregs)
284  : PredMacroOp(mnem, machInst, __opClass),
285  dest(_dest), gp(_gp), base(_base), imm(_imm), numregs(_numregs)
286  {
287  numMicroops = numregs * 2;
288 
290 
291  for (int i = 0; i < numregs; ++i) {
292  microOps[i] = new MicroopIntrlvType<Element>(
293  mnem, machInst, static_cast<IntRegIndex>(INTRLVREG0 + i),
294  _dest, _numregs, i, this);
295  }
296 
297  for (int i = 0; i < numregs; ++i) {
298  microOps[i + numregs] = new MicroopStMemType<Element>(
299  mnem, machInst, static_cast<IntRegIndex>(INTRLVREG0 + i),
300  _gp, _base, _imm, _numregs, i);
301  }
302 
305 
306  for (StaticInstPtr *uop = microOps; !(*uop)->isLastMicroop(); uop++) {
307  (*uop)->setDelayedCommit();
308  }
309  }
310 
311  Fault
312  execute(ExecContext *, Trace::InstRecord *) const override
313  {
314  panic("Execute method called when it shouldn't!");
315  return NoFault;
316  }
317 
318  std::string
320  const loader::SymbolTable *symtab) const override
321  {
322  std::stringstream ss;
323  printMnemonic(ss, "", false);
324  ccprintf(ss, "{");
325  for (int i = 0; i < numregs; ++i) {
326  printVecReg(ss, (dest + i) % 32, true);
327  if (i < numregs - 1)
328  ccprintf(ss, ", ");
329  }
330  ccprintf(ss, "}, ");
332  ccprintf(ss, ", [");
333  printIntReg(ss, base);
334  if (imm != 0) {
335  ccprintf(ss, ", #%d, MUL VL", imm);
336  }
337  ccprintf(ss, "]");
338  return ss.str();
339  }
340 };
341 
342 template <typename RegElemType, typename MemElemType,
343  template <typename, typename> class MicroopType,
344  template <typename> class FirstFaultWritebackMicroopType>
346 {
347  protected:
348  IntRegIndex dest;
349  IntRegIndex gp;
350  IntRegIndex base;
351  uint64_t imm;
352 
353  public:
354  SveIndexedMemVI(const char *mnem, ExtMachInst machInst, OpClass __opClass,
355  IntRegIndex _dest, IntRegIndex _gp, IntRegIndex _base,
356  uint64_t _imm, bool firstFault)
357  : PredMacroOp(mnem, machInst, __opClass),
358  dest(_dest), gp(_gp), base(_base), imm(_imm)
359  {
360  bool isLoad = (__opClass == MemReadOp);
361  assert(!firstFault || isLoad);
362 
363  int num_elems = ((machInst.sveLen + 1) * 16) / sizeof(RegElemType);
364 
365  numMicroops = num_elems;
366  if (isLoad) {
367  if (firstFault) {
368  numMicroops += 2;
369  } else {
370  numMicroops++;
371  }
372  }
373 
375 
376  StaticInstPtr *uop = microOps;
377 
378  if (isLoad) {
379  // The first microop of a gather load copies the source vector
380  // register used for address calculation to an auxiliary register,
381  // with all subsequent microops reading from the latter. This is
382  // needed to properly handle cases where the source vector
383  // register is the same as the destination register
384  *uop = new ArmISAInst::SveGatherLoadCpySrcVecMicroop(
385  mnem, machInst, _base, this);
386  uop++;
387  }
388 
389  for (int i = 0; i < num_elems; i++, uop++) {
390  *uop = new MicroopType<RegElemType, MemElemType>(
391  mnem, machInst, __opClass, _dest, _gp,
392  isLoad ? (IntRegIndex) VECREG_UREG0 : _base, _imm, i,
393  num_elems, firstFault);
394  }
395 
396  if (firstFault) {
397  *uop = new FirstFaultWritebackMicroopType<RegElemType>(
398  mnem, machInst, __opClass, num_elems, this);
399  } else {
400  --uop;
401  }
402 
403  (*uop)->setLastMicroop();
405 
406  for (StaticInstPtr *uop = microOps; !(*uop)->isLastMicroop(); uop++) {
407  (*uop)->setDelayedCommit();
408  }
409  }
410 
411  Fault
412  execute(ExecContext *, Trace::InstRecord *) const override
413  {
414  panic("Execute method called when it shouldn't!");
415  return NoFault;
416  }
417 
418  std::string
420  const loader::SymbolTable *symtab) const override
421  {
422  // TODO: add suffix to transfer and base registers
423  std::stringstream ss;
424  printMnemonic(ss, "", false);
425  ccprintf(ss, "{");
426  printVecReg(ss, dest, true);
427  ccprintf(ss, "}, ");
429  ccprintf(ss, "/z, [");
430  printVecReg(ss, base, true);
431  if (imm != 0) {
432  ccprintf(ss, ", #%d", imm * sizeof(MemElemType));
433  }
434  ccprintf(ss, "]");
435  return ss.str();
436  }
437 };
438 
439 template <typename RegElemType, typename MemElemType,
440  template <typename, typename> class MicroopType,
441  template <typename> class FirstFaultWritebackMicroopType>
443 {
444  protected:
445  IntRegIndex dest;
446  IntRegIndex gp;
447  IntRegIndex base;
448  IntRegIndex offset;
449 
453 
454  public:
455  SveIndexedMemSV(const char *mnem, ExtMachInst machInst, OpClass __opClass,
456  IntRegIndex _dest, IntRegIndex _gp, IntRegIndex _base,
457  IntRegIndex _offset, bool _offsetIs32,
458  bool _offsetIsSigned, bool _offsetIsScaled,
459  bool firstFault)
460  : PredMacroOp(mnem, machInst, __opClass),
461  dest(_dest), gp(_gp), base(_base), offset(_offset),
462  offsetIs32(_offsetIs32), offsetIsSigned(_offsetIsSigned),
463  offsetIsScaled(_offsetIsScaled)
464  {
465  bool isLoad = (__opClass == MemReadOp);
466  assert(!firstFault || isLoad);
467 
468  int num_elems = ((machInst.sveLen + 1) * 16) / sizeof(RegElemType);
469 
470  numMicroops = num_elems;
471  if (isLoad) {
472  if (firstFault) {
473  numMicroops += 2;
474  } else {
475  numMicroops++;
476  }
477  }
478 
480 
481  StaticInstPtr *uop = microOps;
482 
483  if (isLoad) {
484  // The first microop of a gather load copies the source vector
485  // register used for address calculation to an auxiliary register,
486  // with all subsequent microops reading from the latter. This is
487  // needed to properly handle cases where the source vector
488  // register is the same as the destination register
489  *uop = new ArmISAInst::SveGatherLoadCpySrcVecMicroop(
490  mnem, machInst, _offset, this);
491  uop++;
492  }
493 
494  for (int i = 0; i < num_elems; i++, uop++) {
495  *uop = new MicroopType<RegElemType, MemElemType>(
496  mnem, machInst, __opClass, _dest, _gp, _base,
497  isLoad ? (IntRegIndex) VECREG_UREG0 : _offset, _offsetIs32,
498  _offsetIsSigned, _offsetIsScaled, i, num_elems, firstFault);
499  }
500 
501  if (firstFault) {
502  *uop = new FirstFaultWritebackMicroopType<RegElemType>(
503  mnem, machInst, __opClass, num_elems, this);
504  } else {
505  --uop;
506  }
507 
508  (*uop)->setLastMicroop();
510 
511  for (StaticInstPtr *uop = microOps; !(*uop)->isLastMicroop(); uop++) {
512  (*uop)->setDelayedCommit();
513  }
514  }
515 
516  Fault
517  execute(ExecContext *, Trace::InstRecord *) const override
518  {
519  panic("Execute method called when it shouldn't!");
520  return NoFault;
521  }
522 
523  std::string
525  const loader::SymbolTable *symtab) const override
526  {
527  // TODO: add suffix to transfer and base registers
528  std::stringstream ss;
529  printMnemonic(ss, "", false);
530  ccprintf(ss, "{");
531  printVecReg(ss, dest, true);
532  ccprintf(ss, "}, ");
534  ccprintf(ss, "/z, [");
535  printIntReg(ss, base);
536  ccprintf(ss, ", ");
537  printVecReg(ss, offset, true);
538  ccprintf(ss, "]");
539  return ss.str();
540  }
541 };
542 
543 } // namespace ArmISA
544 } // namespace gem5
545 
546 #endif // __ARCH_ARM_SVE_MACROMEM_HH__
gem5::ArmISA::SveStStructSI::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve_macromem.hh:319
gem5::ArmISA::ArmStaticInst::printVecReg
void printVecReg(std::ostream &os, RegIndex reg_idx, bool isSveVecReg=false) const
Definition: static_inst.cc:351
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:260
gem5::ArmISA::SveStStructSS::base
IntRegIndex base
Definition: sve_macromem.hh:129
gem5::ArmISA::SveIndexedMemVI::gp
IntRegIndex gp
Definition: sve_macromem.hh:349
gem5::ArmISA::SveIndexedMemVI
Definition: sve_macromem.hh:345
gem5::ArmISA::SveLdStructSS::SveLdStructSS
SveLdStructSS(const char *mnem, ExtMachInst machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _gp, IntRegIndex _base, IntRegIndex _offset, uint8_t _numregs)
Definition: sve_macromem.hh:62
gem5::ArmISA::SveIndexedMemVI::SveIndexedMemVI
SveIndexedMemVI(const char *mnem, ExtMachInst machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _gp, IntRegIndex _base, uint64_t _imm, bool firstFault)
Definition: sve_macromem.hh:354
gem5::ArmISA::SveStStructSS::gp
IntRegIndex gp
Definition: sve_macromem.hh:128
gem5::ArmISA::SveStStructSS
Definition: sve_macromem.hh:124
gem5::ArmISA::SveLdStructSS::offset
IntRegIndex offset
Definition: sve_macromem.hh:58
gem5::ArmISA::SveStStructSS::numregs
uint8_t numregs
Definition: sve_macromem.hh:131
gem5::ArmISA::SveIndexedMemSV::offsetIsSigned
bool offsetIsSigned
Definition: sve_macromem.hh:451
gem5::ArmISA::SveStStructSI::numregs
uint8_t numregs
Definition: sve_macromem.hh:278
gem5::ArmISA::ArmStaticInst::printMnemonic
void printMnemonic(std::ostream &os, const std::string &suffix="", bool withPred=true, bool withCond64=false, ConditionCode cond64=COND_UC) const
Definition: static_inst.cc:377
gem5::ArmISA::SveIndexedMemVI::imm
uint64_t imm
Definition: sve_macromem.hh:351
gem5::ArmISA::PredMacroOp::numMicroops
uint32_t numMicroops
Definition: pred_inst.hh:344
gem5::ArmISA::SveIndexedMemSV::SveIndexedMemSV
SveIndexedMemSV(const char *mnem, ExtMachInst machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _gp, IntRegIndex _base, IntRegIndex _offset, bool _offsetIs32, bool _offsetIsSigned, bool _offsetIsScaled, bool firstFault)
Definition: sve_macromem.hh:455
gem5::ArmISA::SveIndexedMemSV::dest
IntRegIndex dest
Definition: sve_macromem.hh:445
gem5::ArmISA::SveLdStructSI::dest
IntRegIndex dest
Definition: sve_macromem.hh:201
gem5::ArmISA::SveIndexedMemSV::execute
Fault execute(ExecContext *, Trace::InstRecord *) const override
Definition: sve_macromem.hh:517
gem5::loader::SymbolTable
Definition: symtab.hh:65
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
gem5::ArmISA::SveStStructSS::SveStStructSS
SveStStructSS(const char *mnem, ExtMachInst machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _gp, IntRegIndex _base, IntRegIndex _offset, uint8_t _numregs)
Definition: sve_macromem.hh:134
gem5::ArmISA::SveStStructSI::gp
IntRegIndex gp
Definition: sve_macromem.hh:275
gem5::ArmISA::ArmStaticInst::machInst
ExtMachInst machInst
Definition: static_inst.hh:149
gem5::ArmISA::SveLdStructSS
Definition: sve_macromem.hh:52
gem5::ArmISA::VECREG_UREG0
const int VECREG_UREG0
Definition: vec.hh:89
gem5::ArmISA::SveIndexedMemSV::base
IntRegIndex base
Definition: sve_macromem.hh:447
gem5::ccprintf
void ccprintf(cp::Print &print)
Definition: cprintf.hh:130
gem5::ArmISA::SveStStructSS::execute
Fault execute(ExecContext *, Trace::InstRecord *) const override
Definition: sve_macromem.hh:165
gem5::RefCountingPtr< StaticInst >
gem5::ArmISA::SveIndexedMemSV::offset
IntRegIndex offset
Definition: sve_macromem.hh:448
gem5::ArmISA::SveLdStructSI::numregs
uint8_t numregs
Definition: sve_macromem.hh:205
gem5::ArmISA::SveLdStructSS::numregs
uint8_t numregs
Definition: sve_macromem.hh:59
gem5::ArmISA::SveIndexedMemVI::dest
IntRegIndex dest
Definition: sve_macromem.hh:348
gem5::ArmISA::SveLdStructSI::SveLdStructSI
SveLdStructSI(const char *mnem, ExtMachInst machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _gp, IntRegIndex _base, int64_t _imm, uint8_t _numregs)
Definition: sve_macromem.hh:208
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::ArmISA::SveIndexedMemVI::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve_macromem.hh:419
gem5::ArmISA::SveLdStructSS::gp
IntRegIndex gp
Definition: sve_macromem.hh:56
gem5::ArmISA::SveLdStructSS::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve_macromem.hh:99
gem5::ArmISA::SveStStructSS::dest
IntRegIndex dest
Definition: sve_macromem.hh:127
gem5::ArmISA::PredMacroOp::microOps
StaticInstPtr * microOps
Definition: pred_inst.hh:345
gem5::ArmISA::SveLdStructSS::execute
Fault execute(ExecContext *, Trace::InstRecord *) const override
Definition: sve_macromem.hh:92
gem5::StaticInst::isLoad
bool isLoad() const
Definition: static_inst.hh:169
gem5::ArmISA::SveLdStructSI::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve_macromem.hh:245
gem5::ArmISA::SveIndexedMemSV::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve_macromem.hh:524
gem5::ArmISA::SveStStructSI::execute
Fault execute(ExecContext *, Trace::InstRecord *) const override
Definition: sve_macromem.hh:312
gem5::ArmISA::ArmStaticInst::printVecPredReg
void printVecPredReg(std::ostream &os, RegIndex reg_idx) const
Definition: static_inst.cc:358
gem5::ArmISA::SveIndexedMemSV
Definition: sve_macromem.hh:442
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ArmISA::SveStStructSI
Definition: sve_macromem.hh:271
gem5::ArmISA::SveStStructSS::offset
IntRegIndex offset
Definition: sve_macromem.hh:130
pred_inst.hh
gem5::MemReadOp
static const OpClass MemReadOp
Definition: op_class.hh:102
gem5::StaticInst::isLastMicroop
bool isLastMicroop() const
Definition: static_inst.hh:210
gem5::StaticInst::setLastMicroop
void setLastMicroop()
Definition: static_inst.hh:227
gem5::ArmISA::PredMacroOp
Base class for predicated macro-operations.
Definition: pred_inst.hh:340
gem5::ArmISA::SveStStructSI::imm
int64_t imm
Definition: sve_macromem.hh:277
gem5::ArmISA::SveLdStructSI::gp
IntRegIndex gp
Definition: sve_macromem.hh:202
gem5::X86ISA::ExtMachInst
Definition: types.hh:206
gem5::ArmISA::SveLdStructSS::base
IntRegIndex base
Definition: sve_macromem.hh:57
gem5::ArmISA::SveLdStructSI::execute
Fault execute(ExecContext *, Trace::InstRecord *) const override
Definition: sve_macromem.hh:238
gem5::ArmISA::SveStStructSS::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve_macromem.hh:172
gem5::ArmISA::SveIndexedMemSV::gp
IntRegIndex gp
Definition: sve_macromem.hh:446
gem5::ArmISA::SveStStructSI::base
IntRegIndex base
Definition: sve_macromem.hh:276
gem5::ArmISA::INTRLVREG0
const int INTRLVREG0
Definition: vec.hh:85
gem5::ArmISA::SveIndexedMemSV::offsetIs32
bool offsetIs32
Definition: sve_macromem.hh:450
gem5::ArmISA::SveLdStructSI::imm
int64_t imm
Definition: sve_macromem.hh:204
gem5::ArmISA::ss
Bitfield< 21 > ss
Definition: misc_types.hh:59
gem5::ArmISA::SveLdStructSI::base
IntRegIndex base
Definition: sve_macromem.hh:203
gem5::StaticInst::setFirstMicroop
void setFirstMicroop()
Definition: static_inst.hh:226
gem5::ArmISA::SveLdStructSS::dest
IntRegIndex dest
Definition: sve_macromem.hh:55
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::ExecContext
The ExecContext is an abstract base class the provides the interface used by the ISA to manipulate th...
Definition: exec_context.hh:73
gem5::ArmISA::SveLdStructSI
Definition: sve_macromem.hh:198
gem5::ArmISA::SveStStructSI::dest
IntRegIndex dest
Definition: sve_macromem.hh:274
gem5::ArmISA::SveIndexedMemVI::execute
Fault execute(ExecContext *, Trace::InstRecord *) const override
Definition: sve_macromem.hh:412
gem5::ArmISA::SveIndexedMemSV::offsetIsScaled
bool offsetIsScaled
Definition: sve_macromem.hh:452
gem5::Trace::InstRecord
Definition: insttracer.hh:58
gem5::ArmISA::SveIndexedMemVI::base
IntRegIndex base
Definition: sve_macromem.hh:350
gem5::ArmISA::ArmStaticInst::printIntReg
void printIntReg(std::ostream &os, RegIndex reg_idx, uint8_t opWidth=0) const
Print a register name for disassembly given the unique dependence tag number (FP or int).
Definition: static_inst.cc:299
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::ArmISA::SveStStructSI::SveStStructSI
SveStStructSI(const char *mnem, ExtMachInst machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _gp, IntRegIndex _base, int64_t _imm, uint8_t _numregs)
Definition: sve_macromem.hh:281
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177

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