gem5  v21.1.0.2
AbstractController.cc
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40 
42 
43 #include "debug/RubyQueue.hh"
45 #include "mem/ruby/protocol/MemoryMsg.hh"
48 #include "sim/system.hh"
49 
50 namespace gem5
51 {
52 
53 namespace ruby
54 {
55 
57  : ClockedObject(p), Consumer(this), m_version(p.version),
58  m_clusterID(p.cluster_id),
59  m_id(p.system->getRequestorId(this)), m_is_blocking(false),
60  m_number_of_TBEs(p.number_of_TBEs),
61  m_transitions_per_cycle(p.transitions_per_cycle),
62  m_buffer_size(p.buffer_size), m_recycle_latency(p.recycle_latency),
63  m_mandatory_queue_latency(p.mandatory_queue_latency),
64  memoryPort(csprintf("%s.memory", name()), this),
65  addrRanges(p.addr_ranges.begin(), p.addr_ranges.end()),
66  stats(this)
67 {
68  if (m_version == 0) {
69  // Combine the statistics from all controllers
70  // of this particular type.
72  }
73 }
74 
75 void
77 {
79  uint32_t size = Network::getNumberOfVirtualNetworks();
80  for (uint32_t i = 0; i < size; i++) {
81  stats.delayVCHistogram.push_back(new statistics::Histogram(this));
82  stats.delayVCHistogram[i]->init(10);
83  }
84 
85  if (getMemReqQueue()) {
86  getMemReqQueue()->setConsumer(this);
87  }
88 
89  // Initialize the addr->downstream machine mappings. Multiple machines
90  // in downstream_destinations can have the same address range if they have
91  // different types. If this is the case, mapAddressToDownstreamMachine
92  // needs to specify the machine type
94  for (auto abs_cntrl : params().downstream_destinations) {
95  MachineID mid = abs_cntrl->getMachineID();
96  const AddrRangeList &ranges = abs_cntrl->getAddrRanges();
97  for (const auto &addr_range : ranges) {
98  auto i = downstreamAddrMap.intersects(addr_range);
99  if (i == downstreamAddrMap.end()) {
100  i = downstreamAddrMap.insert(addr_range, AddrMapEntry());
101  }
102  AddrMapEntry &entry = i->second;
103  fatal_if(entry.count(mid.getType()) > 0,
104  "%s: %s mapped to multiple machines of the same type\n",
105  name(), addr_range.to_string());
106  entry[mid.getType()] = mid;
107  }
109  }
110 
111 }
112 
113 void
115 {
117  uint32_t size = Network::getNumberOfVirtualNetworks();
118  for (uint32_t i = 0; i < size; i++) {
119  stats.delayVCHistogram[i]->reset();
120  }
121 }
122 
123 void
125 {
127 }
128 
129 void
130 AbstractController::profileMsgDelay(uint32_t virtualNetwork, Cycles delay)
131 {
132  assert(virtualNetwork < stats.delayVCHistogram.size());
133  stats.delayHistogram.sample(delay);
134  stats.delayVCHistogram[virtualNetwork]->sample(delay);
135 }
136 
137 void
139 {
140  if (m_waiting_buffers.count(addr) == 0) {
141  MsgVecType* msgVec = new MsgVecType;
142  msgVec->resize(m_in_ports, NULL);
143  m_waiting_buffers[addr] = msgVec;
144  }
145  DPRINTF(RubyQueue, "stalling %s port %d addr %#x\n", buf, m_cur_in_port,
146  addr);
147  assert(m_in_ports > m_cur_in_port);
148  (*(m_waiting_buffers[addr]))[m_cur_in_port] = buf;
149 }
150 
151 void
153 {
154  auto iter = m_waiting_buffers.find(addr);
155  if (iter != m_waiting_buffers.end()) {
156  bool has_other_msgs = false;
157  MsgVecType* msgVec = iter->second;
158  for (unsigned int port = 0; port < msgVec->size(); ++port) {
159  if ((*msgVec)[port] == buf) {
161  (*msgVec)[port] = NULL;
162  } else if ((*msgVec)[port] != NULL) {
163  has_other_msgs = true;
164  }
165  }
166  if (!has_other_msgs) {
167  delete msgVec;
168  m_waiting_buffers.erase(iter);
169  }
170  }
171 }
172 
173 void
175 {
176  if (m_waiting_buffers.count(addr) > 0) {
177  //
178  // Wake up all possible lower rank (i.e. lower priority) buffers that could
179  // be waiting on this message.
180  //
181  for (int in_port_rank = m_cur_in_port - 1;
182  in_port_rank >= 0;
183  in_port_rank--) {
184  if ((*(m_waiting_buffers[addr]))[in_port_rank] != NULL) {
185  (*(m_waiting_buffers[addr]))[in_port_rank]->
186  reanalyzeMessages(addr, clockEdge());
187  }
188  }
189  delete m_waiting_buffers[addr];
190  m_waiting_buffers.erase(addr);
191  }
192 }
193 
194 void
196 {
197  if (m_waiting_buffers.count(addr) > 0) {
198  //
199  // Wake up all possible buffers that could be waiting on this message.
200  //
201  for (int in_port_rank = m_in_ports - 1;
202  in_port_rank >= 0;
203  in_port_rank--) {
204  if ((*(m_waiting_buffers[addr]))[in_port_rank] != NULL) {
205  (*(m_waiting_buffers[addr]))[in_port_rank]->
206  reanalyzeMessages(addr, clockEdge());
207  }
208  }
209  delete m_waiting_buffers[addr];
210  m_waiting_buffers.erase(addr);
211  }
212 }
213 
214 void
216 {
217  //
218  // Wake up all possible buffers that could be waiting on any message.
219  //
220 
221  std::vector<MsgVecType*> wokeUpMsgVecs;
222  MsgBufType wokeUpMsgBufs;
223 
224  if (m_waiting_buffers.size() > 0) {
225  for (WaitingBufType::iterator buf_iter = m_waiting_buffers.begin();
226  buf_iter != m_waiting_buffers.end();
227  ++buf_iter) {
228  for (MsgVecType::iterator vec_iter = buf_iter->second->begin();
229  vec_iter != buf_iter->second->end();
230  ++vec_iter) {
231  //
232  // Make sure the MessageBuffer has not already be reanalyzed
233  //
234  if (*vec_iter != NULL &&
235  (wokeUpMsgBufs.count(*vec_iter) == 0)) {
236  (*vec_iter)->reanalyzeAllMessages(clockEdge());
237  wokeUpMsgBufs.insert(*vec_iter);
238  }
239  }
240  wokeUpMsgVecs.push_back(buf_iter->second);
241  }
242 
243  for (std::vector<MsgVecType*>::iterator wb_iter = wokeUpMsgVecs.begin();
244  wb_iter != wokeUpMsgVecs.end();
245  ++wb_iter) {
246  delete (*wb_iter);
247  }
248 
249  m_waiting_buffers.clear();
250  }
251 }
252 
253 bool
255 {
256  auto mem_queue = getMemReqQueue();
257  assert(mem_queue);
258  if (!mem_queue->isReady(clockEdge())) {
259  return false;
260  }
261 
262  const MemoryMsg *mem_msg = (const MemoryMsg*)mem_queue->peek();
263  unsigned int req_size = RubySystem::getBlockSizeBytes();
264  if (mem_msg->m_Len > 0) {
265  req_size = mem_msg->m_Len;
266  }
267 
268  RequestPtr req
269  = std::make_shared<Request>(mem_msg->m_addr, req_size, 0, m_id);
270  PacketPtr pkt;
271  if (mem_msg->getType() == MemoryRequestType_MEMORY_WB) {
272  pkt = Packet::createWrite(req);
273  pkt->allocate();
274  pkt->setData(mem_msg->m_DataBlk.getData(getOffset(mem_msg->m_addr),
275  req_size));
276  } else if (mem_msg->getType() == MemoryRequestType_MEMORY_READ) {
277  pkt = Packet::createRead(req);
278  uint8_t *newData = new uint8_t[req_size];
279  pkt->dataDynamic(newData);
280  } else {
281  panic("Unknown memory request type (%s) for addr %p",
282  MemoryRequestType_to_string(mem_msg->getType()),
283  mem_msg->m_addr);
284  }
285 
286  SenderState *s = new SenderState(mem_msg->m_Sender);
287  pkt->pushSenderState(s);
288 
290  // Use functional rather than timing accesses during warmup
291  mem_queue->dequeue(clockEdge());
293  // Since the queue was popped the controller may be able
294  // to make more progress. Make sure it wakes up
295  scheduleEvent(Cycles(1));
296  recvTimingResp(pkt);
297  } else if (memoryPort.sendTimingReq(pkt)) {
298  mem_queue->dequeue(clockEdge());
299  // Since the queue was popped the controller may be able
300  // to make more progress. Make sure it wakes up
301  scheduleEvent(Cycles(1));
302  } else {
303  scheduleEvent(Cycles(1));
304  delete pkt;
305  delete s;
306  }
307 
308  return true;
309 }
310 
311 void
313 {
314  m_is_blocking = true;
315  m_block_map[addr] = port;
316 }
317 
318 bool
320 {
321  return m_is_blocking && (m_block_map.find(addr) != m_block_map.end());
322 }
323 
324 void
326 {
327  m_block_map.erase(addr);
328  if (m_block_map.size() == 0) {
329  m_is_blocking = false;
330  }
331 }
332 
333 bool
335 {
336  return (m_block_map.count(addr) > 0);
337 }
338 
339 Port &
340 AbstractController::getPort(const std::string &if_name, PortID idx)
341 {
342  return memoryPort;
343 }
344 
345 void
347 {
348  // read from mem. req. queue if write data is pending there
349  MessageBuffer *req_queue = getMemReqQueue();
350  if (!req_queue || !req_queue->functionalRead(pkt))
352 }
353 
354 int
356 {
357  int num_functional_writes = 0;
358 
359  // Update memory itself.
361  return num_functional_writes + 1;
362 }
363 
364 void
366 {
367  assert(getMemRespQueue());
368  assert(pkt->isResponse());
369 
370  std::shared_ptr<MemoryMsg> msg = std::make_shared<MemoryMsg>(clockEdge());
371  (*msg).m_addr = pkt->getAddr();
372  (*msg).m_Sender = m_machineID;
373 
374  SenderState *s = dynamic_cast<SenderState *>(pkt->senderState);
375  (*msg).m_OriginalRequestorMachId = s->id;
376  delete s;
377 
378  if (pkt->isRead()) {
379  (*msg).m_Type = MemoryRequestType_MEMORY_READ;
380  (*msg).m_MessageSize = MessageSizeType_Response_Data;
381 
382  // Copy data from the packet
383  (*msg).m_DataBlk.setData(pkt->getPtr<uint8_t>(), 0,
385  } else if (pkt->isWrite()) {
386  (*msg).m_Type = MemoryRequestType_MEMORY_WB;
387  (*msg).m_MessageSize = MessageSizeType_Writeback_Control;
388  } else {
389  panic("Incorrect packet type received from memory controller!");
390  }
391 
393  delete pkt;
394 }
395 
396 Tick
398 {
399  return ticksToCycles(memoryPort.sendAtomic(pkt));
400 }
401 
402 MachineID
404 {
405  NodeID node = m_net_ptr->addressToNodeID(addr, mtype);
406  MachineID mach = {mtype, node};
407  return mach;
408 }
409 
410 MachineID
412 const
413 {
414  const auto i = downstreamAddrMap.contains(addr);
416  "%s: couldn't find mapping for address %x\n", name(), addr);
417 
418  const AddrMapEntry &entry = i->second;
419  assert(!entry.empty());
420 
421  if (mtype == MachineType_NUM) {
422  fatal_if(entry.size() > 1,
423  "%s: address %x mapped to multiple machine types.\n", name(), addr);
424  return entry.begin()->second;
425  } else {
426  auto j = entry.find(mtype);
427  fatal_if(j == entry.end(),
428  "%s: couldn't find mapping for address %x\n", name(), addr);
429  return j->second;
430  }
431 }
432 
433 
434 bool
436 {
438  return true;
439 }
440 
441 void
443 {
444  controller->serviceMemoryQueue();
445 }
446 
448  AbstractController *_controller,
449  PortID id)
450  : RequestPort(_name, _controller, id), controller(_controller)
451 {
452 }
453 
456  : statistics::Group(parent),
457  ADD_STAT(fullyBusyCycles,
458  "cycles for which number of transistions == max transitions"),
459  ADD_STAT(delayHistogram, "delay_histogram")
460 {
465 }
466 
467 } // namespace ruby
468 } // namespace gem5
gem5::ruby::MachineID::getType
MachineType getType() const
Definition: MachineID.hh:66
gem5::PortID
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:252
gem5::ruby::Network::getNumberOfVirtualNetworks
static uint32_t getNumberOfVirtualNetworks()
Definition: Network.hh:90
gem5::ruby::AbstractController::MsgBufType
std::set< MessageBuffer * > MsgBufType
Definition: AbstractController.hh:320
gem5::RequestPort::sendTimingReq
bool sendTimingReq(PacketPtr pkt)
Attempt to send a timing request to the responder port by calling its corresponding receive function.
Definition: port.hh:495
gem5::ruby::AbstractController::ControllerStats::fullyBusyCycles
statistics::Scalar fullyBusyCycles
Counter for the number of cycles when the transitions carried out were equal to the maximum allowed.
Definition: AbstractController.hh:397
system.hh
gem5::ruby::AbstractController::getMemReqQueue
virtual MessageBuffer * getMemReqQueue() const =0
gem5::ruby::AbstractController::profileMsgDelay
void profileMsgDelay(uint32_t virtualNetwork, Cycles delay)
Profiles the delay associated with messages.
Definition: AbstractController.cc:130
gem5::Packet::setData
void setData(const uint8_t *p)
Copy data into the packet from the provided pointer.
Definition: packet.hh:1252
gem5::Packet::pushSenderState
void pushSenderState(SenderState *sender_state)
Push a new sender state to the packet and make the current sender state the predecessor of the new on...
Definition: packet.cc:316
gem5::RequestPort::sendAtomic
Tick sendAtomic(PacketPtr pkt)
Send an atomic request packet, where the data is moved and the state is updated in zero time,...
Definition: port.hh:464
gem5::ruby::AbstractController::serviceMemoryQueue
bool serviceMemoryQueue()
Definition: AbstractController.cc:254
gem5::statistics::nozero
const FlagsType nozero
Don't print if this is zero.
Definition: info.hh:68
gem5::ruby::AbstractController::wakeUpBuffers
void wakeUpBuffers(Addr addr)
Definition: AbstractController.cc:174
gem5::ruby::AbstractController::resetStats
virtual void resetStats()=0
Callback to reset stats.
Definition: AbstractController.cc:114
AbstractController.hh
gem5::ruby::MessageBuffer::enqueue
void enqueue(MsgPtr message, Tick curTime, Tick delta)
Definition: MessageBuffer.cc:197
gem5::Packet::isWrite
bool isWrite() const
Definition: packet.hh:583
gem5::ruby::RubySystem::getBlockSizeBytes
static uint32_t getBlockSizeBytes()
Definition: RubySystem.hh:72
gem5::Packet::createWrite
static PacketPtr createWrite(const RequestPtr &req)
Definition: packet.hh:1013
gem5::X86ISA::system
Bitfield< 15 > system
Definition: misc.hh:1003
gem5::ruby::AbstractController::mapAddressToDownstreamMachine
MachineID mapAddressToDownstreamMachine(Addr addr, MachineType mtype=MachineType_NUM) const
Maps an address to the correct dowstream MachineID (i.e.
Definition: AbstractController.cc:411
std::vector
STL vector class.
Definition: stl.hh:37
gem5::ruby::AbstractController::m_block_map
std::map< Addr, MessageBuffer * > m_block_map
Definition: AbstractController.hh:317
gem5::ruby::AbstractController::isBlocked
bool isBlocked(Addr) const
Definition: AbstractController.cc:319
gem5::csprintf
std::string csprintf(const char *format, const Args &...args)
Definition: cprintf.hh:161
gem5::ruby::Consumer
Definition: Consumer.hh:61
gem5::ruby::AbstractController::getPort
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID)
A function used to return the port associated with this bus object.
Definition: AbstractController.cc:340
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
gem5::ruby::AbstractController::MsgVecType
std::vector< MessageBuffer * > MsgVecType
Definition: AbstractController.hh:319
gem5::ruby::AbstractController::m_is_blocking
bool m_is_blocking
Definition: AbstractController.hh:316
gem5::ruby::AbstractController
Definition: AbstractController.hh:82
gem5::ruby::MessageBuffer::reanalyzeMessages
void reanalyzeMessages(Addr addr, Tick current_time)
Definition: MessageBuffer.cc:379
gem5::statistics::DistBase::sample
void sample(const U &v, int n=1)
Add a value to the distribtion n times.
Definition: statistics.hh:1325
gem5::ruby::AbstractController::ControllerStats::delayHistogram
statistics::Histogram delayHistogram
Histogram for profiling delay for the messages this controller cares for.
Definition: AbstractController.hh:401
gem5::RequestPort
A RequestPort is a specialisation of a Port, which implements the default protocol for the three diff...
Definition: port.hh:77
gem5::AddrRangeMap::contains
const_iterator contains(const AddrRange &r) const
Find entry that contains the given address range.
Definition: addr_range_map.hh:90
gem5::statistics::registerDumpCallback
void registerDumpCallback(const std::function< void()> &callback)
Register a callback that should be called whenever statistics are about to be dumped.
Definition: statistics.cc:324
gem5::Cycles
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:78
gem5::statistics::Histogram
A simple histogram stat.
Definition: statistics.hh:2123
gem5::ruby::AbstractController::ControllerStats::delayVCHistogram
std::vector< statistics::Histogram * > delayVCHistogram
Definition: AbstractController.hh:402
gem5::ruby::AbstractController::MemoryPort::recvReqRetry
void recvReqRetry()
Called by the peer if sendTimingReq was called on this peer (causing recvTimingReq to be called on th...
Definition: AbstractController.cc:442
gem5::ArmISA::j
Bitfield< 24 > j
Definition: misc_types.hh:57
gem5::ruby::AbstractController::collateStats
virtual void collateStats()
Function for collating statistics from all the controllers of this particular type.
Definition: AbstractController.hh:158
gem5::RequestPort::sendFunctional
void sendFunctional(PacketPtr pkt) const
Send a functional request packet, where the data is instantly updated everywhere in the memory system...
Definition: port.hh:485
gem5::Packet::isRead
bool isRead() const
Definition: packet.hh:582
gem5::ruby::AbstractController::functionalMemoryWrite
int functionalMemoryWrite(PacketPtr)
Definition: AbstractController.cc:355
gem5::Named::name
virtual std::string name() const
Definition: named.hh:47
gem5::Clocked::cyclesToTicks
Tick cyclesToTicks(Cycles c) const
Definition: clocked_object.hh:227
gem5::SimObject::params
const Params & params() const
Definition: sim_object.hh:176
gem5::ruby::Consumer::scheduleEvent
void scheduleEvent(Cycles timeDelta)
Definition: Consumer.cc:56
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
ADD_STAT
#define ADD_STAT(n,...)
Convenience macro to add a stat to a statistics group.
Definition: group.hh:75
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::ruby::MessageBuffer::functionalRead
bool functionalRead(Packet *pkt)
Definition: MessageBuffer.hh:176
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::ruby::AbstractController::mapAddressToMachine
MachineID mapAddressToMachine(Addr addr, MachineType mtype) const
Map an address to the correct MachineID.
Definition: AbstractController.cc:403
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::ArmISA::s
Bitfield< 4 > s
Definition: misc_types.hh:561
gem5::ruby::AbstractController::recvAtomic
Tick recvAtomic(PacketPtr pkt)
Definition: AbstractController.cc:397
gem5::ruby::AbstractController::ControllerStats::ControllerStats
ControllerStats(statistics::Group *parent)
Definition: AbstractController.cc:455
gem5::ruby::AbstractController::m_cur_in_port
unsigned int m_cur_in_port
Definition: AbstractController.hh:325
gem5::ruby::AbstractController::downstreamDestinations
NetDest downstreamDestinations
Definition: AbstractController.hh:376
gem5::ruby::getOffset
Addr getOffset(Addr addr)
Definition: Address.cc:54
gem5::AddrRangeMap::end
const_iterator end() const
Definition: addr_range_map.hh:217
gem5::ruby::AbstractController::MemoryPort::MemoryPort
MemoryPort(const std::string &_name, AbstractController *_controller, PortID id=InvalidPortID)
Definition: AbstractController.cc:447
gem5::ruby::AbstractController::AbstractController
AbstractController(const Params &p)
Definition: AbstractController.cc:56
RubySystem.hh
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::statistics::Histogram::init
Histogram & init(size_type size)
Set the parameters of this histogram.
Definition: statistics.hh:2151
gem5::Packet::senderState
SenderState * senderState
This packet's sender state.
Definition: packet.hh:534
name
const std::string & name()
Definition: trace.cc:49
gem5::ruby::AbstractController::SenderState
Definition: AbstractController.hh:359
gem5::ruby::AbstractController::m_waiting_buffers
WaitingBufType m_waiting_buffers
Definition: AbstractController.hh:322
gem5::ruby::AbstractController::m_machineID
MachineID m_machineID
Definition: AbstractController.hh:309
gem5::statistics::Group::regStats
virtual void regStats()
Callback to set stat parameters.
Definition: group.cc:69
gem5::ruby::AbstractController::m_version
const NodeID m_version
Definition: AbstractController.hh:308
gem5::ClockedObject
The ClockedObject class extends the SimObject with a clock and accessor functions to relate ticks to ...
Definition: clocked_object.hh:234
gem5::Clocked::clockEdge
Tick clockEdge(Cycles cycles=Cycles(0)) const
Determine the tick when a cycle begins, by default the current one, but the argument also enables the...
Definition: clocked_object.hh:177
gem5::ruby::AbstractController::init
void init()
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: AbstractController.cc:76
gem5::ruby::AbstractController::unblock
void unblock(Addr)
Definition: AbstractController.cc:325
gem5::ruby::AbstractController::stats
gem5::ruby::AbstractController::ControllerStats stats
gem5::ruby::MessageBuffer::setConsumer
void setConsumer(Consumer *consumer)
Definition: MessageBuffer.hh:102
Network.hh
gem5::ruby::AbstractController::wakeUpAllBuffers
void wakeUpAllBuffers()
Definition: AbstractController.cc:215
gem5::AddrRangeMap::intersects
const_iterator intersects(const AddrRange &r) const
Find entry that intersects with the given address range.
Definition: addr_range_map.hh:140
gem5::Packet::allocate
void allocate()
Allocate memory for the packet.
Definition: packet.hh:1326
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
gem5::ruby::AbstractController::m_in_ports
unsigned int m_in_ports
Definition: AbstractController.hh:324
gem5::ruby::Network::addressToNodeID
NodeID addressToNodeID(Addr addr, MachineType mtype)
Map an address to the correct NodeID.
Definition: Network.cc:235
gem5::ruby::AbstractController::MemoryPort::recvTimingResp
bool recvTimingResp(PacketPtr pkt)
Receive a timing response from the peer.
Definition: AbstractController.cc:435
gem5::ruby::RubySystem::getWarmupEnabled
static bool getWarmupEnabled()
Definition: RubySystem.hh:75
gem5::ruby::AbstractController::m_net_ptr
Network * m_net_ptr
Definition: AbstractController.hh:315
gem5::ruby::AbstractController::functionalMemoryRead
void functionalMemoryRead(PacketPtr)
Definition: AbstractController.cc:346
gem5::Packet::dataDynamic
void dataDynamic(T *p)
Set the data pointer to a value that should have delete [] called on it.
Definition: packet.hh:1172
gem5::AddrRangeMap::insert
iterator insert(const AddrRange &r, const V &d)
Definition: addr_range_map.hh:155
gem5::ruby::NetDest::resize
void resize()
Definition: NetDest.cc:253
gem5::statistics::Group
Statistics container.
Definition: group.hh:93
gem5::ruby::AbstractController::m_id
const RequestorID m_id
Definition: AbstractController.hh:313
gem5::ArmISA::id
Bitfield< 33 > id
Definition: misc_types.hh:250
gem5::ruby::NodeID
unsigned int NodeID
Definition: TypeDefines.hh:40
gem5::ruby::NetDest::add
void add(MachineID newElement)
Definition: NetDest.cc:45
gem5::ruby::AbstractController::AddrMapEntry
std::unordered_map< MachineType, MachineID > AddrMapEntry
Definition: AbstractController.hh:372
gem5::ruby::AbstractController::regStats
virtual void regStats()
Callback to set stat parameters.
Definition: AbstractController.cc:124
gem5::ruby::AbstractController::MemoryPort::controller
AbstractController * controller
Definition: AbstractController.hh:340
gem5::statistics::DistBase::reset
void reset()
Reset stat value to default.
Definition: statistics.hh:1349
gem5::ClockedObject::Params
ClockedObjectParams Params
Parameters of ClockedObject.
Definition: clocked_object.hh:240
gem5::statistics::DataWrap::flags
Derived & flags(Flags _flags)
Set the flags and marks this stat to print at the end of simulation.
Definition: statistics.hh:355
gem5::ruby::AbstractController::downstreamAddrMap
AddrRangeMap< AddrMapEntry, 3 > downstreamAddrMap
Definition: AbstractController.hh:374
gem5::Clocked::ticksToCycles
Cycles ticksToCycles(Tick t) const
Definition: clocked_object.hh:222
gem5::ruby::AbstractController::memoryPort
MemoryPort memoryPort
Definition: AbstractController.hh:356
gem5::ruby::MessageBuffer
Definition: MessageBuffer.hh:74
std::list< AddrRange >
gem5::Packet::getAddr
Addr getAddr() const
Definition: packet.hh:781
fatal_if
#define fatal_if(cond,...)
Conditional fatal macro that checks the supplied condition and only causes a fatal error if the condi...
Definition: logging.hh:225
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::Packet::createRead
static PacketPtr createRead(const RequestPtr &req)
Constructor-like methods that return Packets based on Request objects.
Definition: packet.hh:1007
gem5::ruby::AbstractController::getMemRespQueue
virtual MessageBuffer * getMemRespQueue() const =0
gem5::ruby::MachineID
Definition: MachineID.hh:56
gem5::ruby::AbstractController::blockOnQueue
void blockOnQueue(Addr, MessageBuffer *)
Definition: AbstractController.cc:312
gem5::Packet::isResponse
bool isResponse() const
Definition: packet.hh:587
gem5::ruby::AbstractController::recvTimingResp
void recvTimingResp(PacketPtr pkt)
Definition: AbstractController.cc:365
gem5::Named::_name
const std::string _name
Definition: named.hh:41
gem5::ruby::AbstractController::wakeUpBuffer
void wakeUpBuffer(MessageBuffer *buf, Addr addr)
Definition: AbstractController.cc:152
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::ruby::AbstractController::stallBuffer
void stallBuffer(MessageBuffer *buf, Addr addr)
Definition: AbstractController.cc:138
gem5::SenderState
RubyTester::SenderState SenderState
Definition: Check.cc:40
gem5::Packet::getPtr
T * getPtr()
get a pointer to the data ptr.
Definition: packet.hh:1184
Sequencer.hh

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