gem5 v24.1.0.1
Loading...
Searching...
No Matches
AbstractController.cc
Go to the documentation of this file.
1/*
2 * Copyright (c) 2017,2019-2022 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2011-2014 Mark D. Hill and David A. Wood
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 */
40
42
43#include "debug/RubyQueue.hh"
45#include "mem/ruby/protocol/MemoryMsg.hh"
48#include "sim/system.hh"
49
50namespace gem5
51{
52
53namespace ruby
54{
55
57 : ClockedObject(p), Consumer(this), m_version(p.version),
58 m_clusterID(p.cluster_id),
59 m_id(p.system->getRequestorId(this)), m_is_blocking(false),
60 m_number_of_TBEs(p.number_of_TBEs),
61 m_transitions_per_cycle(p.transitions_per_cycle),
62 m_buffer_size(p.buffer_size), m_recycle_latency(p.recycle_latency),
63 m_mandatory_queue_latency(p.mandatory_queue_latency),
64 m_waiting_mem_retry(false),
65 m_mem_ctrl_waiting_retry(false),
66 memoryPort(csprintf("%s.memory", name()), this),
67 addrRanges(p.addr_ranges.begin(), p.addr_ranges.end()),
68 mRetryRespEvent{*this, false},
69 stats(this)
70{
71 if (m_version == 0) {
72 // Combine the statistics from all controllers
73 // of this particular type.
75 }
76}
77
78void
80{
83 for (uint32_t i = 0; i < size; i++) {
84 stats.delayVCHistogram.push_back(new statistics::Histogram(this));
85 stats.delayVCHistogram[i]->init(10);
86 }
87
88 if (getMemReqQueue()) {
90 }
91
94
95 // Initialize the addr->downstream machine mappings. Multiple machines
96 // in downstream_destinations can have the same address range if they have
97 // different types. If this is the case, mapAddressToDownstreamMachine
98 // needs to specify the machine type
100 for (auto abs_cntrl : params().downstream_destinations) {
101 MachineID mid = abs_cntrl->getMachineID();
102 const AddrRangeList &ranges = abs_cntrl->getAddrRanges();
103 for (const auto &addr_range : ranges) {
104 auto i = downstreamAddrMap.find(mid.getType());
105 if ((i != downstreamAddrMap.end()) &&
106 (i->second.intersects(addr_range) != i->second.end())) {
107 fatal("%s: %s mapped to multiple machines of the same type\n",
108 name(), addr_range.to_string());
109 }
110 downstreamAddrMap[mid.getType()].insert(addr_range, mid);
111 }
113 }
114 // Initialize the addr->upstream machine list.
115 // We do not need to map address -> upstream machine,
116 // so we don't examine the address ranges
118 for (auto abs_cntrl : params().upstream_destinations) {
119 upstreamDestinations.add(abs_cntrl->getMachineID());
120 }
121}
122
123void
125{
127 uint32_t size = Network::getNumberOfVirtualNetworks();
128 for (uint32_t i = 0; i < size; i++) {
129 stats.delayVCHistogram[i]->reset();
130 }
132}
133
134void
139
140void
141AbstractController::profileMsgDelay(uint32_t virtualNetwork, Cycles delay)
142{
143 assert(virtualNetwork < stats.delayVCHistogram.size());
145 stats.delayVCHistogram[virtualNetwork]->sample(delay);
146}
147
148void
150{
151 if (m_waiting_buffers.count(addr) == 0) {
152 MsgVecType* msgVec = new MsgVecType;
153 msgVec->resize(m_in_ports, NULL);
154 m_waiting_buffers[addr] = msgVec;
155 }
156 DPRINTF(RubyQueue, "stalling %s port %d addr %#x\n", buf, m_cur_in_port,
157 addr);
158 assert(m_in_ports > m_cur_in_port);
160}
161
162void
164{
165 auto iter = m_waiting_buffers.find(addr);
166 if (iter != m_waiting_buffers.end()) {
167 bool has_other_msgs = false;
168 MsgVecType* msgVec = iter->second;
169 for (unsigned int port = 0; port < msgVec->size(); ++port) {
170 if ((*msgVec)[port] == buf) {
172 (*msgVec)[port] = NULL;
173 } else if ((*msgVec)[port] != NULL) {
174 has_other_msgs = true;
175 }
176 }
177 if (!has_other_msgs) {
178 delete msgVec;
179 m_waiting_buffers.erase(iter);
180 }
181 }
182}
183
184void
186{
187 if (m_waiting_buffers.count(addr) > 0) {
188 //
189 // Wake up all possible lower rank (i.e. lower priority) buffers that could
190 // be waiting on this message.
191 //
192 for (int in_port_rank = m_cur_in_port - 1;
193 in_port_rank >= 0;
194 in_port_rank--) {
195 if ((*(m_waiting_buffers[addr]))[in_port_rank] != NULL) {
196 (*(m_waiting_buffers[addr]))[in_port_rank]->
197 reanalyzeMessages(addr, clockEdge());
198 }
199 }
200 delete m_waiting_buffers[addr];
201 m_waiting_buffers.erase(addr);
202 }
203}
204
205void
207{
208 if (m_waiting_buffers.count(addr) > 0) {
209 //
210 // Wake up all possible buffers that could be waiting on this message.
211 //
212 for (int in_port_rank = m_in_ports - 1;
213 in_port_rank >= 0;
214 in_port_rank--) {
215 if ((*(m_waiting_buffers[addr]))[in_port_rank] != NULL) {
216 (*(m_waiting_buffers[addr]))[in_port_rank]->
217 reanalyzeMessages(addr, clockEdge());
218 }
219 }
220 delete m_waiting_buffers[addr];
221 m_waiting_buffers.erase(addr);
222 }
223}
224
225void
227{
228 //
229 // Wake up all possible buffers that could be waiting on any message.
230 //
231
232 std::vector<MsgVecType*> wokeUpMsgVecs;
233 MsgBufType wokeUpMsgBufs;
234
235 if (m_waiting_buffers.size() > 0) {
236 for (WaitingBufType::iterator buf_iter = m_waiting_buffers.begin();
237 buf_iter != m_waiting_buffers.end();
238 ++buf_iter) {
239 for (MsgVecType::iterator vec_iter = buf_iter->second->begin();
240 vec_iter != buf_iter->second->end();
241 ++vec_iter) {
242 //
243 // Make sure the MessageBuffer has not already be reanalyzed
244 //
245 if (*vec_iter != NULL &&
246 (wokeUpMsgBufs.count(*vec_iter) == 0)) {
247 (*vec_iter)->reanalyzeAllMessages(clockEdge());
248 wokeUpMsgBufs.insert(*vec_iter);
249 }
250 }
251 wokeUpMsgVecs.push_back(buf_iter->second);
252 }
253
254 for (std::vector<MsgVecType*>::iterator wb_iter = wokeUpMsgVecs.begin();
255 wb_iter != wokeUpMsgVecs.end();
256 ++wb_iter) {
257 delete (*wb_iter);
258 }
259
260 m_waiting_buffers.clear();
261 }
262}
263
264bool
266{
267 auto mem_queue = getMemReqQueue();
268 assert(mem_queue);
269 if (m_waiting_mem_retry || !mem_queue->isReady(clockEdge())) {
270 return false;
271 }
272
273 const MemoryMsg *mem_msg = (const MemoryMsg*)mem_queue->peek();
274 unsigned int req_size = m_ruby_system->getBlockSizeBytes();
275 if (mem_msg->m_Len > 0) {
276 req_size = mem_msg->m_Len;
277 }
278
279 RequestPtr req
280 = std::make_shared<Request>(mem_msg->m_addr, req_size, 0, m_id);
281 PacketPtr pkt;
282 if (mem_msg->getType() == MemoryRequestType_MEMORY_WB) {
283 pkt = Packet::createWrite(req);
284 pkt->allocate();
285 pkt->setData(mem_msg->m_DataBlk.getData(getOffset(mem_msg->m_addr),
286 req_size));
287 } else if (mem_msg->getType() == MemoryRequestType_MEMORY_READ) {
288 pkt = Packet::createRead(req);
289 uint8_t *newData = new uint8_t[req_size];
290 pkt->dataDynamic(newData);
291 } else {
292 panic("Unknown memory request type (%s) for addr %p",
293 MemoryRequestType_to_string(mem_msg->getType()),
294 mem_msg->m_addr);
295 }
296
297 SenderState *s = new SenderState(mem_msg->m_Sender);
298 pkt->pushSenderState(s);
299
301 // Use functional rather than timing accesses during warmup
302 mem_queue->dequeue(clockEdge());
304 // Since the queue was popped the controller may be able
305 // to make more progress. Make sure it wakes up
307 recvTimingResp(pkt);
308 } else if (memoryPort.sendTimingReq(pkt)) {
309 mem_queue->dequeue(clockEdge());
310 // Since the queue was popped the controller may be able
311 // to make more progress. Make sure it wakes up
313 } else {
315 m_waiting_mem_retry = true;
316 delete pkt;
317 delete s;
318 }
319
320 return true;
321}
322
323void
329
330bool
332{
333 return m_is_blocking && (m_block_map.find(addr) != m_block_map.end());
334}
335
336void
338{
339 m_block_map.erase(addr);
340 if (m_block_map.size() == 0) {
341 m_is_blocking = false;
342 }
343}
344
345bool
347{
348 return (m_block_map.count(addr) > 0);
349}
350
351Port &
352AbstractController::getPort(const std::string &if_name, PortID idx)
353{
354 return memoryPort;
355}
356
357void
359{
360 // read from mem. req. queue if write data is pending there
361 MessageBuffer *req_queue = getMemReqQueue();
362 if (!req_queue || !req_queue->functionalRead(pkt))
364}
365
366int
368{
369 int num_functional_writes = 0;
370
371 // Update memory itself.
373 return num_functional_writes + 1;
374}
375
376bool
378{
379 auto* memRspQueue = getMemRespQueue();
380 gem5_assert(memRspQueue);
381 gem5_assert(pkt->isResponse());
382
383 if (!memRspQueue->areNSlotsAvailable(1, curTick())) {
385 return false;
386 }
387
388 int blk_size = m_ruby_system->getBlockSizeBytes();
389
390 std::shared_ptr<MemoryMsg> msg =
391 std::make_shared<MemoryMsg>(clockEdge(), blk_size, m_ruby_system);
392 (*msg).m_addr = pkt->getAddr();
393 (*msg).m_Sender = m_machineID;
394
395 SenderState *s = dynamic_cast<SenderState *>(pkt->senderState);
396 (*msg).m_OriginalRequestorMachId = s->id;
397 delete s;
398
399 if (pkt->isRead()) {
400 (*msg).m_Type = MemoryRequestType_MEMORY_READ;
401 (*msg).m_MessageSize = MessageSizeType_Response_Data;
402
403 // Copy data from the packet
404 (*msg).m_DataBlk.setData(pkt->getPtr<uint8_t>(), 0,
406 } else if (pkt->isWrite()) {
407 (*msg).m_Type = MemoryRequestType_MEMORY_WB;
408 (*msg).m_MessageSize = MessageSizeType_Writeback_Control;
409 } else {
410 panic("Incorrect packet type received from memory controller!");
411 }
412
413 memRspQueue->enqueue(msg, clockEdge(), cyclesToTicks(Cycles(1)),
415 delete pkt;
416 return true;
417}
418
419Tick
424
427{
428 NodeID node = m_net_ptr->addressToNodeID(addr, mtype);
429 MachineID mach = {mtype, node};
430 return mach;
431}
432
435const
436{
437 if (mtype == MachineType_NUM) {
438 // map to the first match
439 for (const auto &i : downstreamAddrMap) {
440 const auto mapping = i.second.contains(addr);
441 if (mapping != i.second.end())
442 return mapping->second;
443 }
444 }
445 else {
446 const auto i = downstreamAddrMap.find(mtype);
447 if (i != downstreamAddrMap.end()) {
448 const auto mapping = i->second.contains(addr);
449 if (mapping != i->second.end())
450 return mapping->second;
451 }
452 }
453 fatal("%s: couldn't find mapping for address %x mtype=%s\n",
454 name(), addr, mtype);
455}
456
457
458void
464
465void
472
473void
480
481Addr
486
487Addr
492
493std::string
498
501{
502 assert(m_ruby_system != nullptr);
504
506 for (NodeID i = 0; i < type_count; i++) {
507 MachineID mach = {type, i};
508 dest.add(mach);
509 }
510 return dest;
511}
512
513int
515{
516 assert(m_ruby_system != nullptr);
517 return m_ruby_system->MachineType_base_count(machType);
518}
519
520bool
525
526void
528{
529 controller->m_waiting_mem_retry = false;
530 controller->serviceMemoryQueue();
531}
532
534 AbstractController *_controller,
535 PortID id)
536 : RequestPort(_name, id), controller(_controller)
537{
538}
539
542 : statistics::Group(parent),
543 ADD_STAT(fullyBusyCycles,
544 "cycles for which number of transistions == max transitions"),
545 ADD_STAT(delayHistogram, "delay_histogram")
546{
551}
552
553} // namespace ruby
554} // namespace gem5
#define DPRINTF(x,...)
Definition trace.hh:209
The ClockedObject class extends the SimObject with a clock and accessor functions to relate ticks to ...
ClockedObjectParams Params
Parameters of ClockedObject.
Tick clockEdge(Cycles cycles=Cycles(0)) const
Determine the tick when a cycle begins, by default the current one, but the argument also enables the...
Tick cyclesToTicks(Cycles c) const
Cycles ticksToCycles(Tick t) const
Cycles is a wrapper class for representing cycle counts, i.e.
Definition types.hh:79
const std::string _name
Definition named.hh:41
virtual std::string name() const
Definition named.hh:47
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition packet.hh:295
bool isRead() const
Definition packet.hh:593
Addr getAddr() const
Definition packet.hh:807
bool isResponse() const
Definition packet.hh:598
static PacketPtr createWrite(const RequestPtr &req)
Definition packet.hh:1044
SenderState * senderState
This packet's sender state.
Definition packet.hh:545
void pushSenderState(SenderState *sender_state)
Push a new sender state to the packet and make the current sender state the predecessor of the new on...
Definition packet.cc:334
T * getPtr()
get a pointer to the data ptr.
Definition packet.hh:1225
void setData(const uint8_t *p)
Copy data into the packet from the provided pointer.
Definition packet.hh:1293
bool isWrite() const
Definition packet.hh:594
static PacketPtr createRead(const RequestPtr &req)
Constructor-like methods that return Packets based on Request objects.
Definition packet.hh:1038
void dataDynamic(T *p)
Set the data pointer to a value that should have delete [] called on it.
Definition packet.hh:1213
void allocate()
Allocate memory for the packet.
Definition packet.hh:1367
Ports are used to interface objects to each other.
Definition port.hh:62
A RequestPort is a specialisation of a Port, which implements the default protocol for the three diff...
Definition port.hh:136
virtual void sendRetryResp()
Send a retry to the response port that previously attempted a sendTimingResp to this request port and...
Definition port.hh:637
Tick sendAtomic(PacketPtr pkt)
Send an atomic request packet, where the data is moved and the state is updated in zero time,...
Definition port.hh:552
bool sendTimingReq(PacketPtr pkt)
Attempt to send a timing request to the responder port by calling its corresponding receive function.
Definition port.hh:603
void sendFunctional(PacketPtr pkt) const
Send a functional request packet, where the data is instantly updated everywhere in the memory system...
Definition port.hh:579
MemoryPort(const std::string &_name, AbstractController *_controller, PortID id=InvalidPortID)
bool recvTimingResp(PacketPtr pkt)
Receive a timing response from the peer.
void recvReqRetry()
Called by the peer if sendTimingReq was called on this peer (causing recvTimingReq to be called on th...
std::vector< MessageBuffer * > MsgVecType
void profileMsgDelay(uint32_t virtualNetwork, Cycles delay)
Profiles the delay associated with messages.
void wakeUpBuffer(MessageBuffer *buf, Addr addr)
virtual void regStats()
Callback to set stat parameters.
std::unordered_map< MachineType, AddrRangeMap< MachineID, 3 > > downstreamAddrMap
virtual MessageBuffer * getMemReqQueue() const =0
std::set< MessageBuffer * > MsgBufType
MachineID mapAddressToDownstreamMachine(Addr addr, MachineType mtype=MachineType_NUM) const
Maps an address to the correct dowstream MachineID (i.e.
virtual void collateStats()
Function for collating statistics from all the controllers of this particular type.
NetDest broadcast(MachineType type)
virtual MessageBuffer * getMemRespQueue() const =0
void init()
init() is called after all C++ SimObjects have been created and all ports are connected.
MemberEventWrapper<&AbstractController::sendRetryRespToMem > mRetryRespEvent
virtual void resetStats()=0
Callback to reset stats.
void blockOnQueue(Addr, MessageBuffer *)
MachineID mapAddressToMachine(Addr addr, MachineType mtype) const
Map an address to the correct MachineID.
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID)
A function used to return the port associated with this bus object.
gem5::ruby::AbstractController::ControllerStats stats
std::map< Addr, MessageBuffer * > m_block_map
Addr makeLineAddress(Addr addr) const
int machineCount(MachineType machType)
void stallBuffer(MessageBuffer *buf, Addr addr)
std::string printAddress(Addr addr) const
void scheduleEvent(Cycles timeDelta)
Definition Consumer.cc:56
void setConsumer(Consumer *consumer)
bool functionalRead(Packet *pkt)
void reanalyzeMessages(Addr addr, Tick current_time)
void add(MachineID newElement)
Definition NetDest.cc:52
void setRubySystem(RubySystem *rs)
Definition NetDest.hh:104
static uint32_t getNumberOfVirtualNetworks()
Definition Network.hh:91
NodeID addressToNodeID(Addr addr, MachineType mtype)
Map an address to the correct NodeID.
Definition Network.cc:237
uint32_t getBlockSizeBits()
Definition RubySystem.hh:74
uint32_t getBlockSizeBytes()
Definition RubySystem.hh:73
int MachineType_base_count(const MachineType &obj)
Derived & flags(Flags _flags)
Set the flags and marks this stat to print at the end of simulation.
void sample(const U &v, int n=1)
Add a value to the distribtion n times.
void reset()
Reset stat value to default.
Statistics container.
Definition group.hh:93
A simple histogram stat.
Histogram & init(size_type size)
Set the parameters of this histogram.
STL vector class.
Definition stl.hh:37
#define ADD_STAT(n,...)
Convenience macro to add a stat to a statistics group.
Definition group.hh:75
bool scheduled() const
Determine if the current event is scheduled.
Definition eventq.hh:458
void schedule(Event &event, Tick when)
Definition eventq.hh:1012
#define panic(...)
This implements a cprintf based panic() function.
Definition logging.hh:188
#define gem5_assert(cond,...)
The assert macro will function like a normal assert, but will use panic instead of straight abort().
Definition logging.hh:317
#define fatal(...)
This implements a cprintf based fatal() function.
Definition logging.hh:200
const Params & params() const
static SimObject * find(const char *name)
Find the SimObject with the given name and return a pointer to it.
virtual void regStats()
Callback to set stat parameters.
Definition group.cc:68
virtual void resetStats()
Callback to reset stats.
Definition group.cc:86
Bitfield< 4 > s
Bitfield< 27 > q
Definition misc_types.hh:55
Bitfield< 7 > i
Definition misc_types.hh:67
Bitfield< 33 > id
Bitfield< 0 > p
Bitfield< 15 > system
Definition misc.hh:1032
Bitfield< 3 > addr
Definition types.hh:84
Addr makeLineAddress(Addr addr, int cacheLineBits)
Definition Address.cc:61
unsigned int NodeID
std::string printAddress(Addr addr, int cacheLineBits)
Definition Address.cc:76
Addr getOffset(Addr addr, int cacheLineBits)
Definition Address.cc:54
void registerDumpCallback(const std::function< void()> &callback)
Register a callback that should be called whenever statistics are about to be dumped.
const FlagsType nozero
Don't print if this is zero.
Definition info.hh:67
Copyright (c) 2024 Arm Limited All rights reserved.
Definition binary32.hh:36
std::shared_ptr< Request > RequestPtr
Definition request.hh:94
Tick curTick()
The universal simulation clock.
Definition cur_tick.hh:46
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition types.hh:147
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition types.hh:245
uint64_t Tick
Tick count type.
Definition types.hh:58
std::string csprintf(const char *format, const Args &...args)
Definition cprintf.hh:161
statistics::Scalar fullyBusyCycles
Counter for the number of cycles when the transitions carried out were equal to the maximum allowed.
statistics::Histogram delayHistogram
Histogram for profiling delay for the messages this controller cares for.
std::vector< statistics::Histogram * > delayVCHistogram
MachineType getType() const
Definition MachineID.hh:66
const std::string & name()
Definition trace.cc:48

Generated on Mon Jan 13 2025 04:28:40 for gem5 by doxygen 1.9.8