gem5  v22.0.0.2
AbstractController.cc
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40 
42 
43 #include "debug/RubyQueue.hh"
45 #include "mem/ruby/protocol/MemoryMsg.hh"
48 #include "sim/system.hh"
49 
50 namespace gem5
51 {
52 
53 namespace ruby
54 {
55 
57  : ClockedObject(p), Consumer(this), m_version(p.version),
58  m_clusterID(p.cluster_id),
59  m_id(p.system->getRequestorId(this)), m_is_blocking(false),
60  m_number_of_TBEs(p.number_of_TBEs),
61  m_transitions_per_cycle(p.transitions_per_cycle),
62  m_buffer_size(p.buffer_size), m_recycle_latency(p.recycle_latency),
63  m_mandatory_queue_latency(p.mandatory_queue_latency),
64  m_waiting_mem_retry(false),
65  memoryPort(csprintf("%s.memory", name()), this),
66  addrRanges(p.addr_ranges.begin(), p.addr_ranges.end()),
67  stats(this)
68 {
69  if (m_version == 0) {
70  // Combine the statistics from all controllers
71  // of this particular type.
73  }
74 }
75 
76 void
78 {
80  uint32_t size = Network::getNumberOfVirtualNetworks();
81  for (uint32_t i = 0; i < size; i++) {
82  stats.delayVCHistogram.push_back(new statistics::Histogram(this));
83  stats.delayVCHistogram[i]->init(10);
84  }
85 
86  if (getMemReqQueue()) {
87  getMemReqQueue()->setConsumer(this);
88  }
89 
90  // Initialize the addr->downstream machine mappings. Multiple machines
91  // in downstream_destinations can have the same address range if they have
92  // different types. If this is the case, mapAddressToDownstreamMachine
93  // needs to specify the machine type
95  for (auto abs_cntrl : params().downstream_destinations) {
96  MachineID mid = abs_cntrl->getMachineID();
97  const AddrRangeList &ranges = abs_cntrl->getAddrRanges();
98  for (const auto &addr_range : ranges) {
99  auto i = downstreamAddrMap.intersects(addr_range);
100  if (i == downstreamAddrMap.end()) {
101  i = downstreamAddrMap.insert(addr_range, AddrMapEntry());
102  }
103  AddrMapEntry &entry = i->second;
104  fatal_if(entry.count(mid.getType()) > 0,
105  "%s: %s mapped to multiple machines of the same type\n",
106  name(), addr_range.to_string());
107  entry[mid.getType()] = mid;
108  }
110  }
111  // Initialize the addr->upstream machine list.
112  // We do not need to map address -> upstream machine,
113  // so we don't examine the address ranges
115  for (auto abs_cntrl : params().upstream_destinations) {
116  upstreamDestinations.add(abs_cntrl->getMachineID());
117  }
118 }
119 
120 void
122 {
124  uint32_t size = Network::getNumberOfVirtualNetworks();
125  for (uint32_t i = 0; i < size; i++) {
126  stats.delayVCHistogram[i]->reset();
127  }
128 }
129 
130 void
132 {
134 }
135 
136 void
137 AbstractController::profileMsgDelay(uint32_t virtualNetwork, Cycles delay)
138 {
139  assert(virtualNetwork < stats.delayVCHistogram.size());
140  stats.delayHistogram.sample(delay);
141  stats.delayVCHistogram[virtualNetwork]->sample(delay);
142 }
143 
144 void
146 {
147  if (m_waiting_buffers.count(addr) == 0) {
148  MsgVecType* msgVec = new MsgVecType;
149  msgVec->resize(m_in_ports, NULL);
150  m_waiting_buffers[addr] = msgVec;
151  }
152  DPRINTF(RubyQueue, "stalling %s port %d addr %#x\n", buf, m_cur_in_port,
153  addr);
154  assert(m_in_ports > m_cur_in_port);
155  (*(m_waiting_buffers[addr]))[m_cur_in_port] = buf;
156 }
157 
158 void
160 {
161  auto iter = m_waiting_buffers.find(addr);
162  if (iter != m_waiting_buffers.end()) {
163  bool has_other_msgs = false;
164  MsgVecType* msgVec = iter->second;
165  for (unsigned int port = 0; port < msgVec->size(); ++port) {
166  if ((*msgVec)[port] == buf) {
168  (*msgVec)[port] = NULL;
169  } else if ((*msgVec)[port] != NULL) {
170  has_other_msgs = true;
171  }
172  }
173  if (!has_other_msgs) {
174  delete msgVec;
175  m_waiting_buffers.erase(iter);
176  }
177  }
178 }
179 
180 void
182 {
183  if (m_waiting_buffers.count(addr) > 0) {
184  //
185  // Wake up all possible lower rank (i.e. lower priority) buffers that could
186  // be waiting on this message.
187  //
188  for (int in_port_rank = m_cur_in_port - 1;
189  in_port_rank >= 0;
190  in_port_rank--) {
191  if ((*(m_waiting_buffers[addr]))[in_port_rank] != NULL) {
192  (*(m_waiting_buffers[addr]))[in_port_rank]->
193  reanalyzeMessages(addr, clockEdge());
194  }
195  }
196  delete m_waiting_buffers[addr];
197  m_waiting_buffers.erase(addr);
198  }
199 }
200 
201 void
203 {
204  if (m_waiting_buffers.count(addr) > 0) {
205  //
206  // Wake up all possible buffers that could be waiting on this message.
207  //
208  for (int in_port_rank = m_in_ports - 1;
209  in_port_rank >= 0;
210  in_port_rank--) {
211  if ((*(m_waiting_buffers[addr]))[in_port_rank] != NULL) {
212  (*(m_waiting_buffers[addr]))[in_port_rank]->
213  reanalyzeMessages(addr, clockEdge());
214  }
215  }
216  delete m_waiting_buffers[addr];
217  m_waiting_buffers.erase(addr);
218  }
219 }
220 
221 void
223 {
224  //
225  // Wake up all possible buffers that could be waiting on any message.
226  //
227 
228  std::vector<MsgVecType*> wokeUpMsgVecs;
229  MsgBufType wokeUpMsgBufs;
230 
231  if (m_waiting_buffers.size() > 0) {
232  for (WaitingBufType::iterator buf_iter = m_waiting_buffers.begin();
233  buf_iter != m_waiting_buffers.end();
234  ++buf_iter) {
235  for (MsgVecType::iterator vec_iter = buf_iter->second->begin();
236  vec_iter != buf_iter->second->end();
237  ++vec_iter) {
238  //
239  // Make sure the MessageBuffer has not already be reanalyzed
240  //
241  if (*vec_iter != NULL &&
242  (wokeUpMsgBufs.count(*vec_iter) == 0)) {
243  (*vec_iter)->reanalyzeAllMessages(clockEdge());
244  wokeUpMsgBufs.insert(*vec_iter);
245  }
246  }
247  wokeUpMsgVecs.push_back(buf_iter->second);
248  }
249 
250  for (std::vector<MsgVecType*>::iterator wb_iter = wokeUpMsgVecs.begin();
251  wb_iter != wokeUpMsgVecs.end();
252  ++wb_iter) {
253  delete (*wb_iter);
254  }
255 
256  m_waiting_buffers.clear();
257  }
258 }
259 
260 bool
262 {
263  auto mem_queue = getMemReqQueue();
264  assert(mem_queue);
265  if (m_waiting_mem_retry || !mem_queue->isReady(clockEdge())) {
266  return false;
267  }
268 
269  const MemoryMsg *mem_msg = (const MemoryMsg*)mem_queue->peek();
270  unsigned int req_size = RubySystem::getBlockSizeBytes();
271  if (mem_msg->m_Len > 0) {
272  req_size = mem_msg->m_Len;
273  }
274 
275  RequestPtr req
276  = std::make_shared<Request>(mem_msg->m_addr, req_size, 0, m_id);
277  PacketPtr pkt;
278  if (mem_msg->getType() == MemoryRequestType_MEMORY_WB) {
279  pkt = Packet::createWrite(req);
280  pkt->allocate();
281  pkt->setData(mem_msg->m_DataBlk.getData(getOffset(mem_msg->m_addr),
282  req_size));
283  } else if (mem_msg->getType() == MemoryRequestType_MEMORY_READ) {
284  pkt = Packet::createRead(req);
285  uint8_t *newData = new uint8_t[req_size];
286  pkt->dataDynamic(newData);
287  } else {
288  panic("Unknown memory request type (%s) for addr %p",
289  MemoryRequestType_to_string(mem_msg->getType()),
290  mem_msg->m_addr);
291  }
292 
293  SenderState *s = new SenderState(mem_msg->m_Sender);
294  pkt->pushSenderState(s);
295 
297  // Use functional rather than timing accesses during warmup
298  mem_queue->dequeue(clockEdge());
300  // Since the queue was popped the controller may be able
301  // to make more progress. Make sure it wakes up
302  scheduleEvent(Cycles(1));
303  recvTimingResp(pkt);
304  } else if (memoryPort.sendTimingReq(pkt)) {
305  mem_queue->dequeue(clockEdge());
306  // Since the queue was popped the controller may be able
307  // to make more progress. Make sure it wakes up
308  scheduleEvent(Cycles(1));
309  } else {
310  scheduleEvent(Cycles(1));
311  m_waiting_mem_retry = true;
312  delete pkt;
313  delete s;
314  }
315 
316  return true;
317 }
318 
319 void
321 {
322  m_is_blocking = true;
323  m_block_map[addr] = port;
324 }
325 
326 bool
328 {
329  return m_is_blocking && (m_block_map.find(addr) != m_block_map.end());
330 }
331 
332 void
334 {
335  m_block_map.erase(addr);
336  if (m_block_map.size() == 0) {
337  m_is_blocking = false;
338  }
339 }
340 
341 bool
343 {
344  return (m_block_map.count(addr) > 0);
345 }
346 
347 Port &
348 AbstractController::getPort(const std::string &if_name, PortID idx)
349 {
350  return memoryPort;
351 }
352 
353 void
355 {
356  // read from mem. req. queue if write data is pending there
357  MessageBuffer *req_queue = getMemReqQueue();
358  if (!req_queue || !req_queue->functionalRead(pkt))
360 }
361 
362 int
364 {
365  int num_functional_writes = 0;
366 
367  // Update memory itself.
369  return num_functional_writes + 1;
370 }
371 
372 void
374 {
375  assert(getMemRespQueue());
376  assert(pkt->isResponse());
377 
378  std::shared_ptr<MemoryMsg> msg = std::make_shared<MemoryMsg>(clockEdge());
379  (*msg).m_addr = pkt->getAddr();
380  (*msg).m_Sender = m_machineID;
381 
382  SenderState *s = dynamic_cast<SenderState *>(pkt->senderState);
383  (*msg).m_OriginalRequestorMachId = s->id;
384  delete s;
385 
386  if (pkt->isRead()) {
387  (*msg).m_Type = MemoryRequestType_MEMORY_READ;
388  (*msg).m_MessageSize = MessageSizeType_Response_Data;
389 
390  // Copy data from the packet
391  (*msg).m_DataBlk.setData(pkt->getPtr<uint8_t>(), 0,
393  } else if (pkt->isWrite()) {
394  (*msg).m_Type = MemoryRequestType_MEMORY_WB;
395  (*msg).m_MessageSize = MessageSizeType_Writeback_Control;
396  } else {
397  panic("Incorrect packet type received from memory controller!");
398  }
399 
401  delete pkt;
402 }
403 
404 Tick
406 {
407  return ticksToCycles(memoryPort.sendAtomic(pkt));
408 }
409 
410 MachineID
412 {
413  NodeID node = m_net_ptr->addressToNodeID(addr, mtype);
414  MachineID mach = {mtype, node};
415  return mach;
416 }
417 
418 MachineID
420 const
421 {
422  const auto i = downstreamAddrMap.contains(addr);
424  "%s: couldn't find mapping for address %x\n", name(), addr);
425 
426  const AddrMapEntry &entry = i->second;
427  assert(!entry.empty());
428 
429  if (mtype == MachineType_NUM) {
430  fatal_if(entry.size() > 1,
431  "%s: address %x mapped to multiple machine types.\n", name(), addr);
432  return entry.begin()->second;
433  } else {
434  auto j = entry.find(mtype);
435  fatal_if(j == entry.end(),
436  "%s: couldn't find mapping for address %x\n", name(), addr);
437  return j->second;
438  }
439 }
440 
441 
442 bool
444 {
446  return true;
447 }
448 
449 void
451 {
452  controller->m_waiting_mem_retry = false;
453  controller->serviceMemoryQueue();
454 }
455 
457  AbstractController *_controller,
458  PortID id)
459  : RequestPort(_name, _controller, id), controller(_controller)
460 {
461 }
462 
465  : statistics::Group(parent),
466  ADD_STAT(fullyBusyCycles,
467  "cycles for which number of transistions == max transitions"),
468  ADD_STAT(delayHistogram, "delay_histogram")
469 {
474 }
475 
476 } // namespace ruby
477 } // namespace gem5
gem5::ruby::MachineID::getType
MachineType getType() const
Definition: MachineID.hh:66
gem5::PortID
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:245
gem5::ruby::Network::getNumberOfVirtualNetworks
static uint32_t getNumberOfVirtualNetworks()
Definition: Network.hh:90
gem5::VegaISA::s
Bitfield< 1 > s
Definition: pagetable.hh:64
gem5::ruby::AbstractController::MsgBufType
std::set< MessageBuffer * > MsgBufType
Definition: AbstractController.hh:355
gem5::RequestPort::sendTimingReq
bool sendTimingReq(PacketPtr pkt)
Attempt to send a timing request to the responder port by calling its corresponding receive function.
Definition: port.hh:495
gem5::ruby::AbstractController::ControllerStats::fullyBusyCycles
statistics::Scalar fullyBusyCycles
Counter for the number of cycles when the transitions carried out were equal to the maximum allowed.
Definition: AbstractController.hh:434
system.hh
gem5::ruby::AbstractController::getMemReqQueue
virtual MessageBuffer * getMemReqQueue() const =0
gem5::ruby::AbstractController::profileMsgDelay
void profileMsgDelay(uint32_t virtualNetwork, Cycles delay)
Profiles the delay associated with messages.
Definition: AbstractController.cc:137
gem5::Packet::setData
void setData(const uint8_t *p)
Copy data into the packet from the provided pointer.
Definition: packet.hh:1265
gem5::Packet::pushSenderState
void pushSenderState(SenderState *sender_state)
Push a new sender state to the packet and make the current sender state the predecessor of the new on...
Definition: packet.cc:330
gem5::RequestPort::sendAtomic
Tick sendAtomic(PacketPtr pkt)
Send an atomic request packet, where the data is moved and the state is updated in zero time,...
Definition: port.hh:464
gem5::ruby::AbstractController::serviceMemoryQueue
bool serviceMemoryQueue()
Definition: AbstractController.cc:261
gem5::statistics::nozero
const FlagsType nozero
Don't print if this is zero.
Definition: info.hh:68
gem5::ruby::AbstractController::wakeUpBuffers
void wakeUpBuffers(Addr addr)
Definition: AbstractController.cc:181
gem5::ruby::AbstractController::resetStats
virtual void resetStats()=0
Callback to reset stats.
Definition: AbstractController.cc:121
AbstractController.hh
gem5::ruby::MessageBuffer::enqueue
void enqueue(MsgPtr message, Tick curTime, Tick delta)
Definition: MessageBuffer.cc:217
gem5::Packet::isWrite
bool isWrite() const
Definition: packet.hh:591
gem5::ruby::RubySystem::getBlockSizeBytes
static uint32_t getBlockSizeBytes()
Definition: RubySystem.hh:72
gem5::Packet::createWrite
static PacketPtr createWrite(const RequestPtr &req)
Definition: packet.hh:1026
gem5::X86ISA::system
Bitfield< 15 > system
Definition: misc.hh:997
gem5::ruby::AbstractController::mapAddressToDownstreamMachine
MachineID mapAddressToDownstreamMachine(Addr addr, MachineType mtype=MachineType_NUM) const
Maps an address to the correct dowstream MachineID (i.e.
Definition: AbstractController.cc:419
std::vector
STL vector class.
Definition: stl.hh:37
gem5::ruby::AbstractController::m_block_map
std::map< Addr, MessageBuffer * > m_block_map
Definition: AbstractController.hh:352
gem5::ruby::AbstractController::isBlocked
bool isBlocked(Addr) const
Definition: AbstractController.cc:327
gem5::csprintf
std::string csprintf(const char *format, const Args &...args)
Definition: cprintf.hh:161
gem5::ruby::Consumer
Definition: Consumer.hh:61
gem5::ruby::AbstractController::getPort
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID)
A function used to return the port associated with this bus object.
Definition: AbstractController.cc:348
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:67
gem5::ruby::AbstractController::MsgVecType
std::vector< MessageBuffer * > MsgVecType
Definition: AbstractController.hh:354
gem5::ruby::AbstractController::m_is_blocking
bool m_is_blocking
Definition: AbstractController.hh:351
gem5::ruby::AbstractController
Definition: AbstractController.hh:82
gem5::ruby::MessageBuffer::reanalyzeMessages
void reanalyzeMessages(Addr addr, Tick current_time)
Definition: MessageBuffer.cc:403
gem5::statistics::DistBase::sample
void sample(const U &v, int n=1)
Add a value to the distribtion n times.
Definition: statistics.hh:1328
gem5::ruby::AbstractController::ControllerStats::delayHistogram
statistics::Histogram delayHistogram
Histogram for profiling delay for the messages this controller cares for.
Definition: AbstractController.hh:438
gem5::ruby::AbstractController::m_waiting_mem_retry
bool m_waiting_mem_retry
Definition: AbstractController.hh:366
gem5::RequestPort
A RequestPort is a specialisation of a Port, which implements the default protocol for the three diff...
Definition: port.hh:77
gem5::AddrRangeMap::contains
const_iterator contains(const AddrRange &r) const
Find entry that contains the given address range.
Definition: addr_range_map.hh:90
gem5::statistics::registerDumpCallback
void registerDumpCallback(const std::function< void()> &callback)
Register a callback that should be called whenever statistics are about to be dumped.
Definition: statistics.cc:330
gem5::Cycles
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:78
gem5::statistics::Histogram
A simple histogram stat.
Definition: statistics.hh:2126
gem5::ruby::AbstractController::ControllerStats::delayVCHistogram
std::vector< statistics::Histogram * > delayVCHistogram
Definition: AbstractController.hh:439
gem5::ruby::AbstractController::MemoryPort::recvReqRetry
void recvReqRetry()
Called by the peer if sendTimingReq was called on this peer (causing recvTimingReq to be called on th...
Definition: AbstractController.cc:450
gem5::ArmISA::j
Bitfield< 24 > j
Definition: misc_types.hh:57
gem5::ruby::AbstractController::collateStats
virtual void collateStats()
Function for collating statistics from all the controllers of this particular type.
Definition: AbstractController.hh:158
gem5::RequestPort::sendFunctional
void sendFunctional(PacketPtr pkt) const
Send a functional request packet, where the data is instantly updated everywhere in the memory system...
Definition: port.hh:485
gem5::Packet::isRead
bool isRead() const
Definition: packet.hh:590
gem5::ruby::AbstractController::functionalMemoryWrite
int functionalMemoryWrite(PacketPtr)
Definition: AbstractController.cc:363
gem5::Named::name
virtual std::string name() const
Definition: named.hh:47
gem5::VegaISA::p
Bitfield< 54 > p
Definition: pagetable.hh:70
gem5::Clocked::cyclesToTicks
Tick cyclesToTicks(Cycles c) const
Definition: clocked_object.hh:227
gem5::SimObject::params
const Params & params() const
Definition: sim_object.hh:176
gem5::ruby::Consumer::scheduleEvent
void scheduleEvent(Cycles timeDelta)
Definition: Consumer.cc:56
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
ADD_STAT
#define ADD_STAT(n,...)
Convenience macro to add a stat to a statistics group.
Definition: group.hh:75
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:291
gem5::ruby::MessageBuffer::functionalRead
bool functionalRead(Packet *pkt)
Definition: MessageBuffer.hh:182
gem5::ruby::AbstractController::mapAddressToMachine
MachineID mapAddressToMachine(Addr addr, MachineType mtype) const
Map an address to the correct MachineID.
Definition: AbstractController.cc:411
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::ruby::AbstractController::recvAtomic
Tick recvAtomic(PacketPtr pkt)
Definition: AbstractController.cc:405
gem5::ruby::AbstractController::ControllerStats::ControllerStats
ControllerStats(statistics::Group *parent)
Definition: AbstractController.cc:464
gem5::ruby::AbstractController::m_cur_in_port
unsigned int m_cur_in_port
Definition: AbstractController.hh:360
gem5::ruby::AbstractController::downstreamDestinations
NetDest downstreamDestinations
Definition: AbstractController.hh:412
gem5::ruby::getOffset
Addr getOffset(Addr addr)
Definition: Address.cc:54
gem5::AddrRangeMap::end
const_iterator end() const
Definition: addr_range_map.hh:217
gem5::ruby::AbstractController::MemoryPort::MemoryPort
MemoryPort(const std::string &_name, AbstractController *_controller, PortID id=InvalidPortID)
Definition: AbstractController.cc:456
gem5::ruby::AbstractController::AbstractController
AbstractController(const Params &p)
Definition: AbstractController.cc:56
RubySystem.hh
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::statistics::Histogram::init
Histogram & init(size_type size)
Set the parameters of this histogram.
Definition: statistics.hh:2154
gem5::Packet::senderState
SenderState * senderState
This packet's sender state.
Definition: packet.hh:542
name
const std::string & name()
Definition: trace.cc:49
gem5::ruby::AbstractController::SenderState
Definition: AbstractController.hh:395
gem5::ruby::AbstractController::m_waiting_buffers
WaitingBufType m_waiting_buffers
Definition: AbstractController.hh:357
gem5::ruby::AbstractController::m_machineID
MachineID m_machineID
Definition: AbstractController.hh:344
gem5::statistics::Group::regStats
virtual void regStats()
Callback to set stat parameters.
Definition: group.cc:69
gem5::ruby::AbstractController::m_version
const NodeID m_version
Definition: AbstractController.hh:343
gem5::ClockedObject
The ClockedObject class extends the SimObject with a clock and accessor functions to relate ticks to ...
Definition: clocked_object.hh:234
gem5::Clocked::clockEdge
Tick clockEdge(Cycles cycles=Cycles(0)) const
Determine the tick when a cycle begins, by default the current one, but the argument also enables the...
Definition: clocked_object.hh:177
gem5::ruby::AbstractController::init
void init()
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: AbstractController.cc:77
gem5::ruby::AbstractController::unblock
void unblock(Addr)
Definition: AbstractController.cc:333
gem5::ruby::AbstractController::stats
gem5::ruby::AbstractController::ControllerStats stats
gem5::ruby::MessageBuffer::setConsumer
void setConsumer(Consumer *consumer)
Definition: MessageBuffer.hh:105
Network.hh
gem5::ruby::AbstractController::wakeUpAllBuffers
void wakeUpAllBuffers()
Definition: AbstractController.cc:222
gem5::AddrRangeMap::intersects
const_iterator intersects(const AddrRange &r) const
Find entry that intersects with the given address range.
Definition: addr_range_map.hh:140
gem5::Packet::allocate
void allocate()
Allocate memory for the packet.
Definition: packet.hh:1339
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
gem5::ruby::AbstractController::m_in_ports
unsigned int m_in_ports
Definition: AbstractController.hh:359
gem5::ruby::Network::addressToNodeID
NodeID addressToNodeID(Addr addr, MachineType mtype)
Map an address to the correct NodeID.
Definition: Network.cc:235
gem5::ruby::AbstractController::MemoryPort::recvTimingResp
bool recvTimingResp(PacketPtr pkt)
Receive a timing response from the peer.
Definition: AbstractController.cc:443
gem5::ruby::RubySystem::getWarmupEnabled
static bool getWarmupEnabled()
Definition: RubySystem.hh:75
gem5::ruby::AbstractController::m_net_ptr
Network * m_net_ptr
Definition: AbstractController.hh:350
gem5::ruby::AbstractController::functionalMemoryRead
void functionalMemoryRead(PacketPtr)
Definition: AbstractController.cc:354
gem5::ruby::AbstractController::upstreamDestinations
NetDest upstreamDestinations
Definition: AbstractController.hh:413
gem5::Packet::dataDynamic
void dataDynamic(T *p)
Set the data pointer to a value that should have delete [] called on it.
Definition: packet.hh:1185
gem5::AddrRangeMap::insert
iterator insert(const AddrRange &r, const V &d)
Definition: addr_range_map.hh:155
gem5::ruby::NetDest::resize
void resize()
Definition: NetDest.cc:253
gem5::statistics::Group
Statistics container.
Definition: group.hh:93
gem5::ruby::AbstractController::m_id
const RequestorID m_id
Definition: AbstractController.hh:348
gem5::ArmISA::id
Bitfield< 33 > id
Definition: misc_types.hh:251
gem5::ruby::NodeID
unsigned int NodeID
Definition: TypeDefines.hh:42
gem5::ruby::NetDest::add
void add(MachineID newElement)
Definition: NetDest.cc:45
gem5::ruby::AbstractController::AddrMapEntry
std::unordered_map< MachineType, MachineID > AddrMapEntry
Definition: AbstractController.hh:408
gem5::ruby::AbstractController::regStats
virtual void regStats()
Callback to set stat parameters.
Definition: AbstractController.cc:131
gem5::ruby::AbstractController::MemoryPort::controller
AbstractController * controller
Definition: AbstractController.hh:376
gem5::statistics::DistBase::reset
void reset()
Reset stat value to default.
Definition: statistics.hh:1352
gem5::ClockedObject::Params
ClockedObjectParams Params
Parameters of ClockedObject.
Definition: clocked_object.hh:240
gem5::statistics::DataWrap::flags
Derived & flags(Flags _flags)
Set the flags and marks this stat to print at the end of simulation.
Definition: statistics.hh:358
gem5::ruby::AbstractController::downstreamAddrMap
AddrRangeMap< AddrMapEntry, 3 > downstreamAddrMap
Definition: AbstractController.hh:410
gem5::Clocked::ticksToCycles
Cycles ticksToCycles(Tick t) const
Definition: clocked_object.hh:222
gem5::ruby::AbstractController::memoryPort
MemoryPort memoryPort
Definition: AbstractController.hh:392
gem5::ruby::MessageBuffer
Definition: MessageBuffer.hh:74
std::list< AddrRange >
gem5::Packet::getAddr
Addr getAddr() const
Definition: packet.hh:790
fatal_if
#define fatal_if(cond,...)
Conditional fatal macro that checks the supplied condition and only causes a fatal error if the condi...
Definition: logging.hh:226
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::Packet::createRead
static PacketPtr createRead(const RequestPtr &req)
Constructor-like methods that return Packets based on Request objects.
Definition: packet.hh:1020
gem5::ruby::AbstractController::getMemRespQueue
virtual MessageBuffer * getMemRespQueue() const =0
gem5::ruby::MachineID
Definition: MachineID.hh:56
gem5::ruby::AbstractController::blockOnQueue
void blockOnQueue(Addr, MessageBuffer *)
Definition: AbstractController.cc:320
gem5::Packet::isResponse
bool isResponse() const
Definition: packet.hh:595
gem5::ruby::AbstractController::recvTimingResp
void recvTimingResp(PacketPtr pkt)
Definition: AbstractController.cc:373
gem5::Named::_name
const std::string _name
Definition: named.hh:41
gem5::ruby::AbstractController::wakeUpBuffer
void wakeUpBuffer(MessageBuffer *buf, Addr addr)
Definition: AbstractController.cc:159
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::ruby::AbstractController::stallBuffer
void stallBuffer(MessageBuffer *buf, Addr addr)
Definition: AbstractController.cc:145
gem5::SenderState
RubyTester::SenderState SenderState
Definition: Check.cc:40
gem5::Packet::getPtr
T * getPtr()
get a pointer to the data ptr.
Definition: packet.hh:1197
Sequencer.hh

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