gem5  v22.0.0.2
aapcs64.hh
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27 
28 #ifndef __ARCH_ARM_AAPCS64_HH__
29 #define __ARCH_ARM_AAPCS64_HH__
30 
31 #include <algorithm>
32 #include <array>
33 #include <type_traits>
34 #include <utility>
35 
36 #include "arch/arm/regs/int.hh"
37 #include "arch/arm/utility.hh"
38 #include "base/intmath.hh"
39 #include "cpu/thread_context.hh"
40 #include "sim/guest_abi.hh"
41 #include "sim/proxy_ptr.hh"
42 
43 namespace gem5
44 {
45 
46 class ThreadContext;
47 
48 struct Aapcs64
49 {
50  using UintPtr = uint64_t;
51 
52  struct State
53  {
54  int ngrn=0; // Next general purpose register number.
55  int nsrn=0; // Next SIMD and floating point register number.
56  Addr nsaa; // Next stacked argument address.
57 
58  // The maximum allowed general purpose register number.
59  static const int MAX_GRN = 7;
60  // The maximum allowed SIMD and floating point register number.
61  static const int MAX_SRN = 7;
62 
63  explicit State(const ThreadContext *tc) :
64  nsaa(tc->getReg(ArmISA::int_reg::Spx))
65  {}
66  };
67 };
68 
69 GEM5_DEPRECATED_NAMESPACE(GuestABI, guest_abi);
70 namespace guest_abi
71 {
72 
73 /*
74  * Short Vectors
75  */
76 
77 // A short vector is a machine type that is composed of repeated instances of
78 // one fundamental integral or floating- point type. It may be 8 or 16 bytes
79 // in total size.
80 
81 template <typename T, typename Enabled=void>
82 struct IsAapcs64ShortVector : public std::false_type {};
83 
84 template <typename E, size_t N>
86  typename std::enable_if_t<
87  (std::is_integral_v<E> || std::is_floating_point_v<E>) &&
88  (sizeof(E) * N == 8 || sizeof(E) * N == 16)>> :
89  public std::true_type
90 {};
91 
92 template <typename T>
94 
95 /*
96  * Composite Types
97  */
98 
99 template <typename T, typename Enabled=void>
100 struct IsAapcs64Composite : public std::false_type {};
101 
102 template <typename T>
103 struct IsAapcs64Composite<T, typename std::enable_if_t<
104  (std::is_array_v<T> || std::is_class_v<T> || std::is_union_v<T>) &&
105  // VarArgs is technically a composite type, but it's not a normal argument.
106  !IsVarArgsV<T> &&
107  // Short vectors are also composite types, but don't treat them as one.
108  !IsAapcs64ShortVectorV<T>
109  >> : public std::true_type
110 {};
111 
112 template <typename T>
114 
115 // Homogeneous Aggregates
116 // These *should* be any aggregate type which has only one type of member, but
117 // we can't actually detect that or manipulate that with templates. Instead,
118 // we approximate that by detecting only arrays with that property.
119 
120 // An Homogeneous Floating-Point Aggregate (HFA) is an Homogeneous Aggregate
121 // with a Fundemental Data Type that is a Floating-Point type and at most four
122 // uniquely addressable members.
123 
124 template <typename T, typename Enabled=void>
125 struct IsAapcs64Hfa : public std::false_type {};
126 
127 template <typename E, size_t N>
128 struct IsAapcs64Hfa<E[N],
129  typename std::enable_if_t<std::is_floating_point_v<E> && N <= 4>> :
130  public std::true_type
131 {};
132 
133 template <typename T>
134 constexpr bool IsAapcs64HfaV = IsAapcs64Hfa<T>::value;
135 
136 // An Homogeneous Short-Vector Aggregate (HVA) is an Homogeneous Aggregate with
137 // a Fundamental Data Type that is a Short-Vector type and at most four
138 // uniquely addressable members.
139 
140 template <typename T, typename Enabled=void>
141 struct IsAapcs64Hva : public std::false_type {};
142 
143 template <typename E, size_t N>
144 struct IsAapcs64Hva<E[N],
145  typename std::enable_if_t<IsAapcs64ShortVectorV<E> && N <= 4>> :
146  public std::true_type
147 {};
148 
149 template <typename T>
150 constexpr bool IsAapcs64HvaV = IsAapcs64Hva<T>::value;
151 
152 // A shorthand to test if a type is an HVA or an HFA.
153 template <typename T, typename Enabled=void>
154 struct IsAapcs64Hxa : public std::false_type {};
155 
156 template <typename T>
157 struct IsAapcs64Hxa<T, typename std::enable_if_t<
158  IsAapcs64HfaV<T> || IsAapcs64HvaV<T>>> :
159  public std::true_type
160 {};
161 
162 template <typename T>
163 constexpr bool IsAapcs64HxaV = IsAapcs64Hxa<T>::value;
164 
165 struct Aapcs64ArgumentBase
166 {
167  template <typename T>
168  static T
169  loadFromStack(ThreadContext *tc, Aapcs64::State &state)
170  {
171  // The alignment is the larger of 8 or the natural alignment of T.
172  size_t align = std::max<size_t>(8, alignof(T));
173  // Increase the size to the next multiple of 8.
174  size_t size = roundUp(sizeof(T), 8);
175 
176  // Align the stack.
177  state.nsaa = roundUp(state.nsaa, align);
178 
179  // Extract the value from it.
180  ConstVPtr<T> val(state.nsaa, tc);
181 
182  // Move the nsaa past this argument.
183  state.nsaa += size;
184 
185  // Return the value we extracted.
186  return gtoh(*val, ArmISA::byteOrder(tc));
187  }
188 };
189 
190 
191 /*
192  * Floating point and Short-Vector arguments and return values.
193  */
194 
195 template <typename Float>
196 struct Argument<Aapcs64, Float, typename std::enable_if_t<
197  std::is_floating_point_v<Float> || IsAapcs64ShortVectorV<Float>>> :
198  public Aapcs64ArgumentBase
199 {
200  static Float
201  get(ThreadContext *tc, Aapcs64::State &state)
202  {
203  if (state.nsrn <= state.MAX_SRN) {
204  RegId id(VecRegClass, state.nsrn++);
206  tc->getReg(id, &vc);
207  return vc.as<Float>()[0];
208  }
209 
210  return loadFromStack<Float>(tc, state);
211  }
212 };
213 
214 template <typename Float>
215 struct Result<Aapcs64, Float, typename std::enable_if_t<
216  std::is_floating_point_v<Float> || IsAapcs64ShortVectorV<Float>>>
217 {
218  static void
219  store(ThreadContext *tc, const Float &f)
220  {
221  RegId id(VecRegClass, 0);
223  tc->getReg(id, &reg);
224  reg.as<Float>()[0] = f;
225  tc->setReg(id, &reg);
226  }
227 };
228 
229 
230 /*
231  * Integer arguments and return values.
232  */
233 
234 // This will pick up Addr as well, which should be used for guest pointers.
235 template <typename Integer>
236 struct Argument<Aapcs64, Integer, typename std::enable_if_t<
237  std::is_integral_v<Integer> && (sizeof(Integer) <= 8)>> :
238  public Aapcs64ArgumentBase
239 {
240  static Integer
242  {
243  if (state.ngrn <= state.MAX_GRN)
244  return tc->getReg(RegId(IntRegClass, state.ngrn++));
245 
246  // Max out ngrn since we've effectively saturated it.
247  state.ngrn = state.MAX_GRN + 1;
248 
249  return loadFromStack<Integer>(tc, state);
250  }
251 };
252 
253 template <typename Integer>
254 struct Argument<Aapcs64, Integer, typename std::enable_if_t<
255  std::is_integral_v<Integer> && (sizeof(Integer) > 8)>> :
256  public Aapcs64ArgumentBase
257 {
258  static Integer
260  {
261  if (alignof(Integer) == 16 && (state.ngrn % 2))
262  state.ngrn++;
263 
264  if (sizeof(Integer) == 16 && state.ngrn + 1 <= state.MAX_GRN) {
265  Integer low = tc->getReg(RegId(IntRegClass, state.ngrn++));
266  Integer high = tc->getReg(RegId(IntRegClass, state.ngrn++));
267  high = high << 64;
268  return high | low;
269  }
270 
271  // Max out ngrn since we've effectively saturated it.
272  state.ngrn = state.MAX_GRN + 1;
273 
274  return loadFromStack<Integer>(tc, state);
275  }
276 };
277 
278 template <typename Integer>
279 struct Result<Aapcs64, Integer, typename std::enable_if_t<
280  std::is_integral_v<Integer> && (sizeof(Integer) <= 8)>>
281 {
282  static void
283  store(ThreadContext *tc, const Integer &i)
284  {
285  tc->setReg(ArmISA::int_reg::X0, i);
286  }
287 };
288 
289 template <typename Integer>
290 struct Result<Aapcs64, Integer, typename std::enable_if_t<
291  std::is_integral_v<Integer> && (sizeof(Integer) > 8)>>
292 {
293  static void
294  store(ThreadContext *tc, const Integer &i)
295  {
296  tc->setReg(ArmISA::int_reg::X0, (uint64_t)i);
297  tc->setReg(ArmISA::int_reg::X1, (uint64_t)(i >> 64));
298  }
299 };
300 
301 
302 /*
303  * Homogeneous Floating-Point and Short-Vector Aggregates (HFAs and HVAs)
304  * argument and return values.
305  */
306 
307 template <typename T>
308 struct Aapcs64ArrayType { using Type = void; };
309 
310 template <typename E, size_t N>
311 struct Aapcs64ArrayType<E[N]> { using Type = E; };
312 
313 template <typename HA>
314 struct Argument<Aapcs64, HA, typename std::enable_if_t<
315  IsAapcs64HxaV<HA>>> : public Aapcs64ArgumentBase
316 {
317  static HA
319  {
320  using Elem = typename Aapcs64ArrayType<HA>::Type;
321  constexpr size_t Count = sizeof(HA) / sizeof(Elem);
322 
323  if (state.nsrn + Count - 1 <= state.MAX_SRN) {
324  HA ha;
325  for (int i = 0; i < Count; i++)
327  return ha;
328  }
329 
330  // Max out the nsrn since we effectively exhausted it.
331  state.nsrn = state.MAX_SRN + 1;
332 
333  return loadFromStack<HA>(tc, state);
334  }
335 };
336 
337 template <typename HA>
338 struct Result<Aapcs64, HA, typename std::enable_if_t<IsAapcs64HxaV<HA>>>
339 {
340  static HA
341  store(ThreadContext *tc, const HA &ha)
342  {
343  using Elem = typename Aapcs64ArrayType<HA>::Type;
344  constexpr size_t Count = sizeof(HA) / sizeof(Elem);
345 
346  for (int i = 0; i < Count; i++)
348  }
349 };
350 
351 
352 /*
353  * Composite arguments and return values which are not HVAs or HFAs.
354  */
355 
356 template <typename Composite>
357 struct Argument<Aapcs64, Composite, typename std::enable_if_t<
358  IsAapcs64CompositeV<Composite> && !IsAapcs64HxaV<Composite>>> :
359  public Aapcs64ArgumentBase
360 {
361  static Composite
363  {
364  if (sizeof(Composite) > 16) {
365  // Composite values larger than 16 which aren't HFAs or HVAs are
366  // kept in a buffer, and the argument is actually a pointer to that
367  // buffer.
369  ConstVPtr<Composite> composite(addr, tc);
370  return gtoh(*composite, ArmISA::byteOrder(tc));
371  }
372 
373  // The size of Composite must be 16 bytes or less after this point.
374 
375  size_t bytes = sizeof(Composite);
376  using Chunk = uint64_t;
377 
378  const int chunk_size = sizeof(Chunk);
379  const int regs = (bytes + chunk_size - 1) / chunk_size;
380 
381  // Can it fit in GPRs?
382  if (state.ngrn + regs - 1 <= state.MAX_GRN) {
383  alignas(alignof(Composite)) uint8_t buf[bytes];
384  for (int i = 0; i < regs; i++) {
385  Chunk val = tc->getReg(RegId(IntRegClass, state.ngrn++));
386  val = htog(val, ArmISA::byteOrder(tc));
387  size_t to_copy = std::min<size_t>(bytes, chunk_size);
388  memcpy(buf + i * chunk_size, &val, to_copy);
389  bytes -= to_copy;
390  }
391  return gtoh(*(Composite *)buf, ArmISA::byteOrder(tc));
392  }
393 
394  // Max out the ngrn since we effectively exhausted it.
395  state.ngrn = state.MAX_GRN;
396 
397  return loadFromStack<Composite>(tc, state);
398  }
399 };
400 
401 template <typename Composite>
402 struct Result<Aapcs64, Composite, typename std::enable_if_t<
403  IsAapcs64CompositeV<Composite> && !IsAapcs64HxaV<Composite>>>
404 {
405  static void
406  store(ThreadContext *tc, const Composite &c)
407  {
408  if (sizeof(Composite) > 16) {
409  Addr addr = tc->getReg(ArmISA::int_reg::X8);
410  VPtr<Composite> composite(addr, tc);
411  *composite = htog(c, ArmISA::byteOrder(tc));
412  return;
413  }
414 
415  // The size of Composite must be 16 bytes or less after this point.
416 
417  size_t bytes = sizeof(Composite);
418  using Chunk = uint64_t;
419 
420  const int chunk_size = sizeof(Chunk);
421  const int regs = (bytes + chunk_size - 1) / chunk_size;
422 
423  Composite cp = htog(c, ArmISA::byteOrder(tc));
424  uint8_t *buf = (uint8_t *)&cp;
425  for (int i = 0; i < regs; i++) {
426  size_t to_copy = std::min<size_t>(bytes, chunk_size);
427 
428  Chunk val;
429  memcpy(&val, buf, to_copy);
430  val = gtoh(val, ArmISA::byteOrder(tc));
431 
433 
434  bytes -= to_copy;
435  buf += to_copy;
436  }
437  }
438 };
439 
440 } // namespace guest_abi
441 } // namespace gem5
442 
443 #endif // __ARCH_ARM_AAPCS64_HH__
gem5::VegaISA::f
Bitfield< 56 > f
Definition: pagetable.hh:53
gem5::ConstProxyPtr
Definition: proxy_ptr.hh:109
gem5::Aapcs64::State::nsrn
int nsrn
Definition: aapcs64.hh:55
gem5::statistics::Result
double Result
All results are doubles.
Definition: types.hh:56
gem5::ThreadContext::getReg
virtual RegVal getReg(const RegId &reg) const
Definition: thread_context.cc:171
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:769
gem5::ArmISA::byteOrder
ByteOrder byteOrder(const ThreadContext *tc)
Definition: utility.hh:370
proxy_ptr.hh
gem5::guest_abi::Aapcs64ArrayType< E[N]>::Type
E Type
Definition: aapcs64.hh:311
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:67
sc_dt::align
void align(const scfx_rep &lhs, const scfx_rep &rhs, int &new_wp, int &len_mant, scfx_mant_ref &lhs_mant, scfx_mant_ref &rhs_mant)
Definition: scfx_rep.cc:2083
gem5::Aapcs64::UintPtr
uint64_t UintPtr
Definition: aapcs64.hh:50
gem5::guest_abi::Argument< Aapcs64, Composite, typename std::enable_if_t< IsAapcs64CompositeV< Composite > &&!IsAapcs64HxaV< Composite > > >::get
static Composite get(ThreadContext *tc, Aapcs64::State &state)
Definition: aapcs64.hh:362
gem5::VegaISA::c
Bitfield< 2 > c
Definition: pagetable.hh:63
gem5::Aapcs64::State::MAX_GRN
static const int MAX_GRN
Definition: aapcs64.hh:59
gem5::high
high
Definition: intmath.hh:176
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::guest_abi::Aapcs64ArrayType
Definition: aapcs64.hh:308
gem5::VegaISA::x
Bitfield< 4 > x
Definition: pagetable.hh:61
gem5::Aapcs64::State::State
State(const ThreadContext *tc)
Definition: aapcs64.hh:63
gem5::guest_abi::IsAapcs64Composite
Definition: aapcs64.hh:100
gem5::gtoh
T gtoh(T value, ByteOrder guest_byte_order)
Definition: byteswap.hh:194
gem5::Aapcs64::State
Definition: aapcs64.hh:52
gem5::htog
T htog(T value, ByteOrder guest_byte_order)
Definition: byteswap.hh:187
gem5::guest_abi::Result< Aapcs64, Composite, typename std::enable_if_t< IsAapcs64CompositeV< Composite > &&!IsAapcs64HxaV< Composite > > >::store
static void store(ThreadContext *tc, const Composite &c)
Definition: aapcs64.hh:406
gem5::ProxyPtr
Definition: proxy_ptr.hh:238
gem5::guest_abi::enable_if_t< std::is_integral_v< Integer > &&(sizeof(Integer)<=8)> >::get
static Integer get(ThreadContext *tc, Aapcs64::State &state)
Definition: aapcs64.hh:241
gem5::ArmISA::VecRegContainer
gem5::VecRegContainer< NumVecElemPerVecReg *sizeof(VecElem)> VecRegContainer
Definition: vec.hh:62
gem5::guest_abi::Result< Aapcs64, HA, typename std::enable_if_t< IsAapcs64HxaV< HA > > >::store
static HA store(ThreadContext *tc, const HA &ha)
Definition: aapcs64.hh:341
gem5::guest_abi::enable_if_t< std::is_integral_v< Integer > &&(sizeof(Integer)<=8)> >::store
static void store(ThreadContext *tc, const Integer &i)
Definition: aapcs64.hh:283
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::GEM5_DEPRECATED_NAMESPACE
GEM5_DEPRECATED_NAMESPACE(GuestABI, guest_abi)
gem5::Aapcs64
Definition: aapcs64.hh:48
utility.hh
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::IntRegClass
@ IntRegClass
Integer register.
Definition: reg_class.hh:58
gem5::Aapcs64::State::MAX_SRN
static const int MAX_SRN
Definition: aapcs64.hh:61
state
atomic_var_t state
Definition: helpers.cc:188
gem5::guest_abi::IsAapcs64Hfa
Definition: aapcs64.hh:125
std
Overload hash function for BasicBlockRange type.
Definition: misc.hh:2388
gem5::guest_abi::IsAapcs64CompositeV
constexpr bool IsAapcs64CompositeV
Definition: aapcs64.hh:113
gem5::guest_abi::IsAapcs64ShortVectorV
constexpr bool IsAapcs64ShortVectorV
Definition: aapcs64.hh:93
guest_abi.hh
gem5::X86ISA::E
Bitfield< 31, 0 > E
Definition: int.hh:55
gem5::roundUp
static constexpr T roundUp(const T &val, const U &align)
This function is used to align addresses in memory.
Definition: intmath.hh:260
gem5::ArmISA::id
Bitfield< 33 > id
Definition: misc_types.hh:251
gem5::guest_abi::Argument
Definition: definition.hh:99
gem5::Aapcs64::State::nsaa
Addr nsaa
Definition: aapcs64.hh:56
gem5::VecRegClass
@ VecRegClass
Vector Register.
Definition: reg_class.hh:61
gem5::guest_abi::Aapcs64ArrayType::Type
void Type
Definition: aapcs64.hh:308
gem5::Aapcs64::State::ngrn
int ngrn
Definition: aapcs64.hh:54
gem5::guest_abi::Argument< Aapcs64, HA, typename std::enable_if_t< IsAapcs64HxaV< HA > > >::get
static HA get(ThreadContext *tc, Aapcs64::State &state)
Definition: aapcs64.hh:318
intmath.hh
gem5::guest_abi::IsAapcs64ShortVector
Definition: aapcs64.hh:82
gem5::guest_abi::Result
Definition: definition.hh:64
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::ArmISA::ha
Bitfield< 39 > ha
Definition: misc_types.hh:544
int.hh
thread_context.hh
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:126
gem5::guest_abi::getReg
struct IsAapcs64Hfa< E[N], typename std::enable_if_t< std::is_floating_point_v< E > &&N<=4 > > :public std::true_type{};template< typename T >constexpr bool IsAapcs64HfaV=IsAapcs64Hfa< T >::value;template< typename T, typename Enabled=void >struct IsAapcs64Hva :public std::false_type {};template< typename E, size_t N >struct IsAapcs64Hva< E[N], typename std::enable_if_t< IsAapcs64ShortVectorV< E > &&N<=4 > > :public std::true_type{};template< typename T >constexpr bool IsAapcs64HvaV=IsAapcs64Hva< T >::value;template< typename T, typename Enabled=void >struct IsAapcs64Hxa :public std::false_type {};template< typename T >struct IsAapcs64Hxa< T, typename std::enable_if_t< IsAapcs64HfaV< T >||IsAapcs64HvaV< T > > > :public std::true_type{};template< typename T >constexpr bool IsAapcs64HxaV=IsAapcs64Hxa< T >::value;struct Aapcs64ArgumentBase{ template< typename T > static T loadFromStack(ThreadContext *tc, Aapcs64::State &state) { size_t align=std::max< size_t >(8, alignof(T));size_t size=roundUp(sizeof(T), 8);state.nsaa=roundUp(state.nsaa, align);ConstVPtr< T > val(state.nsaa, tc);state.nsaa+=size;return gtoh(*val, ArmISA::byteOrder(tc));}};template< typename Float >struct Argument< Aapcs64, Float, typename std::enable_if_t< std::is_floating_point_v< Float >||IsAapcs64ShortVectorV< Float > > > :public Aapcs64ArgumentBase{ static Float get(ThreadContext *tc, Aapcs64::State &state) { if(state.nsrn<=state.MAX_SRN) { RegId id(VecRegClass, state.nsrn++);ArmISA::VecRegContainer vc;tc->getReg(id, &vc);return vc.as< Float >()[0];} return loadFromStack< Float >(tc, state);}};template< typename Float >struct Result< Aapcs64, Float, typename std::enable_if_t< std::is_floating_point_v< Float >||IsAapcs64ShortVectorV< Float > > >{ static void store(ThreadContext *tc, const Float &f) { RegId id(VecRegClass, 0);ArmISA::VecRegContainer reg;tc-> getReg(id, &reg)
Definition: aapcs64.hh:223
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::ThreadContext::setReg
virtual void setReg(const RegId &reg, RegVal val)
Definition: thread_context.cc:183

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