int.cc

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 * licensed hereunder.  You may use the software subject to the license
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 * Copyright (c) 2009 The Regents of The University of Michigan
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#include "arch/arm/regs/int.hh"
 
#include "arch/arm/isa.hh"
#include "arch/arm/regs/misc.hh"
#include "arch/arm/utility.hh"
#include "base/logging.hh"
 
namespace gem5
{
 
namespace ArmISA
{
 
RegId
IntRegClassOps::flatten(const BaseISA &isa, const RegId &id) const
{
    const RegIndex reg_idx = id.index();
 
    auto &arm_isa = static_cast<const ArmISA::ISA &>(isa);
 
    if (reg_idx < int_reg::NumArchRegs) {
        return {flatIntRegClass, arm_isa.mapIntRegId(reg_idx)};
    } else if (reg_idx < int_reg::NumRegs) {
        return {flatIntRegClass, id};
    } else if (reg_idx == int_reg::Spx) {
        auto &arm_isa = static_cast<const ArmISA::ISA &>(isa);
        CPSR cpsr = arm_isa.readMiscRegNoEffect(MISCREG_CPSR);
        ExceptionLevel el = opModeToEL((OperatingMode)(uint8_t)cpsr.mode);
 
        if (!cpsr.sp && el != EL0)
            return {flatIntRegClass, int_reg::Sp0};
 
        switch (el) {
          case EL3:
            return {flatIntRegClass, int_reg::Sp3};
          case EL2:
            return {flatIntRegClass, int_reg::Sp2};
          case EL1:
            return {flatIntRegClass, int_reg::Sp1};
          case EL0:
            return {flatIntRegClass, int_reg::Sp0};
          default:
            panic("Invalid exception level");
        }
    } else {
        return {flatIntRegClass, flattenIntRegModeIndex(reg_idx)};
    }
}
 
} // namespace ArmISA
} // namespace gem5