gem5  v21.1.0.2
tlb.hh
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40 
41 #ifndef __ARCH_ARM_TLB_HH__
42 #define __ARCH_ARM_TLB_HH__
43 
44 
45 #include "arch/arm/faults.hh"
46 #include "arch/arm/pagetable.hh"
47 #include "arch/arm/utility.hh"
48 #include "arch/generic/tlb.hh"
49 #include "base/statistics.hh"
50 #include "mem/request.hh"
51 #include "params/ArmTLB.hh"
52 #include "sim/probe/pmu.hh"
53 
54 namespace gem5
55 {
56 
57 class ThreadContext;
58 
59 namespace ArmISA {
60 
61 class TableWalker;
62 class Stage2LookUp;
63 class TLB;
64 
65 class TLBIALL;
66 class TLBIALLEL;
67 class TLBIVMALL;
68 class TLBIALLN;
69 class TLBIMVA;
70 class TLBIASID;
71 class TLBIMVAA;
72 
74 {
75  public:
77  virtual ~TlbTestInterface() {}
78 
87  virtual Fault translationCheck(const RequestPtr &req, bool is_priv,
90 
103  virtual Fault walkCheck(Addr pa, Addr size, Addr va, bool is_secure,
104  Addr is_priv, BaseMMU::Mode mode,
106  LookupLevel lookup_level) = 0;
107 };
108 
109 class TLB : public BaseTLB
110 {
111  public:
112  enum ArmFlags
113  {
115 
116  AlignByte = 0x0,
118  AlignWord = 0x2,
122 
124  // Priv code operating as if it wasn't
125  UserMode = 0x10
126  };
127 
129  {
131  S1CTran = 0x1,
132  HypMode = 0x2,
133  // Secure code operating as if it wasn't (required by some Address
134  // Translate operations)
135  S1S2NsTran = 0x4,
136  // Address translation instructions (eg AT S1E0R_Xt) need to be handled
137  // in special ways during translation because they could need to act
138  // like a different EL than the current EL. The following flags are
139  // for these instructions
140  S1E0Tran = 0x8,
141  S1E1Tran = 0x10,
142  S1E2Tran = 0x20,
143  S1E3Tran = 0x40,
144  S12E0Tran = 0x80,
145  S12E1Tran = 0x100
146  };
147 
154 
155  protected:
156  TlbEntry* table; // the Page Table
157  int size; // TLB Size
158  bool isStage2; // Indicates this TLB is part of the second stage MMU
159  bool stage2Req; // Indicates whether a stage 2 lookup is also required
160  // Indicates whether a stage 2 lookup of the table descriptors is required.
161  // Certain address translation instructions will intercept the IPA but the
162  // table descriptors still need to be translated by the stage2.
164  uint64_t _attr; // Memory attributes for last accessed TLB entry
165  bool directToStage2; // Indicates whether all translation requests should
166  // be routed directly to the stage 2 TLB
167 
170 
172 
173  struct TlbStats : public statistics::Group
174  {
175  TlbStats(statistics::Group *parent);
176  // Access Stats
193 
200  } stats;
201 
204 
205  int rangeMRU; //On lookup, only move entries ahead when outside rangeMRU
206 
207  public:
208  using Params = ArmTLBParams;
209  TLB(const Params &p);
210  TLB(const Params &p, int _size, TableWalker *_walker);
211 
225  TlbEntry *lookup(Addr vpn, uint16_t asn, vmid_t vmid, bool hyp,
226  bool secure, bool functional,
227  bool ignore_asn, ExceptionLevel target_el,
228  bool in_host, BaseMMU::Mode mode);
229 
230  virtual ~TLB();
231 
232  void takeOverFrom(BaseTLB *otlb) override;
233 
235 
236  void setStage2Tlb(TLB *stage2_tlb) { stage2Tlb = stage2_tlb; }
237 
238  void setTableWalker(TableWalker *table_walker);
239 
241 
242  int getsize() const { return size; }
243 
244  void insert(Addr vaddr, TlbEntry &pte);
245 
246  Fault getTE(TlbEntry **te, const RequestPtr &req,
248  BaseMMU::Translation *translation,
249  bool timing, bool functional,
250  bool is_secure, ArmTranslationType tranType);
251 
252  Fault getResultTe(TlbEntry **te, const RequestPtr &req,
254  BaseMMU::Translation *translation, bool timing,
255  bool functional, TlbEntry *mergeTe);
256 
261  bool checkPAN(ThreadContext *tc, uint8_t ap, const RequestPtr &req,
262  BaseMMU::Mode mode, const bool is_priv);
263 
267  void flushAll() override;
268 
269 
272  void flush(const TLBIALL &tlbi_op);
273 
277  void flush(const TLBIALLEL &tlbi_op);
278 
282  void flush(const TLBIVMALL &tlbi_op);
283 
287  void flush(const TLBIALLN &tlbi_op);
288 
291  void flush(const TLBIMVA &tlbi_op);
292 
295  void flush(const TLBIASID &tlbi_op);
296 
299  void flush(const TLBIMVAA &tlbi_op);
300 
303 
304  Fault walkTrickBoxCheck(Addr pa, bool is_secure, Addr va, Addr sz,
305  bool is_exec, bool is_write,
307  LookupLevel lookup_level);
308 
309  void printTlb() const;
310 
311  void demapPage(Addr vaddr, uint64_t asn) override
312  {
313  // needed for x86 only
314  panic("demapPage() is not implemented.\n");
315  }
316 
325  bool translateFunctional(ThreadContext *tc, Addr vaddr, Addr &paddr);
326 
333  Fault
335  ThreadContext *tc, BaseMMU::Mode mode) override
336  {
337  return translateFunctional(req, tc, mode, NormalTran);
338  }
339 
342  void
343  setAttr(uint64_t attr)
344  {
345  _attr = attr;
346  }
347 
348  uint64_t
349  getAttr() const
350  {
351  return _attr;
352  }
353 
356  Addr vaddr, bool long_desc_format);
358  BaseMMU::Mode mode, BaseMMU::Translation *translation, bool &delay,
359  bool timing, bool functional,
360  Addr vaddr, ArmFault::TranMethod tranMethod);
361 
362  Fault translateFs(const RequestPtr &req, ThreadContext *tc,
364  bool &delay, bool timing, ArmTranslationType tranType,
365  bool functional = false);
366  Fault translateSe(const RequestPtr &req, ThreadContext *tc,
368  bool &delay, bool timing);
369 
372 
373  Fault
375  ThreadContext *tc, BaseMMU::Mode mode) override
376  {
377  return translateAtomic(req, tc, mode, NormalTran);
378  }
379  void translateTiming(
380  const RequestPtr &req, ThreadContext *tc,
382  ArmTranslationType tranType);
383  void
385  BaseMMU::Translation *translation,
386  BaseMMU::Mode mode) override
387  {
388  translateTiming(req, tc, translation, mode, NormalTran);
389  }
392  ArmTranslationType tranType, bool callFromS2);
394  const RequestPtr &req,
395  ThreadContext *tc, BaseMMU::Mode mode) const override;
396 
397  void drainResume() override;
398 
399  void regProbePoints() override;
400 
411  Port *getTableWalkerPort() override;
412 
413  // Caching misc register values here.
414  // Writing to misc registers needs to invalidate them.
415  // translateFunctional/translateSe/translateFs checks if they are
416  // invalid and call updateMiscReg if necessary.
417 protected:
418  CPSR cpsr;
419  bool aarch64;
421  SCTLR sctlr;
422  SCR scr;
423  bool isPriv;
424  bool isSecure;
425  bool isHyp;
426  TTBCR ttbcr;
427  uint16_t asid;
429  PRRR prrr;
430  NMRR nmrr;
431  HCR hcr;
432  uint32_t dacr;
436 
437  // Cached copies of system-level properties
438  bool haveLPAE;
441  uint8_t physAddrRange;
442 
444 
445  void updateMiscReg(ThreadContext *tc,
446  ArmTranslationType tranType = NormalTran);
447 
450  vmid_t getVMID(ThreadContext *tc) const;
451 
452 public:
453  void invalidateMiscReg() { miscRegValid = false; }
454 
455 private:
463  void _flushMva(Addr mva, uint64_t asn, bool secure_lookup,
464  bool ignore_asn, ExceptionLevel target_el,
465  bool in_host);
466 
467  public: /* Testing */
470 
471  Fault testWalk(Addr pa, Addr size, Addr va, bool is_secure,
473  LookupLevel lookup_level);
474 };
475 
476 } // namespace ArmISA
477 } // namespace gem5
478 
479 #endif // __ARCH_ARM_TLB_HH__
gem5::statistics::Scalar
This is a simple scalar statistic, like a counter.
Definition: statistics.hh:1927
gem5::ArmISA::TLB::tableWalker
TableWalker * tableWalker
Definition: tlb.hh:168
gem5::ArmISA::TLB::finalizePhysical
Fault finalizePhysical(const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode) const override
Do post-translation physical address finalization.
Definition: tlb.cc:137
gem5::ArmISA::TLB::aarch64EL
ExceptionLevel aarch64EL
Definition: tlb.hh:420
gem5::ArmISA::TlbTestInterface::TlbTestInterface
TlbTestInterface()
Definition: tlb.hh:76
gem5::ArmISA::TLB::ppRefills
probing::PMUUPtr ppRefills
PMU probe for TLB refills.
Definition: tlb.hh:203
gem5::ArmISA::TLB::cpsr
CPSR cpsr
Definition: tlb.hh:418
gem5::ArmISA::TLB::isStage2
bool isStage2
Definition: tlb.hh:158
gem5::ArmISA::TLBIALLEL
Implementaton of AArch64 TLBI ALLE(1,2,3)(IS) instructions.
Definition: tlbi_op.hh:162
gem5::ArmISA::TLB::miscRegContext
ContextID miscRegContext
Definition: tlb.hh:434
gem5::ArmISA::TLB::TlbStats::prefetchFaults
statistics::Scalar prefetchFaults
Definition: tlb.hh:190
gem5::ArmISA::TLB::AllowUnaligned
@ AllowUnaligned
Definition: tlb.hh:123
gem5::ArmISA::TLB::aarch64
bool aarch64
Definition: tlb.hh:419
gem5::ArmISA::TLB::stage2DescReq
bool stage2DescReq
Definition: tlb.hh:163
gem5::ArmISA::TLBIASID
TLB Invalidate by ASID match.
Definition: tlbi_op.hh:216
gem5::ArmISA::TLBIALL
TLB Invalidate All.
Definition: tlbi_op.hh:106
gem5::ArmISA::TLB::translateSe
Fault translateSe(const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode, BaseMMU::Translation *translation, bool &delay, bool timing)
Definition: tlb.cc:541
gem5::ArmISA::TLB::isSecure
bool isSecure
Definition: tlb.hh:424
gem5::ArmISA::TLB::stage2Req
bool stage2Req
Definition: tlb.hh:159
gem5::ArmISA::TLB::table
TlbEntry * table
Definition: tlb.hh:156
gem5::ArmISA::TLB::getsize
int getsize() const
Definition: tlb.hh:242
gem5::ArmISA::TLB::AlignByte
@ AlignByte
Definition: tlb.hh:116
gem5::ArmISA::TLB::size
int size
Definition: tlb.hh:157
gem5::ArmISA::TLB::translateFs
Fault translateFs(const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode, BaseMMU::Translation *translation, bool &delay, bool timing, ArmTranslationType tranType, bool functional=false)
Definition: tlb.cc:1174
gem5::ArmISA::TLB::TlbStats::readHits
statistics::Scalar readHits
Definition: tlb.hh:179
gem5::ArmISA::TLB::prrr
PRRR prrr
Definition: tlb.hh:429
gem5::BaseMMU::Mode
Mode
Definition: mmu.hh:53
gem5::ArmISA::attr
attr
Definition: misc_types.hh:655
gem5::ArmISA::domain
Bitfield< 7, 4 > domain
Definition: misc_types.hh:423
gem5::ArmISA::TLB::dacr
uint32_t dacr
Definition: tlb.hh:432
pagetable.hh
gem5::ArmISA::TLB::walkTrickBoxCheck
Fault walkTrickBoxCheck(Addr pa, bool is_secure, Addr va, Addr sz, bool is_exec, bool is_write, TlbEntry::DomainType domain, LookupLevel lookup_level)
gem5::ArmISA::TLB::TLB
TLB(const Params &p)
Definition: tlb.cc:79
gem5::ArmISA::vmid_t
uint16_t vmid_t
Definition: types.hh:57
tlb.hh
gem5::ArmISA::LookupLevel
LookupLevel
Definition: pagetable.hh:76
gem5::ArmISA::TLB
Definition: tlb.hh:109
gem5::ArmISA::TLB::checkPermissions
Fault checkPermissions(TlbEntry *te, const RequestPtr &req, BaseMMU::Mode mode)
Definition: tlb.cc:581
gem5::ArmISA::TLB::translateTiming
void translateTiming(const RequestPtr &req, ThreadContext *tc, BaseMMU::Translation *translation, BaseMMU::Mode mode) override
Definition: tlb.hh:384
gem5::ArmISA::TlbTestInterface::~TlbTestInterface
virtual ~TlbTestInterface()
Definition: tlb.hh:77
gem5::statistics::Formula
A formula for statistics that is calculated when printed.
Definition: statistics.hh:2536
gem5::ArmISA::TLB::TlbStats::hits
statistics::Formula hits
Definition: tlb.hh:197
gem5::ArmISA::TLB::AlignmentMask
@ AlignmentMask
Definition: tlb.hh:114
gem5::ArmISA::TLB::S1CTran
@ S1CTran
Definition: tlb.hh:131
gem5::ArmISA::TLB::HypMode
@ HypMode
Definition: tlb.hh:132
gem5::ArmISA::TLB::setStage2Tlb
void setStage2Tlb(TLB *stage2_tlb)
Definition: tlb.hh:236
gem5::ArmISA::TLB::invalidateMiscReg
void invalidateMiscReg()
Definition: tlb.hh:453
gem5::ArmISA::TLB::lookup
TlbEntry * lookup(Addr vpn, uint16_t asn, vmid_t vmid, bool hyp, bool secure, bool functional, bool ignore_asn, ExceptionLevel target_el, bool in_host, BaseMMU::Mode mode)
Lookup an entry in the TLB.
Definition: tlb.cc:166
gem5::ArmISA::TLB::TlbStats::alignFaults
statistics::Scalar alignFaults
Definition: tlb.hh:189
gem5::ArmISA::TLB::TlbStats::misses
statistics::Formula misses
Definition: tlb.hh:198
gem5::ArmISA::TlbTestInterface
Definition: tlb.hh:73
request.hh
gem5::ArmISA::TlbEntry
Definition: pagetable.hh:86
gem5::ArmISA::TlbTestInterface::translationCheck
virtual Fault translationCheck(const RequestPtr &req, bool is_priv, BaseMMU::Mode mode, TlbEntry::DomainType domain)=0
Check if a TLB translation should be forced to fail.
gem5::ArmISA::TLB::sctlr
SCTLR sctlr
Definition: tlb.hh:421
gem5::ArmISA::TLB::translateAtomic
Fault translateAtomic(const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode) override
Definition: tlb.hh:374
gem5::ArmISA::TlbEntry::DomainType
DomainType
Definition: pagetable.hh:96
gem5::ArmISA::TLB::isPriv
bool isPriv
Definition: tlb.hh:423
gem5::ArmISA::TLB::curTranType
ArmTranslationType curTranType
Definition: tlb.hh:435
gem5::ArmISA::TLB::S1E3Tran
@ S1E3Tran
Definition: tlb.hh:143
pmu.hh
gem5::ArmISA::TLB::stage2Tlb
TLB * stage2Tlb
Definition: tlb.hh:169
gem5::ArmISA::TLBIALLN
TLB Invalidate All, Non-Secure.
Definition: tlbi_op.hh:258
gem5::ArmISA::TLB::Params
ArmTLBParams Params
Definition: tlb.hh:208
gem5::ArmISA::pa
Bitfield< 39, 12 > pa
Definition: misc_types.hh:656
gem5::ArmISA::TLB::ttbcr
TTBCR ttbcr
Definition: tlb.hh:426
gem5::ArmISA::TLB::TlbStats::instHits
statistics::Scalar instHits
Definition: tlb.hh:177
gem5::ArmISA::TLB::TlbStats::domainFaults
statistics::Scalar domainFaults
Definition: tlb.hh:191
gem5::ArmISA::TLB::printTlb
void printTlb() const
Definition: tlb.cc:260
gem5::ArmISA::TLB::getResultTe
Fault getResultTe(TlbEntry **te, const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode, BaseMMU::Translation *translation, bool timing, bool functional, TlbEntry *mergeTe)
Definition: tlb.cc:1640
gem5::ArmISA::TLB::TlbStats::writeHits
statistics::Scalar writeHits
Definition: tlb.hh:181
gem5::ArmISA::TLB::AlignWord
@ AlignWord
Definition: tlb.hh:118
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::ArmISA::TLB::translateAtomic
Fault translateAtomic(const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode, ArmTranslationType tranType)
Definition: tlb.cc:1256
gem5::ArmISA::TLB::takeOverFrom
void takeOverFrom(BaseTLB *otlb) override
Take over from an old tlb context.
Definition: tlb.cc:466
gem5::ArmISA::TLB::translateFunctional
bool translateFunctional(ThreadContext *tc, Addr vaddr, Addr &paddr)
Do a functional lookup on the TLB (for debugging) and don't modify any internal state.
Definition: tlb.cc:119
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::ArmISA::TLB::getTableWalkerPort
Port * getTableWalkerPort() override
Get the table walker port.
Definition: tlb.cc:1346
gem5::probing::PMUUPtr
std::unique_ptr< PMU > PMUUPtr
Definition: pmu.hh:61
gem5::ArmISA::TLB::NormalTran
@ NormalTran
Definition: tlb.hh:130
gem5::ArmISA::TLB::TlbStats::readMisses
statistics::Scalar readMisses
Definition: tlb.hh:180
gem5::ArmISA::TLB::stats
gem5::ArmISA::TLB::TlbStats stats
gem5::ArmISA::TLBIMVAA
TLB Invalidate by VA, All ASID.
Definition: tlbi_op.hh:281
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
statistics.hh
gem5::ArmISA::TLB::flush
void flush(const TLBIALL &tlbi_op)
Reset the entire TLB.
Definition: tlb.cc:292
gem5::X86ISA::type
type
Definition: misc.hh:733
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::ArmISA::TLB::physAddrRange
uint8_t physAddrRange
Definition: tlb.hh:441
gem5::ArmISA::TLB::TlbStats::instAccesses
statistics::Formula instAccesses
Definition: tlb.hh:196
gem5::BaseTLB
Definition: tlb.hh:54
gem5::ArmISA::TLB::S1S2NsTran
@ S1S2NsTran
Definition: tlb.hh:135
gem5::ArmISA::TLB::miscRegValid
bool miscRegValid
Definition: tlb.hh:433
gem5::ArmISA::TLB::UserMode
@ UserMode
Definition: tlb.hh:125
gem5::ArmISA::TLB::ArmFlags
ArmFlags
Definition: tlb.hh:112
gem5::ArmISA::TLB::translateTiming
void translateTiming(const RequestPtr &req, ThreadContext *tc, BaseMMU::Translation *translation, BaseMMU::Mode mode, ArmTranslationType tranType)
Definition: tlb.cc:1298
gem5::ArmISA::TLB::nmrr
NMRR nmrr
Definition: tlb.hh:430
gem5::ArmISA::TLB::testTranslation
Fault testTranslation(const RequestPtr &req, BaseMMU::Mode mode, TlbEntry::DomainType domain)
Definition: tlb.cc:1725
gem5::ArmISA::te
Bitfield< 30 > te
Definition: misc_types.hh:337
gem5::ArmISA::TLB::S1E2Tran
@ S1E2Tran
Definition: tlb.hh:142
gem5::ArmISA::TLB::TlbStats::flushTlbMva
statistics::Scalar flushTlbMva
Definition: tlb.hh:185
gem5::SimObject
Abstract superclass for simulation objects.
Definition: sim_object.hh:146
gem5::ArmISA::TLB::TlbStats::accesses
statistics::Formula accesses
Definition: tlb.hh:199
gem5::ArmISA::TLB::isHyp
bool isHyp
Definition: tlb.hh:425
faults.hh
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ArmISA::TLB::haveLargeAsid64
bool haveLargeAsid64
Definition: tlb.hh:440
gem5::ArmISA::TLB::flushAll
void flushAll() override
Reset the entire TLB.
Definition: tlb.cc:274
gem5::ArmISA::TLB::TlbStats::permsFaults
statistics::Scalar permsFaults
Definition: tlb.hh:192
gem5::ArmISA::TLB::TlbStats::writeAccesses
statistics::Formula writeAccesses
Definition: tlb.hh:195
gem5::ArmISA::TLB::testWalk
Fault testWalk(Addr pa, Addr size, Addr va, bool is_secure, BaseMMU::Mode mode, TlbEntry::DomainType domain, LookupLevel lookup_level)
Definition: tlb.cc:1737
gem5::ArmISA::TLB::tranTypeEL
static ExceptionLevel tranTypeEL(CPSR cpsr, ArmTranslationType type)
Determine the EL to use for the purpose of a translation given a specific translation type.
Definition: tlb.cc:1557
gem5::MipsISA::ti
Bitfield< 30 > ti
Definition: pra_constants.hh:179
gem5::ArmISA::TLB::TlbStats::flushTlb
statistics::Scalar flushTlb
Definition: tlb.hh:184
gem5::ArmISA::va
Bitfield< 8 > va
Definition: misc_types.hh:275
utility.hh
gem5::ArmISA::TLB::TlbStats::TlbStats
TlbStats(statistics::Group *parent)
gem5::ArmISA::TLB::checkPermissions64
Fault checkPermissions64(TlbEntry *te, const RequestPtr &req, BaseMMU::Mode mode, ThreadContext *tc)
Definition: tlb.cc:759
gem5::ArmISA::TLB::TlbStats::flushTlbAsid
statistics::Scalar flushTlbAsid
Definition: tlb.hh:187
gem5::ArmISA::TLB::TlbStats::writeMisses
statistics::Scalar writeMisses
Definition: tlb.hh:182
gem5::BaseMMU::Translation
Definition: mmu.hh:55
gem5::ArmISA::TLB::demapPage
void demapPage(Addr vaddr, uint64_t asn) override
Definition: tlb.hh:311
gem5::ArmISA::TLB::S1E0Tran
@ S1E0Tran
Definition: tlb.hh:140
gem5::ArmISA::TLB::TlbStats::instMisses
statistics::Scalar instMisses
Definition: tlb.hh:178
gem5::ArmISA::TableWalker
Definition: table_walker.hh:66
gem5::ArmISA::ArmFault::TranMethod
TranMethod
Definition: faults.hh:150
gem5::ArmISA::TLB::updateMiscReg
void updateMiscReg(ThreadContext *tc, ArmTranslationType tranType=NormalTran)
Definition: tlb.cc:1381
gem5::ArmISA::TLB::_attr
uint64_t _attr
Definition: tlb.hh:164
gem5::ArmISA::TLB::vmid
vmid_t vmid
Definition: tlb.hh:428
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
gem5::ArmISA::TLB::regProbePoints
void regProbePoints() override
Register probe points for this object.
Definition: tlb.cc:535
gem5::ArmISA::TLB::getAttr
uint64_t getAttr() const
Definition: tlb.hh:349
gem5::ArmISA::TLB::translateFunctional
Fault translateFunctional(const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode) override
Definition: tlb.hh:334
gem5::ArmISA::TLB::S1E1Tran
@ S1E1Tran
Definition: tlb.hh:141
gem5::ArmISA::TLB::haveLPAE
bool haveLPAE
Definition: tlb.hh:438
gem5::ArmISA::TLB::setTableWalker
void setTableWalker(TableWalker *table_walker)
Definition: tlb.cc:112
gem5::ArmISA::TLBIMVA
TLB Invalidate by VA.
Definition: tlbi_op.hh:296
gem5::ContextID
int ContextID
Globally unique thread context ID.
Definition: types.hh:246
gem5::ArmISA::TLB::S12E1Tran
@ S12E1Tran
Definition: tlb.hh:145
gem5::ArmISA::TLBIVMALL
Implementaton of AArch64 TLBI VMALLE1(IS)/VMALLS112E1(IS) instructions.
Definition: tlbi_op.hh:188
gem5::ArmISA::TLB::haveVirtualization
bool haveVirtualization
Definition: tlb.hh:439
gem5::statistics::Group
Statistics container.
Definition: group.hh:93
gem5::ArmISA::TLB::insert
void insert(Addr vaddr, TlbEntry &pte)
Definition: tlb.cc:230
gem5::ArmISA::TLB::directToStage2
bool directToStage2
Definition: tlb.hh:165
gem5::ArmISA::TLB::ArmTranslationType
ArmTranslationType
Definition: tlb.hh:128
gem5::ArmISA::TLB::TlbStats::inserts
statistics::Scalar inserts
Definition: tlb.hh:183
gem5::ArmISA::TLB::TlbStats::flushedEntries
statistics::Scalar flushedEntries
Definition: tlb.hh:188
gem5::ArmISA::TLB::S12E0Tran
@ S12E0Tran
Definition: tlb.hh:144
gem5::ArmISA::TLB::getVMID
vmid_t getVMID(ThreadContext *tc) const
Returns the current VMID (information stored in the VTTBR_EL2 register)
Definition: tlb.cc:1352
gem5::ArmISA::TLB::drainResume
void drainResume() override
Resume execution after a successful drain.
Definition: tlb.cc:458
gem5::ArmISA::TLB::AlignOctWord
@ AlignOctWord
Definition: tlb.hh:121
gem5::ArmISA::TLB::getTableWalker
TableWalker * getTableWalker()
Definition: tlb.hh:240
gem5::MipsISA::vaddr
vaddr
Definition: pra_constants.hh:278
gem5::ArmISA::TLB::m5opRange
AddrRange m5opRange
Definition: tlb.hh:443
gem5::ArmISA::TLB::~TLB
virtual ~TLB()
Definition: tlb.cc:106
gem5::AddrRange
The AddrRange class encapsulates an address range, and supports a number of tests to check if two ran...
Definition: addr_range.hh:71
gem5::ArmISA::TLB::AlignDoubleWord
@ AlignDoubleWord
Definition: tlb.hh:119
gem5::ArmISA::TLB::TlbStats
Definition: tlb.hh:173
gem5::ArmISA::TLB::translateMmuOff
Fault translateMmuOff(ThreadContext *tc, const RequestPtr &req, BaseMMU::Mode mode, TLB::ArmTranslationType tranType, Addr vaddr, bool long_desc_format)
Definition: tlb.cc:1028
gem5::ArmISA::TLB::scr
SCR scr
Definition: tlb.hh:422
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::ArmISA::TLB::test
TlbTestInterface * test
Definition: tlb.hh:171
gem5::ArmISA::TLB::trickBoxCheck
Fault trickBoxCheck(const RequestPtr &req, BaseMMU::Mode mode, TlbEntry::DomainType domain)
gem5::ArmISA::TLB::TlbStats::readAccesses
statistics::Formula readAccesses
Definition: tlb.hh:194
gem5::ArmISA::TlbTestInterface::walkCheck
virtual Fault walkCheck(Addr pa, Addr size, Addr va, bool is_secure, Addr is_priv, BaseMMU::Mode mode, TlbEntry::DomainType domain, LookupLevel lookup_level)=0
Check if a page table walker access should be forced to fail.
gem5::ArmISA::TLB::AlignHalfWord
@ AlignHalfWord
Definition: tlb.hh:117
gem5::ArmISA::TLB::AlignQuadWord
@ AlignQuadWord
Definition: tlb.hh:120
gem5::ArmISA::TLB::setTestInterface
void setTestInterface(SimObject *ti)
Definition: tlb.cc:1713
gem5::ArmISA::TLB::translateComplete
Fault translateComplete(const RequestPtr &req, ThreadContext *tc, BaseMMU::Translation *translation, BaseMMU::Mode mode, ArmTranslationType tranType, bool callFromS2)
Definition: tlb.cc:1316
gem5::ArmISA::TLB::asid
uint16_t asid
Definition: tlb.hh:427
gem5::ArmISA::TLB::rangeMRU
int rangeMRU
Definition: tlb.hh:205
gem5::ArmISA::TLB::TlbStats::flushTlbMvaAsid
statistics::Scalar flushTlbMvaAsid
Definition: tlb.hh:186
gem5::ArmISA::TLB::translateMmuOn
Fault translateMmuOn(ThreadContext *tc, const RequestPtr &req, BaseMMU::Mode mode, BaseMMU::Translation *translation, bool &delay, bool timing, bool functional, Addr vaddr, ArmFault::TranMethod tranMethod)
Definition: tlb.cc:1101
gem5::ArmISA::TLB::setAttr
void setAttr(uint64_t attr)
Accessor functions for memory attributes for last accessed TLB entry.
Definition: tlb.hh:343
gem5::ArmISA::TLB::hcr
HCR hcr
Definition: tlb.hh:431
gem5::ArmISA::TLB::_flushMva
void _flushMva(Addr mva, uint64_t asn, bool secure_lookup, bool ignore_asn, ExceptionLevel target_el, bool in_host)
Remove any entries that match both a va and asn.
Definition: tlb.cc:435
gem5::ArmISA::TLB::checkPAN
bool checkPAN(ThreadContext *tc, uint8_t ap, const RequestPtr &req, BaseMMU::Mode mode, const bool is_priv)
Definition: tlb.cc:1000
gem5::ArmISA::ExceptionLevel
ExceptionLevel
Definition: types.hh:264
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::ArmISA::mode
Bitfield< 4, 0 > mode
Definition: misc_types.hh:73
gem5::ArmISA::TLB::getTE
Fault getTE(TlbEntry **te, const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode, BaseMMU::Translation *translation, bool timing, bool functional, bool is_secure, ArmTranslationType tranType)
Definition: tlb.cc:1586

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