gem5  v21.2.1.1
tlb.hh
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2010-2013, 2016, 2019-2021 Arm Limited
3  * All rights reserved
4  *
5  * The license below extends only to copyright in the software and shall
6  * not be construed as granting a license to any other intellectual
7  * property including but not limited to intellectual property relating
8  * to a hardware implementation of the functionality of the software
9  * licensed hereunder. You may use the software subject to the license
10  * terms below provided that you ensure that this notice is replicated
11  * unmodified and in its entirety in all distributions of the software,
12  * modified or unmodified, in source code or in binary form.
13  *
14  * Copyright (c) 2001-2005 The Regents of The University of Michigan
15  * All rights reserved.
16  *
17  * Redistribution and use in source and binary forms, with or without
18  * modification, are permitted provided that the following conditions are
19  * met: redistributions of source code must retain the above copyright
20  * notice, this list of conditions and the following disclaimer;
21  * redistributions in binary form must reproduce the above copyright
22  * notice, this list of conditions and the following disclaimer in the
23  * documentation and/or other materials provided with the distribution;
24  * neither the name of the copyright holders nor the names of its
25  * contributors may be used to endorse or promote products derived from
26  * this software without specific prior written permission.
27  *
28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39  */
40 
41 #ifndef __ARCH_ARM_TLB_HH__
42 #define __ARCH_ARM_TLB_HH__
43 
44 
45 #include "arch/arm/faults.hh"
46 #include "arch/arm/pagetable.hh"
47 #include "arch/arm/utility.hh"
48 #include "arch/generic/tlb.hh"
49 #include "base/statistics.hh"
50 #include "enums/TypeTLB.hh"
51 #include "mem/request.hh"
52 #include "params/ArmTLB.hh"
53 #include "sim/probe/pmu.hh"
54 
55 namespace gem5
56 {
57 
58 class ThreadContext;
59 
60 namespace ArmISA {
61 
62 class TableWalker;
63 class TLB;
64 
65 class TLBIALL;
66 class ITLBIALL;
67 class DTLBIALL;
68 class TLBIALLEL;
69 class TLBIVMALL;
70 class TLBIALLN;
71 class TLBIMVA;
72 class ITLBIMVA;
73 class DTLBIMVA;
74 class TLBIASID;
75 class ITLBIASID;
76 class DTLBIASID;
77 class TLBIMVAA;
78 
80 {
81  public:
83  virtual ~TlbTestInterface() {}
84 
93  virtual Fault translationCheck(const RequestPtr &req, bool is_priv,
96 
109  virtual Fault walkCheck(Addr pa, Addr size, Addr va, bool is_secure,
110  Addr is_priv, BaseMMU::Mode mode,
112  enums::ArmLookupLevel lookup_level) = 0;
113 };
114 
115 class TLB : public BaseTLB
116 {
117  protected:
119 
121  int size;
122 
124  bool isStage2;
125 
131  std::unordered_map<enums::ArmLookupLevel, bool> partialLevels;
132 
137 
139 
140  struct TlbStats : public statistics::Group
141  {
142  TlbStats(TLB &parent);
143 
144  const TLB &tlb;
145 
146  // Access Stats
160 
167  } stats;
168 
171 
172  int rangeMRU; //On lookup, only move entries ahead when outside rangeMRU
174 
175  public:
176  using Params = ArmTLBParams;
178  using LookupLevel = enums::ArmLookupLevel;
179 
180  TLB(const Params &p);
181  TLB(const Params &p, int _size, TableWalker *_walker);
182 
186  TlbEntry *lookup(const Lookup &lookup_data);
187 
194  TlbEntry *multiLookup(const Lookup &lookup_data);
195 
196  virtual ~TLB();
197 
198  void takeOverFrom(BaseTLB *otlb) override;
199 
200  void setTableWalker(TableWalker *table_walker);
201 
203 
204  int getsize() const { return size; }
205 
206  bool walkCache() const { return _walkCache; }
207 
208  void setVMID(vmid_t _vmid) { vmid = _vmid; }
209 
211  void insert(TlbEntry &pte);
212 
214  void multiInsert(TlbEntry &pte);
215 
219  void flushAll() override;
220 
221 
224  void flush(const TLBIALL &tlbi_op);
225  void flush(const ITLBIALL &tlbi_op);
226  void flush(const DTLBIALL &tlbi_op);
227 
231  void flush(const TLBIALLEL &tlbi_op);
232 
236  void flush(const TLBIVMALL &tlbi_op);
237 
241  void flush(const TLBIALLN &tlbi_op);
242 
245  void flush(const TLBIMVA &tlbi_op);
246  void flush(const ITLBIMVA &tlbi_op);
247  void flush(const DTLBIMVA &tlbi_op);
248 
251  void flush(const TLBIASID &tlbi_op);
252  void flush(const ITLBIASID &tlbi_op);
253  void flush(const DTLBIASID &tlbi_op);
254 
257  void flush(const TLBIMVAA &tlbi_op);
258 
261 
262  Fault walkTrickBoxCheck(Addr pa, bool is_secure, Addr va, Addr sz,
263  bool is_exec, bool is_write,
265  LookupLevel lookup_level);
266 
267  void printTlb() const;
268 
269  void demapPage(Addr vaddr, uint64_t asn) override
270  {
271  // needed for x86 only
272  panic("demapPage() is not implemented.\n");
273  }
274 
275  Fault
277  BaseMMU::Mode mode) override
278  {
279  panic("unimplemented");
280  }
281 
282  void
284  BaseMMU::Translation *translation,
285  BaseMMU::Mode mode) override
286  {
287  panic("unimplemented");
288  }
289 
290  Fault
292  BaseMMU::Mode mode) const override
293  {
294  panic("unimplemented");
295  }
296 
297  void regProbePoints() override;
298 
309  Port *getTableWalkerPort() override;
310 
311  // Caching misc register values here.
312  // Writing to misc registers needs to invalidate them.
313  // translateFunctional/translateSe/translateFs checks if they are
314  // invalid and call updateMiscReg if necessary.
315 
316  private:
325  void _flushMva(Addr mva, uint64_t asn, bool secure_lookup,
326  bool ignore_asn, ExceptionLevel target_el,
327  bool in_host, TypeTLB entry_type);
328 
335 
338  TlbEntry *match(const Lookup &lookup_data);
339 };
340 
341 } // namespace ArmISA
342 } // namespace gem5
343 
344 #endif // __ARCH_ARM_TLB_HH__
gem5::statistics::Scalar
This is a simple scalar statistic, like a counter.
Definition: statistics.hh:1930
gem5::ArmISA::ITLBIALL
Instruction TLB Invalidate All.
Definition: tlbi_op.hh:136
gem5::ArmISA::TLB::tableWalker
TableWalker * tableWalker
Definition: tlb.hh:138
gem5::ArmISA::TLB::finalizePhysical
Fault finalizePhysical(const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode) const override
Do post-translation physical address finalization.
Definition: tlb.hh:291
gem5::ArmISA::TlbTestInterface::TlbTestInterface
TlbTestInterface()
Definition: tlb.hh:82
gem5::ArmISA::TLB::ppRefills
probing::PMUUPtr ppRefills
PMU probe for TLB refills.
Definition: tlb.hh:170
gem5::ArmISA::TLB::lookup
TlbEntry * lookup(const Lookup &lookup_data)
Lookup an entry in the TLB.
Definition: tlb.cc:157
gem5::ArmISA::TLB::isStage2
bool isStage2
Indicates this TLB caches IPA->PA translations.
Definition: tlb.hh:124
gem5::ArmISA::TLBIALLEL
Implementaton of AArch64 TLBI ALLE(1,2,3)(IS) instructions.
Definition: tlbi_op.hh:162
gem5::ArmISA::TLBIASID
TLB Invalidate by ASID match.
Definition: tlbi_op.hh:216
gem5::ArmISA::TLBIALL
TLB Invalidate All.
Definition: tlbi_op.hh:106
gem5::ArmISA::TLB::TlbStats::partialHits
statistics::Scalar partialHits
Definition: tlb.hh:147
gem5::ArmISA::TLB::table
TlbEntry * table
Definition: tlb.hh:118
gem5::ArmISA::TLB::getsize
int getsize() const
Definition: tlb.hh:204
gem5::ArmISA::TLB::size
int size
TLB Size.
Definition: tlb.hh:121
gem5::ArmISA::TLB::match
TlbEntry * match(const Lookup &lookup_data)
Helper function looking up for a matching TLB entry Does not update stats; see lookup method instead.
Definition: tlb.cc:106
gem5::ArmISA::TLB::TlbStats::readHits
statistics::Scalar readHits
Definition: tlb.hh:150
gem5::BaseMMU::Mode
Mode
Definition: mmu.hh:56
gem5::ArmISA::domain
Bitfield< 7, 4 > domain
Definition: misc_types.hh:424
pagetable.hh
gem5::ArmISA::TLB::walkTrickBoxCheck
Fault walkTrickBoxCheck(Addr pa, bool is_secure, Addr va, Addr sz, bool is_exec, bool is_write, TlbEntry::DomainType domain, LookupLevel lookup_level)
gem5::ArmISA::TLB::TLB
TLB(const Params &p)
Definition: tlb.cc:61
gem5::ArmISA::vmid_t
uint16_t vmid_t
Definition: types.hh:57
tlb.hh
gem5::ArmISA::TLB
Definition: tlb.hh:115
gem5::ArmISA::TLB::translateTiming
void translateTiming(const RequestPtr &req, ThreadContext *tc, BaseMMU::Translation *translation, BaseMMU::Mode mode) override
Definition: tlb.hh:283
gem5::ArmISA::TlbTestInterface::~TlbTestInterface
virtual ~TlbTestInterface()
Definition: tlb.hh:83
gem5::statistics::Formula
A formula for statistics that is calculated when printed.
Definition: statistics.hh:2539
gem5::ArmISA::TLB::TlbStats::hits
statistics::Formula hits
Definition: tlb.hh:164
gem5::ArmISA::TLB::multiInsert
void multiInsert(TlbEntry &pte)
Insert a PTE in the current TLB and in the higher levels.
Definition: tlb.cc:270
gem5::ArmISA::TLB::TlbStats::misses
statistics::Formula misses
Definition: tlb.hh:165
gem5::ArmISA::DTLBIASID
Data TLB Invalidate by ASID match.
Definition: tlbi_op.hh:245
gem5::ArmISA::TLB::Lookup
TlbEntry::Lookup Lookup
Definition: tlb.hh:177
gem5::ArmISA::ITLBIASID
Instruction TLB Invalidate by ASID match.
Definition: tlbi_op.hh:232
gem5::ArmISA::TlbTestInterface
Definition: tlb.hh:79
request.hh
gem5::ArmISA::TlbEntry
Definition: pagetable.hh:165
gem5::ArmISA::TlbTestInterface::translationCheck
virtual Fault translationCheck(const RequestPtr &req, bool is_priv, BaseMMU::Mode mode, TlbEntry::DomainType domain)=0
Check if a TLB translation should be forced to fail.
gem5::ArmISA::ITLBIMVA
Instruction TLB Invalidate by VA.
Definition: tlbi_op.hh:313
gem5::ArmISA::TLB::translateAtomic
Fault translateAtomic(const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode) override
Definition: tlb.hh:276
gem5::ArmISA::TlbEntry::DomainType
DomainType
Definition: pagetable.hh:177
gem5::ArmISA::TLB::LookupLevel
enums::ArmLookupLevel LookupLevel
Definition: tlb.hh:178
gem5::ArmISA::TlbEntry::Lookup
Definition: pagetable.hh:185
pmu.hh
gem5::ArmISA::TLB::checkPromotion
void checkPromotion(TlbEntry *entry, BaseMMU::Mode mode)
Check if the tlb entry passed as an argument needs to be "promoted" as a unified entry: this should h...
Definition: tlb.cc:227
gem5::ArmISA::TLBIALLN
TLB Invalidate All, Non-Secure.
Definition: tlbi_op.hh:258
gem5::ArmISA::TLB::Params
ArmTLBParams Params
Definition: tlb.hh:176
gem5::ArmISA::pa
Bitfield< 39, 12 > pa
Definition: misc_types.hh:657
gem5::ArmISA::TLB::multiLookup
TlbEntry * multiLookup(const Lookup &lookup_data)
Lookup an entry in the TLB and in the next levels by following the nextLevel pointer.
Definition: tlb.cc:204
gem5::ArmISA::TLB::TlbStats::instHits
statistics::Scalar instHits
Definition: tlb.hh:148
gem5::ArmISA::TLB::printTlb
void printTlb() const
Definition: tlb.cc:284
gem5::ArmISA::TLB::TlbStats::tlb
const TLB & tlb
Definition: tlb.hh:144
gem5::ArmISA::TLB::TlbStats::writeHits
statistics::Scalar writeHits
Definition: tlb.hh:152
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::ArmISA::TLB::takeOverFrom
void takeOverFrom(BaseTLB *otlb) override
Take over from an old tlb context.
Definition: tlb.cc:628
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::ArmISA::TLB::getTableWalkerPort
Port * getTableWalkerPort() override
Get the table walker port.
Definition: tlb.cc:703
gem5::probing::PMUUPtr
std::unique_ptr< PMU > PMUUPtr
Definition: pmu.hh:61
gem5::ArmISA::TLB::TlbStats::readMisses
statistics::Scalar readMisses
Definition: tlb.hh:151
gem5::ArmISA::TLB::stats
gem5::ArmISA::TLB::TlbStats stats
gem5::ArmISA::TLB::TlbStats::TlbStats
TlbStats(TLB &parent)
Definition: tlb.cc:632
gem5::ArmISA::TLBIMVAA
TLB Invalidate by VA, All ASID.
Definition: tlbi_op.hh:281
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
statistics.hh
gem5::ArmISA::TLB::flush
void flush(const TLBIALL &tlbi_op)
Reset the entire TLB.
Definition: tlb.cc:318
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::ArmISA::TLB::_walkCache
bool _walkCache
True if the TLB caches partial translations.
Definition: tlb.hh:136
gem5::ArmISA::TLB::TlbStats::instAccesses
statistics::Formula instAccesses
Definition: tlb.hh:163
gem5::BaseTLB
Definition: tlb.hh:58
gem5::ArmISA::TLB::TlbStats::flushTlbMva
statistics::Scalar flushTlbMva
Definition: tlb.hh:156
gem5::ArmISA::TLB::TlbStats::accesses
statistics::Formula accesses
Definition: tlb.hh:166
faults.hh
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ArmISA::TLB::flushAll
void flushAll() override
Reset the entire TLB.
Definition: tlb.cc:298
gem5::ArmISA::TLB::TlbStats::writeAccesses
statistics::Formula writeAccesses
Definition: tlb.hh:162
gem5::ArmISA::TLB::setVMID
void setVMID(vmid_t _vmid)
Definition: tlb.hh:208
gem5::ArmISA::TLB::TlbStats::flushTlb
statistics::Scalar flushTlb
Definition: tlb.hh:155
gem5::ArmISA::va
Bitfield< 8 > va
Definition: misc_types.hh:276
utility.hh
gem5::ArmISA::TLB::TlbStats::flushTlbAsid
statistics::Scalar flushTlbAsid
Definition: tlb.hh:158
gem5::ArmISA::TLB::TlbStats::writeMisses
statistics::Scalar writeMisses
Definition: tlb.hh:153
gem5::ArmISA::TLB::walkCache
bool walkCache() const
Definition: tlb.hh:206
gem5::BaseMMU::Translation
Definition: mmu.hh:58
gem5::ArmISA::TLB::demapPage
void demapPage(Addr vaddr, uint64_t asn) override
Definition: tlb.hh:269
gem5::ArmISA::TLB::TlbStats::instMisses
statistics::Scalar instMisses
Definition: tlb.hh:149
gem5::ArmISA::TableWalker
Definition: table_walker.hh:66
gem5::ArmISA::TLB::vmid
vmid_t vmid
Definition: tlb.hh:173
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
gem5::ArmISA::TLB::regProbePoints
void regProbePoints() override
Register probe points for this object.
Definition: tlb.cc:697
gem5::ArmISA::TLB::partialLevels
std::unordered_map< enums::ArmLookupLevel, bool > partialLevels
Hash map containing one entry per lookup level The TLB is caching partial translations from the key l...
Definition: tlb.hh:131
gem5::ArmISA::DTLBIALL
Data TLB Invalidate All.
Definition: tlbi_op.hh:149
gem5::ArmISA::TLB::setTableWalker
void setTableWalker(TableWalker *table_walker)
Definition: tlb.cc:99
gem5::ArmISA::TLBIMVA
TLB Invalidate by VA.
Definition: tlbi_op.hh:296
gem5::ArmISA::TLBIVMALL
Implementaton of AArch64 TLBI VMALLE1(IS)/VMALLS112E1(IS) instructions.
Definition: tlbi_op.hh:188
gem5::ArmISA::TLB::insert
void insert(TlbEntry &pte)
Insert a PTE in the current TLB.
Definition: tlb.cc:241
gem5::statistics::Group
Statistics container.
Definition: group.hh:93
gem5::ArmISA::TLB::_flushMva
void _flushMva(Addr mva, uint64_t asn, bool secure_lookup, bool ignore_asn, ExceptionLevel target_el, bool in_host, TypeTLB entry_type)
Remove any entries that match both a va and asn.
Definition: tlb.cc:597
gem5::ArmISA::TLB::TlbStats::inserts
statistics::Scalar inserts
Definition: tlb.hh:154
gem5::ArmISA::TLB::TlbStats::flushedEntries
statistics::Scalar flushedEntries
Definition: tlb.hh:159
gem5::ArmISA::TLB::getTableWalker
TableWalker * getTableWalker()
Definition: tlb.hh:202
gem5::MipsISA::vaddr
vaddr
Definition: pra_constants.hh:278
gem5::ArmISA::DTLBIMVA
Data TLB Invalidate by VA.
Definition: tlbi_op.hh:327
gem5::ArmISA::TLB::~TLB
virtual ~TLB()
Definition: tlb.cc:93
gem5::ArmISA::TLB::TlbStats
Definition: tlb.hh:140
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::ArmISA::TLB::trickBoxCheck
Fault trickBoxCheck(const RequestPtr &req, BaseMMU::Mode mode, TlbEntry::DomainType domain)
gem5::ArmISA::TLB::TlbStats::readAccesses
statistics::Formula readAccesses
Definition: tlb.hh:161
gem5::ArmISA::TlbTestInterface::walkCheck
virtual Fault walkCheck(Addr pa, Addr size, Addr va, bool is_secure, Addr is_priv, BaseMMU::Mode mode, TlbEntry::DomainType domain, enums::ArmLookupLevel lookup_level)=0
Check if a page table walker access should be forced to fail.
gem5::ArmISA::TLB::rangeMRU
int rangeMRU
Definition: tlb.hh:172
gem5::ArmISA::TLB::TlbStats::flushTlbMvaAsid
statistics::Scalar flushTlbMvaAsid
Definition: tlb.hh:157
gem5::ArmISA::ExceptionLevel
ExceptionLevel
Definition: types.hh:264
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
gem5::ArmISA::mode
Bitfield< 4, 0 > mode
Definition: misc_types.hh:74

Generated on Wed May 4 2022 12:13:35 for gem5 by doxygen 1.8.17