gem5  v21.1.0.2
table_walker.hh
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37 
38 #ifndef __ARCH_ARM_TABLE_WALKER_HH__
39 #define __ARCH_ARM_TABLE_WALKER_HH__
40 
41 #include <list>
42 
43 #include "arch/arm/faults.hh"
44 #include "arch/arm/regs/misc.hh"
45 #include "arch/arm/system.hh"
46 #include "arch/arm/tlb.hh"
47 #include "arch/arm/types.hh"
48 #include "arch/generic/mmu.hh"
49 #include "mem/packet_queue.hh"
50 #include "mem/qport.hh"
51 #include "mem/request.hh"
52 #include "params/ArmTableWalker.hh"
53 #include "sim/clocked_object.hh"
54 #include "sim/eventq.hh"
55 
56 namespace gem5
57 {
58 
59 class ThreadContext;
60 
61 namespace ArmISA {
62 class Translation;
63 class TLB;
64 class MMU;
65 
66 class TableWalker : public ClockedObject
67 {
68  public:
69  class WalkerState;
70 
72  {
73  public:
75 
78 
79  virtual Addr pfn() const = 0;
80  virtual TlbEntry::DomainType domain() const = 0;
81  virtual bool xn() const = 0;
82  virtual uint8_t ap() const = 0;
83  virtual bool global(WalkerState *currState) const = 0;
84  virtual uint8_t offsetBits() const = 0;
85  virtual bool secure(bool have_security, WalkerState *currState) const = 0;
86  virtual std::string dbgHeader() const = 0;
87  virtual uint64_t getRawData() const = 0;
88  virtual uint8_t texcb() const
89  {
90  panic("texcb() not implemented for this class\n");
91  }
92  virtual bool shareable() const
93  {
94  panic("shareable() not implemented for this class\n");
95  }
96  };
97 
99  {
100  public:
103  {
108  };
109 
111  uint32_t data;
112 
115  bool _dirty;
116 
118  L1Descriptor() : data(0), _dirty(false)
119  {
120  lookupLevel = L1;
121  }
122 
123  virtual uint64_t getRawData() const
124  {
125  return (data);
126  }
127 
128  virtual std::string dbgHeader() const
129  {
130  return "Inserting Section Descriptor into TLB\n";
131  }
132 
133  virtual uint8_t offsetBits() const
134  {
135  return 20;
136  }
137 
138  EntryType type() const
139  {
140  return (EntryType)(data & 0x3);
141  }
142 
144  bool supersection() const
145  {
146  return bits(data, 18);
147  }
148 
150  Addr paddr() const
151  {
152  if (supersection())
153  panic("Super sections not implemented\n");
154  return mbits(data, 31, 20);
155  }
157  Addr paddr(Addr va) const
158  {
159  if (supersection())
160  panic("Super sections not implemented\n");
161  return mbits(data, 31, 20) | mbits(va, 19, 0);
162  }
163 
164 
166  Addr pfn() const
167  {
168  if (supersection())
169  panic("Super sections not implemented\n");
170  return bits(data, 31, 20);
171  }
172 
175  {
176  return !bits(data, 17);
177  }
178 
180  bool xn() const
181  {
182  return bits(data, 4);
183  }
184 
186  uint8_t ap() const
187  {
188  return (bits(data, 15) << 2) | bits(data, 11, 10);
189  }
190 
193  {
194  return static_cast<TlbEntry::DomainType>(bits(data, 8, 5));
195  }
196 
198  Addr l2Addr() const
199  {
200  return mbits(data, 31, 10);
201  }
202 
208  uint8_t texcb() const
209  {
210  return bits(data, 2) | bits(data, 3) << 1 | bits(data, 14, 12) << 2;
211  }
212 
214  bool shareable() const
215  {
216  return bits(data, 16);
217  }
218 
222  void setAp0()
223  {
224  data |= 1 << 10;
225  _dirty = true;
226  }
227 
229  bool dirty() const
230  {
231  return _dirty;
232  }
233 
238  bool secure(bool have_security, WalkerState *currState) const
239  {
240  if (have_security && currState->secureLookup) {
241  if (type() == PageTable)
242  return !bits(data, 3);
243  else
244  return !bits(data, 19);
245  }
246  return false;
247  }
248  };
249 
252  {
253  public:
255  uint32_t data;
257 
260  bool _dirty;
261 
263  L2Descriptor() : data(0), l1Parent(nullptr), _dirty(false)
264  {
265  lookupLevel = L2;
266  }
267 
268  L2Descriptor(L1Descriptor &parent) : data(0), l1Parent(&parent),
269  _dirty(false)
270  {
271  lookupLevel = L2;
272  }
273 
274  virtual uint64_t getRawData() const
275  {
276  return (data);
277  }
278 
279  virtual std::string dbgHeader() const
280  {
281  return "Inserting L2 Descriptor into TLB\n";
282  }
283 
284  virtual TlbEntry::DomainType domain() const
285  {
286  return l1Parent->domain();
287  }
288 
289  bool secure(bool have_security, WalkerState *currState) const
290  {
291  return l1Parent->secure(have_security, currState);
292  }
293 
294  virtual uint8_t offsetBits() const
295  {
296  return large() ? 16 : 12;
297  }
298 
300  bool invalid() const
301  {
302  return bits(data, 1, 0) == 0;
303  }
304 
306  bool large() const
307  {
308  return bits(data, 1) == 0;
309  }
310 
312  bool xn() const
313  {
314  return large() ? bits(data, 15) : bits(data, 0);
315  }
316 
319  {
320  return !bits(data, 11);
321  }
322 
324  uint8_t ap() const
325  {
326  return bits(data, 5, 4) | (bits(data, 9) << 2);
327  }
328 
330  uint8_t texcb() const
331  {
332  return large() ?
333  (bits(data, 2) | (bits(data, 3) << 1) | (bits(data, 14, 12) << 2)) :
334  (bits(data, 2) | (bits(data, 3) << 1) | (bits(data, 8, 6) << 2));
335  }
336 
338  Addr pfn() const
339  {
340  return large() ? bits(data, 31, 16) : bits(data, 31, 12);
341  }
342 
344  Addr paddr(Addr va) const
345  {
346  if (large())
347  return mbits(data, 31, 16) | mbits(va, 15, 0);
348  else
349  return mbits(data, 31, 12) | mbits(va, 11, 0);
350  }
351 
353  bool shareable() const
354  {
355  return bits(data, 10);
356  }
357 
361  void setAp0()
362  {
363  data |= 1 << 4;
364  _dirty = true;
365  }
366 
368  bool dirty() const
369  {
370  return _dirty;
371  }
372 
373  };
374 
375  // Granule sizes for AArch64 long descriptors
377  {
378  Grain4KB = 12,
379  Grain16KB = 14,
380  Grain64KB = 16,
382  };
383 
386  {
387  public:
390  {
395  };
396 
398  : data(0), _dirty(false), aarch64(false), grainSize(Grain4KB),
399  physAddrRange(0)
400  {}
401 
403  uint64_t data;
404 
407  bool _dirty;
408 
410  bool aarch64;
411 
414 
415  uint8_t physAddrRange;
416 
417 
418  virtual uint64_t getRawData() const
419  {
420  return (data);
421  }
422 
423  virtual std::string dbgHeader() const
424  {
425  if (type() == LongDescriptor::Page) {
426  assert(lookupLevel == L3);
427  return "Inserting Page descriptor into TLB\n";
428  } else {
429  assert(lookupLevel < L3);
430  return "Inserting Block descriptor into TLB\n";
431  }
432  }
433 
438  bool secure(bool have_security, WalkerState *currState) const
439  {
440  assert(type() == Block || type() == Page);
441  return have_security && (currState->secureLookup && !bits(data, 5));
442  }
443 
445  EntryType type() const
446  {
447  switch (bits(data, 1, 0)) {
448  case 0x1:
449  // In AArch64 blocks are not allowed at L0 for the
450  // 4 KiB granule and at L1 for 16/64 KiB granules
451  switch (grainSize) {
452  case Grain4KB:
453  if (lookupLevel == L0 || lookupLevel == L3)
454  return Invalid;
455  else
456  return Block;
457 
458  case Grain16KB:
459  if (lookupLevel == L2)
460  return Block;
461  else
462  return Invalid;
463 
464  case Grain64KB:
465  // With Armv8.2-LPA (52bit PA) L1 Block descriptors
466  // are allowed for 64KiB granule
467  if ((lookupLevel == L1 && physAddrRange == 52) ||
468  lookupLevel == L2)
469  return Block;
470  else
471  return Invalid;
472 
473  default:
474  return Invalid;
475  }
476  case 0x3:
477  return lookupLevel == L3 ? Page : Table;
478  default:
479  return Invalid;
480  }
481  }
482 
484  uint8_t offsetBits() const
485  {
486  if (type() == Block) {
487  switch (grainSize) {
488  case Grain4KB:
489  return lookupLevel == L1 ? 30 /* 1 GiB */
490  : 21 /* 2 MiB */;
491  case Grain16KB:
492  return 25 /* 32 MiB */;
493  case Grain64KB:
494  return lookupLevel == L1 ? 42 /* 4 TiB */
495  : 29 /* 512 MiB */;
496  default:
497  panic("Invalid AArch64 VM granule size\n");
498  }
499  } else if (type() == Page) {
500  switch (grainSize) {
501  case Grain4KB:
502  case Grain16KB:
503  case Grain64KB:
504  return grainSize; /* enum -> uint okay */
505  default:
506  panic("Invalid AArch64 VM granule size\n");
507  }
508  } else {
509  panic("AArch64 page table entry must be block or page\n");
510  }
511  }
512 
514  Addr pfn() const
515  {
516  return paddr() >> offsetBits();
517  }
518 
520  Addr paddr() const
521  {
522  Addr addr = 0;
523  if (aarch64) {
524  addr = mbits(data, 47, offsetBits());
525  if (physAddrRange == 52 && grainSize == Grain64KB) {
526  addr |= bits(data, 15, 12) << 48;
527  }
528  } else {
529  addr = mbits(data, 39, offsetBits());
530  }
531  return addr;
532  }
533 
536  {
537  assert(type() == Table);
538  Addr table_address = 0;
539  if (aarch64) {
540  table_address = mbits(data, 47, grainSize);
541  // Using 52bit if Armv8.2-LPA is implemented
542  if (physAddrRange == 52 && grainSize == Grain64KB)
543  table_address |= bits(data, 15, 12) << 48;
544  } else {
545  table_address = mbits(data, 39, 12);
546  }
547 
548  return table_address;
549  }
550 
553  {
554  assert(type() == Table);
555  Addr pa = 0;
556  if (aarch64) {
557  int stride = grainSize - 3;
558  int va_lo = stride * (3 - (lookupLevel + 1)) + grainSize;
559  int va_hi = va_lo + stride - 1;
560  pa = nextTableAddr() | (bits(va, va_hi, va_lo) << 3);
561  } else {
562  if (lookupLevel == L1)
563  pa = nextTableAddr() | (bits(va, 29, 21) << 3);
564  else // lookupLevel == L2
565  pa = nextTableAddr() | (bits(va, 20, 12) << 3);
566  }
567  return pa;
568  }
569 
571  bool xn() const
572  {
573  assert(type() == Block || type() == Page);
574  return bits(data, 54);
575  }
576 
578  bool pxn() const
579  {
580  assert(type() == Block || type() == Page);
581  return bits(data, 53);
582  }
583 
585  bool contiguousHint() const
586  {
587  assert(type() == Block || type() == Page);
588  return bits(data, 52);
589  }
590 
593  {
594  assert(currState && (type() == Block || type() == Page));
595  if (!currState->aarch64 && (currState->isSecure &&
596  !currState->secureLookup)) {
597  return false; // ARM ARM issue C B3.6.3
598  } else if (currState->aarch64) {
599  if (currState->el == EL2 || currState->el == EL3) {
600  return true; // By default translations are treated as global
601  // in AArch64 EL2 and EL3
602  } else if (currState->isSecure && !currState->secureLookup) {
603  return false;
604  }
605  }
606  return !bits(data, 11);
607  }
608 
610  bool af() const
611  {
612  assert(type() == Block || type() == Page);
613  return bits(data, 10);
614  }
615 
617  uint8_t sh() const
618  {
619  assert(type() == Block || type() == Page);
620  return bits(data, 9, 8);
621  }
622 
624  uint8_t ap() const
625  {
626  assert(type() == Block || type() == Page);
627  // Long descriptors only support the AP[2:1] scheme
628  return bits(data, 7, 6);
629  }
630 
632  bool rw() const
633  {
634  assert(type() == Block || type() == Page);
635  return !bits(data, 7);
636  }
637 
639  bool user() const
640  {
641  assert(type() == Block || type() == Page);
642  return bits(data, 6);
643  }
644 
648  static uint8_t ap(bool rw, bool user)
649  {
650  return ((!rw) << 2) | (user << 1);
651  }
652 
654  {
655  // Long-desc. format only supports Client domain
656  assert(type() == Block || type() == Page);
658  }
659 
661  uint8_t attrIndx() const
662  {
663  assert(type() == Block || type() == Page);
664  return bits(data, 4, 2);
665  }
666 
668  uint8_t memAttr() const
669  {
670  assert(type() == Block || type() == Page);
671  return bits(data, 5, 2);
672  }
673 
676  void setAf()
677  {
678  data |= 1 << 10;
679  _dirty = true;
680  }
681 
683  bool dirty() const
684  {
685  return _dirty;
686  }
687 
689  bool secureTable() const
690  {
691  assert(type() == Table);
692  return !bits(data, 63);
693  }
694 
696  uint8_t apTable() const
697  {
698  assert(type() == Table);
699  return bits(data, 62, 61);
700  }
701 
703  uint8_t rwTable() const
704  {
705  assert(type() == Table);
706  return !bits(data, 62);
707  }
708 
711  uint8_t userTable() const
712  {
713  assert(type() == Table);
714  return !bits(data, 61);
715  }
716 
718  bool xnTable() const
719  {
720  assert(type() == Table);
721  return bits(data, 60);
722  }
723 
725  bool pxnTable() const
726  {
727  assert(type() == Table);
728  return bits(data, 59);
729  }
730  };
731 
733  {
734  public:
737 
739  bool aarch64;
740 
743 
746 
749 
751  uint16_t asid;
753  bool isHyp;
754 
757 
760 
763 
766 
768  SCTLR sctlr;
769 
771  SCR scr;
772 
774  CPSR cpsr;
775 
777  union
778  {
779  TTBCR ttbcr; // AArch32 translations
780  TCR tcr; // AArch64 translations
781  };
782 
784  HTCR htcr;
785 
787  HCR hcr;
788 
790  VTCR_t vtcr;
791 
793  bool isWrite;
794 
796  bool isFetch;
797 
799  bool isSecure;
800 
803 
807  bool rwTable;
808  bool userTable;
809  bool xnTable;
810  bool pxnTable;
811 
813  bool hpd;
814 
816  bool stage2Req;
817 
820 
822  bool timing;
823 
826 
829 
832 
836 
839 
842  bool delayed;
843 
845 
848 
850  unsigned levels;
851 
852  void doL1Descriptor();
853  void doL2Descriptor();
854 
855  void doLongDescriptor();
856 
857  WalkerState();
858 
859  std::string name() const { return tableWalker->name(); }
860  };
861 
863  {
864  public:
865  Tick delay = 0;
866  Event *event = nullptr;
867  };
868 
869  class Port : public QueuedRequestPort
870  {
871  public:
872  Port(TableWalker* _walker, RequestorID id);
873 
874  void sendFunctionalReq(Addr desc_addr, int size,
875  uint8_t *data, Request::Flags flag);
876  void sendAtomicReq(Addr desc_addr, int size,
877  uint8_t *data, Request::Flags flag, Tick delay);
878  void sendTimingReq(Addr desc_addr, int size,
879  uint8_t *data, Request::Flags flag, Tick delay,
880  Event *event);
881 
882  bool recvTimingResp(PacketPtr pkt) override;
883 
884  private:
885  void handleRespPacket(PacketPtr pkt, Tick delay=0);
886  void handleResp(TableWalkerState *state, Addr addr,
887  Addr size, Tick delay=0);
888 
889  PacketPtr createPacket(Addr desc_addr, int size,
890  uint8_t *data, Request::Flags flag,
891  Tick delay, Event *event);
892 
893  private:
896 
899 
902  };
903 
907  {
908  private:
909  uint8_t *data;
910  int numBytes;
915 
916  public:
918 
919  Stage2Walk(TableWalker &_parent, uint8_t *_data, Event *_event,
920  Addr vaddr);
921 
922  void markDelayed() {}
923 
924  void finish(const Fault &fault, const RequestPtr &req,
926 
927  void
928  setVirt(Addr vaddr, int size, Request::Flags flags,
929  int requestorId)
930  {
931  numBytes = size;
932  req->setVirt(vaddr, size, flags, requestorId, 0);
933  }
934 
935  void translateTiming(ThreadContext *tc);
936  };
937 
939  uint8_t *data, int num_bytes, Request::Flags flags,
940  bool functional);
941  void readDataTimed(ThreadContext *tc, Addr desc_addr,
942  Stage2Walk *translation, int num_bytes,
943  Request::Flags flags);
944 
945  protected:
946 
949 
953 
956 
959 
962 
964  const bool isStage2;
965 
968 
970  SCTLR sctlr;
971 
973 
975  bool pending;
976 
979  unsigned numSquashable;
980 
983  bool _haveLPAE;
985  uint8_t _physAddrRange;
987 
990  {
1001  // Essentially "L" of queueing theory
1005  } stats;
1006 
1007  mutable unsigned pendingReqs;
1009 
1010  static const unsigned REQUESTED = 0;
1011  static const unsigned COMPLETED = 1;
1012 
1013  public:
1014  PARAMS(ArmTableWalker);
1015  TableWalker(const Params &p);
1016  virtual ~TableWalker();
1017 
1018  bool haveLPAE() const { return _haveLPAE; }
1019  bool haveVirtualization() const { return _haveVirtualization; }
1020  bool haveLargeAsid64() const { return _haveLargeAsid64; }
1021  uint8_t physAddrRange() const { return _physAddrRange; }
1023  void completeDrain();
1024  DrainState drain() override;
1025  void drainResume() override;
1026 
1027  gem5::Port &getPort(const std::string &if_name,
1028  PortID idx=InvalidPortID) override;
1029 
1031 
1032  Fault walk(const RequestPtr &req, ThreadContext *tc,
1033  uint16_t asid, vmid_t _vmid,
1034  bool _isHyp, BaseMMU::Mode mode, BaseMMU::Translation *_trans,
1035  bool timing, bool functional, bool secure,
1036  TLB::ArmTranslationType tranType, bool _stage2Req);
1037 
1038  void setMmu(MMU *_mmu) { mmu = _mmu; }
1039  void setTlb(TLB *_tlb) { tlb = _tlb; }
1040  void setPort(Port *_port) { port = _port; }
1041  TLB* getTlb() { return tlb; }
1042  void memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr,
1043  uint8_t texcb, bool s);
1045  LongDescriptor &lDescriptor);
1047  LongDescriptor &lDescriptor);
1048 
1049  static LookupLevel toLookupLevel(uint8_t lookup_level_as_int);
1050 
1051  private:
1052 
1053  void doL1Descriptor();
1054  void doL1DescriptorWrapper();
1056 
1057  void doL2Descriptor();
1058  void doL2DescriptorWrapper();
1060 
1061  void doLongDescriptor();
1062 
1071 
1072  void doLongDescriptorWrapper(LookupLevel curr_lookup_level);
1074 
1075  bool fetchDescriptor(Addr descAddr, uint8_t *data, int numBytes,
1076  Request::Flags flags, int queueIndex, Event *event,
1077  void (TableWalker::*doDescriptor)());
1078 
1080 
1081  void insertTableEntry(DescriptorBase &descriptor, bool longDescriptor);
1082 
1083  Fault processWalk();
1085 
1086  bool checkVAddrSizeFaultAArch64(Addr addr, int top_bit,
1087  GrainSize granule, int tsz, bool low_range);
1088 
1091  bool checkAddrSizeFaultAArch64(Addr addr, int pa_range);
1092 
1094  void processWalkWrapper();
1096 
1097  void nextWalk(ThreadContext *tc);
1098 
1099  void pendingChange();
1100 
1101  static uint8_t pageSizeNtoStatBin(uint8_t N);
1102 
1104  LookupLevel lookup_level);
1105 };
1106 
1107 } // namespace ArmISA
1108 } // namespace gem5
1109 
1110 #endif //__ARCH_ARM_TABLE_WALKER_HH__
gem5::statistics::Scalar
This is a simple scalar statistic, like a counter.
Definition: statistics.hh:1927
gem5::ArmISA::TableWalker::doL1DescEvent
EventFunctionWrapper doL1DescEvent
Definition: table_walker.hh:1055
gem5::ArmISA::TableWalker::haveLPAE
bool haveLPAE() const
Definition: table_walker.hh:1018
gem5::ArmISA::TableWalker::DescriptorBase::dbgHeader
virtual std::string dbgHeader() const =0
gem5::PortID
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:252
gem5::ArmISA::TableWalker::doLongDescriptorWrapper
void doLongDescriptorWrapper(LookupLevel curr_lookup_level)
Definition: table_walker.cc:2141
gem5::ArmISA::TableWalker::_haveVirtualization
bool _haveVirtualization
Definition: table_walker.hh:984
gem5::ArmISA::TableWalker::L1Descriptor::texcb
uint8_t texcb() const
Memory region attributes: ARM DDI 0406B: B3-32.
Definition: table_walker.hh:208
gem5::ArmISA::TableWalker::L1Descriptor::L1Descriptor
L1Descriptor()
Default ctor.
Definition: table_walker.hh:118
gem5::ArmISA::TableWalker::WalkerState::isSecure
bool isSecure
If the access comes from the secure state.
Definition: table_walker.hh:799
gem5::ArmISA::TableWalker::L2Descriptor::xn
bool xn() const
Is execution allowed on this mapping?
Definition: table_walker.hh:312
gem5::ArmISA::TableWalker::LongDescEventByLevel
Event * LongDescEventByLevel[4]
Definition: table_walker.hh:1073
gem5::ArmISA::TableWalker::TableWalkerStats::walksLongDescriptor
statistics::Scalar walksLongDescriptor
Definition: table_walker.hh:994
gem5::ArmISA::TableWalker::WalkerState::pxnTable
bool pxnTable
Definition: table_walker.hh:810
gem5::ArmISA::TableWalker::Port
Definition: table_walker.hh:869
gem5::ArmISA::TableWalker::LongDescriptor::pxnTable
bool pxnTable() const
Is privileged execution allowed on subsequent lookup levels?
Definition: table_walker.hh:725
gem5::ArmISA::TableWalker::WalkerState::sctlr
SCTLR sctlr
Cached copy of the sctlr as it existed when translation began.
Definition: table_walker.hh:768
gem5::ArmISA::TableWalker::walk
Fault walk(const RequestPtr &req, ThreadContext *tc, uint16_t asid, vmid_t _vmid, bool _isHyp, BaseMMU::Mode mode, BaseMMU::Translation *_trans, bool timing, bool functional, bool secure, TLB::ArmTranslationType tranType, bool _stage2Req)
Definition: table_walker.cc:282
gem5::ArmISA::TableWalker::WalkerState::el
ExceptionLevel el
Current exception level.
Definition: table_walker.hh:742
gem5::ArmISA::TableWalker::Port::sendAtomicReq
void sendAtomicReq(Addr desc_addr, int size, uint8_t *data, Request::Flags flag, Tick delay)
Definition: table_walker.cc:178
gem5::ArmISA::TableWalker::pendingChangeTick
Tick pendingChangeTick
Definition: table_walker.hh:1008
gem5::ArmISA::TableWalker::TableWalkerStats::walks
statistics::Scalar walks
Definition: table_walker.hh:992
gem5::ArmISA::TableWalker::L2Descriptor::global
bool global(WalkerState *currState) const
Is the translation global (no asid used)?
Definition: table_walker.hh:318
gem5::ArmISA::TableWalker::WalkerState::longDesc
LongDescriptor longDesc
Long-format descriptor (LPAE and AArch64)
Definition: table_walker.hh:838
gem5::ArmISA::TableWalker::L2Descriptor::texcb
uint8_t texcb() const
Memory region attributes: ARM DDI 0406B: B3-32.
Definition: table_walker.hh:330
gem5::ArmISA::TableWalker::doProcessEvent
EventFunctionWrapper doProcessEvent
Definition: table_walker.hh:1095
gem5::ArmISA::TableWalker::L2Descriptor::dbgHeader
virtual std::string dbgHeader() const
Definition: table_walker.hh:279
gem5::ArmISA::TableWalker::readDataTimed
void readDataTimed(ThreadContext *tc, Addr desc_addr, Stage2Walk *translation, int num_bytes, Request::Flags flags)
Definition: table_walker.cc:2451
gem5::ArmISA::TableWalker::completeDrain
void completeDrain()
Checks if all state is cleared and if so, completes drain.
Definition: table_walker.cc:238
gem5::ArmISA::TableWalker::memAttrsAArch64
void memAttrsAArch64(ThreadContext *tc, TlbEntry &te, LongDescriptor &lDescriptor)
Definition: table_walker.cc:1576
gem5::ArmISA::TableWalker::TableWalkerStats::walksLongTerminatedAtLevel
statistics::Vector walksLongTerminatedAtLevel
Definition: table_walker.hh:996
data
const char data[]
Definition: circlebuf.test.cc:48
gem5::ArmISA::TableWalker::doL1LongDescriptorWrapper
void doL1LongDescriptorWrapper()
Definition: table_walker.cc:2123
gem5::ArmISA::TableWalker::LongDescriptor::pfn
Addr pfn() const
Return the physical frame, bits shifted right.
Definition: table_walker.hh:514
gem5::ArmISA::TableWalker::pendingQueue
std::list< WalkerState * > pendingQueue
Queue of requests that have passed are waiting because the walker is currently busy.
Definition: table_walker.hh:952
gem5::ArmISA::TableWalker::LongDescriptor::Block
@ Block
Definition: table_walker.hh:393
gem5::ArmISA::TableWalker::WalkerState::vaddr
Addr vaddr
The virtual address that is being translated with tagging removed.
Definition: table_walker.hh:762
gem5::ArmISA::TableWalker::L2Descriptor
Level 2 page table descriptor.
Definition: table_walker.hh:251
gem5::ArmISA::TableWalker::requestorId
RequestorID requestorId
Requestor id assigned by the MMU.
Definition: table_walker.hh:958
gem5::ArmISA::TableWalker::WalkerState::tcr
TCR tcr
Definition: table_walker.hh:780
gem5::ArmISA::TableWalker::L1Descriptor::Section
@ Section
Definition: table_walker.hh:106
gem5::ArmISA::TableWalker::LongDescriptor::global
bool global(WalkerState *currState) const
Is the translation global (no asid used)?
Definition: table_walker.hh:592
gem5::ArmISA::TableWalker::Stage2Walk::req
RequestPtr req
Definition: table_walker.hh:911
gem5::ArmISA::TableWalker::LongDescriptor::rw
bool rw() const
Read/write access protection flag.
Definition: table_walker.hh:632
gem5::ArmISA::TableWalker::LongDescriptor::apTable
uint8_t apTable() const
Two bit access protection flags for subsequent levels of lookup.
Definition: table_walker.hh:696
gem5::ArmISA::TableWalker::getTableWalkerPort
Port & getTableWalkerPort()
Definition: table_walker.cc:106
gem5::ArmISA::TableWalker::nextWalk
void nextWalk(ThreadContext *tc)
Definition: table_walker.cc:2197
gem5::QueuedRequestPort
The QueuedRequestPort combines two queues, a request queue and a snoop response queue,...
Definition: qport.hh:109
gem5::ArmISA::TableWalker::LongDescriptor::paddr
Addr paddr() const
Return the physical address of the entry.
Definition: table_walker.hh:520
gem5::BaseMMU::Mode
Mode
Definition: mmu.hh:53
gem5::ArmISA::TableWalker::WalkerState::cpsr
CPSR cpsr
Cached copy of the cpsr as it existed when translation began.
Definition: table_walker.hh:774
gem5::ArmISA::asid
asid
Definition: misc_types.hh:617
gem5::ArmISA::TableWalker::L2Descriptor::domain
virtual TlbEntry::DomainType domain() const
Definition: table_walker.hh:284
gem5::ArmISA::TableWalker::WalkerState::userTable
bool userTable
Definition: table_walker.hh:808
gem5::ArmISA::domain
Bitfield< 7, 4 > domain
Definition: misc_types.hh:423
gem5::ArmISA::TableWalker::Stage2Walk
This translation class is used to trigger the data fetch once a timing translation returns the transl...
Definition: table_walker.hh:906
gem5::ArmISA::TableWalker::TableWalkerStats::requestOrigin
statistics::Vector2d requestOrigin
Definition: table_walker.hh:1004
gem5::ArmISA::TableWalker::DescriptorBase::xn
virtual bool xn() const =0
gem5::ArmISA::TableWalker::LongDescriptor::nextDescAddr
Addr nextDescAddr(Addr va) const
Return the address of the next descriptor.
Definition: table_walker.hh:552
gem5::MipsISA::event
Bitfield< 10, 5 > event
Definition: pra_constants.hh:300
gem5::ArmISA::TableWalker::LongDescriptor::EntryType
EntryType
Descriptor type.
Definition: table_walker.hh:389
gem5::ArmISA::vmid_t
uint16_t vmid_t
Definition: types.hh:57
gem5::ArmISA::L2
@ L2
Definition: pagetable.hh:80
gem5::ArmISA::TableWalker::DescriptorBase::texcb
virtual uint8_t texcb() const
Definition: table_walker.hh:88
gem5::ArmISA::TableWalker::WalkerState::secureLookup
bool secureLookup
Helper variables used to implement hierarchical access permissions when the long-desc.
Definition: table_walker.hh:806
gem5::ArmISA::TableWalker::LongDescriptor::Table
@ Table
Definition: table_walker.hh:392
gem5::ArmISA::LookupLevel
LookupLevel
Definition: pagetable.hh:76
gem5::ArmISA::TableWalker::TableWalkerState::delay
Tick delay
Definition: table_walker.hh:865
gem5::ArmISA::TableWalker::TableWalkerStats::squashedAfter
statistics::Scalar squashedAfter
Definition: table_walker.hh:998
gem5::ArmISA::TableWalker::toLookupLevel
static LookupLevel toLookupLevel(uint8_t lookup_level_as_int)
Definition: table_walker.cc:2349
gem5::ArmISA::TableWalker::LongDescriptor::LongDescriptor
LongDescriptor()
Definition: table_walker.hh:397
gem5::ArmISA::TableWalker::L2Descriptor::offsetBits
virtual uint8_t offsetBits() const
Definition: table_walker.hh:294
gem5::ArmISA::TableWalker::LongDescriptor::_dirty
bool _dirty
This entry has been modified (access flag set) and needs to be written back to memory.
Definition: table_walker.hh:407
gem5::ArmISA::TLB
Definition: tlb.hh:109
gem5::statistics::Vector2d
A 2-Dimensional vecto of scalar stats.
Definition: statistics.hh:2055
gem5::ArmISA::TableWalker::L1Descriptor::data
uint32_t data
The raw bits of the entry.
Definition: table_walker.hh:111
gem5::statistics::Vector
A vector of scalar stats.
Definition: statistics.hh:2003
gem5::ArmISA::TableWalker::L1Descriptor::Ignore
@ Ignore
Definition: table_walker.hh:104
gem5::ArmISA::TableWalker::_haveLPAE
bool _haveLPAE
Definition: table_walker.hh:983
tlb.hh
gem5::ArmISA::TableWalker::L2Descriptor::data
uint32_t data
The raw bits of the entry.
Definition: table_walker.hh:255
gem5::ArmISA::TlbEntry::DomainType::Client
@ Client
gem5::ArmISA::TableWalker::WalkerState::name
std::string name() const
Definition: table_walker.hh:859
gem5::ArmISA::TableWalker::fetchDescriptor
bool fetchDescriptor(Addr descAddr, uint8_t *data, int numBytes, Request::Flags flags, int queueIndex, Event *event, void(TableWalker::*doDescriptor)())
Definition: table_walker.cc:2206
gem5::ArmISA::TableWalker::TableWalkerStats::walkServiceTime
statistics::Histogram walkServiceTime
Definition: table_walker.hh:1000
gem5::ArmISA::TableWalker::Port::handleResp
void handleResp(TableWalkerState *state, Addr addr, Addr size, Tick delay=0)
Definition: table_walker.cc:228
gem5::mbits
constexpr T mbits(T val, unsigned first, unsigned last)
Mask off the given bits in place like bits() but without shifting.
Definition: bitfield.hh:103
gem5::ArmISA::TableWalker::L1Descriptor::pfn
Addr pfn() const
Return the physical frame, bits shifted right.
Definition: table_walker.hh:166
gem5::ArmISA::TableWalker::Stage2Walk::setVirt
void setVirt(Addr vaddr, int size, Request::Flags flags, int requestorId)
Definition: table_walker.hh:928
system.hh
gem5::ArmISA::TableWalker::WalkerState::stage2Tran
BaseMMU::Translation * stage2Tran
A pointer to the stage 2 translation that's in progress.
Definition: table_walker.hh:819
gem5::InvalidPortID
const PortID InvalidPortID
Definition: types.hh:253
gem5::ArmISA::TableWalker::WalkerState::vmid
vmid_t vmid
Definition: table_walker.hh:752
gem5::ArmISA::TableWalker::WalkerState::vaddr_tainted
Addr vaddr_tainted
The virtual address that is being translated.
Definition: table_walker.hh:765
gem5::ArmISA::TableWalker::Grain64KB
@ Grain64KB
Definition: table_walker.hh:380
types.hh
gem5::ArmISA::TableWalker::WalkerState::doLongDescriptor
void doLongDescriptor()
gem5::ArmISA::TableWalker::L2Descriptor::large
bool large() const
What is the size of the mapping?
Definition: table_walker.hh:306
gem5::ArmISA::TableWalker::Port::requestorId
RequestorID requestorId
Cached requestorId of the table walker.
Definition: table_walker.hh:901
request.hh
gem5::ArmISA::TlbEntry
Definition: pagetable.hh:86
gem5::ArmISA::TableWalker::LongDescriptor::ap
static uint8_t ap(bool rw, bool user)
Return the AP bits as compatible with the AP[2:0] format.
Definition: table_walker.hh:648
gem5::ArmISA::TableWalker::physAddrRange
uint8_t physAddrRange() const
Definition: table_walker.hh:1021
gem5::ArmISA::TableWalker::Port::Port
Port(TableWalker *_walker, RequestorID id)
Definition: table_walker.cc:136
gem5::ArmISA::TlbEntry::DomainType
DomainType
Definition: pagetable.hh:96
gem5::ArmISA::TableWalker::getPort
gem5::Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
Definition: table_walker.cc:112
gem5::ArmISA::TableWalker::Stage2Walk::event
Event * event
Definition: table_walker.hh:912
gem5::ArmISA::TableWalker::Stage2Walk::data
uint8_t * data
Definition: table_walker.hh:909
gem5::ArmISA::TableWalker::L1Descriptor::shareable
bool shareable() const
If the section is shareable.
Definition: table_walker.hh:214
gem5::ArmISA::TableWalker::COMPLETED
static const unsigned COMPLETED
Definition: table_walker.hh:1011
gem5::ArmISA::TableWalker::WalkerState::functional
bool functional
If the atomic mode should be functional.
Definition: table_walker.hh:825
gem5::ArmISA::TableWalker::TableWalkerStats::walksShortDescriptor
statistics::Scalar walksShortDescriptor
Definition: table_walker.hh:993
gem5::ArmISA::TableWalker::LongDescriptor::nextTableAddr
Addr nextTableAddr() const
Return the address of the next page table.
Definition: table_walker.hh:535
gem5::ArmISA::TableWalker::L1Descriptor::getRawData
virtual uint64_t getRawData() const
Definition: table_walker.hh:123
gem5::ArmISA::TableWalker::REQUESTED
static const unsigned REQUESTED
Definition: table_walker.hh:1010
gem5::ArmISA::TableWalker::LongDescriptor::ap
uint8_t ap() const
2-bit access protection flags
Definition: table_walker.hh:624
gem5::ArmISA::TableWalker::L1Descriptor::ap
uint8_t ap() const
Three bit access protection flags.
Definition: table_walker.hh:186
gem5::ArmISA::TableWalker::L1Descriptor::setAp0
void setAp0()
Set access flag that this entry has been touched.
Definition: table_walker.hh:222
gem5::ArmISA::TableWalker::testWalk
Fault testWalk(Addr pa, Addr size, TlbEntry::DomainType domain, LookupLevel lookup_level)
Definition: table_walker.cc:2382
gem5::ArmISA::TableWalker::doL1Descriptor
void doL1Descriptor()
Definition: table_walker.cc:1676
gem5::ArmISA::TableWalker::TableWalkerStats::TableWalkerStats
TableWalkerStats(statistics::Group *parent)
Definition: table_walker.cc:2501
gem5::ArmISA::TableWalker::Port::handleRespPacket
void handleRespPacket(PacketPtr pkt, Tick delay=0)
Definition: table_walker.cc:213
gem5::ArmISA::TableWalker::WalkerState::asid
uint16_t asid
ASID that we're servicing the request under.
Definition: table_walker.hh:751
gem5::ArmISA::TableWalker::LongDescriptor::xnTable
bool xnTable() const
Is execution allowed on subsequent lookup levels?
Definition: table_walker.hh:718
gem5::ArmISA::TableWalker::haveSecurity
bool haveSecurity
Cached copies of system-level properties.
Definition: table_walker.hh:982
gem5::statistics::Histogram
A simple histogram stat.
Definition: statistics.hh:2123
gem5::ArmISA::TableWalker::L1Descriptor::PageTable
@ PageTable
Definition: table_walker.hh:105
gem5::ArmISA::pa
Bitfield< 39, 12 > pa
Definition: misc_types.hh:656
gem5::ArmISA::TableWalker::LongDescriptor::secureTable
bool secureTable() const
Whether the subsequent levels of lookup are secure.
Definition: table_walker.hh:689
gem5::ArmISA::TableWalker::Stage2Walk::parent
TableWalker & parent
Definition: table_walker.hh:913
gem5::Flags< FlagsType >
gem5::DrainState
DrainState
Object drain/handover states.
Definition: drain.hh:74
gem5::ArmISA::TableWalker::haveLargeAsid64
bool haveLargeAsid64() const
Definition: table_walker.hh:1020
gem5::ArmISA::TableWalker::sctlr
SCTLR sctlr
Cached copy of the sctlr as it existed when translation began.
Definition: table_walker.hh:970
gem5::ArmISA::TableWalker::WalkerState::isHyp
bool isHyp
Definition: table_walker.hh:753
gem5::ArmISA::TableWalker::LongDescriptor::data
uint64_t data
The raw bits of the entry.
Definition: table_walker.hh:403
gem5::ArmISA::TableWalker::LongDescriptor::sh
uint8_t sh() const
2-bit shareability field
Definition: table_walker.hh:617
gem5::ArmISA::TableWalker::LongDescriptor::domain
TlbEntry::DomainType domain() const
Definition: table_walker.hh:653
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::Named::name
virtual std::string name() const
Definition: named.hh:47
gem5::ArmISA::TableWalker::Stage2Walk::finish
void finish(const Fault &fault, const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode)
Definition: table_walker.cc:2470
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::ArmISA::TableWalker::Port::sendFunctionalReq
void sendFunctionalReq(Addr desc_addr, int size, uint8_t *data, Request::Flags flag)
Definition: table_walker.cc:166
gem5::ArmISA::ArmFault::FaultSource
FaultSource
Generic fault source enums used to index into {short/long/aarch64}DescFaultSources[] to get the actua...
Definition: faults.hh:95
gem5::ArmISA::TableWalker::LongDescriptor::getRawData
virtual uint64_t getRawData() const
Definition: table_walker.hh:418
gem5::ArmISA::TableWalker::L2Descriptor::dirty
bool dirty() const
This entry needs to be written back to memory.
Definition: table_walker.hh:368
gem5::Event
Definition: eventq.hh:251
gem5::ArmISA::TableWalker::processWalkAArch64
Fault processWalkAArch64()
Definition: table_walker.cc:868
gem5::ArmISA::TableWalker::pageSizeNtoStatBin
static uint8_t pageSizeNtoStatBin(uint8_t N)
Definition: table_walker.cc:2391
gem5::ArmISA::TableWalker::WalkerState::delayed
bool delayed
Whether the response is delayed in timing mode due to additional lookups.
Definition: table_walker.hh:842
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::ArmISA::TableWalker::L2Descriptor::l1Parent
L1Descriptor * l1Parent
Definition: table_walker.hh:256
gem5::ArmISA::TableWalker::L1Descriptor::EntryType
EntryType
Type of page table entry ARM DDI 0406B: B3-8.
Definition: table_walker.hh:102
gem5::ArmISA::TableWalker::doL0LongDescriptorWrapper
void doL0LongDescriptorWrapper()
Definition: table_walker.cc:2117
gem5::ArmISA::TableWalker::WalkerState::tc
ThreadContext * tc
Thread context that we're doing the walk for.
Definition: table_walker.hh:736
gem5::ArmISA::EL2
@ EL2
Definition: types.hh:268
gem5::ArmISA::TableWalker::processWalkLPAE
Fault processWalkLPAE()
Definition: table_walker.cc:672
gem5::ArmISA::TableWalker::WalkerState::physAddrRange
int physAddrRange
Current physical address range in bits.
Definition: table_walker.hh:745
gem5::ArmISA::TableWalker::L1Descriptor::global
bool global(WalkerState *currState) const
Is the translation global (no asid used)?
Definition: table_walker.hh:174
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::ArmISA::TableWalker::PARAMS
PARAMS(ArmTableWalker)
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::ArmISA::TableWalker::GrainSize
GrainSize
Definition: table_walker.hh:376
gem5::ArmISA::TableWalker::setTlb
void setTlb(TLB *_tlb)
Definition: table_walker.hh:1039
gem5::ArmISA::TableWalker::WalkerState::startTime
Tick startTime
Timestamp for calculating elapsed time in service (for stats)
Definition: table_walker.hh:847
gem5::ArmISA::TableWalker::L1Descriptor::l2Addr
Addr l2Addr() const
Address of L2 descriptor if it exists.
Definition: table_walker.hh:198
gem5::ArmISA::TableWalker::LongDescriptor::type
EntryType type() const
Return the descriptor type.
Definition: table_walker.hh:445
gem5::ArmISA::TableWalker::L1Descriptor::dirty
bool dirty() const
This entry needs to be written back to memory.
Definition: table_walker.hh:229
gem5::ArmISA::TableWalker::LongDescriptor::dbgHeader
virtual std::string dbgHeader() const
Definition: table_walker.hh:423
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::ArmISA::s
Bitfield< 4 > s
Definition: misc_types.hh:561
gem5::ArmISA::TableWalker::DescriptorBase::pfn
virtual Addr pfn() const =0
gem5::ArmISA::TableWalker::doL2DescEvent
EventFunctionWrapper doL2DescEvent
Definition: table_walker.hh:1059
gem5::ArmISA::TableWalker::DescriptorBase::offsetBits
virtual uint8_t offsetBits() const =0
gem5::ArmISA::TableWalker::WalkerState::ttbcr
TTBCR ttbcr
Definition: table_walker.hh:779
mmu.hh
gem5::ArmISA::TableWalker::L1Descriptor::domain
TlbEntry::DomainType domain() const
Domain Client/Manager: ARM DDI 0406B: B3-31.
Definition: table_walker.hh:192
gem5::ArmISA::TableWalker::TableWalkerStats::pageSizes
statistics::Vector pageSizes
Definition: table_walker.hh:1003
packet_queue.hh
gem5::ArmISA::TableWalker::WalkerState::isFetch
bool isFetch
If the access is a fetch (for execution, and no-exec) must be checked?
Definition: table_walker.hh:796
gem5::ArmISA::TableWalker::port
Port * port
Port shared by the two table walkers.
Definition: table_walker.hh:961
gem5::ArmISA::TableWalker::DescriptorBase::getRawData
virtual uint64_t getRawData() const =0
gem5::ArmISA::TableWalker::Stage2Walk::translateTiming
void translateTiming(ThreadContext *tc)
Definition: table_walker.cc:2496
gem5::ArmISA::TableWalker::doL2LongDescriptorWrapper
void doL2LongDescriptorWrapper()
Definition: table_walker.cc:2129
gem5::ArmISA::TableWalker::doL1DescriptorWrapper
void doL1DescriptorWrapper()
Definition: table_walker.cc:2017
gem5::ArmISA::TableWalker::WalkerState::req
RequestPtr req
Request that is currently being serviced.
Definition: table_walker.hh:748
gem5::ArmISA::TableWalker::L2Descriptor::L2Descriptor
L2Descriptor()
Default ctor.
Definition: table_walker.hh:263
gem5::ArmISA::TableWalker::processWalkWrapper
void processWalkWrapper()
Definition: table_walker.cc:472
gem5::ArmISA::TableWalker::LongDescriptor::physAddrRange
uint8_t physAddrRange
Definition: table_walker.hh:415
gem5::ArmISA::TableWalker::LongDescriptor::Invalid
@ Invalid
Definition: table_walker.hh:391
gem5::ArmISA::TableWalker::haveVirtualization
bool haveVirtualization() const
Definition: table_walker.hh:1019
gem5::ArmISA::TableWalker::_physAddrRange
uint8_t _physAddrRange
Definition: table_walker.hh:985
Block
Definition: global.h:77
gem5::ArmISA::TableWalker::numSquashable
unsigned numSquashable
The number of walks belonging to squashed instructions that can be removed from the pendingQueue per ...
Definition: table_walker.hh:979
gem5::ArmISA::te
Bitfield< 30 > te
Definition: misc_types.hh:337
gem5::ArmISA::TableWalker::LongDescriptor::user
bool user() const
User/privileged level access protection flag.
Definition: table_walker.hh:639
gem5::ArmISA::TableWalker::WalkerState::transState
BaseMMU::Translation * transState
Translation state for delayed requests.
Definition: table_walker.hh:756
gem5::ArmISA::TableWalker::DescriptorBase::secure
virtual bool secure(bool have_security, WalkerState *currState) const =0
gem5::ArmISA::TableWalker::_haveLargeAsid64
bool _haveLargeAsid64
Definition: table_walker.hh:986
gem5::ArmISA::TableWalker::LongDescriptor::grainSize
GrainSize grainSize
Width of the granule size in bits.
Definition: table_walker.hh:413
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
gem5::ArmISA::TableWalker::DescriptorBase
Definition: table_walker.hh:71
gem5::ArmISA::TableWalker::WalkerState::tableWalker
TableWalker * tableWalker
Definition: table_walker.hh:844
gem5::ArmISA::EL3
@ EL3
Definition: types.hh:269
gem5::ArmISA::TableWalker::Port::reqQueue
ReqPacketQueue reqQueue
Packet queue used to store outgoing requests.
Definition: table_walker.hh:895
gem5::ArmISA::TableWalker::WalkerState::htcr
HTCR htcr
Cached copy of the htcr as it existed when translation began.
Definition: table_walker.hh:784
gem5::ArmISA::TableWalker::TableWalkerState
Definition: table_walker.hh:862
gem5::ArmISA::TableWalker::L2Descriptor::secure
bool secure(bool have_security, WalkerState *currState) const
Definition: table_walker.hh:289
gem5::ArmISA::TableWalker::WalkerState::isWrite
bool isWrite
If the access is a write.
Definition: table_walker.hh:793
gem5::ArmISA::L3
@ L3
Definition: pagetable.hh:81
gem5::Packet::SenderState
A virtual base opaque structure used to hold state associated with the packet (e.g....
Definition: packet.hh:457
gem5::ArmISA::TableWalker::checkVAddrSizeFaultAArch64
bool checkVAddrSizeFaultAArch64(Addr addr, int top_bit, GrainSize granule, int tsz, bool low_range)
Definition: table_walker.cc:844
gem5::ArmISA::TableWalker::L1Descriptor::Reserved
@ Reserved
Definition: table_walker.hh:107
gem5::ArmISA::TableWalker::WalkerState::vtcr
VTCR_t vtcr
Cached copy of the vtcr as it existed when translation began.
Definition: table_walker.hh:790
gem5::ArmISA::MAX_LOOKUP_LEVELS
@ MAX_LOOKUP_LEVELS
Definition: pagetable.hh:82
faults.hh
gem5::ArmISA::TableWalker::L1Descriptor::type
EntryType type() const
Definition: table_walker.hh:138
gem5::ArmISA::TableWalker::generateLongDescFault
Fault generateLongDescFault(ArmFault::FaultSource src)
Definition: table_walker.cc:1781
gem5::ArmISA::TableWalker::Grain16KB
@ Grain16KB
Definition: table_walker.hh:379
gem5::ArmISA::TableWalker::L1Descriptor::xn
bool xn() const
Is the translation not allow execution?
Definition: table_walker.hh:180
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ArmISA::TableWalker::LongDescriptor
Long-descriptor format (LPAE)
Definition: table_walker.hh:385
gem5::ArmISA::TableWalker::TableWalkerStats
Statistics.
Definition: table_walker.hh:989
gem5::ArmISA::TableWalker::LongDescriptor::contiguousHint
bool contiguousHint() const
Contiguous hint bit.
Definition: table_walker.hh:585
gem5::ArmISA::TableWalker::L2Descriptor::pfn
Addr pfn() const
Return the physical frame, bits shifted right.
Definition: table_walker.hh:338
gem5::ArmISA::TableWalker::Stage2Walk::Stage2Walk
Stage2Walk(TableWalker &_parent, uint8_t *_data, Event *_event, Addr vaddr)
Definition: table_walker.cc:2461
gem5::ArmISA::TableWalker::LongDescriptor::Page
@ Page
Definition: table_walker.hh:394
gem5::ArmISA::TableWalker::TableWalkerStats::pendingWalks
statistics::Histogram pendingWalks
Definition: table_walker.hh:1002
gem5::ArmISA::TableWalker::doL2Descriptor
void doL2Descriptor()
Definition: table_walker.cc:1961
gem5::ArmISA::TableWalker::pendingReqs
unsigned pendingReqs
Definition: table_walker.hh:1007
gem5::ArmISA::va
Bitfield< 8 > va
Definition: misc_types.hh:275
gem5::ArmISA::TableWalker::TableWalkerStats::walkWaitTime
statistics::Histogram walkWaitTime
Definition: table_walker.hh:999
gem5::ClockedObject
The ClockedObject class extends the SimObject with a clock and accessor functions to relate ticks to ...
Definition: clocked_object.hh:234
gem5::ArmISA::TableWalker::Stage2Walk::markDelayed
void markDelayed()
Signal that the translation has been delayed due to a hw page table walk.
Definition: table_walker.hh:922
gem5::ArmISA::TableWalker::DescriptorBase::lookupLevel
LookupLevel lookupLevel
Current lookup level for this descriptor.
Definition: table_walker.hh:77
gem5::ArmISA::TableWalker::DescriptorBase::global
virtual bool global(WalkerState *currState) const =0
gem5::ArmISA::TableWalker::Port::snoopRespQueue
SnoopRespPacketQueue snoopRespQueue
Packet queue used to store outgoing snoop responses.
Definition: table_walker.hh:898
gem5::ArmISA::TableWalker::WalkerState::doL2Descriptor
void doL2Descriptor()
gem5::ArmISA::TableWalker::L1Descriptor::supersection
bool supersection() const
Is the page a Supersection (16 MiB)?
Definition: table_walker.hh:144
gem5::ArmISA::TableWalker::LongDescriptor::aarch64
bool aarch64
True if the current lookup is performed in AArch64 state.
Definition: table_walker.hh:410
gem5::ArmISA::TableWalker::WalkerState::xnTable
bool xnTable
Definition: table_walker.hh:809
gem5::ArmISA::L1
@ L1
Definition: pagetable.hh:79
gem5::ArmISA::TableWalker::LongDescriptor::af
bool af() const
Returns true if the access flag (AF) is set.
Definition: table_walker.hh:610
gem5::EventFunctionWrapper
Definition: eventq.hh:1115
gem5::ArmISA::TableWalker::L1Descriptor::offsetBits
virtual uint8_t offsetBits() const
Definition: table_walker.hh:133
gem5::ArmISA::TableWalker::WalkerState::stage2Req
bool stage2Req
Flag indicating if a second stage of lookup is required.
Definition: table_walker.hh:816
gem5::ArmISA::TableWalker::stateQueues
std::list< WalkerState * > stateQueues[MAX_LOOKUP_LEVELS]
Queues of requests for all the different lookup levels.
Definition: table_walker.hh:948
gem5::BaseMMU::Translation
Definition: mmu.hh:55
gem5::ArmISA::TableWalker::L1Descriptor
Definition: table_walker.hh:98
gem5::ArmISA::TableWalker::Port::sendTimingReq
void sendTimingReq(Addr desc_addr, int size, uint8_t *data, Request::Flags flag, Tick delay, Event *event)
Definition: table_walker.cc:190
gem5::ArmISA::TableWalker::setPort
void setPort(Port *_port)
Definition: table_walker.hh:1040
gem5::ArmISA::TableWalker::L1Descriptor::paddr
Addr paddr() const
Return the physcal address of the entry, bits in position.
Definition: table_walker.hh:150
gem5::ArmISA::TableWalker::LongDescriptor::rwTable
uint8_t rwTable() const
R/W protection flag for subsequent levels of lookup.
Definition: table_walker.hh:703
gem5::ArmISA::TableWalker
Definition: table_walker.hh:66
gem5::ArmISA::TableWalker::WalkerState::levels
unsigned levels
Page entries walked during service (for stats)
Definition: table_walker.hh:850
gem5::ArmISA::TableWalker::doL3LongDescEvent
EventFunctionWrapper doL3LongDescEvent
Definition: table_walker.hh:1070
gem5::ArmISA::TableWalker::WalkerState::rwTable
bool rwTable
Definition: table_walker.hh:807
gem5::ArmISA::TableWalker::currState
WalkerState * currState
Definition: table_walker.hh:972
gem5::ArmISA::TableWalker::TableWalker
TableWalker(const Params &p)
Definition: table_walker.cc:61
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
gem5::ArmISA::TableWalker::L2Descriptor::_dirty
bool _dirty
This entry has been modified (access flag set) and needs to be written back to memory.
Definition: table_walker.hh:260
gem5::ArmISA::L0
@ L0
Definition: pagetable.hh:78
gem5::ArmISA::TableWalker::WalkerState::doL1Descriptor
void doL1Descriptor()
gem5::ArmISA::TableWalker::WalkerState::hpd
bool hpd
Hierarchical access permission disable.
Definition: table_walker.hh:813
gem5::ArmISA::TableWalker::LongDescriptor::offsetBits
uint8_t offsetBits() const
Return the bit width of the page/block offset.
Definition: table_walker.hh:484
qport.hh
gem5::ArmISA::TableWalker::LongDescriptor::memAttr
uint8_t memAttr() const
Memory attributes, only used by stage 2 translations.
Definition: table_walker.hh:668
gem5::ArmISA::TableWalker::LongDescriptor::xn
bool xn() const
Is execution allowed on this mapping?
Definition: table_walker.hh:571
gem5::ArmISA::TableWalker::drain
DrainState drain() override
Draining is the process of clearing out the states of SimObjects.These are the SimObjects that are pa...
Definition: table_walker.cc:251
gem5::ArmISA::TableWalker::drainResume
void drainResume() override
Resume execution after a successful drain.
Definition: table_walker.cc:272
gem5::ArmISA::TableWalker::L1Descriptor::_dirty
bool _dirty
This entry has been modified (access flag set) and needs to be written back to memory.
Definition: table_walker.hh:115
gem5::ArmISA::TableWalker::memAttrs
void memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr, uint8_t texcb, bool s)
Definition: table_walker.cc:1243
clocked_object.hh
misc.hh
gem5::ArmISA::TableWalker::WalkerState::scr
SCR scr
Cached copy of the scr as it existed when translation began.
Definition: table_walker.hh:771
gem5::ArmISA::TableWalker::mmu
MMU * mmu
The MMU to forward second stage look upts to.
Definition: table_walker.hh:955
gem5::ArmISA::TableWalker::~TableWalker
virtual ~TableWalker()
Definition: table_walker.cc:100
gem5::ArmISA::TableWalker::doL2DescriptorWrapper
void doL2DescriptorWrapper()
Definition: table_walker.cc:2076
gem5::ArmISA::TableWalker::LongDescriptor::attrIndx
uint8_t attrIndx() const
Attribute index.
Definition: table_walker.hh:661
gem5::ArmISA::TableWalker::memAttrsLPAE
void memAttrsLPAE(ThreadContext *tc, TlbEntry &te, LongDescriptor &lDescriptor)
Definition: table_walker.cc:1450
gem5::ArmISA::TableWalker::WalkerState::isUncacheable
bool isUncacheable
True if table walks are uncacheable (for table descriptors)
Definition: table_walker.hh:802
gem5::ArmISA::TableWalker::L2Descriptor::L2Descriptor
L2Descriptor(L1Descriptor &parent)
Definition: table_walker.hh:268
gem5::ArmISA::TableWalker::WalkerState::l2Desc
L2Descriptor l2Desc
Definition: table_walker.hh:835
gem5::ArmISA::TableWalker::LongDescriptor::dirty
bool dirty() const
This entry needs to be written back to memory.
Definition: table_walker.hh:683
gem5::ArmISA::TableWalker::L2Descriptor::paddr
Addr paddr(Addr va) const
Return complete physical address given a VA.
Definition: table_walker.hh:344
gem5::ArmISA::TableWalker::L2Descriptor::shareable
bool shareable() const
If the section is shareable.
Definition: table_walker.hh:353
gem5::statistics::Group
Statistics container.
Definition: group.hh:93
gem5::ArmISA::TableWalker::DescriptorBase::DescriptorBase
DescriptorBase()
Definition: table_walker.hh:74
gem5::ArmISA::TLB::ArmTranslationType
ArmTranslationType
Definition: tlb.hh:128
gem5::ArmISA::TableWalker::checkAddrSizeFaultAArch64
bool checkAddrSizeFaultAArch64(Addr addr, int pa_range)
Returns true if the address exceeds the range permitted by the system-wide setting or by the TCR_ELx ...
Definition: table_walker.cc:861
gem5::ReqPacketQueue
Definition: packet_queue.hh:226
gem5::ArmISA::TableWalker::Grain4KB
@ Grain4KB
Definition: table_walker.hh:378
gem5::ArmISA::TableWalker::L2Descriptor::ap
uint8_t ap() const
Three bit access protection flags.
Definition: table_walker.hh:324
gem5::ArmISA::TableWalker::L1Descriptor::dbgHeader
virtual std::string dbgHeader() const
Definition: table_walker.hh:128
gem5::ArmISA::TableWalker::doL2LongDescEvent
EventFunctionWrapper doL2LongDescEvent
Definition: table_walker.hh:1068
gem5::ArmISA::TableWalker::L2Descriptor::setAp0
void setAp0()
Set access flag that this entry has been touched.
Definition: table_walker.hh:361
gem5::ArmISA::TableWalker::L2Descriptor::invalid
bool invalid() const
Is the entry invalid.
Definition: table_walker.hh:300
gem5::ArmISA::TableWalker::isStage2
const bool isStage2
Indicates whether this table walker is part of the stage 2 mmu.
Definition: table_walker.hh:964
gem5::RequestorID
uint16_t RequestorID
Definition: request.hh:95
gem5::ArmISA::TableWalker::Port::recvTimingResp
bool recvTimingResp(PacketPtr pkt) override
Receive a timing response from the peer.
Definition: table_walker.cc:201
gem5::ClockedObject::Params
ClockedObjectParams Params
Parameters of ClockedObject.
Definition: clocked_object.hh:240
gem5::ArmISA::TableWalker::L2Descriptor::getRawData
virtual uint64_t getRawData() const
Definition: table_walker.hh:274
gem5::MipsISA::vaddr
vaddr
Definition: pra_constants.hh:278
gem5::ArmISA::TableWalker::doL3LongDescriptorWrapper
void doL3LongDescriptorWrapper()
Definition: table_walker.cc:2135
gem5::ArmISA::TableWalker::L1Descriptor::secure
bool secure(bool have_security, WalkerState *currState) const
Returns true if this entry targets the secure physical address map.
Definition: table_walker.hh:238
gem5::ArmISA::TableWalker::stats
gem5::ArmISA::TableWalker::TableWalkerStats stats
std::list
STL list class.
Definition: stl.hh:51
gem5::ArmISA::TableWalker::DescriptorBase::ap
virtual uint8_t ap() const =0
gem5::ArmISA::TableWalker::LongDescriptor::setAf
void setAf()
Set access flag that this entry has been touched.
Definition: table_walker.hh:676
gem5::SnoopRespPacketQueue
Definition: packet_queue.hh:262
gem5::ArmISA::TableWalker::WalkerState::hcr
HCR hcr
Cached copy of the htcr as it existed when translation began.
Definition: table_walker.hh:787
gem5::ArmISA::TableWalker::WalkerState::WalkerState
WalkerState()
Definition: table_walker.cc:120
gem5::ArmISA::TableWalker::readDataUntimed
Fault readDataUntimed(ThreadContext *tc, Addr vaddr, Addr desc_addr, uint8_t *data, int num_bytes, Request::Flags flags, bool functional)
Definition: table_walker.cc:2412
gem5::ArmISA::TableWalker::WalkerState::aarch64
bool aarch64
If the access is performed in AArch64 state.
Definition: table_walker.hh:739
gem5::ArmISA::TableWalker::processWalk
Fault processWalk()
Definition: table_walker.cc:563
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::ArmISA::TableWalker::WalkerState::timing
bool timing
If the mode is timing or atomic.
Definition: table_walker.hh:822
gem5::ArmISA::TableWalker::Stage2Walk::numBytes
int numBytes
Definition: table_walker.hh:910
gem5::ArmISA::TableWalker::DescriptorBase::shareable
virtual bool shareable() const
Definition: table_walker.hh:92
gem5::ArmISA::stride
Bitfield< 21, 20 > stride
Definition: misc_types.hh:446
gem5::ArmISA::TableWalker::LongDescriptor::userTable
uint8_t userTable() const
User/privileged mode protection flag for subsequent levels of lookup.
Definition: table_walker.hh:711
gem5::ArmISA::TableWalker::Stage2Walk::fault
Fault fault
Definition: table_walker.hh:917
gem5::ArmISA::MMU
Definition: mmu.hh:52
gem5::ArmISA::TableWalker::doLongDescriptor
void doLongDescriptor()
Definition: table_walker.cc:1801
gem5::ArmISA::TableWalker::WalkerState
Definition: table_walker.hh:732
gem5::ArmISA::TableWalker::pendingChange
void pendingChange()
Definition: table_walker.cc:2366
gem5::ArmISA::TableWalker::DescriptorBase::domain
virtual TlbEntry::DomainType domain() const =0
gem5::ArmISA::TableWalker::WalkerState::fault
Fault fault
The fault that we are going to return.
Definition: table_walker.hh:759
gem5::ArmISA::TableWalker::Stage2Walk::oVAddr
Addr oVAddr
Definition: table_walker.hh:914
gem5::ArmISA::TableWalker::ReservedGrain
@ ReservedGrain
Definition: table_walker.hh:381
gem5::ArmISA::TableWalker::doL1LongDescEvent
EventFunctionWrapper doL1LongDescEvent
Definition: table_walker.hh:1066
gem5::ArmISA::TableWalker::LongDescriptor::secure
bool secure(bool have_security, WalkerState *currState) const
Returns true if this entry targets the secure physical address map.
Definition: table_walker.hh:438
gem5::ArmISA::TableWalker::L1Descriptor::paddr
Addr paddr(Addr va) const
Return the physcal address of the entry, bits in position.
Definition: table_walker.hh:157
gem5::ArmISA::TableWalker::tlb
TLB * tlb
TLB that is initiating these table walks.
Definition: table_walker.hh:967
gem5::ArmISA::TableWalker::WalkerState::tranType
TLB::ArmTranslationType tranType
The translation type that has been requested.
Definition: table_walker.hh:831
gem5::ArmISA::TableWalker::WalkerState::l1Desc
L1Descriptor l1Desc
Short-format descriptors.
Definition: table_walker.hh:834
gem5::ArmISA::TableWalker::setMmu
void setMmu(MMU *_mmu)
Definition: table_walker.hh:1038
gem5::ArmISA::TableWalker::TableWalkerStats::walksShortTerminatedAtLevel
statistics::Vector walksShortTerminatedAtLevel
Definition: table_walker.hh:995
gem5::ArmISA::TableWalker::Port::createPacket
PacketPtr createPacket(Addr desc_addr, int size, uint8_t *data, Request::Flags flag, Tick delay, Event *event)
Definition: table_walker.cc:145
gem5::ArmISA::TableWalker::WalkerState::mode
BaseMMU::Mode mode
Save mode for use in delayed response.
Definition: table_walker.hh:828
gem5::ArmISA::TableWalker::LongDescriptor::pxn
bool pxn() const
Is privileged execution allowed on this mapping? (LPAE only)
Definition: table_walker.hh:578
gem5::ArmISA::ExceptionLevel
ExceptionLevel
Definition: types.hh:264
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::ArmISA::TableWalker::pending
bool pending
If a timing translation is currently in progress.
Definition: table_walker.hh:975
gem5::ArmISA::mode
Bitfield< 4, 0 > mode
Definition: misc_types.hh:73
gem5::ArmISA::TableWalker::getTlb
TLB * getTlb()
Definition: table_walker.hh:1041
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::ArmISA::TableWalker::insertTableEntry
void insertTableEntry(DescriptorBase &descriptor, bool longDescriptor)
Definition: table_walker.cc:2274
gem5::ArmISA::TableWalker::doL0LongDescEvent
EventFunctionWrapper doL0LongDescEvent
Definition: table_walker.hh:1064
eventq.hh
gem5::ArmISA::TableWalker::TableWalkerStats::squashedBefore
statistics::Scalar squashedBefore
Definition: table_walker.hh:997

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