gem5  v21.2.1.1
table_walker.hh
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37 
38 #ifndef __ARCH_ARM_TABLE_WALKER_HH__
39 #define __ARCH_ARM_TABLE_WALKER_HH__
40 
41 #include <list>
42 
43 #include "arch/arm/faults.hh"
44 #include "arch/arm/mmu.hh"
45 #include "arch/arm/regs/misc.hh"
46 #include "arch/arm/system.hh"
47 #include "arch/arm/tlb.hh"
48 #include "arch/arm/types.hh"
49 #include "arch/generic/mmu.hh"
50 #include "mem/packet_queue.hh"
51 #include "mem/qport.hh"
52 #include "mem/request.hh"
53 #include "params/ArmTableWalker.hh"
54 #include "sim/clocked_object.hh"
55 #include "sim/eventq.hh"
56 
57 namespace gem5
58 {
59 
60 class ThreadContext;
61 
62 namespace ArmISA {
63 class Translation;
64 class TLB;
65 
66 class TableWalker : public ClockedObject
67 {
68  using LookupLevel = enums::ArmLookupLevel;
69 
70  public:
71  class WalkerState;
72 
74  {
75  public:
77 
80 
81  virtual Addr pfn() const = 0;
82  virtual TlbEntry::DomainType domain() const = 0;
83  virtual bool xn() const = 0;
84  virtual uint8_t ap() const = 0;
85  virtual bool global(WalkerState *currState) const = 0;
86  virtual uint8_t offsetBits() const = 0;
87  virtual bool secure(bool have_security, WalkerState *currState) const = 0;
88  virtual std::string dbgHeader() const = 0;
89  virtual uint64_t getRawData() const = 0;
90  virtual uint8_t texcb() const
91  {
92  panic("texcb() not implemented for this class\n");
93  }
94  virtual bool shareable() const
95  {
96  panic("shareable() not implemented for this class\n");
97  }
98  };
99 
101  {
102  public:
105  {
110  };
111 
113  uint32_t data;
114 
117  bool _dirty;
118 
120  L1Descriptor() : data(0), _dirty(false)
121  {
122  lookupLevel = LookupLevel::L1;
123  }
124 
125  uint64_t
126  getRawData() const override
127  {
128  return (data);
129  }
130 
131  std::string
132  dbgHeader() const override
133  {
134  return "Inserting Section Descriptor into TLB\n";
135  }
136 
137  uint8_t
138  offsetBits() const override
139  {
140  return 20;
141  }
142 
143  EntryType
144  type() const
145  {
146  return (EntryType)(data & 0x3);
147  }
148 
150  bool
151  supersection() const
152  {
153  return bits(data, 18);
154  }
155 
157  Addr
158  paddr() const
159  {
160  if (supersection())
161  panic("Super sections not implemented\n");
162  return mbits(data, 31, 20);
163  }
164 
166  Addr
167  paddr(Addr va) const
168  {
169  if (supersection())
170  panic("Super sections not implemented\n");
171  return mbits(data, 31, 20) | mbits(va, 19, 0);
172  }
173 
175  Addr
176  pfn() const override
177  {
178  if (supersection())
179  panic("Super sections not implemented\n");
180  return bits(data, 31, 20);
181  }
182 
184  bool
185  global(WalkerState *currState) const override
186  {
187  return !bits(data, 17);
188  }
189 
191  bool
192  xn() const override
193  {
194  return bits(data, 4);
195  }
196 
198  uint8_t
199  ap() const override
200  {
201  return (bits(data, 15) << 2) | bits(data, 11, 10);
202  }
203 
206  domain() const override
207  {
208  return static_cast<TlbEntry::DomainType>(bits(data, 8, 5));
209  }
210 
212  Addr
213  l2Addr() const
214  {
215  return mbits(data, 31, 10);
216  }
217 
223  uint8_t
224  texcb() const override
225  {
226  return bits(data, 2) | bits(data, 3) << 1 | bits(data, 14, 12) << 2;
227  }
228 
230  bool
231  shareable() const override
232  {
233  return bits(data, 16);
234  }
235 
239  void
241  {
242  data |= 1 << 10;
243  _dirty = true;
244  }
245 
247  bool
248  dirty() const
249  {
250  return _dirty;
251  }
252 
257  bool
258  secure(bool have_security, WalkerState *currState) const override
259  {
260  if (have_security && currState->secureLookup) {
261  if (type() == PageTable)
262  return !bits(data, 3);
263  else
264  return !bits(data, 19);
265  }
266  return false;
267  }
268  };
269 
272  {
273  public:
275  uint32_t data;
277 
280  bool _dirty;
281 
283  L2Descriptor() : data(0), l1Parent(nullptr), _dirty(false)
284  {
285  lookupLevel = LookupLevel::L2;
286  }
287 
288  L2Descriptor(L1Descriptor &parent) : data(0), l1Parent(&parent),
289  _dirty(false)
290  {
291  lookupLevel = LookupLevel::L2;
292  }
293 
294  uint64_t
295  getRawData() const override
296  {
297  return (data);
298  }
299 
300  std::string
301  dbgHeader() const override
302  {
303  return "Inserting L2 Descriptor into TLB\n";
304  }
305 
307  domain() const override
308  {
309  return l1Parent->domain();
310  }
311 
312  bool
313  secure(bool have_security, WalkerState *currState) const override
314  {
315  return l1Parent->secure(have_security, currState);
316  }
317 
318  uint8_t
319  offsetBits() const override
320  {
321  return large() ? 16 : 12;
322  }
323 
325  bool
326  invalid() const
327  {
328  return bits(data, 1, 0) == 0;
329  }
330 
332  bool
333  large() const
334  {
335  return bits(data, 1) == 0;
336  }
337 
339  bool
340  xn() const override
341  {
342  return large() ? bits(data, 15) : bits(data, 0);
343  }
344 
346  bool
347  global(WalkerState *currState) const override
348  {
349  return !bits(data, 11);
350  }
351 
353  uint8_t
354  ap() const override
355  {
356  return bits(data, 5, 4) | (bits(data, 9) << 2);
357  }
358 
360  uint8_t
361  texcb() const override
362  {
363  return large() ?
364  (bits(data, 2) | (bits(data, 3) << 1) | (bits(data, 14, 12) << 2)) :
365  (bits(data, 2) | (bits(data, 3) << 1) | (bits(data, 8, 6) << 2));
366  }
367 
369  Addr
370  pfn() const override
371  {
372  return large() ? bits(data, 31, 16) : bits(data, 31, 12);
373  }
374 
376  Addr
377  paddr(Addr va) const
378  {
379  if (large())
380  return mbits(data, 31, 16) | mbits(va, 15, 0);
381  else
382  return mbits(data, 31, 12) | mbits(va, 11, 0);
383  }
384 
386  bool
387  shareable() const override
388  {
389  return bits(data, 10);
390  }
391 
395  void
397  {
398  data |= 1 << 4;
399  _dirty = true;
400  }
401 
403  bool
404  dirty() const
405  {
406  return _dirty;
407  }
408 
409  };
410 
413  {
414  public:
417  {
422  };
423 
425  : data(0), _dirty(false), aarch64(false), grainSize(Grain4KB),
426  physAddrRange(0)
427  {}
428 
430  uint64_t data;
431 
434  bool _dirty;
435 
437  bool aarch64;
438 
441 
442  uint8_t physAddrRange;
443 
444  uint64_t
445  getRawData() const override
446  {
447  return (data);
448  }
449 
450  std::string
451  dbgHeader() const override
452  {
453  switch (type()) {
455  assert(lookupLevel == LookupLevel::L3);
456  return "Inserting Page descriptor into TLB\n";
458  assert(lookupLevel < LookupLevel::L3);
459  return "Inserting Block descriptor into TLB\n";
461  return "Inserting Table descriptor into TLB\n";
462  default:
463  panic("Trying to insert and invalid descriptor\n");
464  }
465  }
466 
471  bool
472  secure(bool have_security, WalkerState *currState) const override
473  {
474  if (type() == Block || type() == Page) {
475  return have_security &&
476  (currState->secureLookup && !bits(data, 5));
477  } else {
478  return have_security && currState->secureLookup;
479  }
480  }
481 
483  EntryType
484  type() const
485  {
486  switch (bits(data, 1, 0)) {
487  case 0x1:
488  // In AArch64 blocks are not allowed at L0 for the
489  // 4 KiB granule and at L1 for 16/64 KiB granules
490  switch (grainSize) {
491  case Grain4KB:
492  if (lookupLevel == LookupLevel::L0 ||
493  lookupLevel == LookupLevel::L3)
494  return Invalid;
495  else
496  return Block;
497 
498  case Grain16KB:
499  if (lookupLevel == LookupLevel::L2)
500  return Block;
501  else
502  return Invalid;
503 
504  case Grain64KB:
505  // With Armv8.2-LPA (52bit PA) L1 Block descriptors
506  // are allowed for 64KiB granule
507  if ((lookupLevel == LookupLevel::L1 && physAddrRange == 52) ||
508  lookupLevel == LookupLevel::L2)
509  return Block;
510  else
511  return Invalid;
512 
513  default:
514  return Invalid;
515  }
516  case 0x3:
517  return lookupLevel == LookupLevel::L3 ? Page : Table;
518  default:
519  return Invalid;
520  }
521  }
522 
524  uint8_t
525  offsetBits() const override
526  {
527  if (type() == Block) {
528  switch (grainSize) {
529  case Grain4KB:
530  return lookupLevel == LookupLevel::L1 ?
531  30 /* 1 GiB */ : 21 /* 2 MiB */;
532  case Grain16KB:
533  return 25 /* 32 MiB */;
534  case Grain64KB:
535  return lookupLevel == LookupLevel::L1 ?
536  42 /* 4 TiB */ : 29 /* 512 MiB */;
537  default:
538  panic("Invalid AArch64 VM granule size\n");
539  }
540  } else if (type() == Page) {
541  switch (grainSize) {
542  case Grain4KB:
543  case Grain16KB:
544  case Grain64KB:
545  return grainSize; /* enum -> uint okay */
546  default:
547  panic("Invalid AArch64 VM granule size\n");
548  }
549  } else if (type() == Table) {
550  const auto* ptops = getPageTableOps(grainSize);
551  return ptops->walkBits(lookupLevel);
552  }
553  panic("AArch64 page table entry must be block or page\n");
554  }
555 
557  Addr
558  pfn() const override
559  {
560  return paddr() >> offsetBits();
561  }
562 
564  Addr
565  paddr() const
566  {
567  Addr addr = 0;
568  if (aarch64) {
569  addr = mbits(data, 47, offsetBits());
570  if (physAddrRange == 52 && grainSize == Grain64KB) {
571  addr |= bits(data, 15, 12) << 48;
572  }
573  } else {
574  addr = mbits(data, 39, offsetBits());
575  }
576  return addr;
577  }
578 
580  Addr
582  {
583  assert(type() == Table);
584  Addr table_address = 0;
585  if (aarch64) {
586  table_address = mbits(data, 47, grainSize);
587  // Using 52bit if Armv8.2-LPA is implemented
588  if (physAddrRange == 52 && grainSize == Grain64KB)
589  table_address |= bits(data, 15, 12) << 48;
590  } else {
591  table_address = mbits(data, 39, 12);
592  }
593 
594  return table_address;
595  }
596 
598  Addr
600  {
601  assert(type() == Table);
602  Addr pa = 0;
603  if (aarch64) {
604  int stride = grainSize - 3;
605  int va_lo = stride * (3 - (lookupLevel + 1)) + grainSize;
606  int va_hi = va_lo + stride - 1;
607  pa = nextTableAddr() | (bits(va, va_hi, va_lo) << 3);
608  } else {
609  if (lookupLevel == LookupLevel::L1)
610  pa = nextTableAddr() | (bits(va, 29, 21) << 3);
611  else // lookupLevel == L2
612  pa = nextTableAddr() | (bits(va, 20, 12) << 3);
613  }
614  return pa;
615  }
616 
618  bool
619  xn() const override
620  {
621  assert(type() == Block || type() == Page);
622  return bits(data, 54);
623  }
624 
626  bool
627  pxn() const
628  {
629  assert(type() == Block || type() == Page);
630  return bits(data, 53);
631  }
632 
634  bool
636  {
637  assert(type() == Block || type() == Page);
638  return bits(data, 52);
639  }
640 
642  bool
643  global(WalkerState *currState) const override
644  {
645  assert(currState && (type() == Block || type() == Page));
646  if (!currState->aarch64 && (currState->isSecure &&
647  !currState->secureLookup)) {
648  return false; // ARM ARM issue C B3.6.3
649  } else if (currState->aarch64) {
650  if (currState->el == EL2 || currState->el == EL3) {
651  return true; // By default translations are treated as global
652  // in AArch64 EL2 and EL3
653  } else if (currState->isSecure && !currState->secureLookup) {
654  return false;
655  }
656  }
657  return !bits(data, 11);
658  }
659 
661  bool
662  af() const
663  {
664  assert(type() == Block || type() == Page);
665  return bits(data, 10);
666  }
667 
669  uint8_t
670  sh() const
671  {
672  assert(type() == Block || type() == Page);
673  return bits(data, 9, 8);
674  }
675 
677  uint8_t
678  ap() const override
679  {
680  assert(type() == Block || type() == Page);
681  // Long descriptors only support the AP[2:1] scheme
682  return bits(data, 7, 6);
683  }
684 
686  bool
687  rw() const
688  {
689  assert(type() == Block || type() == Page);
690  return !bits(data, 7);
691  }
692 
694  bool
695  user() const
696  {
697  assert(type() == Block || type() == Page);
698  return bits(data, 6);
699  }
700 
704  static uint8_t
705  ap(bool rw, bool user)
706  {
707  return ((!rw) << 2) | (user << 1);
708  }
709 
711  domain() const override
712  {
713  // Long-desc. format only supports Client domain
715  }
716 
718  uint8_t
719  attrIndx() const
720  {
721  assert(type() == Block || type() == Page);
722  return bits(data, 4, 2);
723  }
724 
726  uint8_t
727  memAttr() const
728  {
729  assert(type() == Block || type() == Page);
730  return bits(data, 5, 2);
731  }
732 
735  void
737  {
738  data |= 1 << 10;
739  _dirty = true;
740  }
741 
743  bool
744  dirty() const
745  {
746  return _dirty;
747  }
748 
750  bool
751  secureTable() const
752  {
753  assert(type() == Table);
754  return !bits(data, 63);
755  }
756 
758  uint8_t
759  apTable() const
760  {
761  assert(type() == Table);
762  return bits(data, 62, 61);
763  }
764 
766  uint8_t
767  rwTable() const
768  {
769  assert(type() == Table);
770  return !bits(data, 62);
771  }
772 
775  uint8_t
776  userTable() const
777  {
778  assert(type() == Table);
779  return !bits(data, 61);
780  }
781 
783  bool
784  xnTable() const
785  {
786  assert(type() == Table);
787  return bits(data, 60);
788  }
789 
791  bool
792  pxnTable() const
793  {
794  assert(type() == Table);
795  return bits(data, 59);
796  }
797  };
798 
800  {
801  public:
804 
806  bool aarch64;
807 
810 
813 
816 
819 
821  uint16_t asid;
823  bool isHyp;
824 
827 
830 
833 
836 
838  SCTLR sctlr;
839 
841  SCR scr;
842 
844  CPSR cpsr;
845 
847  union
848  {
849  TTBCR ttbcr; // AArch32 translations
850  TCR tcr; // AArch64 translations
851  };
852 
854  HTCR htcr;
855 
857  HCR hcr;
858 
860  VTCR_t vtcr;
861 
863  bool isWrite;
864 
866  bool isFetch;
867 
869  bool isSecure;
870 
873 
877  bool rwTable;
878  bool userTable;
879  bool xnTable;
880  bool pxnTable;
881 
883  bool hpd;
884 
886  bool stage2Req;
887 
890 
892  bool timing;
893 
896 
899 
902 
906 
909 
912  bool delayed;
913 
915 
918 
920  unsigned levels;
921 
922  void doL1Descriptor();
923  void doL2Descriptor();
924 
925  void doLongDescriptor();
926 
927  WalkerState();
928 
929  std::string name() const { return tableWalker->name(); }
930  };
931 
933  {
934  public:
935  Tick delay = 0;
936  Event *event = nullptr;
937  };
938 
939  class Port : public QueuedRequestPort
940  {
941  public:
942  Port(TableWalker* _walker, RequestorID id);
943 
944  void sendFunctionalReq(Addr desc_addr, int size,
945  uint8_t *data, Request::Flags flag);
946  void sendAtomicReq(Addr desc_addr, int size,
947  uint8_t *data, Request::Flags flag, Tick delay);
948  void sendTimingReq(Addr desc_addr, int size,
949  uint8_t *data, Request::Flags flag, Tick delay,
950  Event *event);
951 
952  bool recvTimingResp(PacketPtr pkt) override;
953 
954  private:
955  void handleRespPacket(PacketPtr pkt, Tick delay=0);
956  void handleResp(TableWalkerState *state, Addr addr,
957  Addr size, Tick delay=0);
958 
959  PacketPtr createPacket(Addr desc_addr, int size,
960  uint8_t *data, Request::Flags flag,
961  Tick delay, Event *event);
962 
963  private:
966 
969 
972  };
973 
977  {
978  private:
979  uint8_t *data;
980  int numBytes;
987 
988  public:
990 
991  Stage2Walk(TableWalker &_parent, uint8_t *_data, Event *_event,
993  MMU::ArmTranslationType tran_type);
994 
995  void markDelayed() {}
996 
997  void finish(const Fault &fault, const RequestPtr &req,
999 
1000  void
1001  setVirt(Addr vaddr, int size, Request::Flags flags,
1002  int requestorId)
1003  {
1004  numBytes = size;
1005  req->setVirt(vaddr, size, flags, requestorId, 0);
1006  }
1007 
1008  void translateTiming(ThreadContext *tc);
1009  };
1010 
1012  uint8_t *data, int num_bytes, Request::Flags flags,
1014  bool functional);
1015  void readDataTimed(ThreadContext *tc, Addr desc_addr,
1016  Stage2Walk *translation, int num_bytes,
1017  Request::Flags flags);
1018 
1019  protected:
1020 
1022  std::list<WalkerState *> stateQueues[LookupLevel::Num_ArmLookupLevel];
1023 
1027 
1030 
1033 
1036 
1038  const bool isStage2;
1039 
1042 
1044  SCTLR sctlr;
1045 
1047 
1049  bool pending;
1050 
1053  unsigned numSquashable;
1054 
1059 
1062  {
1073  // Essentially "L" of queueing theory
1077  } stats;
1078 
1079  mutable unsigned pendingReqs;
1081 
1082  static const unsigned REQUESTED = 0;
1083  static const unsigned COMPLETED = 1;
1084 
1085  public:
1086  PARAMS(ArmTableWalker);
1087  TableWalker(const Params &p);
1088  virtual ~TableWalker();
1089 
1090  bool haveLargeAsid64() const { return _haveLargeAsid64; }
1091  uint8_t physAddrRange() const { return _physAddrRange; }
1093  void completeDrain();
1094  DrainState drain() override;
1095  void drainResume() override;
1096 
1097  gem5::Port &getPort(const std::string &if_name,
1098  PortID idx=InvalidPortID) override;
1099 
1101 
1102  Fault walk(const RequestPtr &req, ThreadContext *tc,
1103  uint16_t asid, vmid_t _vmid,
1104  bool hyp, BaseMMU::Mode mode, BaseMMU::Translation *_trans,
1105  bool timing, bool functional, bool secure,
1106  MMU::ArmTranslationType tran_type, bool stage2,
1107  const TlbEntry *walk_entry);
1108 
1109  void setMmu(MMU *_mmu);
1110  void setTlb(TLB *_tlb) { tlb = _tlb; }
1111  TLB* getTlb() { return tlb; }
1112  void memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr,
1113  uint8_t texcb, bool s);
1115  LongDescriptor &lDescriptor);
1117  LongDescriptor &lDescriptor);
1118 
1119  static LookupLevel toLookupLevel(uint8_t lookup_level_as_int);
1120 
1121  private:
1122 
1123  void doL1Descriptor();
1124  void doL1DescriptorWrapper();
1126 
1127  void doL2Descriptor();
1128  void doL2DescriptorWrapper();
1130 
1131  void doLongDescriptor();
1132 
1141 
1142  void doLongDescriptorWrapper(LookupLevel curr_lookup_level);
1144 
1145  bool fetchDescriptor(Addr descAddr, uint8_t *data, int numBytes,
1146  Request::Flags flags, int queueIndex, Event *event,
1147  void (TableWalker::*doDescriptor)());
1148 
1150 
1151  void insertTableEntry(DescriptorBase &descriptor, bool longDescriptor);
1152  void insertPartialTableEntry(LongDescriptor &descriptor);
1153 
1159  std::tuple<Addr, Addr, LookupLevel> walkAddresses(
1160  Addr ttbr, GrainSize tg, int tsz, int pa_range);
1161 
1162  Fault processWalk();
1164 
1165  bool checkVAddrSizeFaultAArch64(Addr addr, int top_bit,
1166  GrainSize granule, int tsz, bool low_range);
1167 
1170  bool checkAddrSizeFaultAArch64(Addr addr, int pa_range);
1171 
1173  void processWalkWrapper();
1175 
1176  void nextWalk(ThreadContext *tc);
1177 
1178  void pendingChange();
1179 
1180  static uint8_t pageSizeNtoStatBin(uint8_t N);
1181 
1183  LookupLevel lookup_level, bool stage2);
1184 };
1185 
1186 } // namespace ArmISA
1187 } // namespace gem5
1188 
1189 #endif //__ARCH_ARM_TABLE_WALKER_HH__
gem5::statistics::Scalar
This is a simple scalar statistic, like a counter.
Definition: statistics.hh:1930
gem5::ArmISA::TableWalker::doL1DescEvent
EventFunctionWrapper doL1DescEvent
Definition: table_walker.hh:1125
gem5::ArmISA::TableWalker::testWalk
Fault testWalk(Addr pa, Addr size, TlbEntry::DomainType domain, LookupLevel lookup_level, bool stage2)
Definition: table_walker.cc:2450
gem5::ArmISA::TableWalker::DescriptorBase::dbgHeader
virtual std::string dbgHeader() const =0
gem5::PortID
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:252
gem5::ArmISA::TableWalker::doLongDescriptorWrapper
void doLongDescriptorWrapper(LookupLevel curr_lookup_level)
Definition: table_walker.cc:2150
gem5::ArmISA::TableWalker::LookupLevel
enums::ArmLookupLevel LookupLevel
Definition: table_walker.hh:68
gem5::ArmISA::TableWalker::L1Descriptor::L1Descriptor
L1Descriptor()
Default ctor.
Definition: table_walker.hh:120
gem5::ArmISA::TableWalker::L1Descriptor::secure
bool secure(bool have_security, WalkerState *currState) const override
Returns true if this entry targets the secure physical address map.
Definition: table_walker.hh:258
gem5::ArmISA::TableWalker::LongDescriptor::pfn
Addr pfn() const override
Return the physical frame, bits shifted right.
Definition: table_walker.hh:558
gem5::ArmISA::TableWalker::WalkerState::isSecure
bool isSecure
If the access comes from the secure state.
Definition: table_walker.hh:869
gem5::ArmISA::TableWalker::LongDescEventByLevel
Event * LongDescEventByLevel[4]
Definition: table_walker.hh:1143
gem5::ArmISA::TableWalker::TableWalkerStats::walksLongDescriptor
statistics::Scalar walksLongDescriptor
Definition: table_walker.hh:1066
gem5::ArmISA::TableWalker::WalkerState::pxnTable
bool pxnTable
Definition: table_walker.hh:880
gem5::ArmISA::TableWalker::Port
Definition: table_walker.hh:939
gem5::ArmISA::TableWalker::WalkerState::walkEntry
TlbEntry walkEntry
Initial walk entry allowing to skip lookup levels.
Definition: table_walker.hh:818
gem5::ArmISA::TableWalker::LongDescriptor::pxnTable
bool pxnTable() const
Is privileged execution allowed on subsequent lookup levels?
Definition: table_walker.hh:792
gem5::ArmISA::TableWalker::WalkerState::sctlr
SCTLR sctlr
Cached copy of the sctlr as it existed when translation began.
Definition: table_walker.hh:838
gem5::ArmISA::TableWalker::WalkerState::el
ExceptionLevel el
Current exception level.
Definition: table_walker.hh:809
gem5::ArmISA::TableWalker::Port::sendAtomicReq
void sendAtomicReq(Addr desc_addr, int size, uint8_t *data, Request::Flags flag, Tick delay)
Definition: table_walker.cc:183
gem5::ArmISA::TableWalker::pendingChangeTick
Tick pendingChangeTick
Definition: table_walker.hh:1080
gem5::ArmISA::TableWalker::TableWalkerStats::walks
statistics::Scalar walks
Definition: table_walker.hh:1064
gem5::ArmISA::TableWalker::L2Descriptor::ap
uint8_t ap() const override
Three bit access protection flags.
Definition: table_walker.hh:354
gem5::ArmISA::TableWalker::WalkerState::longDesc
LongDescriptor longDesc
Long-format descriptor (LPAE and AArch64)
Definition: table_walker.hh:908
gem5::ArmISA::TableWalker::doProcessEvent
EventFunctionWrapper doProcessEvent
Definition: table_walker.hh:1174
gem5::ArmISA::TableWalker::readDataTimed
void readDataTimed(ThreadContext *tc, Addr desc_addr, Stage2Walk *translation, int num_bytes, Request::Flags flags)
Definition: table_walker.cc:2522
gem5::ArmISA::TableWalker::completeDrain
void completeDrain()
Checks if all state is cleared and if so, completes drain.
Definition: table_walker.cc:243
gem5::ArmISA::TableWalker::memAttrsAArch64
void memAttrsAArch64(ThreadContext *tc, TlbEntry &te, LongDescriptor &lDescriptor)
Definition: table_walker.cc:1573
gem5::ArmISA::TableWalker::TableWalkerStats::walksLongTerminatedAtLevel
statistics::Vector walksLongTerminatedAtLevel
Definition: table_walker.hh:1068
data
const char data[]
Definition: circlebuf.test.cc:48
gem5::ArmISA::TableWalker::doL1LongDescriptorWrapper
void doL1LongDescriptorWrapper()
Definition: table_walker.cc:2132
gem5::ArmISA::TableWalker::pendingQueue
std::list< WalkerState * > pendingQueue
Queue of requests that have passed are waiting because the walker is currently busy.
Definition: table_walker.hh:1026
gem5::ArmISA::TableWalker::release
const ArmRelease * release
Cached copies of system-level properties.
Definition: table_walker.hh:1056
gem5::ArmISA::Grain64KB
@ Grain64KB
Definition: pagetable.hh:65
gem5::ArmISA::TableWalker::LongDescriptor::Block
@ Block
Definition: table_walker.hh:420
gem5::ArmISA::TableWalker::WalkerState::vaddr
Addr vaddr
The virtual address that is being translated with tagging removed.
Definition: table_walker.hh:832
gem5::ArmISA::TableWalker::L2Descriptor
Level 2 page table descriptor.
Definition: table_walker.hh:271
gem5::ArmISA::TableWalker::requestorId
RequestorID requestorId
Requestor id assigned by the MMU.
Definition: table_walker.hh:1032
gem5::ArmISA::TableWalker::WalkerState::tcr
TCR tcr
Definition: table_walker.hh:850
gem5::ArmISA::TableWalker::L1Descriptor::Section
@ Section
Definition: table_walker.hh:108
gem5::ArmISA::TableWalker::Stage2Walk::req
RequestPtr req
Definition: table_walker.hh:981
gem5::ArmISA::TableWalker::LongDescriptor::rw
bool rw() const
Read/write access protection flag.
Definition: table_walker.hh:687
gem5::ArmISA::TableWalker::LongDescriptor::apTable
uint8_t apTable() const
Two bit access protection flags for subsequent levels of lookup.
Definition: table_walker.hh:759
gem5::ArmISA::TableWalker::getTableWalkerPort
Port & getTableWalkerPort()
Definition: table_walker.cc:104
gem5::ArmISA::TableWalker::nextWalk
void nextWalk(ThreadContext *tc)
Definition: table_walker.cc:2209
gem5::QueuedRequestPort
The QueuedRequestPort combines two queues, a request queue and a snoop response queue,...
Definition: qport.hh:109
gem5::ArmISA::getPageTableOps
const PageTableOps * getPageTableOps(GrainSize trans_granule)
Definition: pagetable.cc:476
gem5::ArmISA::TableWalker::LongDescriptor::paddr
Addr paddr() const
Return the physical address of the entry.
Definition: table_walker.hh:565
gem5::BaseMMU::Mode
Mode
Definition: mmu.hh:56
gem5::ArmISA::TableWalker::WalkerState::cpsr
CPSR cpsr
Cached copy of the cpsr as it existed when translation began.
Definition: table_walker.hh:844
gem5::ArmISA::asid
asid
Definition: misc_types.hh:618
gem5::ArmISA::TableWalker::WalkerState::userTable
bool userTable
Definition: table_walker.hh:878
gem5::ArmISA::domain
Bitfield< 7, 4 > domain
Definition: misc_types.hh:424
gem5::ArmISA::TableWalker::Stage2Walk
This translation class is used to trigger the data fetch once a timing translation returns the transl...
Definition: table_walker.hh:976
gem5::ArmISA::TableWalker::TableWalkerStats::requestOrigin
statistics::Vector2d requestOrigin
Definition: table_walker.hh:1076
gem5::ArmISA::TableWalker::DescriptorBase::xn
virtual bool xn() const =0
gem5::ArmISA::TableWalker::LongDescriptor::secure
bool secure(bool have_security, WalkerState *currState) const override
Returns true if this entry targets the secure physical address map.
Definition: table_walker.hh:472
gem5::ArmISA::TableWalker::LongDescriptor::nextDescAddr
Addr nextDescAddr(Addr va) const
Return the address of the next descriptor.
Definition: table_walker.hh:599
gem5::MipsISA::event
Bitfield< 10, 5 > event
Definition: pra_constants.hh:300
gem5::ArmISA::TableWalker::LongDescriptor::EntryType
EntryType
Descriptor type.
Definition: table_walker.hh:416
gem5::ArmISA::vmid_t
uint16_t vmid_t
Definition: types.hh:57
gem5::ArmISA::TableWalker::DescriptorBase::texcb
virtual uint8_t texcb() const
Definition: table_walker.hh:90
gem5::ArmISA::TableWalker::WalkerState::secureLookup
bool secureLookup
Helper variables used to implement hierarchical access permissions when the long-desc.
Definition: table_walker.hh:876
gem5::ArmISA::TableWalker::L1Descriptor::offsetBits
uint8_t offsetBits() const override
Definition: table_walker.hh:138
gem5::ArmISA::TableWalker::LongDescriptor::Table
@ Table
Definition: table_walker.hh:419
gem5::ArmISA::TableWalker::TableWalkerState::delay
Tick delay
Definition: table_walker.hh:935
gem5::ArmISA::TableWalker::TableWalkerStats::squashedAfter
statistics::Scalar squashedAfter
Definition: table_walker.hh:1070
gem5::ArmISA::TableWalker::L2Descriptor::offsetBits
uint8_t offsetBits() const override
Definition: table_walker.hh:319
gem5::ArmISA::TableWalker::LongDescriptor::LongDescriptor
LongDescriptor()
Definition: table_walker.hh:424
gem5::ArmISA::TableWalker::LongDescriptor::_dirty
bool _dirty
This entry has been modified (access flag set) and needs to be written back to memory.
Definition: table_walker.hh:434
gem5::ArmISA::TLB
Definition: tlb.hh:115
gem5::statistics::Vector2d
A 2-Dimensional vecto of scalar stats.
Definition: statistics.hh:2058
gem5::ArmISA::TableWalker::L1Descriptor::data
uint32_t data
The raw bits of the entry.
Definition: table_walker.hh:113
gem5::ArmISA::Grain16KB
@ Grain16KB
Definition: pagetable.hh:64
gem5::statistics::Vector
A vector of scalar stats.
Definition: statistics.hh:2006
gem5::ArmISA::TableWalker::L1Descriptor::Ignore
@ Ignore
Definition: table_walker.hh:106
tlb.hh
gem5::ArmISA::TableWalker::L2Descriptor::data
uint32_t data
The raw bits of the entry.
Definition: table_walker.hh:275
gem5::ArmISA::TlbEntry::DomainType::Client
@ Client
gem5::ArmISA::TableWalker::L2Descriptor::pfn
Addr pfn() const override
Return the physical frame, bits shifted right.
Definition: table_walker.hh:370
gem5::ArmISA::TableWalker::WalkerState::name
std::string name() const
Definition: table_walker.hh:929
gem5::ArmISA::TableWalker::fetchDescriptor
bool fetchDescriptor(Addr descAddr, uint8_t *data, int numBytes, Request::Flags flags, int queueIndex, Event *event, void(TableWalker::*doDescriptor)())
Definition: table_walker.cc:2218
gem5::ArmISA::TableWalker::LongDescriptor::ap
uint8_t ap() const override
2-bit access protection flags
Definition: table_walker.hh:678
gem5::ArmISA::TableWalker::TableWalkerStats::walkServiceTime
statistics::Histogram walkServiceTime
Definition: table_walker.hh:1072
gem5::ArmISA::TableWalker::Port::handleResp
void handleResp(TableWalkerState *state, Addr addr, Addr size, Tick delay=0)
Definition: table_walker.cc:233
gem5::mbits
constexpr T mbits(T val, unsigned first, unsigned last)
Mask off the given bits in place like bits() but without shifting.
Definition: bitfield.hh:103
gem5::ArmISA::TableWalker::Stage2Walk::setVirt
void setVirt(Addr vaddr, int size, Request::Flags flags, int requestorId)
Definition: table_walker.hh:1001
system.hh
gem5::ArmISA::TableWalker::WalkerState::stage2Tran
BaseMMU::Translation * stage2Tran
A pointer to the stage 2 translation that's in progress.
Definition: table_walker.hh:889
gem5::ArmISA::TableWalker::walk
Fault walk(const RequestPtr &req, ThreadContext *tc, uint16_t asid, vmid_t _vmid, bool hyp, BaseMMU::Mode mode, BaseMMU::Translation *_trans, bool timing, bool functional, bool secure, MMU::ArmTranslationType tran_type, bool stage2, const TlbEntry *walk_entry)
Definition: table_walker.cc:289
gem5::ArmISA::TableWalker::L2Descriptor::shareable
bool shareable() const override
If the section is shareable.
Definition: table_walker.hh:387
gem5::InvalidPortID
const PortID InvalidPortID
Definition: types.hh:253
gem5::ArmISA::TableWalker::WalkerState::vmid
vmid_t vmid
Definition: table_walker.hh:822
gem5::ArmISA::TableWalker::WalkerState::vaddr_tainted
Addr vaddr_tainted
The virtual address that is being translated.
Definition: table_walker.hh:835
gem5::ArmISA::Grain4KB
@ Grain4KB
Definition: pagetable.hh:63
types.hh
gem5::ArmISA::TableWalker::WalkerState::doLongDescriptor
void doLongDescriptor()
gem5::ArmISA::TableWalker::L2Descriptor::large
bool large() const
What is the size of the mapping?
Definition: table_walker.hh:333
gem5::ArmISA::TableWalker::Port::requestorId
RequestorID requestorId
Cached requestorId of the table walker.
Definition: table_walker.hh:971
gem5::ArmISA::TableWalker::WalkerState::tranType
MMU::ArmTranslationType tranType
The translation type that has been requested.
Definition: table_walker.hh:901
request.hh
gem5::ArmISA::TlbEntry
Definition: pagetable.hh:165
gem5::ArmISA::TableWalker::LongDescriptor::ap
static uint8_t ap(bool rw, bool user)
Return the AP bits as compatible with the AP[2:0] format.
Definition: table_walker.hh:705
gem5::ArmISA::TableWalker::physAddrRange
uint8_t physAddrRange() const
Definition: table_walker.hh:1091
gem5::ArmISA::TableWalker::L1Descriptor::global
bool global(WalkerState *currState) const override
Is the translation global (no asid used)?
Definition: table_walker.hh:185
gem5::ArmISA::TableWalker::Port::Port
Port(TableWalker *_walker, RequestorID id)
Definition: table_walker.cc:141
gem5::ArmISA::TlbEntry::DomainType
DomainType
Definition: pagetable.hh:177
gem5::ArmISA::TableWalker::getPort
gem5::Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
Definition: table_walker.cc:110
gem5::ArmISA::TableWalker::L1Descriptor::ap
uint8_t ap() const override
Three bit access protection flags.
Definition: table_walker.hh:199
gem5::ArmISA::TableWalker::Stage2Walk::event
Event * event
Definition: table_walker.hh:982
gem5::ArmISA::TableWalker::Stage2Walk::data
uint8_t * data
Definition: table_walker.hh:979
gem5::ArmISA::TableWalker::COMPLETED
static const unsigned COMPLETED
Definition: table_walker.hh:1083
gem5::ArmISA::TableWalker::WalkerState::functional
bool functional
If the atomic mode should be functional.
Definition: table_walker.hh:895
gem5::ArmISA::TableWalker::TableWalkerStats::walksShortDescriptor
statistics::Scalar walksShortDescriptor
Definition: table_walker.hh:1065
gem5::ArmISA::TableWalker::LongDescriptor::nextTableAddr
Addr nextTableAddr() const
Return the address of the next page table.
Definition: table_walker.hh:581
gem5::ArmISA::TableWalker::REQUESTED
static const unsigned REQUESTED
Definition: table_walker.hh:1082
gem5::ArmISA::TableWalker::L1Descriptor::setAp0
void setAp0()
Set access flag that this entry has been touched.
Definition: table_walker.hh:240
gem5::ArmISA::TableWalker::doL1Descriptor
void doL1Descriptor()
Definition: table_walker.cc:1673
gem5::ArmISA::TableWalker::TableWalkerStats::TableWalkerStats
TableWalkerStats(statistics::Group *parent)
Definition: table_walker.cc:2573
gem5::ArmISA::TableWalker::Port::handleRespPacket
void handleRespPacket(PacketPtr pkt, Tick delay=0)
Definition: table_walker.cc:218
gem5::ArmISA::TableWalker::WalkerState::asid
uint16_t asid
ASID that we're servicing the request under.
Definition: table_walker.hh:821
mmu.hh
gem5::ArmISA::TableWalker::LongDescriptor::xnTable
bool xnTable() const
Is execution allowed on subsequent lookup levels?
Definition: table_walker.hh:784
gem5::statistics::Histogram
A simple histogram stat.
Definition: statistics.hh:2126
gem5::ArmISA::TableWalker::L1Descriptor::PageTable
@ PageTable
Definition: table_walker.hh:107
gem5::ArmISA::pa
Bitfield< 39, 12 > pa
Definition: misc_types.hh:657
gem5::ArmISA::TableWalker::LongDescriptor::secureTable
bool secureTable() const
Whether the subsequent levels of lookup are secure.
Definition: table_walker.hh:751
gem5::ArmISA::TableWalker::Stage2Walk::parent
TableWalker & parent
Definition: table_walker.hh:983
gem5::Flags< FlagsType >
gem5::DrainState
DrainState
Object drain/handover states.
Definition: drain.hh:74
gem5::ArmISA::TableWalker::haveLargeAsid64
bool haveLargeAsid64() const
Definition: table_walker.hh:1090
gem5::ArmISA::TableWalker::sctlr
SCTLR sctlr
Cached copy of the sctlr as it existed when translation began.
Definition: table_walker.hh:1044
gem5::ArmISA::TableWalker::WalkerState::isHyp
bool isHyp
Definition: table_walker.hh:823
gem5::ArmISA::TableWalker::LongDescriptor::data
uint64_t data
The raw bits of the entry.
Definition: table_walker.hh:430
gem5::ArmISA::TableWalker::walkAddresses
std::tuple< Addr, Addr, LookupLevel > walkAddresses(Addr ttbr, GrainSize tg, int tsz, int pa_range)
Returns a tuple made of: 1) The address of the first page table 2) The address of the first descripto...
Definition: table_walker.cc:1192
gem5::ArmISA::TableWalker::LongDescriptor::sh
uint8_t sh() const
2-bit shareability field
Definition: table_walker.hh:670
gem5::ArmISA::TableWalker::LongDescriptor::getRawData
uint64_t getRawData() const override
Definition: table_walker.hh:445
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::ArmISA::TableWalker::L1Descriptor::texcb
uint8_t texcb() const override
Memory region attributes: ARM DDI 0406B: B3-32.
Definition: table_walker.hh:224
gem5::Named::name
virtual std::string name() const
Definition: named.hh:47
gem5::ArmISA::TableWalker::L1Descriptor::pfn
Addr pfn() const override
Return the physical frame, bits shifted right.
Definition: table_walker.hh:176
gem5::ArmISA::TableWalker::Stage2Walk::finish
void finish(const Fault &fault, const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode)
Definition: table_walker.cc:2542
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::ArmISA::TableWalker::Port::sendFunctionalReq
void sendFunctionalReq(Addr desc_addr, int size, uint8_t *data, Request::Flags flag)
Definition: table_walker.cc:171
gem5::ArmISA::ArmFault::FaultSource
FaultSource
Generic fault source enums used to index into {short/long/aarch64}DescFaultSources[] to get the actua...
Definition: faults.hh:95
gem5::ArmISA::TableWalker::L1Descriptor::shareable
bool shareable() const override
If the section is shareable.
Definition: table_walker.hh:231
gem5::ArmISA::TableWalker::L2Descriptor::dirty
bool dirty() const
This entry needs to be written back to memory.
Definition: table_walker.hh:404
gem5::ArmISA::TableWalker::L1Descriptor::domain
TlbEntry::DomainType domain() const override
Domain Client/Manager: ARM DDI 0406B: B3-31.
Definition: table_walker.hh:206
gem5::Event
Definition: eventq.hh:251
gem5::ArmISA::TableWalker::processWalkAArch64
Fault processWalkAArch64()
Definition: table_walker.cc:889
gem5::ArmISA::TableWalker::pageSizeNtoStatBin
static uint8_t pageSizeNtoStatBin(uint8_t N)
Definition: table_walker.cc:2459
gem5::ArmISA::TableWalker::WalkerState::delayed
bool delayed
Whether the response is delayed in timing mode due to additional lookups.
Definition: table_walker.hh:912
gem5::ArmISA::TableWalker::stateQueues
std::list< WalkerState * > stateQueues[LookupLevel::Num_ArmLookupLevel]
Queues of requests for all the different lookup levels.
Definition: table_walker.hh:1022
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::ArmISA::TableWalker::L2Descriptor::l1Parent
L1Descriptor * l1Parent
Definition: table_walker.hh:276
gem5::ArmISA::TableWalker::L1Descriptor::EntryType
EntryType
Type of page table entry ARM DDI 0406B: B3-8.
Definition: table_walker.hh:104
gem5::ArmISA::TableWalker::doL0LongDescriptorWrapper
void doL0LongDescriptorWrapper()
Definition: table_walker.cc:2126
gem5::ArmISA::TableWalker::WalkerState::tc
ThreadContext * tc
Thread context that we're doing the walk for.
Definition: table_walker.hh:803
gem5::ArmISA::EL2
@ EL2
Definition: types.hh:268
gem5::ArmISA::TableWalker::L2Descriptor::getRawData
uint64_t getRawData() const override
Definition: table_walker.hh:295
gem5::ArmISA::TableWalker::processWalkLPAE
Fault processWalkLPAE()
Definition: table_walker.cc:691
gem5::ArmISA::TableWalker::WalkerState::physAddrRange
int physAddrRange
Current physical address range in bits.
Definition: table_walker.hh:812
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::ArmISA::TableWalker::PARAMS
PARAMS(ArmTableWalker)
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::ArmISA::TableWalker::setTlb
void setTlb(TLB *_tlb)
Definition: table_walker.hh:1110
gem5::ArmISA::TableWalker::WalkerState::startTime
Tick startTime
Timestamp for calculating elapsed time in service (for stats)
Definition: table_walker.hh:917
gem5::ArmISA::TableWalker::L1Descriptor::l2Addr
Addr l2Addr() const
Address of L2 descriptor if it exists.
Definition: table_walker.hh:213
gem5::ArmISA::TableWalker::LongDescriptor::type
EntryType type() const
Return the descriptor type.
Definition: table_walker.hh:484
gem5::ArmISA::TableWalker::L1Descriptor::dirty
bool dirty() const
This entry needs to be written back to memory.
Definition: table_walker.hh:248
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::ArmISA::s
Bitfield< 4 > s
Definition: misc_types.hh:562
gem5::ArmISA::TableWalker::DescriptorBase::pfn
virtual Addr pfn() const =0
gem5::ArmISA::TableWalker::L2Descriptor::secure
bool secure(bool have_security, WalkerState *currState) const override
Definition: table_walker.hh:313
gem5::ArmISA::TableWalker::insertPartialTableEntry
void insertPartialTableEntry(LongDescriptor &descriptor)
Definition: table_walker.cc:2289
gem5::ArmISA::TableWalker::doL2DescEvent
EventFunctionWrapper doL2DescEvent
Definition: table_walker.hh:1129
gem5::ArmISA::TableWalker::DescriptorBase::offsetBits
virtual uint8_t offsetBits() const =0
gem5::ArmISA::TableWalker::WalkerState::ttbcr
TTBCR ttbcr
Definition: table_walker.hh:849
mmu.hh
gem5::ArmISA::TableWalker::TableWalkerStats::pageSizes
statistics::Vector pageSizes
Definition: table_walker.hh:1075
packet_queue.hh
gem5::ArmISA::TableWalker::WalkerState::isFetch
bool isFetch
If the access is a fetch (for execution, and no-exec) must be checked?
Definition: table_walker.hh:866
gem5::ArmISA::TableWalker::port
Port * port
Port shared by the two table walkers.
Definition: table_walker.hh:1035
gem5::ArmISA::TableWalker::DescriptorBase::getRawData
virtual uint64_t getRawData() const =0
gem5::ArmISA::TableWalker::Stage2Walk::translateTiming
void translateTiming(ThreadContext *tc)
Definition: table_walker.cc:2568
gem5::ArmISA::TableWalker::L2Descriptor::global
bool global(WalkerState *currState) const override
Is the translation global (no asid used)?
Definition: table_walker.hh:347
gem5::ArmISA::TableWalker::doL2LongDescriptorWrapper
void doL2LongDescriptorWrapper()
Definition: table_walker.cc:2138
gem5::ArmISA::TableWalker::doL1DescriptorWrapper
void doL1DescriptorWrapper()
Definition: table_walker.cc:2020
gem5::ArmISA::TableWalker::WalkerState::req
RequestPtr req
Request that is currently being serviced.
Definition: table_walker.hh:815
gem5::ArmISA::TableWalker::L2Descriptor::L2Descriptor
L2Descriptor()
Default ctor.
Definition: table_walker.hh:283
gem5::ArmISA::TableWalker::processWalkWrapper
void processWalkWrapper()
Definition: table_walker.cc:484
gem5::ArmISA::TableWalker::LongDescriptor::physAddrRange
uint8_t physAddrRange
Definition: table_walker.hh:442
gem5::ArmISA::TableWalker::LongDescriptor::Invalid
@ Invalid
Definition: table_walker.hh:418
gem5::ArmISA::TableWalker::_physAddrRange
uint8_t _physAddrRange
Definition: table_walker.hh:1057
Block
Definition: global.h:77
gem5::ArmISA::TableWalker::numSquashable
unsigned numSquashable
The number of walks belonging to squashed instructions that can be removed from the pendingQueue per ...
Definition: table_walker.hh:1053
gem5::ArmISA::te
Bitfield< 30 > te
Definition: misc_types.hh:338
gem5::ArmISA::TableWalker::LongDescriptor::user
bool user() const
User/privileged level access protection flag.
Definition: table_walker.hh:695
gem5::ArmISA::TableWalker::WalkerState::transState
BaseMMU::Translation * transState
Translation state for delayed requests.
Definition: table_walker.hh:826
gem5::ArmISA::TableWalker::DescriptorBase::secure
virtual bool secure(bool have_security, WalkerState *currState) const =0
gem5::ArmISA::TableWalker::_haveLargeAsid64
bool _haveLargeAsid64
Definition: table_walker.hh:1058
gem5::ArmISA::TableWalker::Stage2Walk::tranType
MMU::ArmTranslationType tranType
Definition: table_walker.hh:986
gem5::ArmISA::TableWalker::LongDescriptor::grainSize
GrainSize grainSize
Width of the granule size in bits.
Definition: table_walker.hh:440
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
gem5::ArmISA::TableWalker::DescriptorBase
Definition: table_walker.hh:73
gem5::ArmISA::TableWalker::WalkerState::tableWalker
TableWalker * tableWalker
Definition: table_walker.hh:914
gem5::ArmISA::EL3
@ EL3
Definition: types.hh:269
gem5::ArmISA::TableWalker::Port::reqQueue
ReqPacketQueue reqQueue
Packet queue used to store outgoing requests.
Definition: table_walker.hh:965
gem5::ArmISA::TableWalker::WalkerState::htcr
HTCR htcr
Cached copy of the htcr as it existed when translation began.
Definition: table_walker.hh:854
gem5::ArmISA::TableWalker::TableWalkerState
Definition: table_walker.hh:932
gem5::ArmISA::TableWalker::L1Descriptor::getRawData
uint64_t getRawData() const override
Definition: table_walker.hh:126
gem5::ArmISA::TableWalker::WalkerState::isWrite
bool isWrite
If the access is a write.
Definition: table_walker.hh:863
gem5::Packet::SenderState
A virtual base opaque structure used to hold state associated with the packet (e.g....
Definition: packet.hh:457
gem5::ArmISA::TableWalker::checkVAddrSizeFaultAArch64
bool checkVAddrSizeFaultAArch64(Addr addr, int top_bit, GrainSize granule, int tsz, bool low_range)
Definition: table_walker.cc:865
gem5::ArmISA::TableWalker::L1Descriptor::Reserved
@ Reserved
Definition: table_walker.hh:109
gem5::ArmISA::TableWalker::WalkerState::vtcr
VTCR_t vtcr
Cached copy of the vtcr as it existed when translation began.
Definition: table_walker.hh:860
faults.hh
gem5::ArmISA::TableWalker::L1Descriptor::type
EntryType type() const
Definition: table_walker.hh:144
gem5::ArmISA::TableWalker::generateLongDescFault
Fault generateLongDescFault(ArmFault::FaultSource src)
Definition: table_walker.cc:1779
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ArmISA::TableWalker::Stage2Walk::mode
BaseMMU::Mode mode
Definition: table_walker.hh:985
gem5::ArmISA::TableWalker::LongDescriptor
Long-descriptor format (LPAE)
Definition: table_walker.hh:412
gem5::ArmISA::TableWalker::TableWalkerStats
Statistics.
Definition: table_walker.hh:1061
gem5::ArmISA::TableWalker::LongDescriptor::contiguousHint
bool contiguousHint() const
Contiguous hint bit.
Definition: table_walker.hh:635
gem5::ArmISA::TableWalker::LongDescriptor::Page
@ Page
Definition: table_walker.hh:421
gem5::ArmISA::TableWalker::TableWalkerStats::pendingWalks
statistics::Histogram pendingWalks
Definition: table_walker.hh:1074
gem5::ArmISA::TableWalker::doL2Descriptor
void doL2Descriptor()
Definition: table_walker.cc:1964
gem5::ArmISA::TableWalker::pendingReqs
unsigned pendingReqs
Definition: table_walker.hh:1079
gem5::ArmISA::va
Bitfield< 8 > va
Definition: misc_types.hh:276
gem5::ArmISA::TableWalker::TableWalkerStats::walkWaitTime
statistics::Histogram walkWaitTime
Definition: table_walker.hh:1071
gem5::ClockedObject
The ClockedObject class extends the SimObject with a clock and accessor functions to relate ticks to ...
Definition: clocked_object.hh:234
gem5::ArmISA::TableWalker::Stage2Walk::markDelayed
void markDelayed()
Signal that the translation has been delayed due to a hw page table walk.
Definition: table_walker.hh:995
gem5::ArmISA::TableWalker::DescriptorBase::lookupLevel
LookupLevel lookupLevel
Current lookup level for this descriptor.
Definition: table_walker.hh:79
gem5::ArmISA::TableWalker::DescriptorBase::global
virtual bool global(WalkerState *currState) const =0
gem5::ArmRelease
Definition: system.hh:68
gem5::ArmISA::TableWalker::Port::snoopRespQueue
SnoopRespPacketQueue snoopRespQueue
Packet queue used to store outgoing snoop responses.
Definition: table_walker.hh:968
gem5::ArmISA::TableWalker::WalkerState::doL2Descriptor
void doL2Descriptor()
gem5::ArmISA::TableWalker::L1Descriptor::supersection
bool supersection() const
Is the page a Supersection (16 MiB)?
Definition: table_walker.hh:151
gem5::ArmISA::TableWalker::LongDescriptor::aarch64
bool aarch64
True if the current lookup is performed in AArch64 state.
Definition: table_walker.hh:437
gem5::ArmISA::TableWalker::WalkerState::xnTable
bool xnTable
Definition: table_walker.hh:879
gem5::ArmISA::TableWalker::LongDescriptor::af
bool af() const
Returns true if the access flag (AF) is set.
Definition: table_walker.hh:662
gem5::ArmISA::TableWalker::L1Descriptor::xn
bool xn() const override
Is the translation not allow execution?
Definition: table_walker.hh:192
gem5::EventFunctionWrapper
Definition: eventq.hh:1115
gem5::ArmISA::TableWalker::WalkerState::stage2Req
bool stage2Req
Flag indicating if a second stage of lookup is required.
Definition: table_walker.hh:886
gem5::BaseMMU::Translation
Definition: mmu.hh:58
gem5::ArmISA::TableWalker::L1Descriptor
Definition: table_walker.hh:100
gem5::ArmISA::TableWalker::Port::sendTimingReq
void sendTimingReq(Addr desc_addr, int size, uint8_t *data, Request::Flags flag, Tick delay, Event *event)
Definition: table_walker.cc:195
gem5::ArmISA::TableWalker::readDataUntimed
Fault readDataUntimed(ThreadContext *tc, Addr vaddr, Addr desc_addr, uint8_t *data, int num_bytes, Request::Flags flags, BaseMMU::Mode mode, MMU::ArmTranslationType tran_type, bool functional)
Definition: table_walker.cc:2480
gem5::ArmISA::MMU::ArmTranslationType
ArmTranslationType
Definition: mmu.hh:113
gem5::ArmISA::TableWalker::L1Descriptor::paddr
Addr paddr() const
Return the physcal address of the entry, bits in position.
Definition: table_walker.hh:158
gem5::ArmISA::TableWalker::LongDescriptor::rwTable
uint8_t rwTable() const
R/W protection flag for subsequent levels of lookup.
Definition: table_walker.hh:767
gem5::ArmISA::TableWalker
Definition: table_walker.hh:66
gem5::ArmISA::TableWalker::WalkerState::levels
unsigned levels
Page entries walked during service (for stats)
Definition: table_walker.hh:920
gem5::ArmISA::TableWalker::doL3LongDescEvent
EventFunctionWrapper doL3LongDescEvent
Definition: table_walker.hh:1140
gem5::ArmISA::TableWalker::WalkerState::rwTable
bool rwTable
Definition: table_walker.hh:877
gem5::ArmISA::TableWalker::currState
WalkerState * currState
Definition: table_walker.hh:1046
gem5::ArmISA::TableWalker::TableWalker
TableWalker(const Params &p)
Definition: table_walker.cc:62
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
gem5::ArmISA::TableWalker::L2Descriptor::_dirty
bool _dirty
This entry has been modified (access flag set) and needs to be written back to memory.
Definition: table_walker.hh:280
gem5::ArmISA::TableWalker::L2Descriptor::domain
TlbEntry::DomainType domain() const override
Definition: table_walker.hh:307
gem5::ArmISA::TableWalker::WalkerState::doL1Descriptor
void doL1Descriptor()
gem5::ArmISA::TableWalker::WalkerState::hpd
bool hpd
Hierarchical access permission disable.
Definition: table_walker.hh:883
qport.hh
gem5::ArmISA::TableWalker::LongDescriptor::memAttr
uint8_t memAttr() const
Memory attributes, only used by stage 2 translations.
Definition: table_walker.hh:727
gem5::ArmISA::TableWalker::drain
DrainState drain() override
Draining is the process of clearing out the states of SimObjects.These are the SimObjects that are pa...
Definition: table_walker.cc:258
gem5::ArmISA::TableWalker::drainResume
void drainResume() override
Resume execution after a successful drain.
Definition: table_walker.cc:279
gem5::ArmISA::TableWalker::LongDescriptor::domain
TlbEntry::DomainType domain() const override
Definition: table_walker.hh:711
gem5::ArmISA::TableWalker::L1Descriptor::_dirty
bool _dirty
This entry has been modified (access flag set) and needs to be written back to memory.
Definition: table_walker.hh:117
gem5::ArmISA::TableWalker::memAttrs
void memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr, uint8_t texcb, bool s)
Definition: table_walker.cc:1240
clocked_object.hh
misc.hh
gem5::ArmISA::TableWalker::WalkerState::scr
SCR scr
Cached copy of the scr as it existed when translation began.
Definition: table_walker.hh:841
gem5::ArmISA::TableWalker::mmu
MMU * mmu
The MMU to forward second stage look upts to.
Definition: table_walker.hh:1029
gem5::ArmISA::TableWalker::~TableWalker
virtual ~TableWalker()
Definition: table_walker.cc:98
gem5::ArmISA::TableWalker::doL2DescriptorWrapper
void doL2DescriptorWrapper()
Definition: table_walker.cc:2082
gem5::ArmISA::TableWalker::L2Descriptor::dbgHeader
std::string dbgHeader() const override
Definition: table_walker.hh:301
gem5::ArmISA::TableWalker::LongDescriptor::attrIndx
uint8_t attrIndx() const
Attribute index.
Definition: table_walker.hh:719
gem5::ArmISA::TableWalker::memAttrsLPAE
void memAttrsLPAE(ThreadContext *tc, TlbEntry &te, LongDescriptor &lDescriptor)
Definition: table_walker.cc:1447
gem5::ArmISA::TableWalker::WalkerState::isUncacheable
bool isUncacheable
True if table walks are uncacheable (for table descriptors)
Definition: table_walker.hh:872
gem5::ArmISA::TableWalker::L2Descriptor::L2Descriptor
L2Descriptor(L1Descriptor &parent)
Definition: table_walker.hh:288
gem5::ArmISA::TableWalker::WalkerState::l2Desc
L2Descriptor l2Desc
Definition: table_walker.hh:905
gem5::ArmISA::TableWalker::LongDescriptor::dirty
bool dirty() const
This entry needs to be written back to memory.
Definition: table_walker.hh:744
gem5::ArmISA::TableWalker::L2Descriptor::paddr
Addr paddr(Addr va) const
Return complete physical address given a VA.
Definition: table_walker.hh:377
gem5::ArmISA::TableWalker::LongDescriptor::offsetBits
uint8_t offsetBits() const override
Return the bit width of the page/block offset.
Definition: table_walker.hh:525
gem5::ArmISA::TableWalker::LongDescriptor::dbgHeader
std::string dbgHeader() const override
Definition: table_walker.hh:451
gem5::statistics::Group
Statistics container.
Definition: group.hh:93
gem5::ArmISA::TableWalker::L2Descriptor::xn
bool xn() const override
Is execution allowed on this mapping?
Definition: table_walker.hh:340
gem5::ArmISA::TableWalker::DescriptorBase::DescriptorBase
DescriptorBase()
Definition: table_walker.hh:76
gem5::ArmISA::TableWalker::checkAddrSizeFaultAArch64
bool checkAddrSizeFaultAArch64(Addr addr, int pa_range)
Returns true if the address exceeds the range permitted by the system-wide setting or by the TCR_ELx ...
Definition: table_walker.cc:882
gem5::ReqPacketQueue
Definition: packet_queue.hh:226
gem5::ArmISA::TableWalker::doL2LongDescEvent
EventFunctionWrapper doL2LongDescEvent
Definition: table_walker.hh:1138
gem5::ArmISA::TableWalker::L2Descriptor::setAp0
void setAp0()
Set access flag that this entry has been touched.
Definition: table_walker.hh:396
gem5::ArmISA::TableWalker::L2Descriptor::invalid
bool invalid() const
Is the entry invalid.
Definition: table_walker.hh:326
gem5::ArmISA::TableWalker::isStage2
const bool isStage2
Indicates whether this table walker is part of the stage 2 mmu.
Definition: table_walker.hh:1038
gem5::RequestorID
uint16_t RequestorID
Definition: request.hh:95
gem5::ArmISA::TableWalker::Port::recvTimingResp
bool recvTimingResp(PacketPtr pkt) override
Receive a timing response from the peer.
Definition: table_walker.cc:206
gem5::ClockedObject::Params
ClockedObjectParams Params
Parameters of ClockedObject.
Definition: clocked_object.hh:240
gem5::MipsISA::vaddr
vaddr
Definition: pra_constants.hh:278
gem5::ArmISA::TableWalker::doL3LongDescriptorWrapper
void doL3LongDescriptorWrapper()
Definition: table_walker.cc:2144
gem5::ArmISA::TableWalker::stats
gem5::ArmISA::TableWalker::TableWalkerStats stats
gem5::ArmISA::TableWalker::L1Descriptor::dbgHeader
std::string dbgHeader() const override
Definition: table_walker.hh:132
std::list
STL list class.
Definition: stl.hh:51
gem5::ArmISA::TableWalker::DescriptorBase::ap
virtual uint8_t ap() const =0
gem5::ArmISA::TableWalker::LongDescriptor::setAf
void setAf()
Set access flag that this entry has been touched.
Definition: table_walker.hh:736
gem5::SnoopRespPacketQueue
Definition: packet_queue.hh:262
gem5::ArmISA::TableWalker::WalkerState::hcr
HCR hcr
Cached copy of the htcr as it existed when translation began.
Definition: table_walker.hh:857
gem5::ArmISA::TableWalker::WalkerState::WalkerState
WalkerState()
Definition: table_walker.cc:125
gem5::ArmISA::TableWalker::WalkerState::aarch64
bool aarch64
If the access is performed in AArch64 state.
Definition: table_walker.hh:806
gem5::ArmISA::TableWalker::processWalk
Fault processWalk()
Definition: table_walker.cc:580
gem5::ArmISA::TableWalker::toLookupLevel
static LookupLevel toLookupLevel(uint8_t lookup_level_as_int)
Definition: table_walker.cc:2417
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::ArmISA::TableWalker::WalkerState::timing
bool timing
If the mode is timing or atomic.
Definition: table_walker.hh:892
gem5::ArmISA::TableWalker::LongDescriptor::global
bool global(WalkerState *currState) const override
Is the translation global (no asid used)?
Definition: table_walker.hh:643
gem5::ArmISA::TableWalker::Stage2Walk::numBytes
int numBytes
Definition: table_walker.hh:980
gem5::ArmISA::TableWalker::DescriptorBase::shareable
virtual bool shareable() const
Definition: table_walker.hh:94
gem5::ArmISA::stride
Bitfield< 21, 20 > stride
Definition: misc_types.hh:447
gem5::ArmISA::TableWalker::L2Descriptor::texcb
uint8_t texcb() const override
Memory region attributes: ARM DDI 0406B: B3-32.
Definition: table_walker.hh:361
gem5::ArmISA::TableWalker::LongDescriptor::userTable
uint8_t userTable() const
User/privileged mode protection flag for subsequent levels of lookup.
Definition: table_walker.hh:776
gem5::ArmISA::TableWalker::Stage2Walk::fault
Fault fault
Definition: table_walker.hh:989
gem5::ArmISA::MMU
Definition: mmu.hh:59
gem5::ArmISA::TableWalker::setMmu
void setMmu(MMU *_mmu)
Definition: table_walker.cc:119
gem5::ArmISA::TableWalker::doLongDescriptor
void doLongDescriptor()
Definition: table_walker.cc:1799
gem5::ArmISA::TableWalker::WalkerState
Definition: table_walker.hh:799
gem5::ArmISA::TableWalker::pendingChange
void pendingChange()
Definition: table_walker.cc:2434
gem5::ArmISA::TableWalker::DescriptorBase::domain
virtual TlbEntry::DomainType domain() const =0
gem5::ArmISA::TableWalker::WalkerState::fault
Fault fault
The fault that we are going to return.
Definition: table_walker.hh:829
gem5::ArmISA::TableWalker::Stage2Walk::oVAddr
Addr oVAddr
Definition: table_walker.hh:984
gem5::ArmISA::TableWalker::LongDescriptor::xn
bool xn() const override
Is execution allowed on this mapping?
Definition: table_walker.hh:619
gem5::ArmISA::TableWalker::doL1LongDescEvent
EventFunctionWrapper doL1LongDescEvent
Definition: table_walker.hh:1136
gem5::ArmISA::TableWalker::L1Descriptor::paddr
Addr paddr(Addr va) const
Return the physcal address of the entry, bits in position.
Definition: table_walker.hh:167
gem5::ArmISA::TableWalker::tlb
TLB * tlb
TLB that is initiating these table walks.
Definition: table_walker.hh:1041
gem5::ArmISA::TableWalker::WalkerState::l1Desc
L1Descriptor l1Desc
Short-format descriptors.
Definition: table_walker.hh:904
gem5::ArmISA::GrainSize
GrainSize
Definition: pagetable.hh:61
gem5::ArmISA::TableWalker::Stage2Walk::Stage2Walk
Stage2Walk(TableWalker &_parent, uint8_t *_data, Event *_event, Addr vaddr, BaseMMU::Mode mode, MMU::ArmTranslationType tran_type)
Definition: table_walker.cc:2532
gem5::ArmISA::TableWalker::TableWalkerStats::walksShortTerminatedAtLevel
statistics::Vector walksShortTerminatedAtLevel
Definition: table_walker.hh:1067
gem5::ArmISA::TableWalker::Port::createPacket
PacketPtr createPacket(Addr desc_addr, int size, uint8_t *data, Request::Flags flag, Tick delay, Event *event)
Definition: table_walker.cc:150
gem5::ArmISA::TableWalker::WalkerState::mode
BaseMMU::Mode mode
Save mode for use in delayed response.
Definition: table_walker.hh:898
gem5::ArmISA::TableWalker::LongDescriptor::pxn
bool pxn() const
Is privileged execution allowed on this mapping? (LPAE only)
Definition: table_walker.hh:627
gem5::ArmISA::ExceptionLevel
ExceptionLevel
Definition: types.hh:264
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
gem5::ArmISA::TableWalker::pending
bool pending
If a timing translation is currently in progress.
Definition: table_walker.hh:1049
gem5::ArmISA::mode
Bitfield< 4, 0 > mode
Definition: misc_types.hh:74
gem5::ArmISA::TableWalker::getTlb
TLB * getTlb()
Definition: table_walker.hh:1111
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::ArmISA::TableWalker::insertTableEntry
void insertTableEntry(DescriptorBase &descriptor, bool longDescriptor)
Definition: table_walker.cc:2338
gem5::ArmISA::TableWalker::doL0LongDescEvent
EventFunctionWrapper doL0LongDescEvent
Definition: table_walker.hh:1134
eventq.hh
gem5::ArmISA::TableWalker::TableWalkerStats::squashedBefore
statistics::Scalar squashedBefore
Definition: table_walker.hh:1069

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