#include <thread_context.hh>

Inheritance diagram for gem5::fastmodel::CortexA76TC:

Public Member Functions
	CortexA76TC (gem5::BaseCPU cpu, int id, System system, gem5::BaseMMU mmu, gem5::BaseISA isa, iris::IrisConnectionInterface *iris_if, const std::string &iris_path)

bool	translateAddress (Addr &paddr, Addr vaddr) override

void	initFromIrisInstance (const ResourceMap &resources) override

RegVal	readIntRegFlat (RegIndex idx) const override

void	setIntRegFlat (RegIndex idx, RegVal val) override

RegVal	readCCRegFlat (RegIndex idx) const override

void	setCCRegFlat (RegIndex idx, RegVal val) override

const std::vector< iris::MemorySpaceId > &	getBpSpaceIds () const override

Public Member Functions inherited from gem5::Iris::ThreadContext
	ThreadContext (gem5::BaseCPU cpu, int id, System system, gem5::BaseMMU mmu, gem5::BaseISA isa, iris::IrisConnectionInterface *iris_if, const std::string &iris_path)

virtual	~ThreadContext ()

bool	schedule (PCEvent *e) override

bool	remove (PCEvent *e) override

void	scheduleInstCountEvent (Event *event, Tick count) override

void	descheduleInstCountEvent (Event *event) override

Tick	getCurrentInstCount () override

gem5::BaseCPU *	getCpuPtr () override

int	cpuId () const override

uint32_t	socketId () const override

int	threadId () const override

void	setThreadId (int id) override

int	contextId () const override

void	setContextId (int id) override

BaseMMU *	getMMUPtr () override

CheckerCPU *	getCheckerCpuPtr () override

InstDecoder *	getDecoderPtr () override

System *	getSystemPtr () override

BaseISA *	getIsaPtr () const override

void	sendFunctional (PacketPtr pkt) override

Process *	getProcessPtr () override

void	setProcessPtr (Process *p) override

Status	status () const override

void	setStatus (Status new_status) override

void	activate () override
	Set the status to Active.

void	suspend () override
	Set the status to Suspended.

void	halt () override
	Set the status to Halted.

void	takeOverFrom (gem5::ThreadContext *old_context) override

void	regStats (const std::string &name) override

Tick	readLastActivate () override

Tick	readLastSuspend () override

void	copyArchRegs (gem5::ThreadContext *tc) override

void	clearArchRegs () override

RegVal	getReg (const RegId &reg) const override

void	getReg (const RegId &reg, void *val) const override

void *	getWritableReg (const RegId &reg) override

void	setReg (const RegId &reg, RegVal val) override

void	setReg (const RegId &reg, const void *val) override

iris::ResourceId	getIntRegRscId (RegIndex int_reg) const

virtual RegVal	readIntReg (RegIndex reg_idx) const

iris::ResourceId	getVecRegRscId (RegIndex vec_reg) const

virtual const ArmISA::VecRegContainer &	readVecReg (const RegId &reg) const

virtual ArmISA::VecRegContainer &	getWritableVecReg (const RegId &reg)

virtual RegVal	readVecElem (const RegId &reg) const

iris::ResourceId	getVecPredRegRscId (RegIndex vec_reg) const

virtual const ArmISA::VecPredRegContainer &	readVecPredReg (const RegId &reg) const

virtual ArmISA::VecPredRegContainer &	getWritableVecPredReg (const RegId &reg)

virtual RegVal	readCCReg (RegIndex reg_idx) const

virtual void	setIntReg (RegIndex reg_idx, RegVal val)

virtual void	setVecReg (const RegId &reg, const ArmISA::VecRegContainer &val)

virtual void	setVecElem (const RegId &reg, RegVal val)

virtual void	setVecPredReg (const RegId &reg, const ArmISA::VecPredRegContainer &val)

virtual void	setCCReg (RegIndex reg_idx, RegVal val)

void	pcStateNoRecord (const PCStateBase &val) override

const PCStateBase &	pcState () const override

void	pcState (const PCStateBase &val) override

iris::ResourceId	getMiscRegRscId (RegIndex misc_reg) const

RegVal	readMiscRegNoEffect (RegIndex misc_reg) const override

RegVal	readMiscReg (RegIndex misc_reg) override

void	setMiscRegNoEffect (RegIndex misc_reg, const RegVal val) override

void	setMiscReg (RegIndex misc_reg, const RegVal val) override

unsigned	readStCondFailures () const override

void	setStCondFailures (unsigned sc_failures) override

void	htmAbortTransaction (uint64_t htm_uid, HtmFailureFaultCause cause) override

BaseHTMCheckpointPtr &	getHtmCheckpointPtr () override

void	setHtmCheckpointPtr (BaseHTMCheckpointPtr cpt) override

void	readMemWithCurrentMsn (Addr vaddr, size_t size, char *data)

void	writeMemWithCurrentMsn (Addr vaddr, size_t size, const char *data)

iris::ResourceId	getIntRegFlatRscId (RegIndex int_reg) const
	Flat register interfaces.

virtual const ArmISA::VecRegContainer &	readVecRegFlat (RegIndex idx) const

virtual ArmISA::VecRegContainer &	getWritableVecRegFlat (RegIndex idx)

virtual void	setVecRegFlat (RegIndex idx, const ArmISA::VecRegContainer &val)

virtual RegVal	readVecElemFlat (RegIndex idx) const

virtual void	setVecElemFlat (RegIndex idx, RegVal val)

virtual ArmISA::VecPredRegContainer	readVecPredRegFlat (RegIndex idx) const

virtual ArmISA::VecPredRegContainer &	getWritableVecPredRegFlat (RegIndex idx)

virtual void	setVecPredRegFlat (RegIndex idx, const ArmISA::VecPredRegContainer &val)

iris::ResourceId	getCCRegFlatRscId (RegIndex cc_reg) const

Public Member Functions inherited from gem5::ThreadContext
bool	getUseForClone ()

void	setUseForClone (bool new_val)

void	quiesce ()
	Quiesce thread context.

void	quiesceTick (Tick resume)
	Quiesce, suspend, and schedule activate at resume.

void	pcState (Addr addr)

virtual int	exit ()

Static Protected Attributes
static IdxNameMap	miscRegIdxNameMap

static IdxNameMap	intReg32IdxNameMap

static IdxNameMap	intReg64IdxNameMap

static IdxNameMap	flattenedIntIdxNameMap

static IdxNameMap	ccRegIdxNameMap

static IdxNameMap	vecRegIdxNameMap

static std::vector< iris::MemorySpaceId >	bpSpaceIds

Additional Inherited Members
Public Types inherited from gem5::Iris::ThreadContext
typedef std::map< std::string, iris::ResourceInfo >	ResourceMap

typedef std::vector< iris::ResourceId >	ResourceIds

typedef std::map< int, std::string >	IdxNameMap

typedef std::unordered_map< Iris::CanonicalMsn, iris::MemorySpaceId >	MemorySpaceMap

Public Types inherited from gem5::ThreadContext
enum	Status { Active , Suspended , Halting , Halted }

Static Public Member Functions inherited from gem5::ThreadContext
static void	compare (ThreadContext one, ThreadContext two)
	function to compare two thread contexts (for debugging)

Public Attributes inherited from gem5::ThreadContext
int	intResult = DefaultIntResult

double	floatResult = DefaultFloatResult

int	intOffset = 0

Static Public Attributes inherited from gem5::ThreadContext
static const int	ints []

static const double	floats []

static const int	DefaultIntResult = 0

static const double	DefaultFloatResult = 0.0

Protected Types inherited from gem5::Iris::ThreadContext
using	BpId = uint64_t

using	BpInfoPtr = std::unique_ptr<BpInfo>

using	BpInfoMap = std::map<Addr, BpInfoPtr>

using	BpInfoIt = BpInfoMap::iterator

Protected Member Functions inherited from gem5::Iris::ThreadContext
iris::ResourceId	extractResourceId (const ResourceMap &resources, const std::string &name)

void	extractResourceMap (ResourceIds &ids, const ResourceMap &resources, const IdxNameMap &idx_names)

iris::MemorySpaceId	getMemorySpaceId (const Iris::CanonicalMsn &msn) const

void	maintainStepping ()

BpInfoIt	getOrAllocBp (Addr pc)

void	installBp (BpInfoIt it)

void	uninstallBp (BpInfoIt it)

void	delBp (BpInfoIt it)

iris::IrisErrorCode	instanceRegistryChanged (uint64_t esId, const iris::IrisValueMap &fields, uint64_t time, uint64_t sInstId, bool syncEc, std::string &error_message_out)

iris::IrisErrorCode	phaseInitLeave (uint64_t esId, const iris::IrisValueMap &fields, uint64_t time, uint64_t sInstId, bool syncEc, std::string &error_message_out)

iris::IrisErrorCode	simulationTimeEvent (uint64_t esId, const iris::IrisValueMap &fields, uint64_t time, uint64_t sInstId, bool syncEc, std::string &error_message_out)

iris::IrisErrorCode	breakpointHit (uint64_t esId, const iris::IrisValueMap &fields, uint64_t time, uint64_t sInstId, bool syncEc, std::string &error_message_out)

iris::IrisErrorCode	semihostingEvent (uint64_t esId, const iris::IrisValueMap &fields, uint64_t time, uint64_t sInstId, bool syncEc, std::string &error_message_out)

iris::IrisCppAdapter &	call () const

iris::IrisCppAdapter &	noThrow () const

void	readMem (iris::MemorySpaceId space, Addr addr, void *p, size_t size)

void	writeMem (iris::MemorySpaceId space, Addr addr, const void *p, size_t size)

bool	translateAddress (Addr &paddr, iris::MemorySpaceId p_space, Addr vaddr, iris::MemorySpaceId v_space)

Protected Attributes inherited from gem5::Iris::ThreadContext
gem5::BaseCPU *	_cpu

int	_threadId

ContextID	_contextId

System *	_system

gem5::BaseMMU *	_mmu

gem5::BaseISA *	_isa

std::string	_irisPath

iris::InstanceId	_instId = iris::IRIS_UINT64_MAX

std::vector< ArmISA::VecRegContainer >	vecRegs

std::vector< ArmISA::VecPredRegContainer >	vecPredRegs

Status	_status = Active

Event *	enableAfterPseudoEvent

ResourceIds	miscRegIds

ResourceIds	intReg32Ids

ResourceIds	intReg64Ids

ResourceIds	flattenedIntIds

ResourceIds	ccRegIds

iris::ResourceId	pcRscId = iris::IRIS_UINT64_MAX

iris::ResourceId	icountRscId

ResourceIds	vecRegIds

ResourceIds	vecPredRegIds

std::vector< iris::MemorySpaceInfo >	memorySpaces

std::vector< iris::MemorySupportedAddressTranslationResult >	translations

MemorySpaceMap	memorySpaceIds

EventQueue	comInstEventQueue

BpInfoMap	bps

std::optional< Addr >	bpAddr

iris::EventStreamId	regEventStreamId

iris::EventStreamId	initEventStreamId

iris::EventStreamId	timeEventStreamId

iris::EventStreamId	breakpointEventStreamId

iris::EventStreamId	semihostingEventStreamId

iris::IrisInstance	client

ArmISA::PCState	pc

Protected Attributes inherited from gem5::ThreadContext
bool	useForClone = false

Detailed Description

Definition at line 41 of file thread_context.hh.

Constructor & Destructor Documentation

◆ CortexA76TC()

gem5::fastmodel::CortexA76TC::CortexA76TC	(	gem5::BaseCPU *	cpu,
		int	id,
		System *	system,
		gem5::BaseMMU *	mmu,
		gem5::BaseISA *	isa,
		iris::IrisConnectionInterface *	iris_if,
		const std::string &	iris_path )