thread_context.hh

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#ifndef __ARCH_ARM_FASTMODEL_CORTEXA76_THREAD_CONTEXT_HH__
#define __ARCH_ARM_FASTMODEL_CORTEXA76_THREAD_CONTEXT_HH__
 
#include "arch/arm/fastmodel/iris/thread_context.hh"
 
namespace gem5
{
 
namespace fastmodel
{
 
// This ThreadContext class translates accesses to state using gem5's native
// to the Iris API. This includes extracting and translating register indices.
class CortexA76TC : public Iris::ThreadContext
{
  protected:
    static IdxNameMap miscRegIdxNameMap;
    static IdxNameMap intReg32IdxNameMap;
    static IdxNameMap intReg64IdxNameMap;
    static IdxNameMap flattenedIntIdxNameMap;
    static IdxNameMap ccRegIdxNameMap;
    static IdxNameMap vecRegIdxNameMap;
    static std::vector<iris::MemorySpaceId> bpSpaceIds;
 
  public:
    CortexA76TC(gem5::BaseCPU *cpu, int id, System *system,
                gem5::BaseMMU *mmu, gem5::BaseISA *isa,
                iris::IrisConnectionInterface *iris_if,
                const std::string &iris_path);
 
    bool translateAddress(Addr &paddr, Addr vaddr) override;
 
    void initFromIrisInstance(const ResourceMap &resources) override;
 
    RegVal readIntRegFlat(RegIndex idx) const override;
    void setIntRegFlat(RegIndex idx, RegVal val) override;
 
    RegVal readCCRegFlat(RegIndex idx) const override;
    void setCCRegFlat(RegIndex idx, RegVal val) override;
 
    const std::vector<iris::MemorySpaceId> &getBpSpaceIds() const override;
};
class CortexA76TC : public Iris::ThreadContext {…};
 
} // namespace fastmodel
} // namespace gem5
 
#endif // __ARCH_ARM_FASTMODEL_CORTEXA76_THREAD_CONTEXT_HH__