gem5  v21.1.0.2
timing.hh
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40 
41 #ifndef __CPU_SIMPLE_TIMING_HH__
42 #define __CPU_SIMPLE_TIMING_HH__
43 
44 #include "arch/generic/mmu.hh"
45 #include "cpu/simple/base.hh"
47 #include "cpu/translation.hh"
48 #include "params/TimingSimpleCPU.hh"
49 
50 namespace gem5
51 {
52 
54 {
55  public:
56 
57  TimingSimpleCPU(const TimingSimpleCPUParams &params);
58  virtual ~TimingSimpleCPU();
59 
60  void init() override;
61 
62  private:
63 
64  /*
65  * If an access needs to be broken into fragments, currently at most two,
66  * the the following two classes are used as the sender state of the
67  * packets so the CPU can keep track of everything. In the main packet
68  * sender state, there's an array with a spot for each fragment. If a
69  * fragment has already been accepted by the CPU, aka isn't waiting for
70  * a retry, it's pointer is NULL. After each fragment has successfully
71  * been processed, the "outstanding" counter is decremented. Once the
72  * count is zero, the entire larger access is complete.
73  */
75  {
76  public:
79 
80  int
82  {
83  if (fragments[0]) {
84  return 0;
85  } else if (fragments[1]) {
86  return 1;
87  } else {
88  return -1;
89  }
90  }
91  };
92 
94  {
95  public:
96  SplitFragmentSenderState(PacketPtr _bigPkt, int _index) :
97  bigPkt(_bigPkt), index(_index)
98  {}
100  int index;
101 
102  void
104  {
105  SplitMainSenderState * main_send_state =
106  dynamic_cast<SplitMainSenderState *>(bigPkt->senderState);
107  main_send_state->fragments[index] = NULL;
108  }
109  };
110 
112  {
113  protected:
115 
116  public:
118  : cpu(_cpu)
119  {}
120 
121  void
123  {
124  assert(cpu->_status == BaseSimpleCPU::Running);
126  }
127 
128  void
129  finish(const Fault &fault, const RequestPtr &req, ThreadContext *tc,
131  {
132  cpu->sendFetch(fault, req, tc);
133  }
134  };
136 
137  void threadSnoop(PacketPtr pkt, ThreadID sender);
138  void sendData(const RequestPtr &req,
139  uint8_t *data, uint64_t *res, bool read);
140  void sendSplitData(const RequestPtr &req1, const RequestPtr &req2,
141  const RequestPtr &req,
142  uint8_t *data, bool read);
143 
144  void translationFault(const Fault &fault);
145 
146  PacketPtr buildPacket(const RequestPtr &req, bool read);
147  void buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
148  const RequestPtr &req1, const RequestPtr &req2,
149  const RequestPtr &req,
150  uint8_t *data, bool read);
151 
152  bool handleReadPacket(PacketPtr pkt);
153  // This function always implicitly uses dcache_pkt.
154  bool handleWritePacket();
155 
162  class TimingCPUPort : public RequestPort
163  {
164  public:
165 
166  TimingCPUPort(const std::string& _name, TimingSimpleCPU* _cpu)
167  : RequestPort(_name, _cpu), cpu(_cpu),
168  retryRespEvent([this]{ sendRetryResp(); }, name())
169  { }
170 
171  protected:
172 
174 
175  struct TickEvent : public Event
176  {
179 
180  TickEvent(TimingSimpleCPU *_cpu) : pkt(NULL), cpu(_cpu) {}
181  const char *description() const { return "Timing CPU tick"; }
182  void schedule(PacketPtr _pkt, Tick t);
183  };
184 
186  };
187 
188  class IcachePort : public TimingCPUPort
189  {
190  public:
191 
193  : TimingCPUPort(_cpu->name() + ".icache_port", _cpu),
194  tickEvent(_cpu)
195  { }
196 
197  protected:
198 
199  virtual bool recvTimingResp(PacketPtr pkt);
200 
201  virtual void recvReqRetry();
202 
203  struct ITickEvent : public TickEvent
204  {
205 
207  : TickEvent(_cpu) {}
208  void process();
209  const char *description() const { return "Timing CPU icache tick"; }
210  };
211 
213 
214  };
215 
216  class DcachePort : public TimingCPUPort
217  {
218  public:
219 
221  : TimingCPUPort(_cpu->name() + ".dcache_port", _cpu),
222  tickEvent(_cpu)
223  {
224  cacheBlockMask = ~(cpu->cacheLineSize() - 1);
225  }
226 
228  protected:
229 
233  virtual void recvTimingSnoopReq(PacketPtr pkt);
234  virtual void recvFunctionalSnoop(PacketPtr pkt);
235 
236  virtual bool recvTimingResp(PacketPtr pkt);
237 
238  virtual void recvReqRetry();
239 
240  virtual bool isSnooping() const {
241  return true;
242  }
243 
244  struct DTickEvent : public TickEvent
245  {
247  : TickEvent(_cpu) {}
248  void process();
249  const char *description() const { return "Timing CPU dcache tick"; }
250  };
251 
253 
254  };
255 
256  void updateCycleCounts();
257 
260 
263 
265 
266  protected:
267 
269  Port &getDataPort() override { return dcachePort; }
270 
272  Port &getInstPort() override { return icachePort; }
273 
274  public:
275 
276  DrainState drain() override;
277  void drainResume() override;
278 
279  void switchOut() override;
280  void takeOverFrom(BaseCPU *oldCPU) override;
281 
282  void verifyMemoryMode() const override;
283 
284  void activateContext(ThreadID thread_num) override;
285  void suspendContext(ThreadID thread_num) override;
286 
287  Fault initiateMemRead(Addr addr, unsigned size,
288  Request::Flags flags,
289  const std::vector<bool>& byte_enable =std::vector<bool>())
290  override;
291 
292  Fault writeMem(uint8_t *data, unsigned size,
293  Addr addr, Request::Flags flags, uint64_t *res,
294  const std::vector<bool>& byte_enable = std::vector<bool>())
295  override;
296 
297  Fault initiateMemAMO(Addr addr, unsigned size, Request::Flags flags,
298  AtomicOpFunctorPtr amo_op) override;
299 
300  void fetch();
301  void sendFetch(const Fault &fault,
302  const RequestPtr &req, ThreadContext *tc);
303  void completeIfetch(PacketPtr );
304  void completeDataAccess(PacketPtr pkt);
305  void advanceInst(const Fault &fault);
306 
313  bool isSquashed() const { return false; }
314 
319  void printAddr(Addr a);
320 
326 
328  Fault initiateHtmCmd(Request::Flags flags) override;
329 
331 
332  private:
333 
335 
336  struct IprEvent : Event
337  {
340  IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t);
341  virtual void process();
342  virtual const char *description() const;
343  };
344 
361  bool isCpuDrained() const {
363  SimpleThread* thread = t_info.thread;
364 
365  return thread->microPC() == 0 && !t_info.stayAtPC &&
367  }
368 
374  bool tryCompleteDrain();
375 };
376 
377 } // namespace gem5
378 
379 #endif // __CPU_SIMPLE_TIMING_HH__
gem5::TimingSimpleCPU::init
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: timing.cc:65
gem5::TimingSimpleCPU::FetchTranslation::markDelayed
void markDelayed()
Signal that the translation has been delayed due to a hw page table walk.
Definition: timing.hh:122
gem5::TimingSimpleCPU::initiateHtmCmd
Fault initiateHtmCmd(Request::Flags flags) override
hardware transactional memory
Definition: timing.cc:1216
gem5::TimingSimpleCPU::sendData
void sendData(const RequestPtr &req, uint8_t *data, uint64_t *res, bool read)
Definition: timing.cc:298
gem5::BaseSimpleCPU::threadInfo
std::vector< SimpleExecContext * > threadInfo
Definition: base.hh:100
gem5::TimingSimpleCPU::IprEvent::process
virtual void process()
Definition: timing.cc:1197
gem5::Port::name
const std::string name() const
Return port name (for DPRINTF).
Definition: port.hh:111
data
const char data[]
Definition: circlebuf.test.cc:48
gem5::HtmFailureFaultCause
HtmFailureFaultCause
Definition: htm.hh:47
gem5::TimingSimpleCPU::TimingCPUPort::TickEvent::TickEvent
TickEvent(TimingSimpleCPU *_cpu)
Definition: timing.hh:180
gem5::TimingSimpleCPU::DcachePort
Definition: timing.hh:216
gem5::TimingSimpleCPU::TimingCPUPort::retryRespEvent
EventFunctionWrapper retryRespEvent
Definition: timing.hh:185
gem5::TimingSimpleCPU::SplitMainSenderState::fragments
PacketPtr fragments[2]
Definition: timing.hh:78
gem5::TimingSimpleCPU::TimingCPUPort::TickEvent::cpu
TimingSimpleCPU * cpu
Definition: timing.hh:178
gem5::BaseMMU::Mode
Mode
Definition: mmu.hh:53
gem5::TimingSimpleCPU::drain
DrainState drain() override
Draining is the process of clearing out the states of SimObjects.These are the SimObjects that are pa...
Definition: timing.cc:92
gem5::TimingSimpleCPU::buildSplitPacket
void buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2, const RequestPtr &req1, const RequestPtr &req2, const RequestPtr &req, uint8_t *data, bool read)
Definition: timing.cc:419
gem5::BaseSimpleCPU::_status
Status _status
Definition: base.hh:123
gem5::BaseCPU::cacheLineSize
unsigned int cacheLineSize() const
Get the cache line size of the system.
Definition: base.hh:381
gem5::TimingSimpleCPU::DcachePort::cacheBlockMask
Addr cacheBlockMask
Definition: timing.hh:227
gem5::TimingSimpleCPU::FetchTranslation::cpu
TimingSimpleCPU * cpu
Definition: timing.hh:114
gem5::TimingSimpleCPU::DcachePort::isSnooping
virtual bool isSnooping() const
Determine if this request port is snooping or not.
Definition: timing.hh:240
gem5::TimingSimpleCPU::SplitFragmentSenderState
Definition: timing.hh:93
gem5::TimingSimpleCPU::IprEvent
Definition: timing.hh:336
gem5::TimingSimpleCPU::ifetch_pkt
PacketPtr ifetch_pkt
Definition: timing.hh:261
gem5::TimingSimpleCPU::buildPacket
PacketPtr buildPacket(const RequestPtr &req, bool read)
Definition: timing.cc:413
gem5::ArmISA::a
Bitfield< 8 > a
Definition: misc_types.hh:65
gem5::TimingSimpleCPU::verifyMemoryMode
void verifyMemoryMode() const override
Verify that the system is in a memory mode supported by the CPU.
Definition: timing.cc:200
gem5::TimingSimpleCPU::fetch
void fetch()
Definition: timing.cc:677
gem5::TimingSimpleCPU::dcachePort
DcachePort dcachePort
Definition: timing.hh:259
gem5::TimingSimpleCPU::SplitMainSenderState::getPendingFragment
int getPendingFragment()
Definition: timing.hh:81
gem5::BaseSimpleCPU::ITBWaitResponse
@ ITBWaitResponse
Definition: base.hh:113
gem5::TimingSimpleCPU::DcachePort::DTickEvent::process
void process()
Definition: timing.cc:1140
std::vector< bool >
gem5::TimingSimpleCPU::DcachePort::recvTimingSnoopReq
virtual void recvTimingSnoopReq(PacketPtr pkt)
Snoop a coherence request, we need to check if this causes a wakeup event on a cpu that is monitoring...
Definition: timing.cc:1089
gem5::TimingSimpleCPU::sendFetch
void sendFetch(const Fault &fault, const RequestPtr &req, ThreadContext *tc)
Definition: timing.cc:720
gem5::TimingSimpleCPU::IcachePort::recvReqRetry
virtual void recvReqRetry()
Called by the peer if sendTimingReq was called on this peer (causing recvTimingReq to be called on th...
Definition: timing.cc:929
gem5::SimpleThread
The SimpleThread object provides a combination of the ThreadState object and the ThreadContext interf...
Definition: simple_thread.hh:94
gem5::TimingSimpleCPU::completeDataAccess
void completeDataAccess(PacketPtr pkt)
Definition: timing.cc:943
gem5::TimingSimpleCPU::IcachePort::recvTimingResp
virtual bool recvTimingResp(PacketPtr pkt)
Receive a timing response from the peer.
Definition: timing.cc:907
gem5::TimingSimpleCPU::FetchTranslation
Definition: timing.hh:111
gem5::RequestPort
A RequestPort is a specialisation of a Port, which implements the default protocol for the three diff...
Definition: port.hh:77
gem5::TimingSimpleCPU::IcachePort::ITickEvent::description
const char * description() const
Definition: timing.hh:209
gem5::Cycles
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:78
gem5::SimpleThread::microPC
MicroPC microPC() const override
Definition: simple_thread.hh:441
gem5::TimingSimpleCPU::SplitFragmentSenderState::index
int index
Definition: timing.hh:100
gem5::TimingSimpleCPU::SplitFragmentSenderState::SplitFragmentSenderState
SplitFragmentSenderState(PacketPtr _bigPkt, int _index)
Definition: timing.hh:96
gem5::TimingSimpleCPU::DcachePort::DTickEvent
Definition: timing.hh:244
gem5::TimingSimpleCPU::updateCycleCounts
void updateCycleCounts()
Definition: timing.cc:1079
gem5::Flags< FlagsType >
gem5::DrainState
DrainState
Object drain/handover states.
Definition: drain.hh:74
gem5::TimingSimpleCPU::FetchTranslation::finish
void finish(const Fault &fault, const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode)
Definition: timing.hh:129
gem5::TimingSimpleCPU::IprEvent::cpu
TimingSimpleCPU * cpu
Definition: timing.hh:339
gem5::TimingSimpleCPU::DcachePort::DTickEvent::DTickEvent
DTickEvent(TimingSimpleCPU *_cpu)
Definition: timing.hh:246
gem5::TimingSimpleCPU::icachePort
IcachePort icachePort
Definition: timing.hh:258
gem5::TimingSimpleCPU::switchOut
void switchOut() override
Prepare for another CPU to take over execution.
Definition: timing.cc:170
translation.hh
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::TimingSimpleCPU::isSquashed
bool isSquashed() const
This function is used by the page table walker to determine if it could translate the a pending reque...
Definition: timing.hh:313
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::SimObject::params
const Params & params() const
Definition: sim_object.hh:176
gem5::Event
Definition: eventq.hh:251
gem5::TimingSimpleCPU::initiateMemAMO
Fault initiateMemAMO(Addr addr, unsigned size, Request::Flags flags, AtomicOpFunctorPtr amo_op) override
Definition: timing.cc:589
gem5::TimingSimpleCPU::fetchEvent
EventFunctionWrapper fetchEvent
Definition: timing.hh:334
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::TimingSimpleCPU::printAddr
void printAddr(Addr a)
Print state of address in memory system via PrintReq (for debugging).
Definition: timing.cc:1210
gem5::TimingSimpleCPU::~TimingSimpleCPU
virtual ~TimingSimpleCPU()
Definition: timing.cc:87
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::SimpleExecContext::stayAtPC
bool stayAtPC
Definition: exec_context.hh:70
gem5::TimingSimpleCPU::handleWritePacket
bool handleWritePacket()
Definition: timing.cc:503
gem5::TimingSimpleCPU::TimingCPUPort::TickEvent::description
const char * description() const
Return a C string describing the event.
Definition: timing.hh:181
gem5::RequestPort::sendRetryResp
virtual void sendRetryResp()
Send a retry to the response port that previously attempted a sendTimingResp to this request port and...
Definition: port.hh:525
gem5::TimingSimpleCPU::TimingCPUPort::TimingCPUPort
TimingCPUPort(const std::string &_name, TimingSimpleCPU *_cpu)
Definition: timing.hh:166
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
mmu.hh
gem5::TimingSimpleCPU::activateContext
void activateContext(ThreadID thread_num) override
Notify the CPU that the indicated context is now active.
Definition: timing.cc:209
gem5::TimingSimpleCPU::IprEvent::IprEvent
IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t)
Definition: timing.cc:1189
gem5::TimingSimpleCPU::getDataPort
Port & getDataPort() override
Return a reference to the data port.
Definition: timing.hh:269
gem5::TimingSimpleCPU::completeIfetch
void completeIfetch(PacketPtr)
Definition: timing.cc:820
gem5::TimingSimpleCPU::DcachePort::tickEvent
DTickEvent tickEvent
Definition: timing.hh:252
gem5::BaseCPU
Definition: base.hh:107
gem5::TimingSimpleCPU::initiateMemRead
Fault initiateMemRead(Addr addr, unsigned size, Request::Flags flags, const std::vector< bool > &byte_enable=std::vector< bool >()) override
Definition: timing.cc:451
gem5::BaseSimpleCPU
Definition: base.hh:80
gem5::TimingSimpleCPU::advanceInst
void advanceInst(const Fault &fault)
Definition: timing.cc:754
gem5::Packet::SenderState
A virtual base opaque structure used to hold state associated with the packet (e.g....
Definition: packet.hh:457
gem5::ArmISA::t
Bitfield< 5 > t
Definition: misc_types.hh:70
gem5::TimingSimpleCPU::DcachePort::recvFunctionalSnoop
virtual void recvFunctionalSnoop(PacketPtr pkt)
Receive a functional snoop request packet from the peer.
Definition: timing.cc:1109
gem5::TimingSimpleCPU::FetchTranslation::FetchTranslation
FetchTranslation(TimingSimpleCPU *_cpu)
Definition: timing.hh:117
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::TimingSimpleCPU::DcachePort::recvTimingResp
virtual bool recvTimingResp(PacketPtr pkt)
Receive a timing response from the peer.
Definition: timing.cc:1119
gem5::TimingSimpleCPU::threadSnoop
void threadSnoop(PacketPtr pkt, ThreadID sender)
Definition: timing.cc:637
gem5::TimingSimpleCPU::IcachePort::ITickEvent::ITickEvent
ITickEvent(TimingSimpleCPU *_cpu)
Definition: timing.hh:206
gem5::Packet::senderState
SenderState * senderState
This packet's sender state.
Definition: packet.hh:534
gem5::TimingSimpleCPU::IcachePort::IcachePort
IcachePort(TimingSimpleCPU *_cpu)
Definition: timing.hh:192
gem5::TimingSimpleCPU::DcachePort::recvReqRetry
virtual void recvReqRetry()
Called by the peer if sendTimingReq was called on this peer (causing recvTimingReq to be called on th...
Definition: timing.cc:1146
gem5::TimingSimpleCPU::SplitFragmentSenderState::clearFromParent
void clearFromParent()
Definition: timing.hh:103
gem5::EventFunctionWrapper
Definition: eventq.hh:1115
gem5::SimpleExecContext::thread
SimpleThread * thread
Definition: exec_context.hh:64
gem5::TimingSimpleCPU::htmSendAbortSignal
void htmSendAbortSignal(HtmFailureFaultCause) override
This function is used to instruct the memory subsystem that a transaction should be aborted and the s...
Definition: timing.cc:1261
base.hh
gem5::TimingSimpleCPU::takeOverFrom
void takeOverFrom(BaseCPU *oldCPU) override
Load the state of a CPU from the previous CPU object, invoked on all new CPUs that are about to be sw...
Definition: timing.cc:192
gem5::TimingSimpleCPU::IprEvent::pkt
Packet * pkt
Definition: timing.hh:338
gem5::BaseMMU::Translation
Definition: mmu.hh:55
gem5::TimingSimpleCPU::finishTranslation
void finishTranslation(WholeTranslationState *state)
Finish a DTB translation.
Definition: timing.cc:651
gem5::TimingSimpleCPU::tryCompleteDrain
bool tryCompleteDrain()
Try to complete a drain request.
Definition: timing.cc:154
gem5::TimingSimpleCPU::TimingCPUPort::TickEvent::pkt
PacketPtr pkt
Definition: timing.hh:177
gem5::TimingSimpleCPU::drainResume
void drainResume() override
Resume execution after a successful drain.
Definition: timing.cc:119
gem5::TimingSimpleCPU::previousCycle
Cycles previousCycle
Definition: timing.hh:264
gem5::TimingSimpleCPU::translationFault
void translationFault(const Fault &fault)
Definition: timing.cc:396
gem5::WholeTranslationState
This class captures the state of an address translation.
Definition: translation.hh:62
gem5::TimingSimpleCPU::dcache_pkt
PacketPtr dcache_pkt
Definition: timing.hh:262
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
gem5::SimpleExecContext
Definition: exec_context.hh:60
gem5::TimingSimpleCPU::TimingCPUPort::cpu
TimingSimpleCPU * cpu
Definition: timing.hh:173
gem5::BaseSimpleCPU::Running
@ Running
Definition: base.hh:111
gem5::TimingSimpleCPU::handleReadPacket
bool handleReadPacket(PacketPtr pkt)
Definition: timing.cc:263
gem5::TimingSimpleCPU::SplitMainSenderState::outstanding
int outstanding
Definition: timing.hh:77
gem5::TimingSimpleCPU::suspendContext
void suspendContext(ThreadID thread_num) override
Notify the CPU that the indicated context is now suspended.
Definition: timing.cc:233
gem5::TimingSimpleCPU::IprEvent::description
virtual const char * description() const
Return a C string describing the event.
Definition: timing.cc:1203
gem5::TimingSimpleCPU::getInstPort
Port & getInstPort() override
Return a reference to the instruction port.
Definition: timing.hh:272
gem5::TimingSimpleCPU::SplitMainSenderState
Definition: timing.hh:74
exec_context.hh
gem5::TimingSimpleCPU::writeMem
Fault writeMem(uint8_t *data, unsigned size, Addr addr, Request::Flags flags, uint64_t *res, const std::vector< bool > &byte_enable=std::vector< bool >()) override
Definition: timing.cc:525
gem5::TimingSimpleCPU::TimingCPUPort::TickEvent::schedule
void schedule(PacketPtr _pkt, Tick t)
Definition: timing.cc:71
gem5::TimingSimpleCPU::SplitFragmentSenderState::bigPkt
PacketPtr bigPkt
Definition: timing.hh:99
gem5::TimingSimpleCPU::TimingCPUPort
A TimingCPUPort overrides the default behaviour of the recvTiming and recvRetry and implements events...
Definition: timing.hh:162
gem5::TimingSimpleCPU::sendSplitData
void sendSplitData(const RequestPtr &req1, const RequestPtr &req2, const RequestPtr &req, uint8_t *data, bool read)
Definition: timing.cc:346
gem5::AtomicOpFunctorPtr
std::unique_ptr< AtomicOpFunctor > AtomicOpFunctorPtr
Definition: amo.hh:242
gem5::TimingSimpleCPU::fetchTranslation
FetchTranslation fetchTranslation
Definition: timing.hh:135
gem5::TimingSimpleCPU::DcachePort::DTickEvent::description
const char * description() const
Return a C string describing the event.
Definition: timing.hh:249
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::TimingSimpleCPU::IcachePort::ITickEvent::process
void process()
Definition: timing.cc:901
gem5::TimingSimpleCPU
Definition: timing.hh:53
gem5::TimingSimpleCPU::DcachePort::DcachePort
DcachePort(TimingSimpleCPU *_cpu)
Definition: timing.hh:220
gem5::TimingSimpleCPU::IcachePort
Definition: timing.hh:188
gem5::TimingSimpleCPU::IcachePort::ITickEvent
Definition: timing.hh:203
gem5::TimingSimpleCPU::TimingCPUPort::TickEvent
Definition: timing.hh:175
gem5::TimingSimpleCPU::isCpuDrained
bool isCpuDrained() const
Check if a system is in a drained state.
Definition: timing.hh:361
gem5::BaseSimpleCPU::curThread
ThreadID curThread
Definition: base.hh:83
gem5::Named::_name
const std::string _name
Definition: named.hh:41
gem5::Event::scheduled
bool scheduled() const
Determine if the current event is scheduled.
Definition: eventq.hh:465
gem5::ThreadID
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:242
gem5::TimingSimpleCPU::IcachePort::tickEvent
ITickEvent tickEvent
Definition: timing.hh:212
gem5::ArmISA::mode
Bitfield< 4, 0 > mode
Definition: misc_types.hh:73
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::TimingSimpleCPU::TimingSimpleCPU
TimingSimpleCPU(const TimingSimpleCPUParams &params)
Definition: timing.cc:77

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