gem5  v21.1.0.2
exec_context.hh
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40 
41 #ifndef __CPU_SIMPLE_EXEC_CONTEXT_HH__
42 #define __CPU_SIMPLE_EXEC_CONTEXT_HH__
43 
44 #include "arch/vecregs.hh"
45 #include "base/types.hh"
46 #include "config/the_isa.hh"
47 #include "cpu/base.hh"
48 #include "cpu/exec_context.hh"
49 #include "cpu/reg_class.hh"
50 #include "cpu/simple/base.hh"
51 #include "cpu/static_inst_fwd.hh"
52 #include "cpu/translation.hh"
53 #include "mem/request.hh"
54 
55 namespace gem5
56 {
57 
58 class BaseSimpleCPU;
59 
61 {
62  public:
65 
66  // This is the offset from the current pc that fetch should be performed
68  // This flag says to stay at the current pc. This is useful for
69  // instructions which go beyond MachInst boundaries.
70  bool stayAtPC;
71 
72  // Branch prediction
74 
78  // Number of simulated loads
80  // Number of cycles stalled for I-cache responses
82  // Number of cycles stalled for D-cache responses
84 
86  {
88  : statistics::Group(cpu,
89  csprintf("exec_context.thread_%i",
90  thread->threadId()).c_str()),
91  ADD_STAT(numInsts, statistics::units::Count::get(),
92  "Number of instructions committed"),
93  ADD_STAT(numOps, statistics::units::Count::get(),
94  "Number of ops (including micro ops) committed"),
95  ADD_STAT(numIntAluAccesses, statistics::units::Count::get(),
96  "Number of integer alu accesses"),
97  ADD_STAT(numFpAluAccesses, statistics::units::Count::get(),
98  "Number of float alu accesses"),
99  ADD_STAT(numVecAluAccesses, statistics::units::Count::get(),
100  "Number of vector alu accesses"),
101  ADD_STAT(numCallsReturns, statistics::units::Count::get(),
102  "Number of times a function call or return occured"),
103  ADD_STAT(numCondCtrlInsts, statistics::units::Count::get(),
104  "Number of instructions that are conditional controls"),
105  ADD_STAT(numIntInsts, statistics::units::Count::get(),
106  "Number of integer instructions"),
107  ADD_STAT(numFpInsts, statistics::units::Count::get(),
108  "Number of float instructions"),
109  ADD_STAT(numVecInsts, statistics::units::Count::get(),
110  "Number of vector instructions"),
111  ADD_STAT(numIntRegReads, statistics::units::Count::get(),
112  "Number of times the integer registers were read"),
113  ADD_STAT(numIntRegWrites, statistics::units::Count::get(),
114  "Number of times the integer registers were written"),
115  ADD_STAT(numFpRegReads, statistics::units::Count::get(),
116  "Number of times the floating registers were read"),
117  ADD_STAT(numFpRegWrites, statistics::units::Count::get(),
118  "Number of times the floating registers were written"),
119  ADD_STAT(numVecRegReads, statistics::units::Count::get(),
120  "Number of times the vector registers were read"),
121  ADD_STAT(numVecRegWrites, statistics::units::Count::get(),
122  "Number of times the vector registers were written"),
123  ADD_STAT(numVecPredRegReads, statistics::units::Count::get(),
124  "Number of times the predicate registers were read"),
125  ADD_STAT(numVecPredRegWrites, statistics::units::Count::get(),
126  "Number of times the predicate registers were written"),
127  ADD_STAT(numCCRegReads, statistics::units::Count::get(),
128  "Number of times the CC registers were read"),
129  ADD_STAT(numCCRegWrites, statistics::units::Count::get(),
130  "Number of times the CC registers were written"),
131  ADD_STAT(numMemRefs, statistics::units::Count::get(),
132  "Number of memory refs"),
133  ADD_STAT(numLoadInsts, statistics::units::Count::get(),
134  "Number of load instructions"),
135  ADD_STAT(numStoreInsts, statistics::units::Count::get(),
136  "Number of store instructions"),
137  ADD_STAT(numIdleCycles, statistics::units::Cycle::get(),
138  "Number of idle cycles"),
139  ADD_STAT(numBusyCycles, statistics::units::Cycle::get(),
140  "Number of busy cycles"),
141  ADD_STAT(notIdleFraction, statistics::units::Ratio::get(),
142  "Percentage of non-idle cycles"),
143  ADD_STAT(idleFraction, statistics::units::Ratio::get(),
144  "Percentage of idle cycles"),
145  ADD_STAT(icacheStallCycles, statistics::units::Cycle::get(),
146  "ICache total stall cycles"),
147  ADD_STAT(dcacheStallCycles, statistics::units::Cycle::get(),
148  "DCache total stall cycles"),
149  ADD_STAT(numBranches, statistics::units::Count::get(),
150  "Number of branches fetched"),
151  ADD_STAT(numPredictedBranches, statistics::units::Count::get(),
152  "Number of branches predicted as taken"),
153  ADD_STAT(numBranchMispred, statistics::units::Count::get(),
154  "Number of branch mispredictions"),
155  ADD_STAT(statExecutedInstType, statistics::units::Count::get(),
156  "Class of executed instruction.")
157  {
160 
163 
166 
169 
171  .init(enums::Num_OpClass)
173 
174  for (unsigned i = 0; i < Num_OpClasses; ++i) {
175  statExecutedInstType.subname(i, enums::OpClassStrings[i]);
176  }
177 
181 
184 
187 
190  }
191 
192  // Number of simulated instructions
195 
196  // Number of integer alu accesses
198 
199  // Number of float alu accesses
201 
202  // Number of vector alu accesses
204 
205  // Number of function calls/returns
207 
208  // Conditional control instructions;
210 
211  // Number of int instructions
213 
214  // Number of float instructions
216 
217  // Number of vector instructions
219 
220  // Number of integer register file accesses
223 
224  // Number of float register file accesses
227 
228  // Number of vector register file accesses
231 
232  // Number of predicate register file accesses
235 
236  // Number of condition code register file accesses
239 
240  // Number of simulated memory references
244 
245  // Number of idle cycles
247 
248  // Number of busy cycles
250 
251  // Number of idle cycles
254 
255  // Number of cycles stalled for I-cache responses
257 
258  // Number of cycles stalled for D-cache responses
260 
269 
270  // Instruction mix histogram by OpClass
272 
274 
275  public:
278  : cpu(_cpu), thread(_thread), fetchOffset(0), stayAtPC(false),
279  numInst(0), numOp(0), numLoad(0), lastIcacheStall(0),
281  { }
282 
284  RegVal
285  readIntRegOperand(const StaticInst *si, int idx) override
286  {
288  const RegId& reg = si->srcRegIdx(idx);
289  assert(reg.is(IntRegClass));
290  return thread->readIntReg(reg.index());
291  }
292 
294  void
295  setIntRegOperand(const StaticInst *si, int idx, RegVal val) override
296  {
298  const RegId& reg = si->destRegIdx(idx);
299  assert(reg.is(IntRegClass));
300  thread->setIntReg(reg.index(), val);
301  }
302 
305  RegVal
306  readFloatRegOperandBits(const StaticInst *si, int idx) override
307  {
309  const RegId& reg = si->srcRegIdx(idx);
310  assert(reg.is(FloatRegClass));
311  return thread->readFloatReg(reg.index());
312  }
313 
316  void
317  setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) override
318  {
320  const RegId& reg = si->destRegIdx(idx);
321  assert(reg.is(FloatRegClass));
322  thread->setFloatReg(reg.index(), val);
323  }
324 
327  readVecRegOperand(const StaticInst *si, int idx) const override
328  {
330  const RegId& reg = si->srcRegIdx(idx);
331  assert(reg.is(VecRegClass));
332  return thread->readVecReg(reg);
333  }
334 
337  getWritableVecRegOperand(const StaticInst *si, int idx) override
338  {
340  const RegId& reg = si->destRegIdx(idx);
341  assert(reg.is(VecRegClass));
342  return thread->getWritableVecReg(reg);
343  }
344 
346  void
347  setVecRegOperand(const StaticInst *si, int idx,
348  const TheISA::VecRegContainer& val) override
349  {
351  const RegId& reg = si->destRegIdx(idx);
352  assert(reg.is(VecRegClass));
353  thread->setVecReg(reg, val);
354  }
355 
358  readVecElemOperand(const StaticInst *si, int idx) const override
359  {
361  const RegId& reg = si->srcRegIdx(idx);
362  assert(reg.is(VecElemClass));
363  return thread->readVecElem(reg);
364  }
365 
367  void
368  setVecElemOperand(const StaticInst *si, int idx,
369  const TheISA::VecElem val) override
370  {
372  const RegId& reg = si->destRegIdx(idx);
373  assert(reg.is(VecElemClass));
375  }
376 
378  readVecPredRegOperand(const StaticInst *si, int idx) const override
379  {
381  const RegId& reg = si->srcRegIdx(idx);
382  assert(reg.is(VecPredRegClass));
383  return thread->readVecPredReg(reg);
384  }
385 
387  getWritableVecPredRegOperand(const StaticInst *si, int idx) override
388  {
390  const RegId& reg = si->destRegIdx(idx);
391  assert(reg.is(VecPredRegClass));
393  }
394 
395  void
397  const TheISA::VecPredRegContainer& val) override
398  {
400  const RegId& reg = si->destRegIdx(idx);
401  assert(reg.is(VecPredRegClass));
403  }
404 
405  RegVal
406  readCCRegOperand(const StaticInst *si, int idx) override
407  {
409  const RegId& reg = si->srcRegIdx(idx);
410  assert(reg.is(CCRegClass));
411  return thread->readCCReg(reg.index());
412  }
413 
414  void
415  setCCRegOperand(const StaticInst *si, int idx, RegVal val) override
416  {
418  const RegId& reg = si->destRegIdx(idx);
419  assert(reg.is(CCRegClass));
420  thread->setCCReg(reg.index(), val);
421  }
422 
423  RegVal
424  readMiscRegOperand(const StaticInst *si, int idx) override
425  {
427  const RegId& reg = si->srcRegIdx(idx);
428  assert(reg.is(MiscRegClass));
429  return thread->readMiscReg(reg.index());
430  }
431 
432  void
433  setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override
434  {
436  const RegId& reg = si->destRegIdx(idx);
437  assert(reg.is(MiscRegClass));
438  thread->setMiscReg(reg.index(), val);
439  }
440 
445  RegVal
446  readMiscReg(int misc_reg) override
447  {
449  return thread->readMiscReg(misc_reg);
450  }
451 
456  void
457  setMiscReg(int misc_reg, RegVal val) override
458  {
460  thread->setMiscReg(misc_reg, val);
461  }
462 
464  pcState() const override
465  {
466  return thread->pcState();
467  }
468 
469  void
470  pcState(const TheISA::PCState &val) override
471  {
472  thread->pcState(val);
473  }
474 
475  Fault
476  readMem(Addr addr, uint8_t *data, unsigned int size,
477  Request::Flags flags,
478  const std::vector<bool>& byte_enable)
479  override
480  {
481  assert(byte_enable.size() == size);
482  return cpu->readMem(addr, data, size, flags, byte_enable);
483  }
484 
485  Fault
486  initiateMemRead(Addr addr, unsigned int size,
487  Request::Flags flags,
488  const std::vector<bool>& byte_enable)
489  override
490  {
491  assert(byte_enable.size() == size);
492  return cpu->initiateMemRead(addr, size, flags, byte_enable);
493  }
494 
495  Fault
496  writeMem(uint8_t *data, unsigned int size, Addr addr,
497  Request::Flags flags, uint64_t *res,
498  const std::vector<bool>& byte_enable)
499  override
500  {
501  assert(byte_enable.size() == size);
502  return cpu->writeMem(data, size, addr, flags, res,
503  byte_enable);
504  }
505 
506  Fault amoMem(Addr addr, uint8_t *data, unsigned int size,
507  Request::Flags flags, AtomicOpFunctorPtr amo_op) override
508  {
509  return cpu->amoMem(addr, data, size, flags, std::move(amo_op));
510  }
511 
512  Fault initiateMemAMO(Addr addr, unsigned int size,
513  Request::Flags flags,
514  AtomicOpFunctorPtr amo_op) override
515  {
516  return cpu->initiateMemAMO(addr, size, flags, std::move(amo_op));
517  }
518 
520  {
521  return cpu->initiateHtmCmd(flags);
522  }
523 
527  void
528  setStCondFailures(unsigned int sc_failures) override
529  {
530  thread->setStCondFailures(sc_failures);
531  }
532 
536  unsigned int
537  readStCondFailures() const override
538  {
539  return thread->readStCondFailures();
540  }
541 
543  ThreadContext *tcBase() const override { return thread->getTC(); }
544 
545  bool
546  readPredicate() const override
547  {
548  return thread->readPredicate();
549  }
550 
551  void
552  setPredicate(bool val) override
553  {
555 
556  if (cpu->traceData) {
558  }
559  }
560 
561  bool
562  readMemAccPredicate() const override
563  {
564  return thread->readMemAccPredicate();
565  }
566 
567  void
568  setMemAccPredicate(bool val) override
569  {
571  }
572 
573  uint64_t
574  getHtmTransactionUid() const override
575  {
576  return tcBase()->getHtmCheckpointPtr()->getHtmUid();
577  }
578 
579  uint64_t
580  newHtmTransactionUid() const override
581  {
582  return tcBase()->getHtmCheckpointPtr()->newHtmUid();
583  }
584 
585  bool
586  inHtmTransactionalState() const override
587  {
588  return (getHtmTransactionalDepth() > 0);
589  }
590 
591  uint64_t
592  getHtmTransactionalDepth() const override
593  {
596  }
597 
601  void
602  demapPage(Addr vaddr, uint64_t asn) override
603  {
604  thread->demapPage(vaddr, asn);
605  }
606 
607  void
608  armMonitor(Addr address) override
609  {
610  cpu->armMonitor(thread->threadId(), address);
611  }
612 
613  bool
614  mwait(PacketPtr pkt) override
615  {
616  return cpu->mwait(thread->threadId(), pkt);
617  }
618 
619  void
621  {
623  }
624 
626  getAddrMonitor() override
627  {
628  return cpu->getCpuAddrMonitor(thread->threadId());
629  }
630 };
631 
632 } // namespace gem5
633 
634 #endif // __CPU_EXEC_CONTEXT_HH__
gem5::statistics::Scalar
This is a simple scalar statistic, like a counter.
Definition: statistics.hh:1927
gem5::BaseSimpleCPU::initiateMemAMO
virtual Fault initiateMemAMO(Addr addr, unsigned size, Request::Flags flags, AtomicOpFunctorPtr amo_op)
Definition: base.hh:176
gem5::SimpleThread::readMiscReg
RegVal readMiscReg(RegIndex misc_reg) override
Definition: simple_thread.hh:452
gem5::SimpleExecContext::setMiscReg
void setMiscReg(int misc_reg, RegVal val) override
Sets a miscellaneous register, handling any architectural side effects due to writing that register.
Definition: exec_context.hh:457
gem5::SimpleThread::readIntReg
RegVal readIntReg(RegIndex reg_idx) const override
Definition: simple_thread.hh:274
gem5::SimpleExecContext::getWritableVecPredRegOperand
TheISA::VecPredRegContainer & getWritableVecPredRegOperand(const StaticInst *si, int idx) override
Gets destination predicate register operand for modification.
Definition: exec_context.hh:387
gem5::VecElemClass
@ VecElemClass
Vector Register Native Elem lane.
Definition: reg_class.hh:62
gem5::SimpleThread::readVecElem
const TheISA::VecElem & readVecElem(const RegId &reg) const override
Definition: simple_thread.hh:318
gem5::CCRegClass
@ CCRegClass
Condition-code register.
Definition: reg_class.hh:64
gem5::SimpleExecContext::numOp
Counter numOp
Definition: exec_context.hh:77
gem5::BaseCPU::armMonitor
void armMonitor(ThreadID tid, Addr address)
Definition: base.cc:205
gem5::SimpleExecContext::ExecContextStats::numIntRegWrites
statistics::Scalar numIntRegWrites
Definition: exec_context.hh:222
gem5::SimpleThread::htmTransactionStops
int64_t htmTransactionStops
Definition: simple_thread.hh:140
gem5::SimpleExecContext::lastDcacheStall
Counter lastDcacheStall
Definition: exec_context.hh:83
gem5::SimpleExecContext::setCCRegOperand
void setCCRegOperand(const StaticInst *si, int idx, RegVal val) override
Definition: exec_context.hh:415
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::SimpleThread::setIntReg
void setIntReg(RegIndex reg_idx, RegVal val) override
Definition: simple_thread.hh:367
gem5::BaseCPU::mwaitAtomic
void mwaitAtomic(ThreadID tid, ThreadContext *tc, BaseMMU *mmu)
Definition: base.cc:240
gem5::ArmISA::VecPredRegContainer
VecPredReg::Container VecPredRegContainer
Definition: vec.hh:68
gem5::SimpleThread::readVecReg
const TheISA::VecRegContainer & readVecReg(const RegId &reg) const override
Definition: simple_thread.hh:296
data
const char data[]
Definition: circlebuf.test.cc:48
gem5::SimpleExecContext::ExecContextStats::ExecContextStats
ExecContextStats(BaseSimpleCPU *cpu, SimpleThread *thread)
Definition: exec_context.hh:87
gem5::BaseSimpleCPU::traceData
Trace::InstRecord * traceData
Definition: base.hh:97
gem5::SimpleExecContext::readMemAccPredicate
bool readMemAccPredicate() const override
Definition: exec_context.hh:562
gem5::SimpleExecContext::ExecContextStats::icacheStallCycles
statistics::Scalar icacheStallCycles
Definition: exec_context.hh:256
gem5::SimpleExecContext::numLoad
Counter numLoad
Definition: exec_context.hh:79
gem5::SimpleExecContext::readFloatRegOperandBits
RegVal readFloatRegOperandBits(const StaticInst *si, int idx) override
Reads a floating point register in its binary format, instead of by value.
Definition: exec_context.hh:306
gem5::SimpleExecContext::ExecContextStats::numCallsReturns
statistics::Scalar numCallsReturns
Definition: exec_context.hh:206
gem5::SimpleExecContext::ExecContextStats::numVecPredRegWrites
statistics::Scalar numVecPredRegWrites
Definition: exec_context.hh:234
gem5::SimpleExecContext::readVecRegOperand
const TheISA::VecRegContainer & readVecRegOperand(const StaticInst *si, int idx) const override
Reads a vector register.
Definition: exec_context.hh:327
gem5::SimpleExecContext::ExecContextStats::numVecRegReads
statistics::Scalar numVecRegReads
Definition: exec_context.hh:229
gem5::statistics::nozero
const FlagsType nozero
Don't print if this is zero.
Definition: info.hh:68
gem5::FloatRegClass
@ FloatRegClass
Floating-point register.
Definition: reg_class.hh:58
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
gem5::BaseSimpleCPU::amoMem
virtual Fault amoMem(Addr addr, uint8_t *data, unsigned size, Request::Flags flags, AtomicOpFunctorPtr amo_op)
Definition: base.hh:169
gem5::SimpleThread::setMiscReg
void setMiscReg(RegIndex misc_reg, RegVal val) override
Definition: simple_thread.hh:464
gem5::SimpleExecContext::execContextStats
gem5::SimpleExecContext::ExecContextStats execContextStats
gem5::SimpleThread::setStCondFailures
void setStCondFailures(unsigned sc_failures) override
Definition: simple_thread.hh:490
gem5::SimpleExecContext::newHtmTransactionUid
uint64_t newHtmTransactionUid() const override
Definition: exec_context.hh:580
gem5::SimpleExecContext::readMiscReg
RegVal readMiscReg(int misc_reg) override
Reads a miscellaneous register, handling any architectural side effects due to reading that register.
Definition: exec_context.hh:446
gem5::statistics::DataWrapVec::subname
Derived & subname(off_type index, const std::string &name)
Set the subfield name for the given index, and marks this stat to print at the end of simulation.
Definition: statistics.hh:399
gem5::statistics::Average
A stat that calculates the per tick average of a value.
Definition: statistics.hh:1955
gem5::MiscRegClass
@ MiscRegClass
Control (misc) register.
Definition: reg_class.hh:65
gem5::SimpleExecContext::readCCRegOperand
RegVal readCCRegOperand(const StaticInst *si, int idx) override
Definition: exec_context.hh:406
gem5::SimpleExecContext::readStCondFailures
unsigned int readStCondFailures() const override
Returns the number of consecutive store conditional failures.
Definition: exec_context.hh:537
gem5::VecPredRegClass
@ VecPredRegClass
Definition: reg_class.hh:63
gem5::statistics::Vector
A vector of scalar stats.
Definition: statistics.hh:2003
gem5::SimpleThread::setVecReg
void setVecReg(const RegId &reg, const TheISA::VecRegContainer &val) override
Definition: simple_thread.hh:390
gem5::statistics::Formula
A formula for statistics that is calculated when printed.
Definition: statistics.hh:2536
std::vector< bool >
gem5::SimpleThread::readCCReg
RegVal readCCReg(RegIndex reg_idx) const override
Definition: simple_thread.hh:355
gem5::csprintf
std::string csprintf(const char *format, const Args &...args)
Definition: cprintf.hh:161
gem5::Trace::InstRecord::setPredicate
void setPredicate(bool val)
Definition: insttracer.hh:228
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
gem5::SimpleExecContext::pcState
TheISA::PCState pcState() const override
Definition: exec_context.hh:464
gem5::SimpleThread::htmTransactionStarts
int64_t htmTransactionStarts
Definition: simple_thread.hh:139
gem5::SimpleThread
The SimpleThread object provides a combination of the ThreadState object and the ThreadContext interf...
Definition: simple_thread.hh:94
gem5::SimpleExecContext::ExecContextStats::numPredictedBranches
statistics::Scalar numPredictedBranches
Number of branches predicted as taken.
Definition: exec_context.hh:265
request.hh
gem5::SimpleExecContext::ExecContextStats::numVecInsts
statistics::Scalar numVecInsts
Definition: exec_context.hh:218
gem5::SimpleExecContext::getHtmTransactionalDepth
uint64_t getHtmTransactionalDepth() const override
Definition: exec_context.hh:592
gem5::SimpleThread::setVecElem
void setVecElem(const RegId &reg, const TheISA::VecElem &val) override
Definition: simple_thread.hh:400
gem5::SimpleThread::setVecPredReg
void setVecPredReg(const RegId &reg, const TheISA::VecPredRegContainer &val) override
Definition: simple_thread.hh:410
gem5::statistics::dist
const FlagsType dist
Print the distribution.
Definition: info.hh:66
gem5::SimpleExecContext::setPredicate
void setPredicate(bool val) override
Definition: exec_context.hh:552
gem5::AddressMonitor
Definition: base.hh:73
gem5::statistics::constant
Temp constant(T val)
Definition: statistics.hh:2862
gem5::SimpleExecContext::amoMem
Fault amoMem(Addr addr, uint8_t *data, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op) override
For atomic-mode contexts, perform an atomic AMO (a.k.a., Atomic Read-Modify-Write Memory Operation)
Definition: exec_context.hh:506
gem5::statistics::pdf
const FlagsType pdf
Print the percent of the total that this entry represents.
Definition: info.hh:62
gem5::SimpleThread::readStCondFailures
unsigned readStCondFailures() const override
Definition: simple_thread.hh:475
gem5::BaseSimpleCPU::writeMem
virtual Fault writeMem(uint8_t *data, unsigned size, Addr addr, Request::Flags flags, uint64_t *res, const std::vector< bool > &byte_enable=std::vector< bool >())
Definition: base.hh:161
gem5::SimpleThread::mmu
BaseMMU * mmu
Definition: simple_thread.hh:134
gem5::SimpleExecContext::pcState
void pcState(const TheISA::PCState &val) override
Definition: exec_context.hh:470
gem5::SimpleExecContext::mwait
bool mwait(PacketPtr pkt) override
Definition: exec_context.hh:614
gem5::SimpleExecContext::ExecContextStats::numCCRegReads
statistics::Scalar numCCRegReads
Definition: exec_context.hh:237
gem5::SimpleExecContext::setStCondFailures
void setStCondFailures(unsigned int sc_failures) override
Sets the number of consecutive store conditional failures.
Definition: exec_context.hh:528
gem5::SimpleExecContext::setIntRegOperand
void setIntRegOperand(const StaticInst *si, int idx, RegVal val) override
Sets an integer register to a value.
Definition: exec_context.hh:295
gem5::SimpleThread::readMemAccPredicate
bool readMemAccPredicate()
Definition: simple_thread.hh:478
gem5::Flags< FlagsType >
gem5::BaseCPU::baseStats
gem5::BaseCPU::BaseCPUStats baseStats
gem5::SimpleExecContext::ExecContextStats::numIdleCycles
statistics::Formula numIdleCycles
Definition: exec_context.hh:246
gem5::SimpleExecContext::initiateHtmCmd
Fault initiateHtmCmd(Request::Flags flags) override
Initiate an HTM command, e.g.
Definition: exec_context.hh:519
gem5::BaseSimpleCPU::readMem
virtual Fault readMem(Addr addr, uint8_t *data, unsigned size, Request::Flags flags, const std::vector< bool > &byte_enable=std::vector< bool >())
Definition: base.hh:147
gem5::SimpleExecContext::demapPage
void demapPage(Addr vaddr, uint64_t asn) override
Invalidate a page in the DTLB and ITLB.
Definition: exec_context.hh:602
translation.hh
gem5::StaticInst
Base, ISA-independent static instruction class.
Definition: static_inst.hh:88
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::SimpleExecContext::ExecContextStats::numInsts
statistics::Scalar numInsts
Definition: exec_context.hh:193
gem5::SimpleExecContext::fetchOffset
Addr fetchOffset
Definition: exec_context.hh:67
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::SimpleThread::readPredicate
bool readPredicate() const
Definition: simple_thread.hh:442
gem5::SimpleExecContext::inHtmTransactionalState
bool inHtmTransactionalState() const override
Definition: exec_context.hh:586
ADD_STAT
#define ADD_STAT(n,...)
Convenience macro to add a stat to a statistics group.
Definition: group.hh:75
gem5::SimpleExecContext::ExecContextStats::numFpRegReads
statistics::Scalar numFpRegReads
Definition: exec_context.hh:225
gem5::SimpleExecContext::mwaitAtomic
void mwaitAtomic(ThreadContext *tc) override
Definition: exec_context.hh:620
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::SimpleExecContext::ExecContextStats::numCCRegWrites
statistics::Scalar numCCRegWrites
Definition: exec_context.hh:238
gem5::BaseCPU::BaseCPUStats::numCycles
statistics::Scalar numCycles
Definition: base.hh:597
gem5::MipsISA::PCState
GenericISA::DelaySlotPCState< 4 > PCState
Definition: pcstate.hh:40
gem5::SimpleExecContext::ExecContextStats::numCondCtrlInsts
statistics::Scalar numCondCtrlInsts
Definition: exec_context.hh:209
gem5::SimpleExecContext::stayAtPC
bool stayAtPC
Definition: exec_context.hh:70
gem5::SimpleExecContext::readPredicate
bool readPredicate() const override
Definition: exec_context.hh:546
gem5::SimpleThread::setMemAccPredicate
void setMemAccPredicate(bool val)
Definition: simple_thread.hh:484
gem5::SimpleExecContext::ExecContextStats::notIdleFraction
statistics::Average notIdleFraction
Definition: exec_context.hh:252
gem5::SimpleExecContext::cpu
BaseSimpleCPU * cpu
Definition: exec_context.hh:63
gem5::SimpleExecContext::writeMem
Fault writeMem(uint8_t *data, unsigned int size, Addr addr, Request::Flags flags, uint64_t *res, const std::vector< bool > &byte_enable) override
For atomic-mode contexts, perform an atomic memory write operation.
Definition: exec_context.hh:496
gem5::SimpleExecContext::getWritableVecRegOperand
TheISA::VecRegContainer & getWritableVecRegOperand(const StaticInst *si, int idx) override
Reads a vector register for modification.
Definition: exec_context.hh:337
gem5::SimpleExecContext::ExecContextStats::statExecutedInstType
statistics::Vector statExecutedInstType
Definition: exec_context.hh:271
gem5::SimpleThread::threadId
int threadId() const override
Definition: simple_thread.hh:204
gem5::SimpleExecContext::ExecContextStats::numBusyCycles
statistics::Formula numBusyCycles
Definition: exec_context.hh:249
gem5::SimpleExecContext::ExecContextStats::dcacheStallCycles
statistics::Scalar dcacheStallCycles
Definition: exec_context.hh:259
gem5::ArmISA::VecRegContainer
gem5::VecRegContainer< NumVecElemPerVecReg *sizeof(VecElem)> VecRegContainer
Definition: vec.hh:62
gem5::BaseSimpleCPU
Definition: base.hh:80
gem5::SimpleExecContext::numInst
Counter numInst
PER-THREAD STATS.
Definition: exec_context.hh:76
gem5::SimpleThread::pcState
TheISA::PCState pcState() const override
Definition: simple_thread.hh:430
gem5::ThreadContext::getHtmCheckpointPtr
virtual BaseHTMCheckpointPtr & getHtmCheckpointPtr()=0
gem5::SimpleExecContext::readIntRegOperand
RegVal readIntRegOperand(const StaticInst *si, int idx) override
Reads an integer register.
Definition: exec_context.hh:285
gem5::SimpleExecContext::setVecPredRegOperand
void setVecPredRegOperand(const StaticInst *si, int idx, const TheISA::VecPredRegContainer &val) override
Sets a destination predicate register operand to a value.
Definition: exec_context.hh:396
gem5::SimpleExecContext::readVecPredRegOperand
const TheISA::VecPredRegContainer & readVecPredRegOperand(const StaticInst *si, int idx) const override
Predicate registers interface.
Definition: exec_context.hh:378
gem5::ArmISA::si
Bitfield< 6 > si
Definition: misc_types.hh:772
gem5::BaseCPU::getCpuAddrMonitor
AddressMonitor * getCpuAddrMonitor(ThreadID tid)
Definition: base.hh:609
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::SimpleThread::setFloatReg
void setFloatReg(RegIndex reg_idx, RegVal val) override
Definition: simple_thread.hh:377
gem5::SimpleExecContext::ExecContextStats::idleFraction
statistics::Formula idleFraction
Definition: exec_context.hh:253
gem5::SimpleExecContext::lastIcacheStall
Counter lastIcacheStall
Definition: exec_context.hh:81
gem5::SimpleExecContext::ExecContextStats::numFpInsts
statistics::Scalar numFpInsts
Definition: exec_context.hh:215
gem5::SimpleExecContext::setFloatRegOperandBits
void setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) override
Sets the bits of a floating point register of single width to a binary value.
Definition: exec_context.hh:317
gem5::SimpleThread::readFloatReg
RegVal readFloatReg(RegIndex reg_idx) const override
Definition: simple_thread.hh:285
gem5::SimpleExecContext::ExecContextStats::numVecAluAccesses
statistics::Scalar numVecAluAccesses
Definition: exec_context.hh:203
gem5::SimpleExecContext::setMiscRegOperand
void setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override
Definition: exec_context.hh:433
gem5::SimpleExecContext::ExecContextStats::numStoreInsts
statistics::Scalar numStoreInsts
Definition: exec_context.hh:243
gem5::SimpleExecContext::predPC
TheISA::PCState predPC
Definition: exec_context.hh:73
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::SimpleExecContext::initiateMemRead
Fault initiateMemRead(Addr addr, unsigned int size, Request::Flags flags, const std::vector< bool > &byte_enable) override
Initiate a timing memory read operation.
Definition: exec_context.hh:486
gem5::SimpleExecContext::thread
SimpleThread * thread
Definition: exec_context.hh:64
gem5::SimpleThread::getTC
ThreadContext * getTC()
Returns the pointer to this SimpleThread's ThreadContext.
Definition: simple_thread.hh:169
gem5::SimpleThread::getWritableVecPredReg
TheISA::VecPredRegContainer & getWritableVecPredReg(const RegId &reg) override
Definition: simple_thread.hh:342
base.hh
gem5::SimpleExecContext::ExecContextStats::numLoadInsts
statistics::Scalar numLoadInsts
Definition: exec_context.hh:242
gem5::VecRegClass
@ VecRegClass
Vector Register.
Definition: reg_class.hh:60
gem5::SimpleExecContext::setVecElemOperand
void setVecElemOperand(const StaticInst *si, int idx, const TheISA::VecElem val) override
Sets an element of a vector register to a value.
Definition: exec_context.hh:368
gem5::SimpleThread::getWritableVecReg
TheISA::VecRegContainer & getWritableVecReg(const RegId &reg) override
Definition: simple_thread.hh:307
gem5::SimpleThread::readVecPredReg
const TheISA::VecPredRegContainer & readVecPredReg(const RegId &reg) const override
Definition: simple_thread.hh:330
gem5::SimpleExecContext::ExecContextStats::numIntInsts
statistics::Scalar numIntInsts
Definition: exec_context.hh:212
gem5::SimpleExecContext::ExecContextStats::numIntAluAccesses
statistics::Scalar numIntAluAccesses
Definition: exec_context.hh:197
gem5::SimpleExecContext::setMemAccPredicate
void setMemAccPredicate(bool val) override
Definition: exec_context.hh:568
base.hh
gem5::SimpleExecContext
Definition: exec_context.hh:60
gem5::statistics::DataWrap::prereq
Derived & prereq(const Stat &prereq)
Set the prerequisite stat and marks this stat to print at the end of simulation.
Definition: statistics.hh:369
gem5::ArmISA::VecElem
uint32_t VecElem
Definition: vec.hh:60
types.hh
gem5::BaseSimpleCPU::initiateMemRead
virtual Fault initiateMemRead(Addr addr, unsigned size, Request::Flags flags, const std::vector< bool > &byte_enable=std::vector< bool >())
Definition: base.hh:154
gem5::SimpleExecContext::initiateMemAMO
Fault initiateMemAMO(Addr addr, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op) override
For timing-mode contexts, initiate an atomic AMO (atomic read-modify-write memory operation)
Definition: exec_context.hh:512
gem5::SimpleThread::demapPage
void demapPage(Addr vaddr, uint64_t asn)
Definition: simple_thread.hh:172
gem5::SimpleExecContext::ExecContextStats
Definition: exec_context.hh:85
static_inst_fwd.hh
gem5::SimpleExecContext::getAddrMonitor
AddressMonitor * getAddrMonitor() override
Definition: exec_context.hh:626
exec_context.hh
reg_class.hh
gem5::statistics::Counter
double Counter
All counters are of 64-bit values.
Definition: types.hh:47
gem5::SimpleExecContext::tcBase
ThreadContext * tcBase() const override
Returns a pointer to the ThreadContext.
Definition: exec_context.hh:543
gem5::SimpleExecContext::ExecContextStats::numFpAluAccesses
statistics::Scalar numFpAluAccesses
Definition: exec_context.hh:200
gem5::SimpleExecContext::readMiscRegOperand
RegVal readMiscRegOperand(const StaticInst *si, int idx) override
Definition: exec_context.hh:424
gem5::statistics::Group
Statistics container.
Definition: group.hh:93
gem5::SimpleExecContext::ExecContextStats::numVecRegWrites
statistics::Scalar numVecRegWrites
Definition: exec_context.hh:230
gem5::ExecContext
The ExecContext is an abstract base class the provides the interface used by the ISA to manipulate th...
Definition: exec_context.hh:73
gem5::SimpleExecContext::ExecContextStats::numIntRegReads
statistics::Scalar numIntRegReads
Definition: exec_context.hh:221
gem5::SimpleExecContext::ExecContextStats::numBranches
statistics::Scalar numBranches
Definition: exec_context.hh:263
gem5::SimpleExecContext::ExecContextStats::numOps
statistics::Scalar numOps
Definition: exec_context.hh:194
gem5::SimpleExecContext::ExecContextStats::numFpRegWrites
statistics::Scalar numFpRegWrites
Definition: exec_context.hh:226
gem5::Num_OpClasses
static const OpClass Num_OpClasses
Definition: op_class.hh:108
gem5::SimpleExecContext::armMonitor
void armMonitor(Addr address) override
Definition: exec_context.hh:608
gem5::statistics::DataWrap::flags
Derived & flags(Flags _flags)
Set the flags and marks this stat to print at the end of simulation.
Definition: statistics.hh:355
gem5::BaseCPU::mwait
bool mwait(ThreadID tid, PacketPtr pkt)
Definition: base.cc:217
gem5::SimpleExecContext::readMem
Fault readMem(Addr addr, uint8_t *data, unsigned int size, Request::Flags flags, const std::vector< bool > &byte_enable) override
Perform an atomic memory read operation.
Definition: exec_context.hh:476
gem5::MipsISA::vaddr
vaddr
Definition: pra_constants.hh:278
gem5::SimpleExecContext::ExecContextStats::numBranchMispred
statistics::Scalar numBranchMispred
Number of misprediced branches.
Definition: exec_context.hh:267
gem5::AtomicOpFunctorPtr
std::unique_ptr< AtomicOpFunctor > AtomicOpFunctorPtr
Definition: amo.hh:242
gem5::IntRegClass
@ IntRegClass
Integer register.
Definition: reg_class.hh:57
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::statistics::total
const FlagsType total
Print the total.
Definition: info.hh:60
gem5::statistics::VectorBase::init
Derived & init(size_type size)
Set this vector to have the given size.
Definition: statistics.hh:1037
gem5::SimpleExecContext::readVecElemOperand
TheISA::VecElem readVecElemOperand(const StaticInst *si, int idx) const override
Reads an element of a vector register.
Definition: exec_context.hh:358
gem5::SimpleExecContext::getHtmTransactionUid
uint64_t getHtmTransactionUid() const override
Definition: exec_context.hh:574
gem5::SimpleExecContext::ExecContextStats::numVecPredRegReads
statistics::Scalar numVecPredRegReads
Definition: exec_context.hh:233
gem5::SimpleExecContext::setVecRegOperand
void setVecRegOperand(const StaticInst *si, int idx, const TheISA::VecRegContainer &val) override
Sets a vector register to a value.
Definition: exec_context.hh:347
gem5::BaseSimpleCPU::initiateHtmCmd
virtual Fault initiateHtmCmd(Request::Flags flags)=0
Hardware transactional memory commands (HtmCmds), e.g.
gem5::SimpleThread::setPredicate
void setPredicate(bool val)
Definition: simple_thread.hh:443
gem5::SimpleExecContext::ExecContextStats::numMemRefs
statistics::Scalar numMemRefs
Definition: exec_context.hh:241
gem5::SimpleExecContext::SimpleExecContext
SimpleExecContext(BaseSimpleCPU *_cpu, SimpleThread *_thread)
Constructor.
Definition: exec_context.hh:277
gem5::SimpleThread::setCCReg
void setCCReg(RegIndex reg_idx, RegVal val) override
Definition: simple_thread.hh:421
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:88
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84

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