41 #ifndef __CPU_SIMPLE_EXEC_CONTEXT_HH__
42 #define __CPU_SIMPLE_EXEC_CONTEXT_HH__
88 thread->threadId()).c_str()),
90 "Number of instructions committed"),
92 "Number of ops (including micro ops) committed"),
94 "Number of integer alu accesses"),
96 "Number of float alu accesses"),
98 "Number of vector alu accesses"),
100 "Number of times a function call or return occured"),
102 "Number of instructions that are conditional controls"),
104 "Number of integer instructions"),
106 "Number of float instructions"),
108 "Number of vector instructions"),
110 "Number of times the integer registers were read"),
112 "Number of times the integer registers were written"),
114 "Number of times the floating registers were read"),
116 "Number of times the floating registers were written"),
118 "Number of times the vector registers were read"),
120 "Number of times the vector registers were written"),
122 "Number of times the predicate registers were read"),
124 "Number of times the predicate registers were written"),
126 "Number of times the CC registers were read"),
128 "Number of times the CC registers were written"),
130 "Number of times the Misc registers were read"),
132 "Number of times the Misc registers were written"),
134 "Number of memory refs"),
136 "Number of load instructions"),
138 "Number of store instructions"),
140 "Number of idle cycles"),
142 "Number of busy cycles"),
144 "Percentage of non-idle cycles"),
146 "Percentage of idle cycles"),
148 "ICache total stall cycles"),
150 "DCache total stall cycles"),
152 "Number of branches fetched"),
154 "Number of branches predicted as taken"),
156 "Number of branch mispredictions"),
158 "Class of executed instruction."),
189 .
init(enums::Num_OpClass)
410 assert(byte_enable.size() == size);
420 assert(byte_enable.size() == size);
430 assert(byte_enable.size() == size);
Defines global host-dependent types: Counter, Tick, and (indirectly) {int,uint}{8,...
AddressMonitor * getCpuAddrMonitor(ThreadID tid)
void mwaitAtomic(ThreadID tid, ThreadContext *tc, BaseMMU *mmu)
bool mwait(ThreadID tid, PacketPtr pkt)
gem5::BaseCPU::BaseCPUStats baseStats
void armMonitor(ThreadID tid, Addr address)
virtual Fault initiateMemRead(Addr addr, unsigned size, Request::Flags flags, const std::vector< bool > &byte_enable=std::vector< bool >())
virtual Fault readMem(Addr addr, uint8_t *data, unsigned size, Request::Flags flags, const std::vector< bool > &byte_enable=std::vector< bool >())
virtual Fault initiateMemMgmtCmd(Request::Flags flags)=0
Memory management commands such as hardware transactional memory commands or TLB invalidation command...
virtual Fault writeMem(uint8_t *data, unsigned size, Addr addr, Request::Flags flags, uint64_t *res, const std::vector< bool > &byte_enable=std::vector< bool >())
virtual Fault amoMem(Addr addr, uint8_t *data, unsigned size, Request::Flags flags, AtomicOpFunctorPtr amo_op)
virtual Fault initiateMemAMO(Addr addr, unsigned size, Request::Flags flags, AtomicOpFunctorPtr amo_op)
trace::InstRecord * traceData
The ExecContext is an abstract base class the provides the interface used by the ISA to manipulate th...
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Register ID: describe an architectural register with its class and index.
Fault initiateMemRead(Addr addr, unsigned int size, Request::Flags flags, const std::vector< bool > &byte_enable) override
Initiate a timing memory read operation.
Fault readMem(Addr addr, uint8_t *data, unsigned int size, Request::Flags flags, const std::vector< bool > &byte_enable) override
Perform an atomic memory read operation.
void setStCondFailures(unsigned int sc_failures) override
Sets the number of consecutive store conditional failures.
unsigned int readStCondFailures() const override
Returns the number of consecutive store conditional failures.
bool readPredicate() const override
uint64_t getHtmTransactionalDepth() const override
ThreadContext * tcBase() const override
Returns a pointer to the ThreadContext.
void demapPage(Addr vaddr, uint64_t asn) override
Invalidate a page in the DTLB and ITLB.
void mwaitAtomic(ThreadContext *tc) override
void * getWritableRegOperand(const StaticInst *si, int idx) override
Counter numInst
PER-THREAD STATS.
void setMemAccPredicate(bool val) override
void getRegOperand(const StaticInst *si, int idx, void *val) override
void setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override
RegVal getRegOperand(const StaticInst *si, int idx) override
RegVal readMiscReg(int misc_reg) override
Reads a miscellaneous register, handling any architectural side effects due to reading that register.
void setPredicate(bool val) override
SimpleExecContext(BaseSimpleCPU *_cpu, SimpleThread *_thread)
Constructor.
void setRegOperand(const StaticInst *si, int idx, RegVal val) override
std::unique_ptr< PCStateBase > predPC
Fault initiateMemAMO(Addr addr, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op) override
For timing-mode contexts, initiate an atomic AMO (atomic read-modify-write memory operation)
bool readMemAccPredicate() const override
const PCStateBase & pcState() const override
uint64_t newHtmTransactionUid() const override
void setRegOperand(const StaticInst *si, int idx, const void *val) override
bool inHtmTransactionalState() const override
Fault writeMem(uint8_t *data, unsigned int size, Addr addr, Request::Flags flags, uint64_t *res, const std::vector< bool > &byte_enable) override
For atomic-mode contexts, perform an atomic memory write operation.
bool mwait(PacketPtr pkt) override
AddressMonitor * getAddrMonitor() override
void setMiscReg(int misc_reg, RegVal val) override
Sets a miscellaneous register, handling any architectural side effects due to writing that register.
Fault initiateMemMgmtCmd(Request::Flags flags) override
Initiate a memory management command with no valid address.
void pcState(const PCStateBase &val) override
gem5::SimpleExecContext::ExecContextStats execContextStats
Fault amoMem(Addr addr, uint8_t *data, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op) override
For atomic-mode contexts, perform an atomic AMO (a.k.a., Atomic Read-Modify-Write Memory Operation)
RegVal readMiscRegOperand(const StaticInst *si, int idx) override
uint64_t getHtmTransactionUid() const override
void armMonitor(Addr address) override
The SimpleThread object provides a combination of the ThreadState object and the ThreadContext interf...
int threadId() const override
ThreadContext * getTC()
Returns the pointer to this SimpleThread's ThreadContext.
bool readPredicate() const
void setPredicate(bool val)
const PCStateBase & pcState() const override
int64_t htmTransactionStops
bool readMemAccPredicate()
void setStCondFailures(unsigned sc_failures) override
void setMiscReg(RegIndex misc_reg, RegVal val) override
void demapPage(Addr vaddr, uint64_t asn)
void * getWritableReg(const RegId &arch_reg) override
unsigned readStCondFailures() const override
void setReg(const RegId &arch_reg, RegVal val) override
int64_t htmTransactionStarts
RegVal readMiscReg(RegIndex misc_reg) override
void setMemAccPredicate(bool val)
RegVal getReg(const RegId &arch_reg) const override
Base, ISA-independent static instruction class.
ThreadContext is the external interface to all thread state for anything outside of the CPU.
virtual BaseHTMCheckpointPtr & getHtmCheckpointPtr()=0
A stat that calculates the per tick average of a value.
Derived & subname(off_type index, const std::string &name)
Set the subfield name for the given index, and marks this stat to print at the end of simulation.
Derived & flags(Flags _flags)
Set the flags and marks this stat to print at the end of simulation.
Derived & prereq(const Stat &prereq)
Set the prerequisite stat and marks this stat to print at the end of simulation.
This is a simple scalar statistic, like a counter.
Derived & init(size_type size)
Set this vector to have the given size.
A vector of scalar stats.
void setPredicate(bool val)
#define ADD_STAT(n,...)
Convenience macro to add a stat to a statistics group.
std::unique_ptr< AtomicOpFunctor > AtomicOpFunctorPtr
const FlagsType pdf
Print the percent of the total that this entry represents.
const FlagsType nozero
Don't print if this is zero.
const FlagsType total
Print the total.
double Counter
All counters are of 64-bit values.
const FlagsType dist
Print the distribution.
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
std::shared_ptr< FaultBase > Fault
static const OpClass Num_OpClasses
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
std::string csprintf(const char *format, const Args &...args)
@ MiscRegClass
Control (misc) register.
Declaration of a request, the overall memory request consisting of the parts of the request that are ...
statistics::Scalar numCycles
statistics::Scalar numVecRegReads
statistics::Formula idleFraction
statistics::Scalar numLoadInsts
statistics::Scalar numIntRegWrites
statistics::Scalar numBranches
statistics::Scalar numOps
statistics::Scalar numCondCtrlInsts
statistics::Scalar numFpRegReads
statistics::Scalar numIntInsts
statistics::Scalar numIntRegReads
statistics::Formula numBusyCycles
statistics::Scalar numIntAluAccesses
statistics::Vector statExecutedInstType
statistics::Scalar numMiscRegReads
statistics::Scalar numStoreInsts
statistics::Scalar numVecPredRegReads
std::array< statistics::Scalar *, CCRegClass+1 > numRegReads
statistics::Scalar numCCRegWrites
statistics::Scalar numBranchMispred
Number of misprediced branches.
statistics::Scalar numCallsReturns
statistics::Scalar numVecAluAccesses
statistics::Scalar dcacheStallCycles
statistics::Scalar numMemRefs
statistics::Formula numIdleCycles
statistics::Scalar numPredictedBranches
Number of branches predicted as taken.
statistics::Scalar numFpRegWrites
statistics::Scalar numInsts
statistics::Scalar numVecRegWrites
statistics::Scalar icacheStallCycles
statistics::Scalar numVecInsts
std::array< statistics::Scalar *, CCRegClass+1 > numRegWrites
statistics::Scalar numCCRegReads
statistics::Scalar numMiscRegWrites
ExecContextStats(BaseSimpleCPU *cpu, SimpleThread *thread)
statistics::Scalar numFpAluAccesses
statistics::Average notIdleFraction
statistics::Scalar numVecPredRegWrites
statistics::Scalar numFpInsts