gem5  v21.2.1.1
exec_context.hh
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2014-2018, 2020-2021 Arm Limited
3  * All rights reserved
4  *
5  * The license below extends only to copyright in the software and shall
6  * not be construed as granting a license to any other intellectual
7  * property including but not limited to intellectual property relating
8  * to a hardware implementation of the functionality of the software
9  * licensed hereunder. You may use the software subject to the license
10  * terms below provided that you ensure that this notice is replicated
11  * unmodified and in its entirety in all distributions of the software,
12  * modified or unmodified, in source code or in binary form.
13  *
14  * Copyright (c) 2002-2005 The Regents of The University of Michigan
15  * All rights reserved.
16  *
17  * Redistribution and use in source and binary forms, with or without
18  * modification, are permitted provided that the following conditions are
19  * met: redistributions of source code must retain the above copyright
20  * notice, this list of conditions and the following disclaimer;
21  * redistributions in binary form must reproduce the above copyright
22  * notice, this list of conditions and the following disclaimer in the
23  * documentation and/or other materials provided with the distribution;
24  * neither the name of the copyright holders nor the names of its
25  * contributors may be used to endorse or promote products derived from
26  * this software without specific prior written permission.
27  *
28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39  */
40 
41 #ifndef __CPU_SIMPLE_EXEC_CONTEXT_HH__
42 #define __CPU_SIMPLE_EXEC_CONTEXT_HH__
43 
44 #include "arch/vecregs.hh"
45 #include "base/types.hh"
46 #include "config/the_isa.hh"
47 #include "cpu/base.hh"
48 #include "cpu/exec_context.hh"
49 #include "cpu/reg_class.hh"
50 #include "cpu/simple/base.hh"
51 #include "cpu/static_inst_fwd.hh"
52 #include "cpu/translation.hh"
53 #include "mem/request.hh"
54 
55 namespace gem5
56 {
57 
58 class BaseSimpleCPU;
59 
61 {
62  public:
65 
66  // This is the offset from the current pc that fetch should be performed
68  // This flag says to stay at the current pc. This is useful for
69  // instructions which go beyond MachInst boundaries.
70  bool stayAtPC;
71 
72  // Branch prediction
73  std::unique_ptr<PCStateBase> predPC;
74 
78  // Number of simulated loads
80  // Number of cycles stalled for I-cache responses
82  // Number of cycles stalled for D-cache responses
84 
86  {
88  : statistics::Group(cpu,
89  csprintf("exec_context.thread_%i",
90  thread->threadId()).c_str()),
91  ADD_STAT(numInsts, statistics::units::Count::get(),
92  "Number of instructions committed"),
93  ADD_STAT(numOps, statistics::units::Count::get(),
94  "Number of ops (including micro ops) committed"),
95  ADD_STAT(numIntAluAccesses, statistics::units::Count::get(),
96  "Number of integer alu accesses"),
97  ADD_STAT(numFpAluAccesses, statistics::units::Count::get(),
98  "Number of float alu accesses"),
99  ADD_STAT(numVecAluAccesses, statistics::units::Count::get(),
100  "Number of vector alu accesses"),
101  ADD_STAT(numCallsReturns, statistics::units::Count::get(),
102  "Number of times a function call or return occured"),
103  ADD_STAT(numCondCtrlInsts, statistics::units::Count::get(),
104  "Number of instructions that are conditional controls"),
105  ADD_STAT(numIntInsts, statistics::units::Count::get(),
106  "Number of integer instructions"),
107  ADD_STAT(numFpInsts, statistics::units::Count::get(),
108  "Number of float instructions"),
109  ADD_STAT(numVecInsts, statistics::units::Count::get(),
110  "Number of vector instructions"),
111  ADD_STAT(numIntRegReads, statistics::units::Count::get(),
112  "Number of times the integer registers were read"),
113  ADD_STAT(numIntRegWrites, statistics::units::Count::get(),
114  "Number of times the integer registers were written"),
115  ADD_STAT(numFpRegReads, statistics::units::Count::get(),
116  "Number of times the floating registers were read"),
117  ADD_STAT(numFpRegWrites, statistics::units::Count::get(),
118  "Number of times the floating registers were written"),
119  ADD_STAT(numVecRegReads, statistics::units::Count::get(),
120  "Number of times the vector registers were read"),
121  ADD_STAT(numVecRegWrites, statistics::units::Count::get(),
122  "Number of times the vector registers were written"),
123  ADD_STAT(numVecPredRegReads, statistics::units::Count::get(),
124  "Number of times the predicate registers were read"),
125  ADD_STAT(numVecPredRegWrites, statistics::units::Count::get(),
126  "Number of times the predicate registers were written"),
127  ADD_STAT(numCCRegReads, statistics::units::Count::get(),
128  "Number of times the CC registers were read"),
129  ADD_STAT(numCCRegWrites, statistics::units::Count::get(),
130  "Number of times the CC registers were written"),
131  ADD_STAT(numMiscRegReads, statistics::units::Count::get(),
132  "Number of times the Misc registers were read"),
133  ADD_STAT(numMiscRegWrites, statistics::units::Count::get(),
134  "Number of times the Misc registers were written"),
135  ADD_STAT(numMemRefs, statistics::units::Count::get(),
136  "Number of memory refs"),
137  ADD_STAT(numLoadInsts, statistics::units::Count::get(),
138  "Number of load instructions"),
139  ADD_STAT(numStoreInsts, statistics::units::Count::get(),
140  "Number of store instructions"),
141  ADD_STAT(numIdleCycles, statistics::units::Cycle::get(),
142  "Number of idle cycles"),
143  ADD_STAT(numBusyCycles, statistics::units::Cycle::get(),
144  "Number of busy cycles"),
145  ADD_STAT(notIdleFraction, statistics::units::Ratio::get(),
146  "Percentage of non-idle cycles"),
147  ADD_STAT(idleFraction, statistics::units::Ratio::get(),
148  "Percentage of idle cycles"),
149  ADD_STAT(icacheStallCycles, statistics::units::Cycle::get(),
150  "ICache total stall cycles"),
151  ADD_STAT(dcacheStallCycles, statistics::units::Cycle::get(),
152  "DCache total stall cycles"),
153  ADD_STAT(numBranches, statistics::units::Count::get(),
154  "Number of branches fetched"),
155  ADD_STAT(numPredictedBranches, statistics::units::Count::get(),
156  "Number of branches predicted as taken"),
157  ADD_STAT(numBranchMispred, statistics::units::Count::get(),
158  "Number of branch mispredictions"),
159  ADD_STAT(statExecutedInstType, statistics::units::Count::get(),
160  "Class of executed instruction.")
161  {
164 
167 
170 
173 
175  .init(enums::Num_OpClass)
177 
178  for (unsigned i = 0; i < Num_OpClasses; ++i) {
179  statExecutedInstType.subname(i, enums::OpClassStrings[i]);
180  }
181 
183  numIdleCycles = idleFraction * cpu->baseStats.numCycles;
184  numBusyCycles = notIdleFraction * cpu->baseStats.numCycles;
185 
188 
191 
194  }
195 
196  // Number of simulated instructions
199 
200  // Number of integer alu accesses
202 
203  // Number of float alu accesses
205 
206  // Number of vector alu accesses
208 
209  // Number of function calls/returns
211 
212  // Conditional control instructions;
214 
215  // Number of int instructions
217 
218  // Number of float instructions
220 
221  // Number of vector instructions
223 
224  // Number of integer register file accesses
227 
228  // Number of float register file accesses
231 
232  // Number of vector register file accesses
235 
236  // Number of predicate register file accesses
239 
240  // Number of condition code register file accesses
243 
244  // Number of misc register file accesses
247 
248  // Number of simulated memory references
252 
253  // Number of idle cycles
255 
256  // Number of busy cycles
258 
259  // Number of idle cycles
262 
263  // Number of cycles stalled for I-cache responses
265 
266  // Number of cycles stalled for D-cache responses
268 
277 
278  // Instruction mix histogram by OpClass
280 
282 
283  public:
286  : cpu(_cpu), thread(_thread), fetchOffset(0), stayAtPC(false),
287  numInst(0), numOp(0), numLoad(0), lastIcacheStall(0),
289  { }
290 
292  RegVal
293  readIntRegOperand(const StaticInst *si, int idx) override
294  {
296  const RegId& reg = si->srcRegIdx(idx);
297  assert(reg.is(IntRegClass));
298  return thread->readIntReg(reg.index());
299  }
300 
302  void
303  setIntRegOperand(const StaticInst *si, int idx, RegVal val) override
304  {
306  const RegId& reg = si->destRegIdx(idx);
307  assert(reg.is(IntRegClass));
308  thread->setIntReg(reg.index(), val);
309  }
310 
313  RegVal
314  readFloatRegOperandBits(const StaticInst *si, int idx) override
315  {
317  const RegId& reg = si->srcRegIdx(idx);
318  assert(reg.is(FloatRegClass));
319  return thread->readFloatReg(reg.index());
320  }
321 
324  void
325  setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) override
326  {
328  const RegId& reg = si->destRegIdx(idx);
329  assert(reg.is(FloatRegClass));
330  thread->setFloatReg(reg.index(), val);
331  }
332 
335  readVecRegOperand(const StaticInst *si, int idx) const override
336  {
338  const RegId& reg = si->srcRegIdx(idx);
339  assert(reg.is(VecRegClass));
340  return thread->readVecReg(reg);
341  }
342 
345  getWritableVecRegOperand(const StaticInst *si, int idx) override
346  {
348  const RegId& reg = si->destRegIdx(idx);
349  assert(reg.is(VecRegClass));
350  return thread->getWritableVecReg(reg);
351  }
352 
354  void
355  setVecRegOperand(const StaticInst *si, int idx,
356  const TheISA::VecRegContainer& val) override
357  {
359  const RegId& reg = si->destRegIdx(idx);
360  assert(reg.is(VecRegClass));
361  thread->setVecReg(reg, val);
362  }
363 
365  RegVal
366  readVecElemOperand(const StaticInst *si, int idx) const override
367  {
369  const RegId& reg = si->srcRegIdx(idx);
370  assert(reg.is(VecElemClass));
371  return thread->readVecElem(reg);
372  }
373 
375  void
376  setVecElemOperand(const StaticInst *si, int idx, RegVal val) override
377  {
379  const RegId& reg = si->destRegIdx(idx);
380  assert(reg.is(VecElemClass));
382  }
383 
385  readVecPredRegOperand(const StaticInst *si, int idx) const override
386  {
388  const RegId& reg = si->srcRegIdx(idx);
389  assert(reg.is(VecPredRegClass));
390  return thread->readVecPredReg(reg);
391  }
392 
394  getWritableVecPredRegOperand(const StaticInst *si, int idx) override
395  {
397  const RegId& reg = si->destRegIdx(idx);
398  assert(reg.is(VecPredRegClass));
400  }
401 
402  void
404  const TheISA::VecPredRegContainer& val) override
405  {
407  const RegId& reg = si->destRegIdx(idx);
408  assert(reg.is(VecPredRegClass));
410  }
411 
412  RegVal
413  readCCRegOperand(const StaticInst *si, int idx) override
414  {
416  const RegId& reg = si->srcRegIdx(idx);
417  assert(reg.is(CCRegClass));
418  return thread->readCCReg(reg.index());
419  }
420 
421  void
422  setCCRegOperand(const StaticInst *si, int idx, RegVal val) override
423  {
425  const RegId& reg = si->destRegIdx(idx);
426  assert(reg.is(CCRegClass));
427  thread->setCCReg(reg.index(), val);
428  }
429 
430  RegVal
431  readMiscRegOperand(const StaticInst *si, int idx) override
432  {
434  const RegId& reg = si->srcRegIdx(idx);
435  assert(reg.is(MiscRegClass));
436  return thread->readMiscReg(reg.index());
437  }
438 
439  void
440  setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override
441  {
443  const RegId& reg = si->destRegIdx(idx);
444  assert(reg.is(MiscRegClass));
445  thread->setMiscReg(reg.index(), val);
446  }
447 
452  RegVal
453  readMiscReg(int misc_reg) override
454  {
456  return thread->readMiscReg(misc_reg);
457  }
458 
463  void
464  setMiscReg(int misc_reg, RegVal val) override
465  {
467  thread->setMiscReg(misc_reg, val);
468  }
469 
470  const PCStateBase &
471  pcState() const override
472  {
473  return thread->pcState();
474  }
475 
476  void
477  pcState(const PCStateBase &val) override
478  {
479  thread->pcState(val);
480  }
481 
482  Fault
483  readMem(Addr addr, uint8_t *data, unsigned int size,
484  Request::Flags flags,
485  const std::vector<bool>& byte_enable)
486  override
487  {
488  assert(byte_enable.size() == size);
489  return cpu->readMem(addr, data, size, flags, byte_enable);
490  }
491 
492  Fault
493  initiateMemRead(Addr addr, unsigned int size,
494  Request::Flags flags,
495  const std::vector<bool>& byte_enable)
496  override
497  {
498  assert(byte_enable.size() == size);
499  return cpu->initiateMemRead(addr, size, flags, byte_enable);
500  }
501 
502  Fault
503  writeMem(uint8_t *data, unsigned int size, Addr addr,
504  Request::Flags flags, uint64_t *res,
505  const std::vector<bool>& byte_enable)
506  override
507  {
508  assert(byte_enable.size() == size);
509  return cpu->writeMem(data, size, addr, flags, res,
510  byte_enable);
511  }
512 
513  Fault amoMem(Addr addr, uint8_t *data, unsigned int size,
514  Request::Flags flags, AtomicOpFunctorPtr amo_op) override
515  {
516  return cpu->amoMem(addr, data, size, flags, std::move(amo_op));
517  }
518 
519  Fault initiateMemAMO(Addr addr, unsigned int size,
520  Request::Flags flags,
521  AtomicOpFunctorPtr amo_op) override
522  {
523  return cpu->initiateMemAMO(addr, size, flags, std::move(amo_op));
524  }
525 
527  {
528  return cpu->initiateHtmCmd(flags);
529  }
530 
534  void
535  setStCondFailures(unsigned int sc_failures) override
536  {
537  thread->setStCondFailures(sc_failures);
538  }
539 
543  unsigned int
544  readStCondFailures() const override
545  {
546  return thread->readStCondFailures();
547  }
548 
550  ThreadContext *tcBase() const override { return thread->getTC(); }
551 
552  bool
553  readPredicate() const override
554  {
555  return thread->readPredicate();
556  }
557 
558  void
559  setPredicate(bool val) override
560  {
562 
563  if (cpu->traceData) {
565  }
566  }
567 
568  bool
569  readMemAccPredicate() const override
570  {
571  return thread->readMemAccPredicate();
572  }
573 
574  void
575  setMemAccPredicate(bool val) override
576  {
578  }
579 
580  uint64_t
581  getHtmTransactionUid() const override
582  {
583  return tcBase()->getHtmCheckpointPtr()->getHtmUid();
584  }
585 
586  uint64_t
587  newHtmTransactionUid() const override
588  {
589  return tcBase()->getHtmCheckpointPtr()->newHtmUid();
590  }
591 
592  bool
593  inHtmTransactionalState() const override
594  {
595  return (getHtmTransactionalDepth() > 0);
596  }
597 
598  uint64_t
599  getHtmTransactionalDepth() const override
600  {
603  }
604 
608  void
609  demapPage(Addr vaddr, uint64_t asn) override
610  {
611  thread->demapPage(vaddr, asn);
612  }
613 
614  void
615  armMonitor(Addr address) override
616  {
617  cpu->armMonitor(thread->threadId(), address);
618  }
619 
620  bool
621  mwait(PacketPtr pkt) override
622  {
623  return cpu->mwait(thread->threadId(), pkt);
624  }
625 
626  void
628  {
629  cpu->mwaitAtomic(thread->threadId(), tc, thread->mmu);
630  }
631 
632  AddressMonitor *
633  getAddrMonitor() override
634  {
635  return cpu->getCpuAddrMonitor(thread->threadId());
636  }
637 };
638 
639 } // namespace gem5
640 
641 #endif // __CPU_EXEC_CONTEXT_HH__
gem5::statistics::Scalar
This is a simple scalar statistic, like a counter.
Definition: statistics.hh:1930
gem5::BaseSimpleCPU::initiateMemAMO
virtual Fault initiateMemAMO(Addr addr, unsigned size, Request::Flags flags, AtomicOpFunctorPtr amo_op)
Definition: base.hh:180
gem5::SimpleThread::readMiscReg
RegVal readMiscReg(RegIndex misc_reg) override
Definition: simple_thread.hh:441
gem5::SimpleExecContext::setMiscReg
void setMiscReg(int misc_reg, RegVal val) override
Sets a miscellaneous register, handling any architectural side effects due to writing that register.
Definition: exec_context.hh:464
gem5::SimpleThread::readIntReg
RegVal readIntReg(RegIndex reg_idx) const override
Definition: simple_thread.hh:267
gem5::SimpleExecContext::getWritableVecPredRegOperand
TheISA::VecPredRegContainer & getWritableVecPredRegOperand(const StaticInst *si, int idx) override
Gets destination predicate register operand for modification.
Definition: exec_context.hh:394
gem5::SimpleExecContext::numOp
Counter numOp
Definition: exec_context.hh:77
gem5::SimpleExecContext::ExecContextStats::numMiscRegReads
statistics::Scalar numMiscRegReads
Definition: exec_context.hh:245
gem5::SimpleExecContext::ExecContextStats::numIntRegWrites
statistics::Scalar numIntRegWrites
Definition: exec_context.hh:226
gem5::SimpleThread::htmTransactionStops
int64_t htmTransactionStops
Definition: simple_thread.hh:140
gem5::SimpleExecContext::lastDcacheStall
Counter lastDcacheStall
Definition: exec_context.hh:83
gem5::SimpleExecContext::setCCRegOperand
void setCCRegOperand(const StaticInst *si, int idx, RegVal val) override
Definition: exec_context.hh:422
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::SimpleThread::setIntReg
void setIntReg(RegIndex reg_idx, RegVal val) override
Definition: simple_thread.hh:359
gem5::ArmISA::VecPredRegContainer
VecPredReg::Container VecPredRegContainer
Definition: vec.hh:68
gem5::SimpleThread::readVecReg
const TheISA::VecRegContainer & readVecReg(const RegId &reg) const override
Definition: simple_thread.hh:289
data
const char data[]
Definition: circlebuf.test.cc:48
gem5::SimpleExecContext::ExecContextStats::ExecContextStats
ExecContextStats(BaseSimpleCPU *cpu, SimpleThread *thread)
Definition: exec_context.hh:87
gem5::BaseSimpleCPU::traceData
Trace::InstRecord * traceData
Definition: base.hh:99
gem5::SimpleExecContext::readMemAccPredicate
bool readMemAccPredicate() const override
Definition: exec_context.hh:569
gem5::VecElemClass
@ VecElemClass
Vector Register Native Elem lane.
Definition: reg_class.hh:63
gem5::SimpleExecContext::ExecContextStats::icacheStallCycles
statistics::Scalar icacheStallCycles
Definition: exec_context.hh:264
gem5::SimpleExecContext::numLoad
Counter numLoad
Definition: exec_context.hh:79
gem5::SimpleExecContext::readFloatRegOperandBits
RegVal readFloatRegOperandBits(const StaticInst *si, int idx) override
Reads a floating point register in its binary format, instead of by value.
Definition: exec_context.hh:314
gem5::SimpleExecContext::ExecContextStats::numCallsReturns
statistics::Scalar numCallsReturns
Definition: exec_context.hh:210
gem5::CCRegClass
@ CCRegClass
Condition-code register.
Definition: reg_class.hh:65
gem5::SimpleExecContext::ExecContextStats::numVecPredRegWrites
statistics::Scalar numVecPredRegWrites
Definition: exec_context.hh:238
gem5::SimpleExecContext::readVecRegOperand
const TheISA::VecRegContainer & readVecRegOperand(const StaticInst *si, int idx) const override
Reads a vector register.
Definition: exec_context.hh:335
gem5::SimpleExecContext::ExecContextStats::numVecRegReads
statistics::Scalar numVecRegReads
Definition: exec_context.hh:233
gem5::statistics::nozero
const FlagsType nozero
Don't print if this is zero.
Definition: info.hh:68
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
gem5::BaseSimpleCPU::amoMem
virtual Fault amoMem(Addr addr, uint8_t *data, unsigned size, Request::Flags flags, AtomicOpFunctorPtr amo_op)
Definition: base.hh:173
gem5::SimpleThread::setMiscReg
void setMiscReg(RegIndex misc_reg, RegVal val) override
Definition: simple_thread.hh:453
gem5::SimpleExecContext::execContextStats
gem5::SimpleExecContext::ExecContextStats execContextStats
gem5::SimpleThread::setStCondFailures
void setStCondFailures(unsigned sc_failures) override
Definition: simple_thread.hh:479
gem5::SimpleExecContext::newHtmTransactionUid
uint64_t newHtmTransactionUid() const override
Definition: exec_context.hh:587
gem5::SimpleExecContext::readMiscReg
RegVal readMiscReg(int misc_reg) override
Reads a miscellaneous register, handling any architectural side effects due to reading that register.
Definition: exec_context.hh:453
gem5::statistics::DataWrapVec::subname
Derived & subname(off_type index, const std::string &name)
Set the subfield name for the given index, and marks this stat to print at the end of simulation.
Definition: statistics.hh:402
gem5::statistics::Average
A stat that calculates the per tick average of a value.
Definition: statistics.hh:1958
gem5::SimpleExecContext::readCCRegOperand
RegVal readCCRegOperand(const StaticInst *si, int idx) override
Definition: exec_context.hh:413
gem5::SimpleExecContext::readStCondFailures
unsigned int readStCondFailures() const override
Returns the number of consecutive store conditional failures.
Definition: exec_context.hh:544
gem5::statistics::Vector
A vector of scalar stats.
Definition: statistics.hh:2006
gem5::SimpleThread::setVecReg
void setVecReg(const RegId &reg, const TheISA::VecRegContainer &val) override
Definition: simple_thread.hh:382
gem5::statistics::Formula
A formula for statistics that is calculated when printed.
Definition: statistics.hh:2539
std::vector< bool >
gem5::SimpleThread::readCCReg
RegVal readCCReg(RegIndex reg_idx) const override
Definition: simple_thread.hh:347
gem5::csprintf
std::string csprintf(const char *format, const Args &...args)
Definition: cprintf.hh:161
gem5::Trace::InstRecord::setPredicate
void setPredicate(bool val)
Definition: insttracer.hh:230
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:67
gem5::SimpleThread::htmTransactionStarts
int64_t htmTransactionStarts
Definition: simple_thread.hh:139
gem5::SimpleThread
The SimpleThread object provides a combination of the ThreadState object and the ThreadContext interf...
Definition: simple_thread.hh:93
gem5::SimpleExecContext::ExecContextStats::numPredictedBranches
statistics::Scalar numPredictedBranches
Number of branches predicted as taken.
Definition: exec_context.hh:273
request.hh
gem5::SimpleExecContext::ExecContextStats::numVecInsts
statistics::Scalar numVecInsts
Definition: exec_context.hh:222
gem5::SimpleExecContext::getHtmTransactionalDepth
uint64_t getHtmTransactionalDepth() const override
Definition: exec_context.hh:599
gem5::SimpleThread::setVecPredReg
void setVecPredReg(const RegId &reg, const TheISA::VecPredRegContainer &val) override
Definition: simple_thread.hh:402
gem5::statistics::dist
const FlagsType dist
Print the distribution.
Definition: info.hh:66
gem5::SimpleExecContext::setPredicate
void setPredicate(bool val) override
Definition: exec_context.hh:559
gem5::VecPredRegClass
@ VecPredRegClass
Definition: reg_class.hh:64
gem5::statistics::constant
Temp constant(T val)
Definition: statistics.hh:2865
gem5::SimpleExecContext::pcState
const PCStateBase & pcState() const override
Definition: exec_context.hh:471
gem5::SimpleExecContext::amoMem
Fault amoMem(Addr addr, uint8_t *data, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op) override
For atomic-mode contexts, perform an atomic AMO (a.k.a., Atomic Read-Modify-Write Memory Operation)
Definition: exec_context.hh:513
gem5::statistics::pdf
const FlagsType pdf
Print the percent of the total that this entry represents.
Definition: info.hh:62
gem5::SimpleThread::readStCondFailures
unsigned readStCondFailures() const override
Definition: simple_thread.hh:464
gem5::BaseSimpleCPU::writeMem
virtual Fault writeMem(uint8_t *data, unsigned size, Addr addr, Request::Flags flags, uint64_t *res, const std::vector< bool > &byte_enable=std::vector< bool >())
Definition: base.hh:165
gem5::SimpleThread::mmu
BaseMMU * mmu
Definition: simple_thread.hh:134
gem5::FloatRegClass
@ FloatRegClass
Floating-point register.
Definition: reg_class.hh:59
gem5::SimpleExecContext::ExecContextStats::numMiscRegWrites
statistics::Scalar numMiscRegWrites
Definition: exec_context.hh:246
gem5::SimpleExecContext::mwait
bool mwait(PacketPtr pkt) override
Definition: exec_context.hh:621
gem5::SimpleExecContext::ExecContextStats::numCCRegReads
statistics::Scalar numCCRegReads
Definition: exec_context.hh:241
gem5::SimpleExecContext::setStCondFailures
void setStCondFailures(unsigned int sc_failures) override
Sets the number of consecutive store conditional failures.
Definition: exec_context.hh:535
gem5::SimpleExecContext::setIntRegOperand
void setIntRegOperand(const StaticInst *si, int idx, RegVal val) override
Sets an integer register to a value.
Definition: exec_context.hh:303
gem5::SimpleThread::readMemAccPredicate
bool readMemAccPredicate()
Definition: simple_thread.hh:467
gem5::Flags< FlagsType >
gem5::SimpleExecContext::ExecContextStats::numIdleCycles
statistics::Formula numIdleCycles
Definition: exec_context.hh:254
gem5::SimpleExecContext::initiateHtmCmd
Fault initiateHtmCmd(Request::Flags flags) override
Initiate an HTM command, e.g.
Definition: exec_context.hh:526
gem5::BaseSimpleCPU::readMem
virtual Fault readMem(Addr addr, uint8_t *data, unsigned size, Request::Flags flags, const std::vector< bool > &byte_enable=std::vector< bool >())
Definition: base.hh:151
gem5::SimpleExecContext::demapPage
void demapPage(Addr vaddr, uint64_t asn) override
Invalidate a page in the DTLB and ITLB.
Definition: exec_context.hh:609
gem5::SimpleExecContext::setVecElemOperand
void setVecElemOperand(const StaticInst *si, int idx, RegVal val) override
Sets an element of a vector register to a value.
Definition: exec_context.hh:376
translation.hh
gem5::StaticInst
Base, ISA-independent static instruction class.
Definition: static_inst.hh:87
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::SimpleExecContext::ExecContextStats::numInsts
statistics::Scalar numInsts
Definition: exec_context.hh:197
gem5::SimpleExecContext::fetchOffset
Addr fetchOffset
Definition: exec_context.hh:67
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::SimpleThread::readPredicate
bool readPredicate() const
Definition: simple_thread.hh:431
gem5::SimpleExecContext::inHtmTransactionalState
bool inHtmTransactionalState() const override
Definition: exec_context.hh:593
ADD_STAT
#define ADD_STAT(n,...)
Convenience macro to add a stat to a statistics group.
Definition: group.hh:75
gem5::SimpleExecContext::ExecContextStats::numFpRegReads
statistics::Scalar numFpRegReads
Definition: exec_context.hh:229
gem5::SimpleExecContext::mwaitAtomic
void mwaitAtomic(ThreadContext *tc) override
Definition: exec_context.hh:627
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::SimpleExecContext::ExecContextStats::numCCRegWrites
statistics::Scalar numCCRegWrites
Definition: exec_context.hh:242
gem5::SimpleExecContext::ExecContextStats::numCondCtrlInsts
statistics::Scalar numCondCtrlInsts
Definition: exec_context.hh:213
gem5::SimpleExecContext::stayAtPC
bool stayAtPC
Definition: exec_context.hh:70
gem5::SimpleExecContext::readPredicate
bool readPredicate() const override
Definition: exec_context.hh:553
gem5::SimpleThread::setMemAccPredicate
void setMemAccPredicate(bool val)
Definition: simple_thread.hh:473
gem5::SimpleExecContext::ExecContextStats::notIdleFraction
statistics::Average notIdleFraction
Definition: exec_context.hh:260
gem5::SimpleExecContext::cpu
BaseSimpleCPU * cpu
Definition: exec_context.hh:63
gem5::SimpleExecContext::writeMem
Fault writeMem(uint8_t *data, unsigned int size, Addr addr, Request::Flags flags, uint64_t *res, const std::vector< bool > &byte_enable) override
For atomic-mode contexts, perform an atomic memory write operation.
Definition: exec_context.hh:503
gem5::SimpleExecContext::readVecElemOperand
RegVal readVecElemOperand(const StaticInst *si, int idx) const override
Reads an element of a vector register.
Definition: exec_context.hh:366
gem5::SimpleExecContext::getWritableVecRegOperand
TheISA::VecRegContainer & getWritableVecRegOperand(const StaticInst *si, int idx) override
Reads a vector register for modification.
Definition: exec_context.hh:345
gem5::SimpleExecContext::ExecContextStats::statExecutedInstType
statistics::Vector statExecutedInstType
Definition: exec_context.hh:279
gem5::SimpleThread::threadId
int threadId() const override
Definition: simple_thread.hh:204
gem5::SimpleExecContext::ExecContextStats::numBusyCycles
statistics::Formula numBusyCycles
Definition: exec_context.hh:257
gem5::SimpleExecContext::ExecContextStats::dcacheStallCycles
statistics::Scalar dcacheStallCycles
Definition: exec_context.hh:267
gem5::ArmISA::VecRegContainer
gem5::VecRegContainer< NumVecElemPerVecReg *sizeof(VecElem)> VecRegContainer
Definition: vec.hh:62
gem5::BaseSimpleCPU
Definition: base.hh:83
gem5::SimpleExecContext::numInst
Counter numInst
PER-THREAD STATS.
Definition: exec_context.hh:76
gem5::ThreadContext::getHtmCheckpointPtr
virtual BaseHTMCheckpointPtr & getHtmCheckpointPtr()=0
gem5::SimpleExecContext::readIntRegOperand
RegVal readIntRegOperand(const StaticInst *si, int idx) override
Reads an integer register.
Definition: exec_context.hh:293
gem5::SimpleThread::pcState
const PCStateBase & pcState() const override
Definition: simple_thread.hh:422
gem5::SimpleThread::readVecElem
RegVal readVecElem(const RegId &reg) const override
Definition: simple_thread.hh:311
gem5::SimpleExecContext::setVecPredRegOperand
void setVecPredRegOperand(const StaticInst *si, int idx, const TheISA::VecPredRegContainer &val) override
Sets a destination predicate register operand to a value.
Definition: exec_context.hh:403
gem5::SimpleExecContext::readVecPredRegOperand
const TheISA::VecPredRegContainer & readVecPredRegOperand(const StaticInst *si, int idx) const override
Predicate registers interface.
Definition: exec_context.hh:385
gem5::ArmISA::si
Bitfield< 6 > si
Definition: misc_types.hh:773
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::SimpleThread::setFloatReg
void setFloatReg(RegIndex reg_idx, RegVal val) override
Definition: simple_thread.hh:369
gem5::SimpleExecContext::ExecContextStats::idleFraction
statistics::Formula idleFraction
Definition: exec_context.hh:261
gem5::SimpleExecContext::lastIcacheStall
Counter lastIcacheStall
Definition: exec_context.hh:81
gem5::SimpleExecContext::ExecContextStats::numFpInsts
statistics::Scalar numFpInsts
Definition: exec_context.hh:219
gem5::SimpleExecContext::setFloatRegOperandBits
void setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) override
Sets the bits of a floating point register of single width to a binary value.
Definition: exec_context.hh:325
gem5::SimpleThread::readFloatReg
RegVal readFloatReg(RegIndex reg_idx) const override
Definition: simple_thread.hh:278
gem5::SimpleExecContext::pcState
void pcState(const PCStateBase &val) override
Definition: exec_context.hh:477
gem5::SimpleExecContext::ExecContextStats::numVecAluAccesses
statistics::Scalar numVecAluAccesses
Definition: exec_context.hh:207
gem5::SimpleExecContext::setMiscRegOperand
void setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override
Definition: exec_context.hh:440
gem5::SimpleExecContext::ExecContextStats::numStoreInsts
statistics::Scalar numStoreInsts
Definition: exec_context.hh:251
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::SimpleExecContext::initiateMemRead
Fault initiateMemRead(Addr addr, unsigned int size, Request::Flags flags, const std::vector< bool > &byte_enable) override
Initiate a timing memory read operation.
Definition: exec_context.hh:493
gem5::SimpleExecContext::thread
SimpleThread * thread
Definition: exec_context.hh:64
gem5::SimpleThread::getTC
ThreadContext * getTC()
Returns the pointer to this SimpleThread's ThreadContext.
Definition: simple_thread.hh:169
gem5::SimpleThread::getWritableVecPredReg
TheISA::VecPredRegContainer & getWritableVecPredReg(const RegId &reg) override
Definition: simple_thread.hh:334
base.hh
gem5::SimpleExecContext::ExecContextStats::numLoadInsts
statistics::Scalar numLoadInsts
Definition: exec_context.hh:250
gem5::IntRegClass
@ IntRegClass
Integer register.
Definition: reg_class.hh:58
gem5::SimpleThread::getWritableVecReg
TheISA::VecRegContainer & getWritableVecReg(const RegId &reg) override
Definition: simple_thread.hh:300
gem5::SimpleThread::readVecPredReg
const TheISA::VecPredRegContainer & readVecPredReg(const RegId &reg) const override
Definition: simple_thread.hh:322
gem5::SimpleExecContext::ExecContextStats::numIntInsts
statistics::Scalar numIntInsts
Definition: exec_context.hh:216
gem5::SimpleExecContext::ExecContextStats::numIntAluAccesses
statistics::Scalar numIntAluAccesses
Definition: exec_context.hh:201
gem5::SimpleExecContext::setMemAccPredicate
void setMemAccPredicate(bool val) override
Definition: exec_context.hh:575
base.hh
gem5::SimpleExecContext
Definition: exec_context.hh:60
gem5::MiscRegClass
@ MiscRegClass
Control (misc) register.
Definition: reg_class.hh:66
gem5::statistics::DataWrap::prereq
Derived & prereq(const Stat &prereq)
Set the prerequisite stat and marks this stat to print at the end of simulation.
Definition: statistics.hh:372
types.hh
gem5::BaseSimpleCPU::initiateMemRead
virtual Fault initiateMemRead(Addr addr, unsigned size, Request::Flags flags, const std::vector< bool > &byte_enable=std::vector< bool >())
Definition: base.hh:158
gem5::SimpleThread::setVecElem
void setVecElem(const RegId &reg, RegVal val) override
Definition: simple_thread.hh:392
gem5::SimpleExecContext::initiateMemAMO
Fault initiateMemAMO(Addr addr, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op) override
For timing-mode contexts, initiate an atomic AMO (atomic read-modify-write memory operation)
Definition: exec_context.hh:519
gem5::SimpleThread::demapPage
void demapPage(Addr vaddr, uint64_t asn)
Definition: simple_thread.hh:172
gem5::SimpleExecContext::ExecContextStats
Definition: exec_context.hh:85
static_inst_fwd.hh
gem5::SimpleExecContext::getAddrMonitor
AddressMonitor * getAddrMonitor() override
Definition: exec_context.hh:633
exec_context.hh
reg_class.hh
gem5::statistics::Counter
double Counter
All counters are of 64-bit values.
Definition: types.hh:47
gem5::SimpleExecContext::tcBase
ThreadContext * tcBase() const override
Returns a pointer to the ThreadContext.
Definition: exec_context.hh:550
gem5::SimpleExecContext::ExecContextStats::numFpAluAccesses
statistics::Scalar numFpAluAccesses
Definition: exec_context.hh:204
gem5::SimpleExecContext::readMiscRegOperand
RegVal readMiscRegOperand(const StaticInst *si, int idx) override
Definition: exec_context.hh:431
gem5::statistics::Group
Statistics container.
Definition: group.hh:93
gem5::SimpleExecContext::ExecContextStats::numVecRegWrites
statistics::Scalar numVecRegWrites
Definition: exec_context.hh:234
gem5::ExecContext
The ExecContext is an abstract base class the provides the interface used by the ISA to manipulate th...
Definition: exec_context.hh:73
gem5::SimpleExecContext::ExecContextStats::numIntRegReads
statistics::Scalar numIntRegReads
Definition: exec_context.hh:225
gem5::SimpleExecContext::ExecContextStats::numBranches
statistics::Scalar numBranches
Definition: exec_context.hh:271
gem5::SimpleExecContext::ExecContextStats::numOps
statistics::Scalar numOps
Definition: exec_context.hh:198
gem5::SimpleExecContext::ExecContextStats::numFpRegWrites
statistics::Scalar numFpRegWrites
Definition: exec_context.hh:230
gem5::Num_OpClasses
static const OpClass Num_OpClasses
Definition: op_class.hh:108
gem5::SimpleExecContext::armMonitor
void armMonitor(Addr address) override
Definition: exec_context.hh:615
gem5::statistics::DataWrap::flags
Derived & flags(Flags _flags)
Set the flags and marks this stat to print at the end of simulation.
Definition: statistics.hh:358
gem5::SimpleExecContext::readMem
Fault readMem(Addr addr, uint8_t *data, unsigned int size, Request::Flags flags, const std::vector< bool > &byte_enable) override
Perform an atomic memory read operation.
Definition: exec_context.hh:483
gem5::VecRegClass
@ VecRegClass
Vector Register.
Definition: reg_class.hh:61
gem5::MipsISA::vaddr
vaddr
Definition: pra_constants.hh:278
gem5::PCStateBase
Definition: pcstate.hh:57
gem5::SimpleExecContext::ExecContextStats::numBranchMispred
statistics::Scalar numBranchMispred
Number of misprediced branches.
Definition: exec_context.hh:275
gem5::AtomicOpFunctorPtr
std::unique_ptr< AtomicOpFunctor > AtomicOpFunctorPtr
Definition: amo.hh:242
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::statistics::total
const FlagsType total
Print the total.
Definition: info.hh:60
gem5::SimpleExecContext::predPC
std::unique_ptr< PCStateBase > predPC
Definition: exec_context.hh:73
gem5::statistics::VectorBase::init
Derived & init(size_type size)
Set this vector to have the given size.
Definition: statistics.hh:1040
gem5::SimpleExecContext::getHtmTransactionUid
uint64_t getHtmTransactionUid() const override
Definition: exec_context.hh:581
gem5::SimpleExecContext::ExecContextStats::numVecPredRegReads
statistics::Scalar numVecPredRegReads
Definition: exec_context.hh:237
gem5::SimpleExecContext::setVecRegOperand
void setVecRegOperand(const StaticInst *si, int idx, const TheISA::VecRegContainer &val) override
Sets a vector register to a value.
Definition: exec_context.hh:355
gem5::BaseSimpleCPU::initiateHtmCmd
virtual Fault initiateHtmCmd(Request::Flags flags)=0
Hardware transactional memory commands (HtmCmds), e.g.
gem5::SimpleThread::setPredicate
void setPredicate(bool val)
Definition: simple_thread.hh:432
gem5::SimpleExecContext::ExecContextStats::numMemRefs
statistics::Scalar numMemRefs
Definition: exec_context.hh:249
gem5::SimpleExecContext::SimpleExecContext
SimpleExecContext(BaseSimpleCPU *_cpu, SimpleThread *_thread)
Constructor.
Definition: exec_context.hh:285
gem5::SimpleThread::setCCReg
void setCCReg(RegIndex reg_idx, RegVal val) override
Definition: simple_thread.hh:413
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:113
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84

Generated on Wed May 4 2022 12:13:53 for gem5 by doxygen 1.8.17