#include <exec_context.hh>

Inheritance diagram for gem5::SimpleExecContext:

Classes
struct	ExecContextStats

Public Member Functions
	SimpleExecContext (BaseSimpleCPU _cpu, SimpleThread _thread)
	Constructor.

RegVal	getRegOperand (const StaticInst *si, int idx) override

void	getRegOperand (const StaticInst si, int idx, void val) override

void *	getWritableRegOperand (const StaticInst *si, int idx) override

void	setRegOperand (const StaticInst *si, int idx, RegVal val) override

void	setRegOperand (const StaticInst si, int idx, const void val) override

RegVal	readMiscRegOperand (const StaticInst *si, int idx) override

void	setMiscRegOperand (const StaticInst *si, int idx, RegVal val) override

RegVal	readMiscReg (int misc_reg) override
	Reads a miscellaneous register, handling any architectural side effects due to reading that register.

void	setMiscReg (int misc_reg, RegVal val) override
	Sets a miscellaneous register, handling any architectural side effects due to writing that register.

const PCStateBase &	pcState () const override

void	pcState (const PCStateBase &val) override

Fault	readMem (Addr addr, uint8_t *data, unsigned int size, Request::Flags flags, const std::vector< bool > &byte_enable) override
	Perform an atomic memory read operation.

Fault	initiateMemRead (Addr addr, unsigned int size, Request::Flags flags, const std::vector< bool > &byte_enable) override
	Initiate a timing memory read operation.

Fault	writeMem (uint8_t data, unsigned int size, Addr addr, Request::Flags flags, uint64_t res, const std::vector< bool > &byte_enable) override
	For atomic-mode contexts, perform an atomic memory write operation.

Fault	amoMem (Addr addr, uint8_t *data, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op) override
	For atomic-mode contexts, perform an atomic AMO (a.k.a., Atomic Read-Modify-Write Memory Operation)

Fault	initiateMemAMO (Addr addr, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op) override
	For timing-mode contexts, initiate an atomic AMO (atomic read-modify-write memory operation)

Fault	initiateMemMgmtCmd (Request::Flags flags) override
	Initiate a memory management command with no valid address.

void	setStCondFailures (unsigned int sc_failures) override
	Sets the number of consecutive store conditional failures.

unsigned int	readStCondFailures () const override
	Returns the number of consecutive store conditional failures.

ThreadContext *	tcBase () const override
	Returns a pointer to the ThreadContext.

bool	readPredicate () const override

void	setPredicate (bool val) override

bool	readMemAccPredicate () const override

void	setMemAccPredicate (bool val) override

uint64_t	getHtmTransactionUid () const override

uint64_t	newHtmTransactionUid () const override

bool	inHtmTransactionalState () const override

uint64_t	getHtmTransactionalDepth () const override

void	demapPage (Addr vaddr, uint64_t asn) override
	Invalidate a page in the DTLB and ITLB.

void	armMonitor (Addr address) override

bool	mwait (PacketPtr pkt) override

void	mwaitAtomic (ThreadContext *tc) override

AddressMonitor *	getAddrMonitor () override

Misc Register Interfaces
PC Control
Memory Interface
ARM-Specific Interfaces
X86-Specific Interfaces

Public Attributes
BaseSimpleCPU *	cpu

SimpleThread *	thread

Addr	fetchOffset

bool	stayAtPC

std::unique_ptr< PCStateBase >	predPC

Counter	numInst
	PER-THREAD STATS.

Counter	numOp

Counter	numLoad

Counter	lastIcacheStall

Counter	lastDcacheStall

gem5::SimpleExecContext::ExecContextStats	execContextStats

Detailed Description

Definition at line 58 of file exec_context.hh.

Constructor & Destructor Documentation

◆ SimpleExecContext()

gem5::SimpleExecContext::SimpleExecContext	(	BaseSimpleCPU *	_cpu,
		SimpleThread *	_thread )

inline

Constructor.

Definition at line 175 of file exec_context.hh.

Member Function Documentation

◆ amoMem()

Fault gem5::SimpleExecContext::amoMem	(	Addr	addr,
		uint8_t *	data,
		unsigned int	size,
		Request::Flags	flags,
		AtomicOpFunctorPtr	amo_op )

inlineoverridevirtual

For atomic-mode contexts, perform an atomic AMO (a.k.a., Atomic Read-Modify-Write Memory Operation)

Reimplemented from gem5::ExecContext.

Definition at line 309 of file exec_context.hh.

References gem5::X86ISA::addr, gem5::BaseSimpleCPU::amoMem(), cpu, data, and flags.

◆ armMonitor()

void gem5::SimpleExecContext::armMonitor ( Addr address )

inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 413 of file exec_context.hh.

References gem5::BaseCPU::armMonitor(), cpu, thread, and gem5::SimpleThread::threadId().

◆ demapPage()

void gem5::SimpleExecContext::demapPage	(	Addr	vaddr,
		uint64_t	asn )

inlineoverridevirtual

Invalidate a page in the DTLB and ITLB.

Implements gem5::ExecContext.

Definition at line 407 of file exec_context.hh.

References gem5::SimpleThread::demapPage(), thread, and gem5::MipsISA::vaddr.

◆ getAddrMonitor()

AddressMonitor * gem5::SimpleExecContext::getAddrMonitor ( )

inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 431 of file exec_context.hh.

References cpu, gem5::BaseCPU::getCpuAddrMonitor(), thread, and gem5::SimpleThread::threadId().

◆ getHtmTransactionalDepth()

uint64_t gem5::SimpleExecContext::getHtmTransactionalDepth ( ) const

inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 397 of file exec_context.hh.

References gem5::SimpleThread::htmTransactionStarts, gem5::SimpleThread::htmTransactionStops, and thread.

Referenced by inHtmTransactionalState().

◆ getHtmTransactionUid()

uint64_t gem5::SimpleExecContext::getHtmTransactionUid ( ) const

inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 379 of file exec_context.hh.

References gem5::ThreadContext::getHtmCheckpointPtr(), and tcBase().

Referenced by gem5::TimingSimpleCPU::advanceInst(), gem5::TimingSimpleCPU::completeDataAccess(), gem5::TimingSimpleCPU::initiateMemMgmtCmd(), gem5::TimingSimpleCPU::sendData(), and gem5::TimingSimpleCPU::sendSplitData().

◆ getRegOperand() [1/2]

RegVal gem5::SimpleExecContext::getRegOperand	(	const StaticInst *	si,
		int	idx )

inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 182 of file exec_context.hh.

References execContextStats, gem5::SimpleThread::getReg(), gem5::InvalidRegClass, gem5::SimpleExecContext::ExecContextStats::numRegReads, gem5::X86ISA::reg, gem5::ArmISA::si, and thread.

◆ getRegOperand() [2/2]

void gem5::SimpleExecContext::getRegOperand	(	const StaticInst *	si,
		int	idx,
		void *	val )

inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 192 of file exec_context.hh.

References execContextStats, gem5::SimpleThread::getReg(), gem5::SimpleExecContext::ExecContextStats::numRegReads, gem5::X86ISA::reg, gem5::ArmISA::si, thread, and gem5::X86ISA::val.

◆ getWritableRegOperand()

void * gem5::SimpleExecContext::getWritableRegOperand	(	const StaticInst *	si,
		int	idx )

inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 200 of file exec_context.hh.

References execContextStats, gem5::SimpleThread::getWritableReg(), gem5::SimpleExecContext::ExecContextStats::numRegWrites, gem5::X86ISA::reg, gem5::ArmISA::si, and thread.

◆ inHtmTransactionalState()

bool gem5::SimpleExecContext::inHtmTransactionalState ( ) const

inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 391 of file exec_context.hh.

References getHtmTransactionalDepth().

Referenced by gem5::TimingSimpleCPU::advanceInst(), gem5::BaseSimpleCPU::checkForInterrupts(), gem5::TimingSimpleCPU::completeDataAccess(), gem5::TimingSimpleCPU::completeIfetch(), gem5::TimingSimpleCPU::sendData(), gem5::TimingSimpleCPU::sendSplitData(), and gem5::TimingSimpleCPU::switchOut().

◆ initiateMemAMO()

Fault gem5::SimpleExecContext::initiateMemAMO	(	Addr	addr,
		unsigned int	size,
		Request::Flags	flags,
		AtomicOpFunctorPtr	amo_op )

inlineoverridevirtual

For timing-mode contexts, initiate an atomic AMO (atomic read-modify-write memory operation)

Reimplemented from gem5::ExecContext.

Definition at line 316 of file exec_context.hh.

References gem5::X86ISA::addr, cpu, flags, and gem5::BaseSimpleCPU::initiateMemAMO().

◆ initiateMemMgmtCmd()

Fault gem5::SimpleExecContext::initiateMemMgmtCmd ( Request::Flags flags )

inlineoverridevirtual

Initiate a memory management command with no valid address.

Currently, these instructions need to bypass squashing in the O3 model Examples include HTM commands and TLBI commands. e.g. tell Ruby we're starting/stopping a HTM transaction, or tell Ruby to issue a TLBI operation

Implements gem5::ExecContext.

Definition at line 324 of file exec_context.hh.

References cpu, flags, and gem5::BaseSimpleCPU::initiateMemMgmtCmd().

◆ initiateMemRead()

Fault gem5::SimpleExecContext::initiateMemRead	(	Addr	addr,
		unsigned int	size,
		Request::Flags	flags,
		const std::vector< bool > &	byte_enable )

inlineoverridevirtual

Initiate a timing memory read operation.

Must be overridden for exec contexts that support timing memory mode. Not pure virtual since exec contexts that only support atomic memory mode need not override (though in that case this function should never be called).

Reimplemented from gem5::ExecContext.

Definition at line 288 of file exec_context.hh.

References gem5::X86ISA::addr, cpu, flags, and gem5::BaseSimpleCPU::initiateMemRead().

◆ mwait()

bool gem5::SimpleExecContext::mwait ( PacketPtr pkt )

inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 419 of file exec_context.hh.

References cpu, gem5::BaseCPU::mwait(), thread, and gem5::SimpleThread::threadId().

◆ mwaitAtomic()

void gem5::SimpleExecContext::mwaitAtomic ( ThreadContext * tc )

inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 425 of file exec_context.hh.

References cpu, gem5::SimpleThread::mmu, gem5::BaseCPU::mwaitAtomic(), thread, and gem5::SimpleThread::threadId().

◆ newHtmTransactionUid()

uint64_t gem5::SimpleExecContext::newHtmTransactionUid ( ) const

inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 385 of file exec_context.hh.

References gem5::ThreadContext::getHtmCheckpointPtr(), and tcBase().

Referenced by gem5::TimingSimpleCPU::completeIfetch().

◆ pcState() [1/2]

const PCStateBase & gem5::SimpleExecContext::pcState ( ) const

inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 266 of file exec_context.hh.

References gem5::SimpleThread::pcState(), and thread.

◆ pcState() [2/2]

void gem5::SimpleExecContext::pcState ( const PCStateBase & val )

inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 272 of file exec_context.hh.

References gem5::SimpleThread::pcState(), thread, and gem5::X86ISA::val.

◆ readMem()

Fault gem5::SimpleExecContext::readMem	(	Addr	addr,
		uint8_t *	data,
		unsigned int	size,
		Request::Flags	flags,
		const std::vector< bool > &	byte_enable )

inlineoverridevirtual

Perform an atomic memory read operation.

Must be overridden for exec contexts that support atomic memory mode. Not pure virtual since exec contexts that only support timing memory mode need not override (though in that case this function should never be called).

Reimplemented from gem5::ExecContext.

Definition at line 278 of file exec_context.hh.

References gem5::X86ISA::addr, cpu, data, flags, and gem5::BaseSimpleCPU::readMem().

◆ readMemAccPredicate()

bool gem5::SimpleExecContext::readMemAccPredicate ( ) const

inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 367 of file exec_context.hh.

References gem5::SimpleThread::readMemAccPredicate(), and thread.

◆ readMiscReg()

RegVal gem5::SimpleExecContext::readMiscReg ( int misc_reg )

inlineoverridevirtual

Reads a miscellaneous register, handling any architectural side effects due to reading that register.

Implements gem5::ExecContext.

Definition at line 248 of file exec_context.hh.

References cpu, gem5::BaseCPU::executeStats, gem5::SimpleThread::readMiscReg(), thread, and gem5::SimpleThread::threadId().

◆ readMiscRegOperand()

RegVal gem5::SimpleExecContext::readMiscRegOperand	(	const StaticInst *	si,
		int	idx )

inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 226 of file exec_context.hh.

References cpu, gem5::BaseCPU::executeStats, gem5::MiscRegClass, gem5::SimpleThread::readMiscReg(), gem5::X86ISA::reg, gem5::ArmISA::si, thread, and gem5::SimpleThread::threadId().

◆ readPredicate()

bool gem5::SimpleExecContext::readPredicate ( ) const

inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 351 of file exec_context.hh.

References gem5::SimpleThread::readPredicate(), and thread.

◆ readStCondFailures()

unsigned int gem5::SimpleExecContext::readStCondFailures ( ) const

inlineoverridevirtual

Returns the number of consecutive store conditional failures.

Implements gem5::ExecContext.

Definition at line 342 of file exec_context.hh.

References gem5::SimpleThread::readStCondFailures(), and thread.

◆ setMemAccPredicate()

void gem5::SimpleExecContext::setMemAccPredicate ( bool val )

inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 373 of file exec_context.hh.

References gem5::SimpleThread::setMemAccPredicate(), thread, and gem5::X86ISA::val.

Referenced by gem5::BaseSimpleCPU::preExecute().

◆ setMiscReg()

void gem5::SimpleExecContext::setMiscReg	(	int	misc_reg,
		RegVal	val )

inlineoverridevirtual

Sets a miscellaneous register, handling any architectural side effects due to writing that register.

Implements gem5::ExecContext.

Definition at line 259 of file exec_context.hh.

References cpu, gem5::BaseCPU::executeStats, gem5::SimpleThread::setMiscReg(), thread, gem5::SimpleThread::threadId(), and gem5::X86ISA::val.

◆ setMiscRegOperand()

void gem5::SimpleExecContext::setMiscRegOperand	(	const StaticInst *	si,
		int	idx,
		RegVal	val )

inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 235 of file exec_context.hh.

References cpu, gem5::BaseCPU::executeStats, gem5::MiscRegClass, gem5::X86ISA::reg, gem5::SimpleThread::setMiscReg(), gem5::ArmISA::si, thread, gem5::SimpleThread::threadId(), and gem5::X86ISA::val.

◆ setPredicate()

void gem5::SimpleExecContext::setPredicate ( bool val )

inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 357 of file exec_context.hh.

References cpu, gem5::SimpleThread::setPredicate(), gem5::trace::InstRecord::setPredicate(), thread, gem5::BaseSimpleCPU::traceData, and gem5::X86ISA::val.

Referenced by gem5::BaseSimpleCPU::preExecute().

◆ setRegOperand() [1/2]

void gem5::SimpleExecContext::setRegOperand	(	const StaticInst *	si,
		int	idx,
		const void *	val )

inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 218 of file exec_context.hh.

References execContextStats, gem5::SimpleExecContext::ExecContextStats::numRegWrites, gem5::X86ISA::reg, gem5::SimpleThread::setReg(), gem5::ArmISA::si, thread, and gem5::X86ISA::val.

◆ setRegOperand() [2/2]

void gem5::SimpleExecContext::setRegOperand	(	const StaticInst *	si,
		int	idx,
		RegVal	val )

inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 208 of file exec_context.hh.

References execContextStats, gem5::InvalidRegClass, gem5::SimpleExecContext::ExecContextStats::numRegWrites, gem5::X86ISA::reg, gem5::SimpleThread::setReg(), gem5::ArmISA::si, thread, and gem5::X86ISA::val.

◆ setStCondFailures()

void gem5::SimpleExecContext::setStCondFailures ( unsigned int sc_failures )

inlineoverridevirtual

Sets the number of consecutive store conditional failures.

Implements gem5::ExecContext.

Definition at line 333 of file exec_context.hh.

References gem5::SimpleThread::setStCondFailures(), and thread.

◆ tcBase()

ThreadContext * gem5::SimpleExecContext::tcBase ( ) const

inlineoverridevirtual

Returns a pointer to the ThreadContext.

Implements gem5::ExecContext.

Definition at line 348 of file exec_context.hh.

References gem5::SimpleThread::getTC(), and thread.

Referenced by getHtmTransactionUid(), and newHtmTransactionUid().

◆ writeMem()

Fault gem5::SimpleExecContext::writeMem	(	uint8_t *	data,
		unsigned int	size,
		Addr	addr,
		Request::Flags	flags,
		uint64_t *	res,
		const std::vector< bool > &	byte_enable )

inlineoverridevirtual

For atomic-mode contexts, perform an atomic memory write operation.

For timing-mode contexts, initiate a timing memory write operation.

Implements gem5::ExecContext.

Definition at line 298 of file exec_context.hh.

References gem5::X86ISA::addr, cpu, data, flags, and gem5::BaseSimpleCPU::writeMem().

Member Data Documentation

◆ cpu

BaseSimpleCPU* gem5::SimpleExecContext::cpu

Definition at line 61 of file exec_context.hh.

Referenced by amoMem(), armMonitor(), gem5::SimpleExecContext::ExecContextStats::ExecContextStats(), getAddrMonitor(), initiateMemAMO(), initiateMemMgmtCmd(), initiateMemRead(), mwait(), mwaitAtomic(), readMem(), readMiscReg(), readMiscRegOperand(), setMiscReg(), setMiscRegOperand(), setPredicate(), and writeMem().

◆ execContextStats

gem5::SimpleExecContext::ExecContextStats gem5::SimpleExecContext::execContextStats

Referenced by gem5::BaseSimpleCPU::advancePC(), getRegOperand(), getRegOperand(), getWritableRegOperand(), gem5::BaseSimpleCPU::postExecute(), gem5::BaseSimpleCPU::preExecute(), setRegOperand(), and setRegOperand().

◆ fetchOffset

Addr gem5::SimpleExecContext::fetchOffset

Definition at line 65 of file exec_context.hh.

Referenced by gem5::BaseSimpleCPU::advancePC(), gem5::BaseSimpleCPU::checkForInterrupts(), gem5::BaseSimpleCPU::preExecute(), and gem5::BaseSimpleCPU::setupFetchRequest().

◆ lastDcacheStall

Counter gem5::SimpleExecContext::lastDcacheStall

Definition at line 81 of file exec_context.hh.

◆ lastIcacheStall

Counter gem5::SimpleExecContext::lastIcacheStall

Definition at line 79 of file exec_context.hh.

◆ numInst

Counter gem5::SimpleExecContext::numInst

PER-THREAD STATS.

Definition at line 74 of file exec_context.hh.

Referenced by gem5::BaseSimpleCPU::countInst(), gem5::TimingSimpleCPU::htmSendAbortSignal(), gem5::TimingSimpleCPU::initiateMemMgmtCmd(), and gem5::BaseSimpleCPU::serviceInstCountEvents().

◆ numLoad

Counter gem5::SimpleExecContext::numLoad

Definition at line 77 of file exec_context.hh.

Referenced by gem5::BaseSimpleCPU::postExecute().

◆ numOp

Counter gem5::SimpleExecContext::numOp

Definition at line 75 of file exec_context.hh.

Referenced by gem5::BaseSimpleCPU::countInst().

◆ predPC

std::unique_ptr<PCStateBase> gem5::SimpleExecContext::predPC

Definition at line 71 of file exec_context.hh.

Referenced by gem5::BaseSimpleCPU::advancePC(), and gem5::BaseSimpleCPU::preExecute().

◆ stayAtPC

bool gem5::SimpleExecContext::stayAtPC

Definition at line 68 of file exec_context.hh.

Referenced by gem5::TimingSimpleCPU::advanceInst(), gem5::AtomicSimpleCPU::isCpuDrained(), gem5::TimingSimpleCPU::isCpuDrained(), gem5::BaseSimpleCPU::preExecute(), gem5::TimingSimpleCPU::switchOut(), and gem5::AtomicSimpleCPU::tick().

◆ thread

SimpleThread* gem5::SimpleExecContext::thread

Definition at line 62 of file exec_context.hh.

The documentation for this class was generated from the following file:

cpu/simple/exec_context.hh

Classes

Public Member Functions

Public Attributes

Detailed Description

Constructor & Destructor Documentation

◆ SimpleExecContext()

Member Function Documentation

◆ amoMem()

◆ armMonitor()

◆ demapPage()

◆ getAddrMonitor()

◆ getHtmTransactionalDepth()

◆ getHtmTransactionUid()

◆ getRegOperand() [1/2]

◆ getRegOperand() [2/2]

◆ getWritableRegOperand()

◆ inHtmTransactionalState()

◆ initiateMemAMO()

◆ initiateMemMgmtCmd()

◆ initiateMemRead()

◆ mwait()

◆ mwaitAtomic()

◆ newHtmTransactionUid()

◆ pcState() [1/2]

◆ pcState() [2/2]

◆ readMem()

◆ readMemAccPredicate()

◆ readMiscReg()

◆ readMiscRegOperand()

◆ readPredicate()

◆ readStCondFailures()

◆ setMemAccPredicate()

◆ setMiscReg()

◆ setMiscRegOperand()

◆ setPredicate()

◆ setRegOperand() [1/2]

◆ setRegOperand() [2/2]

◆ setStCondFailures()

◆ tcBase()

◆ writeMem()

Member Data Documentation

◆ cpu

◆ execContextStats

◆ fetchOffset

◆ lastDcacheStall

◆ lastIcacheStall

◆ numInst

◆ numLoad

◆ numOp

◆ predPC

◆ stayAtPC

◆ thread