gem5  v22.0.0.2
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gem5::SimpleExecContext Class Reference

#include <exec_context.hh>

Inheritance diagram for gem5::SimpleExecContext:
gem5::ExecContext

Classes

struct  ExecContextStats
 

Public Member Functions

 SimpleExecContext (BaseSimpleCPU *_cpu, SimpleThread *_thread)
 Constructor. More...
 
RegVal getRegOperand (const StaticInst *si, int idx) override
 
void getRegOperand (const StaticInst *si, int idx, void *val) override
 
void * getWritableRegOperand (const StaticInst *si, int idx) override
 
void setRegOperand (const StaticInst *si, int idx, RegVal val) override
 
void setRegOperand (const StaticInst *si, int idx, const void *val) override
 
RegVal readMiscRegOperand (const StaticInst *si, int idx) override
 
void setMiscRegOperand (const StaticInst *si, int idx, RegVal val) override
 
RegVal readMiscReg (int misc_reg) override
 Reads a miscellaneous register, handling any architectural side effects due to reading that register. More...
 
void setMiscReg (int misc_reg, RegVal val) override
 Sets a miscellaneous register, handling any architectural side effects due to writing that register. More...
 
const PCStateBasepcState () const override
 
void pcState (const PCStateBase &val) override
 
Fault readMem (Addr addr, uint8_t *data, unsigned int size, Request::Flags flags, const std::vector< bool > &byte_enable) override
 Perform an atomic memory read operation. More...
 
Fault initiateMemRead (Addr addr, unsigned int size, Request::Flags flags, const std::vector< bool > &byte_enable) override
 Initiate a timing memory read operation. More...
 
Fault writeMem (uint8_t *data, unsigned int size, Addr addr, Request::Flags flags, uint64_t *res, const std::vector< bool > &byte_enable) override
 For atomic-mode contexts, perform an atomic memory write operation. More...
 
Fault amoMem (Addr addr, uint8_t *data, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op) override
 For atomic-mode contexts, perform an atomic AMO (a.k.a., Atomic Read-Modify-Write Memory Operation) More...
 
Fault initiateMemAMO (Addr addr, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op) override
 For timing-mode contexts, initiate an atomic AMO (atomic read-modify-write memory operation) More...
 
Fault initiateMemMgmtCmd (Request::Flags flags) override
 Initiate a memory management command with no valid address. More...
 
void setStCondFailures (unsigned int sc_failures) override
 Sets the number of consecutive store conditional failures. More...
 
unsigned int readStCondFailures () const override
 Returns the number of consecutive store conditional failures. More...
 
ThreadContexttcBase () const override
 Returns a pointer to the ThreadContext. More...
 
bool readPredicate () const override
 
void setPredicate (bool val) override
 
bool readMemAccPredicate () const override
 
void setMemAccPredicate (bool val) override
 
uint64_t getHtmTransactionUid () const override
 
uint64_t newHtmTransactionUid () const override
 
bool inHtmTransactionalState () const override
 
uint64_t getHtmTransactionalDepth () const override
 
void demapPage (Addr vaddr, uint64_t asn) override
 Invalidate a page in the DTLB and ITLB. More...
 
void armMonitor (Addr address) override
 
bool mwait (PacketPtr pkt) override
 
void mwaitAtomic (ThreadContext *tc) override
 
AddressMonitor * getAddrMonitor () override
 
Misc Register Interfaces
PC Control
Memory Interface
ARM-Specific Interfaces
X86-Specific Interfaces

Public Attributes

BaseSimpleCPUcpu
 
SimpleThreadthread
 
Addr fetchOffset
 
bool stayAtPC
 
std::unique_ptr< PCStateBasepredPC
 
Counter numInst
 PER-THREAD STATS. More...
 
Counter numOp
 
Counter numLoad
 
Counter lastIcacheStall
 
Counter lastDcacheStall
 
gem5::SimpleExecContext::ExecContextStats execContextStats
 

Detailed Description

Definition at line 60 of file exec_context.hh.

Constructor & Destructor Documentation

◆ SimpleExecContext()

gem5::SimpleExecContext::SimpleExecContext ( BaseSimpleCPU _cpu,
SimpleThread _thread 
)
inline

Constructor.

Definition at line 304 of file exec_context.hh.

Member Function Documentation

◆ amoMem()

Fault gem5::SimpleExecContext::amoMem ( Addr  addr,
uint8_t *  data,
unsigned int  size,
Request::Flags  flags,
AtomicOpFunctorPtr  amo_op 
)
inlineoverridevirtual

For atomic-mode contexts, perform an atomic AMO (a.k.a., Atomic Read-Modify-Write Memory Operation)

Reimplemented from gem5::ExecContext.

Definition at line 438 of file exec_context.hh.

References gem5::X86ISA::addr, gem5::BaseSimpleCPU::amoMem(), cpu, data, and flags.

◆ armMonitor()

void gem5::SimpleExecContext::armMonitor ( Addr  address)
inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 542 of file exec_context.hh.

References cpu, thread, and gem5::SimpleThread::threadId().

◆ demapPage()

void gem5::SimpleExecContext::demapPage ( Addr  vaddr,
uint64_t  asn 
)
inlineoverridevirtual

Invalidate a page in the DTLB and ITLB.

Implements gem5::ExecContext.

Definition at line 536 of file exec_context.hh.

References gem5::SimpleThread::demapPage(), thread, and gem5::MipsISA::vaddr.

◆ getAddrMonitor()

AddressMonitor* gem5::SimpleExecContext::getAddrMonitor ( )
inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 560 of file exec_context.hh.

References cpu, thread, and gem5::SimpleThread::threadId().

◆ getHtmTransactionalDepth()

uint64_t gem5::SimpleExecContext::getHtmTransactionalDepth ( ) const
inlineoverridevirtual

◆ getHtmTransactionUid()

uint64_t gem5::SimpleExecContext::getHtmTransactionUid ( ) const
inlineoverridevirtual

◆ getRegOperand() [1/2]

RegVal gem5::SimpleExecContext::getRegOperand ( const StaticInst si,
int  idx 
)
inlineoverridevirtual

◆ getRegOperand() [2/2]

void gem5::SimpleExecContext::getRegOperand ( const StaticInst si,
int  idx,
void *  val 
)
inlineoverridevirtual

◆ getWritableRegOperand()

void* gem5::SimpleExecContext::getWritableRegOperand ( const StaticInst si,
int  idx 
)
inlineoverridevirtual

◆ inHtmTransactionalState()

bool gem5::SimpleExecContext::inHtmTransactionalState ( ) const
inlineoverridevirtual

◆ initiateMemAMO()

Fault gem5::SimpleExecContext::initiateMemAMO ( Addr  addr,
unsigned int  size,
Request::Flags  flags,
AtomicOpFunctorPtr  amo_op 
)
inlineoverridevirtual

For timing-mode contexts, initiate an atomic AMO (atomic read-modify-write memory operation)

Reimplemented from gem5::ExecContext.

Definition at line 445 of file exec_context.hh.

References gem5::X86ISA::addr, cpu, flags, and gem5::BaseSimpleCPU::initiateMemAMO().

◆ initiateMemMgmtCmd()

Fault gem5::SimpleExecContext::initiateMemMgmtCmd ( Request::Flags  flags)
inlineoverridevirtual

Initiate a memory management command with no valid address.

Currently, these instructions need to bypass squashing in the O3 model Examples include HTM commands and TLBI commands. e.g. tell Ruby we're starting/stopping a HTM transaction, or tell Ruby to issue a TLBI operation

Implements gem5::ExecContext.

Definition at line 453 of file exec_context.hh.

References cpu, flags, and gem5::BaseSimpleCPU::initiateMemMgmtCmd().

◆ initiateMemRead()

Fault gem5::SimpleExecContext::initiateMemRead ( Addr  addr,
unsigned int  size,
Request::Flags  flags,
const std::vector< bool > &  byte_enable 
)
inlineoverridevirtual

Initiate a timing memory read operation.

Must be overridden for exec contexts that support timing memory mode. Not pure virtual since exec contexts that only support atomic memory mode need not override (though in that case this function should never be called).

Reimplemented from gem5::ExecContext.

Definition at line 417 of file exec_context.hh.

References gem5::X86ISA::addr, cpu, flags, and gem5::BaseSimpleCPU::initiateMemRead().

◆ mwait()

bool gem5::SimpleExecContext::mwait ( PacketPtr  pkt)
inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 548 of file exec_context.hh.

References cpu, thread, and gem5::SimpleThread::threadId().

◆ mwaitAtomic()

void gem5::SimpleExecContext::mwaitAtomic ( ThreadContext tc)
inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 554 of file exec_context.hh.

References cpu, gem5::SimpleThread::mmu, thread, and gem5::SimpleThread::threadId().

◆ newHtmTransactionUid()

uint64_t gem5::SimpleExecContext::newHtmTransactionUid ( ) const
inlineoverridevirtual

◆ pcState() [1/2]

const PCStateBase& gem5::SimpleExecContext::pcState ( ) const
inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 395 of file exec_context.hh.

References gem5::SimpleThread::pcState(), and thread.

◆ pcState() [2/2]

void gem5::SimpleExecContext::pcState ( const PCStateBase val)
inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 401 of file exec_context.hh.

References gem5::SimpleThread::pcState(), thread, and gem5::X86ISA::val.

◆ readMem()

Fault gem5::SimpleExecContext::readMem ( Addr  addr,
uint8_t *  data,
unsigned int  size,
Request::Flags  flags,
const std::vector< bool > &  byte_enable 
)
inlineoverridevirtual

Perform an atomic memory read operation.

Must be overridden for exec contexts that support atomic memory mode. Not pure virtual since exec contexts that only support timing memory mode need not override (though in that case this function should never be called).

Reimplemented from gem5::ExecContext.

Definition at line 407 of file exec_context.hh.

References gem5::X86ISA::addr, cpu, data, flags, and gem5::BaseSimpleCPU::readMem().

◆ readMemAccPredicate()

bool gem5::SimpleExecContext::readMemAccPredicate ( ) const
inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 496 of file exec_context.hh.

References gem5::SimpleThread::readMemAccPredicate(), and thread.

◆ readMiscReg()

RegVal gem5::SimpleExecContext::readMiscReg ( int  misc_reg)
inlineoverridevirtual

Reads a miscellaneous register, handling any architectural side effects due to reading that register.

Implements gem5::ExecContext.

Definition at line 377 of file exec_context.hh.

References execContextStats, gem5::SimpleExecContext::ExecContextStats::numMiscRegReads, gem5::SimpleThread::readMiscReg(), and thread.

◆ readMiscRegOperand()

RegVal gem5::SimpleExecContext::readMiscRegOperand ( const StaticInst si,
int  idx 
)
inlineoverridevirtual

◆ readPredicate()

bool gem5::SimpleExecContext::readPredicate ( ) const
inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 480 of file exec_context.hh.

References gem5::SimpleThread::readPredicate(), and thread.

◆ readStCondFailures()

unsigned int gem5::SimpleExecContext::readStCondFailures ( ) const
inlineoverridevirtual

Returns the number of consecutive store conditional failures.

Implements gem5::ExecContext.

Definition at line 471 of file exec_context.hh.

References gem5::SimpleThread::readStCondFailures(), and thread.

◆ setMemAccPredicate()

void gem5::SimpleExecContext::setMemAccPredicate ( bool  val)
inlineoverridevirtual

◆ setMiscReg()

void gem5::SimpleExecContext::setMiscReg ( int  misc_reg,
RegVal  val 
)
inlineoverridevirtual

Sets a miscellaneous register, handling any architectural side effects due to writing that register.

Implements gem5::ExecContext.

Definition at line 388 of file exec_context.hh.

References execContextStats, gem5::SimpleExecContext::ExecContextStats::numMiscRegWrites, gem5::SimpleThread::setMiscReg(), thread, and gem5::X86ISA::val.

◆ setMiscRegOperand()

void gem5::SimpleExecContext::setMiscRegOperand ( const StaticInst si,
int  idx,
RegVal  val 
)
inlineoverridevirtual

◆ setPredicate()

void gem5::SimpleExecContext::setPredicate ( bool  val)
inlineoverridevirtual

◆ setRegOperand() [1/2]

void gem5::SimpleExecContext::setRegOperand ( const StaticInst si,
int  idx,
const void *  val 
)
inlineoverridevirtual

◆ setRegOperand() [2/2]

void gem5::SimpleExecContext::setRegOperand ( const StaticInst si,
int  idx,
RegVal  val 
)
inlineoverridevirtual

◆ setStCondFailures()

void gem5::SimpleExecContext::setStCondFailures ( unsigned int  sc_failures)
inlineoverridevirtual

Sets the number of consecutive store conditional failures.

Implements gem5::ExecContext.

Definition at line 462 of file exec_context.hh.

References gem5::SimpleThread::setStCondFailures(), and thread.

◆ tcBase()

ThreadContext* gem5::SimpleExecContext::tcBase ( ) const
inlineoverridevirtual

Returns a pointer to the ThreadContext.

Implements gem5::ExecContext.

Definition at line 477 of file exec_context.hh.

References gem5::SimpleThread::getTC(), and thread.

Referenced by getHtmTransactionUid(), and newHtmTransactionUid().

◆ writeMem()

Fault gem5::SimpleExecContext::writeMem ( uint8_t *  data,
unsigned int  size,
Addr  addr,
Request::Flags  flags,
uint64_t *  res,
const std::vector< bool > &  byte_enable 
)
inlineoverridevirtual

For atomic-mode contexts, perform an atomic memory write operation.

For timing-mode contexts, initiate a timing memory write operation.

Implements gem5::ExecContext.

Definition at line 427 of file exec_context.hh.

References gem5::X86ISA::addr, cpu, data, flags, and gem5::BaseSimpleCPU::writeMem().

Member Data Documentation

◆ cpu

BaseSimpleCPU* gem5::SimpleExecContext::cpu

◆ execContextStats

gem5::SimpleExecContext::ExecContextStats gem5::SimpleExecContext::execContextStats

◆ fetchOffset

Addr gem5::SimpleExecContext::fetchOffset

◆ lastDcacheStall

Counter gem5::SimpleExecContext::lastDcacheStall

Definition at line 83 of file exec_context.hh.

◆ lastIcacheStall

Counter gem5::SimpleExecContext::lastIcacheStall

Definition at line 81 of file exec_context.hh.

◆ numInst

Counter gem5::SimpleExecContext::numInst

◆ numLoad

Counter gem5::SimpleExecContext::numLoad

Definition at line 79 of file exec_context.hh.

Referenced by gem5::BaseSimpleCPU::postExecute().

◆ numOp

Counter gem5::SimpleExecContext::numOp

Definition at line 77 of file exec_context.hh.

Referenced by gem5::BaseSimpleCPU::countInst().

◆ predPC

std::unique_ptr<PCStateBase> gem5::SimpleExecContext::predPC

◆ stayAtPC

bool gem5::SimpleExecContext::stayAtPC

◆ thread

SimpleThread* gem5::SimpleExecContext::thread

The documentation for this class was generated from the following file:

Generated on Thu Jul 28 2022 13:33:13 for gem5 by doxygen 1.8.17