gem5
v22.1.0.0
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#include <exec_context.hh>
Classes | |
struct | ExecContextStats |
Public Member Functions | |
SimpleExecContext (BaseSimpleCPU *_cpu, SimpleThread *_thread) | |
Constructor. More... | |
RegVal | getRegOperand (const StaticInst *si, int idx) override |
void | getRegOperand (const StaticInst *si, int idx, void *val) override |
void * | getWritableRegOperand (const StaticInst *si, int idx) override |
void | setRegOperand (const StaticInst *si, int idx, RegVal val) override |
void | setRegOperand (const StaticInst *si, int idx, const void *val) override |
RegVal | readMiscRegOperand (const StaticInst *si, int idx) override |
void | setMiscRegOperand (const StaticInst *si, int idx, RegVal val) override |
RegVal | readMiscReg (int misc_reg) override |
Reads a miscellaneous register, handling any architectural side effects due to reading that register. More... | |
void | setMiscReg (int misc_reg, RegVal val) override |
Sets a miscellaneous register, handling any architectural side effects due to writing that register. More... | |
const PCStateBase & | pcState () const override |
void | pcState (const PCStateBase &val) override |
Fault | readMem (Addr addr, uint8_t *data, unsigned int size, Request::Flags flags, const std::vector< bool > &byte_enable) override |
Perform an atomic memory read operation. More... | |
Fault | initiateMemRead (Addr addr, unsigned int size, Request::Flags flags, const std::vector< bool > &byte_enable) override |
Initiate a timing memory read operation. More... | |
Fault | writeMem (uint8_t *data, unsigned int size, Addr addr, Request::Flags flags, uint64_t *res, const std::vector< bool > &byte_enable) override |
For atomic-mode contexts, perform an atomic memory write operation. More... | |
Fault | amoMem (Addr addr, uint8_t *data, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op) override |
For atomic-mode contexts, perform an atomic AMO (a.k.a., Atomic Read-Modify-Write Memory Operation) More... | |
Fault | initiateMemAMO (Addr addr, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op) override |
For timing-mode contexts, initiate an atomic AMO (atomic read-modify-write memory operation) More... | |
Fault | initiateMemMgmtCmd (Request::Flags flags) override |
Initiate a memory management command with no valid address. More... | |
void | setStCondFailures (unsigned int sc_failures) override |
Sets the number of consecutive store conditional failures. More... | |
unsigned int | readStCondFailures () const override |
Returns the number of consecutive store conditional failures. More... | |
ThreadContext * | tcBase () const override |
Returns a pointer to the ThreadContext. More... | |
bool | readPredicate () const override |
void | setPredicate (bool val) override |
bool | readMemAccPredicate () const override |
void | setMemAccPredicate (bool val) override |
uint64_t | getHtmTransactionUid () const override |
uint64_t | newHtmTransactionUid () const override |
bool | inHtmTransactionalState () const override |
uint64_t | getHtmTransactionalDepth () const override |
void | demapPage (Addr vaddr, uint64_t asn) override |
Invalidate a page in the DTLB and ITLB. More... | |
void | armMonitor (Addr address) override |
bool | mwait (PacketPtr pkt) override |
void | mwaitAtomic (ThreadContext *tc) override |
AddressMonitor * | getAddrMonitor () override |
Misc Register Interfaces | |
PC Control | |
Memory Interface | |
ARM-Specific Interfaces | |
X86-Specific Interfaces |
Public Attributes | |
BaseSimpleCPU * | cpu |
SimpleThread * | thread |
Addr | fetchOffset |
bool | stayAtPC |
std::unique_ptr< PCStateBase > | predPC |
Counter | numInst |
PER-THREAD STATS. More... | |
Counter | numOp |
Counter | numLoad |
Counter | lastIcacheStall |
Counter | lastDcacheStall |
gem5::SimpleExecContext::ExecContextStats | execContextStats |
Definition at line 58 of file exec_context.hh.
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inline |
Constructor.
Definition at line 302 of file exec_context.hh.
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inlineoverridevirtual |
For atomic-mode contexts, perform an atomic AMO (a.k.a., Atomic Read-Modify-Write Memory Operation)
Reimplemented from gem5::ExecContext.
Definition at line 436 of file exec_context.hh.
References gem5::X86ISA::addr, gem5::BaseSimpleCPU::amoMem(), cpu, data, and flags.
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inlineoverridevirtual |
Implements gem5::ExecContext.
Definition at line 540 of file exec_context.hh.
References gem5::BaseCPU::armMonitor(), cpu, thread, and gem5::SimpleThread::threadId().
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inlineoverridevirtual |
Invalidate a page in the DTLB and ITLB.
Implements gem5::ExecContext.
Definition at line 534 of file exec_context.hh.
References gem5::SimpleThread::demapPage(), thread, and gem5::MipsISA::vaddr.
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inlineoverridevirtual |
Implements gem5::ExecContext.
Definition at line 558 of file exec_context.hh.
References cpu, gem5::BaseCPU::getCpuAddrMonitor(), thread, and gem5::SimpleThread::threadId().
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inlineoverridevirtual |
Implements gem5::ExecContext.
Definition at line 524 of file exec_context.hh.
References gem5::SimpleThread::htmTransactionStarts, gem5::SimpleThread::htmTransactionStops, and thread.
Referenced by inHtmTransactionalState().
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inlineoverridevirtual |
Implements gem5::ExecContext.
Definition at line 506 of file exec_context.hh.
References gem5::ThreadContext::getHtmCheckpointPtr(), and tcBase().
Referenced by gem5::TimingSimpleCPU::advanceInst(), gem5::TimingSimpleCPU::completeDataAccess(), gem5::TimingSimpleCPU::initiateMemMgmtCmd(), gem5::TimingSimpleCPU::sendData(), and gem5::TimingSimpleCPU::sendSplitData().
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inlineoverridevirtual |
Implements gem5::ExecContext.
Definition at line 309 of file exec_context.hh.
References execContextStats, gem5::SimpleThread::getReg(), gem5::InvalidRegClass, gem5::SimpleExecContext::ExecContextStats::numRegReads, gem5::X86ISA::reg, gem5::ArmISA::si, and thread.
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inlineoverridevirtual |
Implements gem5::ExecContext.
Definition at line 319 of file exec_context.hh.
References execContextStats, gem5::SimpleThread::getReg(), gem5::SimpleExecContext::ExecContextStats::numRegReads, gem5::X86ISA::reg, gem5::ArmISA::si, thread, and gem5::X86ISA::val.
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inlineoverridevirtual |
Implements gem5::ExecContext.
Definition at line 327 of file exec_context.hh.
References execContextStats, gem5::SimpleThread::getWritableReg(), gem5::SimpleExecContext::ExecContextStats::numRegWrites, gem5::X86ISA::reg, gem5::ArmISA::si, and thread.
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inlineoverridevirtual |
Implements gem5::ExecContext.
Definition at line 518 of file exec_context.hh.
References getHtmTransactionalDepth().
Referenced by gem5::TimingSimpleCPU::advanceInst(), gem5::BaseSimpleCPU::checkForInterrupts(), gem5::TimingSimpleCPU::completeDataAccess(), gem5::TimingSimpleCPU::completeIfetch(), gem5::TimingSimpleCPU::sendData(), gem5::TimingSimpleCPU::sendSplitData(), and gem5::TimingSimpleCPU::switchOut().
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inlineoverridevirtual |
For timing-mode contexts, initiate an atomic AMO (atomic read-modify-write memory operation)
Reimplemented from gem5::ExecContext.
Definition at line 443 of file exec_context.hh.
References gem5::X86ISA::addr, cpu, flags, and gem5::BaseSimpleCPU::initiateMemAMO().
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inlineoverridevirtual |
Initiate a memory management command with no valid address.
Currently, these instructions need to bypass squashing in the O3 model Examples include HTM commands and TLBI commands. e.g. tell Ruby we're starting/stopping a HTM transaction, or tell Ruby to issue a TLBI operation
Implements gem5::ExecContext.
Definition at line 451 of file exec_context.hh.
References cpu, flags, and gem5::BaseSimpleCPU::initiateMemMgmtCmd().
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inlineoverridevirtual |
Initiate a timing memory read operation.
Must be overridden for exec contexts that support timing memory mode. Not pure virtual since exec contexts that only support atomic memory mode need not override (though in that case this function should never be called).
Reimplemented from gem5::ExecContext.
Definition at line 415 of file exec_context.hh.
References gem5::X86ISA::addr, cpu, flags, and gem5::BaseSimpleCPU::initiateMemRead().
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inlineoverridevirtual |
Implements gem5::ExecContext.
Definition at line 546 of file exec_context.hh.
References cpu, gem5::BaseCPU::mwait(), thread, and gem5::SimpleThread::threadId().
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inlineoverridevirtual |
Implements gem5::ExecContext.
Definition at line 552 of file exec_context.hh.
References cpu, gem5::SimpleThread::mmu, gem5::BaseCPU::mwaitAtomic(), thread, and gem5::SimpleThread::threadId().
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inlineoverridevirtual |
Implements gem5::ExecContext.
Definition at line 512 of file exec_context.hh.
References gem5::ThreadContext::getHtmCheckpointPtr(), and tcBase().
Referenced by gem5::TimingSimpleCPU::completeIfetch().
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inlineoverridevirtual |
Implements gem5::ExecContext.
Definition at line 393 of file exec_context.hh.
References gem5::SimpleThread::pcState(), and thread.
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inlineoverridevirtual |
Implements gem5::ExecContext.
Definition at line 399 of file exec_context.hh.
References gem5::SimpleThread::pcState(), thread, and gem5::X86ISA::val.
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inlineoverridevirtual |
Perform an atomic memory read operation.
Must be overridden for exec contexts that support atomic memory mode. Not pure virtual since exec contexts that only support timing memory mode need not override (though in that case this function should never be called).
Reimplemented from gem5::ExecContext.
Definition at line 405 of file exec_context.hh.
References gem5::X86ISA::addr, cpu, data, flags, and gem5::BaseSimpleCPU::readMem().
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inlineoverridevirtual |
Implements gem5::ExecContext.
Definition at line 494 of file exec_context.hh.
References gem5::SimpleThread::readMemAccPredicate(), and thread.
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inlineoverridevirtual |
Reads a miscellaneous register, handling any architectural side effects due to reading that register.
Implements gem5::ExecContext.
Definition at line 375 of file exec_context.hh.
References execContextStats, gem5::SimpleExecContext::ExecContextStats::numMiscRegReads, gem5::SimpleThread::readMiscReg(), and thread.
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inlineoverridevirtual |
Implements gem5::ExecContext.
Definition at line 353 of file exec_context.hh.
References execContextStats, gem5::MiscRegClass, gem5::SimpleExecContext::ExecContextStats::numMiscRegReads, gem5::SimpleThread::readMiscReg(), gem5::X86ISA::reg, gem5::ArmISA::si, and thread.
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inlineoverridevirtual |
Implements gem5::ExecContext.
Definition at line 478 of file exec_context.hh.
References gem5::SimpleThread::readPredicate(), and thread.
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inlineoverridevirtual |
Returns the number of consecutive store conditional failures.
Implements gem5::ExecContext.
Definition at line 469 of file exec_context.hh.
References gem5::SimpleThread::readStCondFailures(), and thread.
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inlineoverridevirtual |
Implements gem5::ExecContext.
Definition at line 500 of file exec_context.hh.
References gem5::SimpleThread::setMemAccPredicate(), thread, and gem5::X86ISA::val.
Referenced by gem5::BaseSimpleCPU::preExecute().
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inlineoverridevirtual |
Sets a miscellaneous register, handling any architectural side effects due to writing that register.
Implements gem5::ExecContext.
Definition at line 386 of file exec_context.hh.
References execContextStats, gem5::SimpleExecContext::ExecContextStats::numMiscRegWrites, gem5::SimpleThread::setMiscReg(), thread, and gem5::X86ISA::val.
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inlineoverridevirtual |
Implements gem5::ExecContext.
Definition at line 362 of file exec_context.hh.
References execContextStats, gem5::MiscRegClass, gem5::SimpleExecContext::ExecContextStats::numMiscRegWrites, gem5::X86ISA::reg, gem5::SimpleThread::setMiscReg(), gem5::ArmISA::si, thread, and gem5::X86ISA::val.
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inlineoverridevirtual |
Implements gem5::ExecContext.
Definition at line 484 of file exec_context.hh.
References cpu, gem5::SimpleThread::setPredicate(), gem5::trace::InstRecord::setPredicate(), thread, gem5::BaseSimpleCPU::traceData, and gem5::X86ISA::val.
Referenced by gem5::BaseSimpleCPU::preExecute().
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inlineoverridevirtual |
Implements gem5::ExecContext.
Definition at line 345 of file exec_context.hh.
References execContextStats, gem5::SimpleExecContext::ExecContextStats::numRegWrites, gem5::X86ISA::reg, gem5::SimpleThread::setReg(), gem5::ArmISA::si, thread, and gem5::X86ISA::val.
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inlineoverridevirtual |
Implements gem5::ExecContext.
Definition at line 335 of file exec_context.hh.
References execContextStats, gem5::InvalidRegClass, gem5::SimpleExecContext::ExecContextStats::numRegWrites, gem5::X86ISA::reg, gem5::SimpleThread::setReg(), gem5::ArmISA::si, thread, and gem5::X86ISA::val.
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inlineoverridevirtual |
Sets the number of consecutive store conditional failures.
Implements gem5::ExecContext.
Definition at line 460 of file exec_context.hh.
References gem5::SimpleThread::setStCondFailures(), and thread.
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inlineoverridevirtual |
Returns a pointer to the ThreadContext.
Implements gem5::ExecContext.
Definition at line 475 of file exec_context.hh.
References gem5::SimpleThread::getTC(), and thread.
Referenced by getHtmTransactionUid(), and newHtmTransactionUid().
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inlineoverridevirtual |
For atomic-mode contexts, perform an atomic memory write operation.
For timing-mode contexts, initiate a timing memory write operation.
Implements gem5::ExecContext.
Definition at line 425 of file exec_context.hh.
References gem5::X86ISA::addr, cpu, data, flags, and gem5::BaseSimpleCPU::writeMem().
BaseSimpleCPU* gem5::SimpleExecContext::cpu |
Definition at line 61 of file exec_context.hh.
Referenced by amoMem(), armMonitor(), gem5::SimpleExecContext::ExecContextStats::ExecContextStats(), getAddrMonitor(), initiateMemAMO(), initiateMemMgmtCmd(), initiateMemRead(), mwait(), mwaitAtomic(), readMem(), setPredicate(), and writeMem().
gem5::SimpleExecContext::ExecContextStats gem5::SimpleExecContext::execContextStats |
Addr gem5::SimpleExecContext::fetchOffset |
Definition at line 65 of file exec_context.hh.
Referenced by gem5::BaseSimpleCPU::advancePC(), gem5::BaseSimpleCPU::checkForInterrupts(), gem5::BaseSimpleCPU::preExecute(), and gem5::BaseSimpleCPU::setupFetchRequest().
Counter gem5::SimpleExecContext::lastDcacheStall |
Definition at line 81 of file exec_context.hh.
Counter gem5::SimpleExecContext::lastIcacheStall |
Definition at line 79 of file exec_context.hh.
Counter gem5::SimpleExecContext::numInst |
PER-THREAD STATS.
Definition at line 74 of file exec_context.hh.
Referenced by gem5::BaseSimpleCPU::countInst(), gem5::TimingSimpleCPU::htmSendAbortSignal(), gem5::TimingSimpleCPU::initiateMemMgmtCmd(), and gem5::BaseSimpleCPU::serviceInstCountEvents().
Counter gem5::SimpleExecContext::numLoad |
Definition at line 77 of file exec_context.hh.
Referenced by gem5::BaseSimpleCPU::postExecute().
Counter gem5::SimpleExecContext::numOp |
Definition at line 75 of file exec_context.hh.
Referenced by gem5::BaseSimpleCPU::countInst().
std::unique_ptr<PCStateBase> gem5::SimpleExecContext::predPC |
Definition at line 71 of file exec_context.hh.
Referenced by gem5::BaseSimpleCPU::advancePC(), and gem5::BaseSimpleCPU::preExecute().
bool gem5::SimpleExecContext::stayAtPC |
Definition at line 68 of file exec_context.hh.
Referenced by gem5::TimingSimpleCPU::advanceInst(), gem5::AtomicSimpleCPU::isCpuDrained(), gem5::TimingSimpleCPU::isCpuDrained(), gem5::BaseSimpleCPU::preExecute(), gem5::TimingSimpleCPU::switchOut(), and gem5::AtomicSimpleCPU::tick().
SimpleThread* gem5::SimpleExecContext::thread |
Definition at line 62 of file exec_context.hh.
Referenced by gem5::BaseSimpleCPU::advancePC(), gem5::AtomicSimpleCPU::amoMem(), armMonitor(), gem5::BaseSimpleCPU::checkForInterrupts(), gem5::TimingSimpleCPU::completeDataAccess(), gem5::TimingSimpleCPU::completeIfetch(), demapPage(), gem5::TimingSimpleCPU::fetch(), getAddrMonitor(), getHtmTransactionalDepth(), getRegOperand(), getWritableRegOperand(), gem5::TimingSimpleCPU::handleReadPacket(), gem5::TimingSimpleCPU::handleWritePacket(), gem5::TimingSimpleCPU::htmSendAbortSignal(), gem5::TimingSimpleCPU::initiateMemAMO(), gem5::TimingSimpleCPU::initiateMemMgmtCmd(), gem5::TimingSimpleCPU::initiateMemRead(), gem5::AtomicSimpleCPU::isCpuDrained(), gem5::TimingSimpleCPU::isCpuDrained(), mwait(), mwaitAtomic(), pcState(), gem5::BaseSimpleCPU::preExecute(), gem5::AtomicSimpleCPU::readMem(), readMemAccPredicate(), readMiscReg(), readMiscRegOperand(), readPredicate(), readStCondFailures(), gem5::TimingSimpleCPU::sendData(), gem5::BaseSimpleCPU::serviceInstCountEvents(), setMemAccPredicate(), setMiscReg(), setMiscRegOperand(), setPredicate(), setRegOperand(), setStCondFailures(), gem5::BaseSimpleCPU::setupFetchRequest(), gem5::TimingSimpleCPU::switchOut(), tcBase(), gem5::AtomicSimpleCPU::tick(), gem5::AtomicSimpleCPU::writeMem(), and gem5::TimingSimpleCPU::writeMem().