gem5  v21.1.0.2
atomic.cc
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41 
42 #include "cpu/simple/atomic.hh"
43 
44 #include "arch/locked_mem.hh"
45 #include "base/output.hh"
46 #include "config/the_isa.hh"
47 #include "cpu/exetrace.hh"
48 #include "cpu/utils.hh"
49 #include "debug/Drain.hh"
50 #include "debug/ExecFaulting.hh"
51 #include "debug/SimpleCPU.hh"
52 #include "mem/packet.hh"
53 #include "mem/packet_access.hh"
54 #include "mem/physical.hh"
55 #include "params/AtomicSimpleCPU.hh"
56 #include "sim/faults.hh"
57 #include "sim/full_system.hh"
58 #include "sim/system.hh"
59 
60 namespace gem5
61 {
62 
63 void
65 {
67 
68  int cid = threadContexts[0]->contextId();
69  ifetch_req->setContext(cid);
70  data_read_req->setContext(cid);
71  data_write_req->setContext(cid);
72  data_amo_req->setContext(cid);
73 }
74 
75 AtomicSimpleCPU::AtomicSimpleCPU(const AtomicSimpleCPUParams &p)
76  : BaseSimpleCPU(p),
77  tickEvent([this]{ tick(); }, "AtomicSimpleCPU tick",
78  false, Event::CPU_Tick_Pri),
79  width(p.width), locked(false),
80  simulate_data_stalls(p.simulate_data_stalls),
81  simulate_inst_stalls(p.simulate_inst_stalls),
82  icachePort(name() + ".icache_port", this),
83  dcachePort(name() + ".dcache_port", this),
84  dcache_access(false), dcache_latency(0),
85  ppCommit(nullptr)
86 {
87  _status = Idle;
88  ifetch_req = std::make_shared<Request>();
89  data_read_req = std::make_shared<Request>();
90  data_write_req = std::make_shared<Request>();
91  data_amo_req = std::make_shared<Request>();
92 }
93 
94 
96 {
97  if (tickEvent.scheduled()) {
99  }
100 }
101 
104 {
105  // Deschedule any power gating event (if any)
107 
108  if (switchedOut())
109  return DrainState::Drained;
110 
111  if (!isCpuDrained()) {
112  DPRINTF(Drain, "Requesting drain.\n");
113  return DrainState::Draining;
114  } else {
115  if (tickEvent.scheduled())
117 
118  activeThreads.clear();
119  DPRINTF(Drain, "Not executing microcode, no need to drain.\n");
120  return DrainState::Drained;
121  }
122 }
123 
124 void
126 {
127  DPRINTF(SimpleCPU, "%s received snoop pkt for addr:%#x %s\n",
128  __func__, pkt->getAddr(), pkt->cmdString());
129 
130  for (ThreadID tid = 0; tid < numThreads; tid++) {
131  if (tid != sender) {
132  if (getCpuAddrMonitor(tid)->doMonitor(pkt)) {
133  wakeup(tid);
134  }
135 
138  }
139  }
140 }
141 
142 void
144 {
145  assert(!tickEvent.scheduled());
146  if (switchedOut())
147  return;
148 
149  DPRINTF(SimpleCPU, "Resume\n");
151 
152  assert(!threadContexts.empty());
153 
155 
156  for (ThreadID tid = 0; tid < numThreads; tid++) {
157  if (threadInfo[tid]->thread->status() == ThreadContext::Active) {
158  threadInfo[tid]->execContextStats.notIdleFraction = 1;
159  activeThreads.push_back(tid);
161 
162  // Tick if any threads active
163  if (!tickEvent.scheduled()) {
165  }
166  } else {
167  threadInfo[tid]->execContextStats.notIdleFraction = 0;
168  }
169  }
170 
171  // Reschedule any power gating event (if any)
173 }
174 
175 bool
177 {
179  return false;
180 
181  DPRINTF(Drain, "tryCompleteDrain.\n");
182  if (!isCpuDrained())
183  return false;
184 
185  DPRINTF(Drain, "CPU done draining, processing drain event\n");
186  signalDrainDone();
187 
188  return true;
189 }
190 
191 
192 void
194 {
196 
197  assert(!tickEvent.scheduled());
198  assert(_status == BaseSimpleCPU::Running || _status == Idle);
199  assert(isCpuDrained());
200 }
201 
202 
203 void
205 {
207 
208  // The tick event should have been descheduled by drain()
209  assert(!tickEvent.scheduled());
210 }
211 
212 void
214 {
216  "The atomic CPU requires the memory system to be in "
217  "'atomic' mode.");
218 }
219 
220 void
222 {
223  DPRINTF(SimpleCPU, "ActivateContext %d\n", thread_num);
224 
225  assert(thread_num < numThreads);
226 
227  threadInfo[thread_num]->execContextStats.notIdleFraction = 1;
228  Cycles delta = ticksToCycles(threadInfo[thread_num]->thread->lastActivate -
229  threadInfo[thread_num]->thread->lastSuspend);
230  baseStats.numCycles += delta;
231 
232  if (!tickEvent.scheduled()) {
233  //Make sure ticks are still on multiples of cycles
235  }
237  if (std::find(activeThreads.begin(), activeThreads.end(), thread_num) ==
238  activeThreads.end()) {
239  activeThreads.push_back(thread_num);
240  }
241 
242  BaseCPU::activateContext(thread_num);
243 }
244 
245 
246 void
248 {
249  DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num);
250 
251  assert(thread_num < numThreads);
252  activeThreads.remove(thread_num);
253 
254  if (_status == Idle)
255  return;
256 
257  assert(_status == BaseSimpleCPU::Running);
258 
259  threadInfo[thread_num]->execContextStats.notIdleFraction = 0;
260 
261  if (activeThreads.empty()) {
262  _status = Idle;
263 
264  if (tickEvent.scheduled()) {
266  }
267  }
268 
269  BaseCPU::suspendContext(thread_num);
270 }
271 
272 Tick
274 {
275  return port.sendAtomic(pkt);
276 }
277 
278 Tick
280 {
281  DPRINTF(SimpleCPU, "%s received atomic snoop pkt for addr:%#x %s\n",
282  __func__, pkt->getAddr(), pkt->cmdString());
283 
284  // X86 ISA: Snooping an invalidation for monitor/mwait
286 
287  for (ThreadID tid = 0; tid < cpu->numThreads; tid++) {
288  if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) {
289  cpu->wakeup(tid);
290  }
291  }
292 
293  // if snoop invalidates, release any associated locks
294  // When run without caches, Invalidation packets will not be received
295  // hence we must check if the incoming packets are writes and wakeup
296  // the processor accordingly
297  if (pkt->isInvalidate() || pkt->isWrite()) {
298  DPRINTF(SimpleCPU, "received invalidation for addr:%#x\n",
299  pkt->getAddr());
300  for (auto &t_info : cpu->threadInfo) {
301  TheISA::handleLockedSnoop(t_info->thread, pkt, cacheBlockMask);
302  }
303  }
304 
305  return 0;
306 }
307 
308 void
310 {
311  DPRINTF(SimpleCPU, "%s received functional snoop pkt for addr:%#x %s\n",
312  __func__, pkt->getAddr(), pkt->cmdString());
313 
314  // X86 ISA: Snooping an invalidation for monitor/mwait
315  AtomicSimpleCPU *cpu = (AtomicSimpleCPU *)(&owner);
316  for (ThreadID tid = 0; tid < cpu->numThreads; tid++) {
317  if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) {
318  cpu->wakeup(tid);
319  }
320  }
321 
322  // if snoop invalidates, release any associated locks
323  if (pkt->isInvalidate()) {
324  DPRINTF(SimpleCPU, "received invalidation for addr:%#x\n",
325  pkt->getAddr());
326  for (auto &t_info : cpu->threadInfo) {
327  TheISA::handleLockedSnoop(t_info->thread, pkt, cacheBlockMask);
328  }
329  }
330 }
331 
332 bool
334  int size, Request::Flags flags,
335  const std::vector<bool> &byte_enable,
336  int &frag_size, int &size_left) const
337 {
338  bool predicate = true;
339  Addr inst_addr = threadInfo[curThread]->thread->pcState().instAddr();
340 
341  frag_size = std::min(
342  cacheLineSize() - addrBlockOffset(frag_addr, cacheLineSize()),
343  (Addr)size_left);
344  size_left -= frag_size;
345 
346  // Set up byte-enable mask for the current fragment
347  auto it_start = byte_enable.begin() + (size - (frag_size + size_left));
348  auto it_end = byte_enable.begin() + (size - size_left);
349  if (isAnyActiveElement(it_start, it_end)) {
350  req->setVirt(frag_addr, frag_size, flags, dataRequestorId(),
351  inst_addr);
352  req->setByteEnable(std::vector<bool>(it_start, it_end));
353  } else {
354  predicate = false;
355  }
356 
357  return predicate;
358 }
359 
360 Fault
361 AtomicSimpleCPU::readMem(Addr addr, uint8_t *data, unsigned size,
362  Request::Flags flags,
363  const std::vector<bool> &byte_enable)
364 {
366  SimpleThread *thread = t_info.thread;
367 
368  // use the CPU's statically allocated read request and packet objects
369  const RequestPtr &req = data_read_req;
370 
371  if (traceData)
372  traceData->setMem(addr, size, flags);
373 
374  dcache_latency = 0;
375 
376  req->taskId(taskId());
377 
378  Addr frag_addr = addr;
379  int frag_size = 0;
380  int size_left = size;
381  bool predicate;
382  Fault fault = NoFault;
383 
384  while (1) {
385  predicate = genMemFragmentRequest(req, frag_addr, size, flags,
386  byte_enable, frag_size, size_left);
387 
388  // translate to physical address
389  if (predicate) {
390  fault = thread->mmu->translateAtomic(req, thread->getTC(),
391  BaseMMU::Read);
392  }
393 
394  // Now do the access.
395  if (predicate && fault == NoFault &&
396  !req->getFlags().isSet(Request::NO_ACCESS)) {
397  Packet pkt(req, Packet::makeReadCmd(req));
398  pkt.dataStatic(data);
399 
400  if (req->isLocalAccess()) {
401  dcache_latency += req->localAccessor(thread->getTC(), &pkt);
402  } else {
404  }
405  dcache_access = true;
406 
407  assert(!pkt.isError());
408 
409  if (req->isLLSC()) {
410  TheISA::handleLockedRead(thread, req);
411  }
412  }
413 
414  //If there's a fault, return it
415  if (fault != NoFault)
416  return req->isPrefetch() ? NoFault : fault;
417 
418  // If we don't need to access further cache lines, stop now.
419  if (size_left == 0) {
420  if (req->isLockedRMW() && fault == NoFault) {
421  assert(!locked);
422  locked = true;
423  }
424  return fault;
425  }
426 
427  /*
428  * Set up for accessing the next cache line.
429  */
430  frag_addr += frag_size;
431 
432  //Move the pointer we're reading into to the correct location.
433  data += frag_size;
434  }
435 }
436 
437 Fault
438 AtomicSimpleCPU::writeMem(uint8_t *data, unsigned size, Addr addr,
439  Request::Flags flags, uint64_t *res,
440  const std::vector<bool>& byte_enable)
441 {
443  SimpleThread *thread = t_info.thread;
444  static uint8_t zero_array[64] = {};
445 
446  if (data == NULL) {
447  assert(size <= 64);
448  assert(flags & Request::STORE_NO_DATA);
449  // This must be a cache block cleaning request
450  data = zero_array;
451  }
452 
453  // use the CPU's statically allocated write request and packet objects
454  const RequestPtr &req = data_write_req;
455 
456  if (traceData)
457  traceData->setMem(addr, size, flags);
458 
459  dcache_latency = 0;
460 
461  req->taskId(taskId());
462 
463  Addr frag_addr = addr;
464  int frag_size = 0;
465  int size_left = size;
466  int curr_frag_id = 0;
467  bool predicate;
468  Fault fault = NoFault;
469 
470  while (1) {
471  predicate = genMemFragmentRequest(req, frag_addr, size, flags,
472  byte_enable, frag_size, size_left);
473 
474  // translate to physical address
475  if (predicate)
476  fault = thread->mmu->translateAtomic(req, thread->getTC(),
478 
479  // Now do the access.
480  if (predicate && fault == NoFault) {
481  bool do_access = true; // flag to suppress cache access
482 
483  if (req->isLLSC()) {
484  assert(curr_frag_id == 0);
485  do_access =
486  TheISA::handleLockedWrite(thread, req,
488  } else if (req->isSwap()) {
489  assert(curr_frag_id == 0);
490  if (req->isCondSwap()) {
491  assert(res);
492  req->setExtraData(*res);
493  }
494  }
495 
496  if (do_access && !req->getFlags().isSet(Request::NO_ACCESS)) {
497  Packet pkt(req, Packet::makeWriteCmd(req));
498  pkt.dataStatic(data);
499 
500  if (req->isLocalAccess()) {
501  dcache_latency +=
502  req->localAccessor(thread->getTC(), &pkt);
503  } else {
505 
506  // Notify other threads on this CPU of write
507  threadSnoop(&pkt, curThread);
508  }
509  dcache_access = true;
510  assert(!pkt.isError());
511 
512  if (req->isSwap()) {
513  assert(res && curr_frag_id == 0);
514  memcpy(res, pkt.getConstPtr<uint8_t>(), size);
515  }
516  }
517 
518  if (res && !req->isSwap()) {
519  *res = req->getExtraData();
520  }
521  }
522 
523  //If there's a fault or we don't need to access a second cache line,
524  //stop now.
525  if (fault != NoFault || size_left == 0) {
526  if (req->isLockedRMW() && fault == NoFault) {
527  assert(!req->isMasked());
528  locked = false;
529  }
530 
531  //Supress faults from prefetches.
532  return req->isPrefetch() ? NoFault : fault;
533  }
534 
535  /*
536  * Set up for accessing the next cache line.
537  */
538  frag_addr += frag_size;
539 
540  //Move the pointer we're reading into to the correct location.
541  data += frag_size;
542 
543  curr_frag_id++;
544  }
545 }
546 
547 Fault
548 AtomicSimpleCPU::amoMem(Addr addr, uint8_t* data, unsigned size,
549  Request::Flags flags, AtomicOpFunctorPtr amo_op)
550 {
552  SimpleThread *thread = t_info.thread;
553 
554  // use the CPU's statically allocated amo request and packet objects
555  const RequestPtr &req = data_amo_req;
556 
557  if (traceData)
558  traceData->setMem(addr, size, flags);
559 
560  //The address of the second part of this access if it needs to be split
561  //across a cache line boundary.
562  Addr secondAddr = roundDown(addr + size - 1, cacheLineSize());
563 
564  // AMO requests that access across a cache line boundary are not
565  // allowed since the cache does not guarantee AMO ops to be executed
566  // atomically in two cache lines
567  // For ISAs such as x86 that requires AMO operations to work on
568  // accesses that cross cache-line boundaries, the cache needs to be
569  // modified to support locking both cache lines to guarantee the
570  // atomicity.
571  panic_if(secondAddr > addr,
572  "AMO request should not access across a cache line boundary.");
573 
574  dcache_latency = 0;
575 
576  req->taskId(taskId());
577  req->setVirt(addr, size, flags, dataRequestorId(),
578  thread->pcState().instAddr(), std::move(amo_op));
579 
580  // translate to physical address
581  Fault fault = thread->mmu->translateAtomic(
582  req, thread->getTC(), BaseMMU::Write);
583 
584  // Now do the access.
585  if (fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) {
586  // We treat AMO accesses as Write accesses with SwapReq command
587  // data will hold the return data of the AMO access
588  Packet pkt(req, Packet::makeWriteCmd(req));
589  pkt.dataStatic(data);
590 
591  if (req->isLocalAccess()) {
592  dcache_latency += req->localAccessor(thread->getTC(), &pkt);
593  } else {
595  }
596 
597  dcache_access = true;
598 
599  assert(!pkt.isError());
600  assert(!req->isLLSC());
601  }
602 
603  if (fault != NoFault && req->isPrefetch()) {
604  return NoFault;
605  }
606 
607  //If there's a fault and we're not doing prefetch, return it
608  return fault;
609 }
610 
611 void
613 {
614  DPRINTF(SimpleCPU, "Tick\n");
615 
616  // Change thread if multi-threaded
618 
619  // Set memory request ids to current thread
620  if (numThreads > 1) {
621  ContextID cid = threadContexts[curThread]->contextId();
622 
623  ifetch_req->setContext(cid);
624  data_read_req->setContext(cid);
625  data_write_req->setContext(cid);
626  data_amo_req->setContext(cid);
627  }
628 
630  SimpleThread *thread = t_info.thread;
631 
632  Tick latency = 0;
633 
634  for (int i = 0; i < width || locked; ++i) {
637 
641  }
642 
643  // We must have just got suspended by a PC event
644  if (_status == Idle) {
646  return;
647  }
648 
650 
651  Fault fault = NoFault;
652 
653  TheISA::PCState pcState = thread->pcState();
654 
655  bool needToFetch = !isRomMicroPC(pcState.microPC()) &&
657  if (needToFetch) {
658  ifetch_req->taskId(taskId());
660  fault = thread->mmu->translateAtomic(ifetch_req, thread->getTC(),
662  }
663 
664  if (fault == NoFault) {
665  Tick icache_latency = 0;
666  bool icache_access = false;
667  dcache_access = false; // assume no dcache access
668 
669  if (needToFetch) {
670  // This is commented out because the decoder would act like
671  // a tiny cache otherwise. It wouldn't be flushed when needed
672  // like the I cache. It should be flushed, and when that works
673  // this code should be uncommented.
674  //Fetch more instruction memory if necessary
675  //if (decoder.needMoreBytes())
676  //{
677  icache_access = true;
678  icache_latency = fetchInstMem();
679  //}
680  }
681 
682  preExecute();
683 
684  Tick stall_ticks = 0;
685  if (curStaticInst) {
686  fault = curStaticInst->execute(&t_info, traceData);
687 
688  // keep an instruction count
689  if (fault == NoFault) {
690  countInst();
691  ppCommit->notify(std::make_pair(thread, curStaticInst));
692  } else if (traceData) {
693  traceFault();
694  }
695 
696  if (fault != NoFault &&
697  std::dynamic_pointer_cast<SyscallRetryFault>(fault)) {
698  // Retry execution of system calls after a delay.
699  // Prevents immediate re-execution since conditions which
700  // caused the retry are unlikely to change every tick.
701  stall_ticks += clockEdge(syscallRetryLatency) - curTick();
702  }
703 
704  postExecute();
705  }
706 
707  // @todo remove me after debugging with legion done
708  if (curStaticInst && (!curStaticInst->isMicroop() ||
710  instCnt++;
711  }
712 
713  if (simulate_inst_stalls && icache_access)
714  stall_ticks += icache_latency;
715 
717  stall_ticks += dcache_latency;
718 
719  if (stall_ticks) {
720  // the atomic cpu does its accounting in ticks, so
721  // keep counting in ticks but round to the clock
722  // period
723  latency += divCeil(stall_ticks, clockPeriod()) *
724  clockPeriod();
725  }
726 
727  }
728  if (fault != NoFault || !t_info.stayAtPC)
729  advancePC(fault);
730  }
731 
732  if (tryCompleteDrain())
733  return;
734 
735  // instruction takes at least one cycle
736  if (latency < clockPeriod())
737  latency = clockPeriod();
738 
739  if (_status != Idle)
740  reschedule(tickEvent, curTick() + latency, true);
741 }
742 
743 Tick
745 {
746  auto &decoder = threadInfo[curThread]->thread->decoder;
747 
749 
750  // ifetch_req is initialized to read the instruction
751  // directly into the CPU object's inst field.
752  pkt.dataStatic(decoder.moreBytesPtr());
753 
754  Tick latency = sendPacket(icachePort, &pkt);
755  assert(!pkt.isError());
756 
757  return latency;
758 }
759 
760 void
762 {
764 
766  (getProbeManager(), "Commit");
767 }
768 
769 void
771 {
773 }
774 
775 } // namespace gem5
gem5::Packet::makeWriteCmd
static MemCmd makeWriteCmd(const RequestPtr &req)
Generate the appropriate write MemCmd based on the Request flags.
Definition: packet.hh:987
gem5::curTick
Tick curTick()
The universal simulation clock.
Definition: cur_tick.hh:46
gem5::Packet::cmdString
const std::string & cmdString() const
Return the string name of the cmd field (for debugging and tracing).
Definition: packet.hh:577
gem5::AtomicSimpleCPU::tryCompleteDrain
bool tryCompleteDrain()
Try to complete a drain request.
Definition: atomic.cc:176
gem5::BaseMMU::Read
@ Read
Definition: mmu.hh:53
utils.hh
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:260
gem5::ThreadContext::Active
@ Active
Running.
Definition: thread_context.hh:108
gem5::BaseCPU::switchedOut
bool switchedOut() const
Determine if the CPU is switched out.
Definition: base.hh:357
gem5::AtomicSimpleCPU::regProbePoints
void regProbePoints() override
Register probe points for this object.
Definition: atomic.cc:761
gem5::StaticInst::isMicroop
bool isMicroop() const
Definition: static_inst.hh:208
gem5::AtomicSimpleCPU::writeMem
Fault writeMem(uint8_t *data, unsigned size, Addr addr, Request::Flags flags, uint64_t *res, const std::vector< bool > &byte_enable=std::vector< bool >()) override
Definition: atomic.cc:438
gem5::BaseSimpleCPU::threadInfo
std::vector< SimpleExecContext * > threadInfo
Definition: base.hh:100
system.hh
gem5::Trace::InstRecord::setMem
void setMem(Addr a, Addr s, unsigned f)
Definition: insttracer.hh:180
data
const char data[]
Definition: circlebuf.test.cc:48
gem5::AtomicSimpleCPU::simulate_data_stalls
const bool simulate_data_stalls
Definition: atomic.hh:67
gem5::BaseSimpleCPU::traceData
Trace::InstRecord * traceData
Definition: base.hh:97
gem5::AtomicSimpleCPU::width
const int width
Definition: atomic.hh:65
gem5::AtomicSimpleCPU::sendPacket
virtual Tick sendPacket(RequestPort &port, const PacketPtr &pkt)
Definition: atomic.cc:273
gem5::Drainable::drainState
DrainState drainState() const
Return the current drain state of an object.
Definition: drain.hh:324
atomic.hh
gem5::isRomMicroPC
static bool isRomMicroPC(MicroPC upc)
Definition: types.hh:166
gem5::BaseSimpleCPU::_status
Status _status
Definition: base.hh:123
gem5::BaseMMU::Write
@ Write
Definition: mmu.hh:53
gem5::AtomicSimpleCPU::readMem
Fault readMem(Addr addr, uint8_t *data, unsigned size, Request::Flags flags, const std::vector< bool > &byte_enable=std::vector< bool >()) override
Definition: atomic.cc:361
gem5::BaseCPU::cacheLineSize
unsigned int cacheLineSize() const
Get the cache line size of the system.
Definition: base.hh:381
gem5::AddressMonitor::doMonitor
bool doMonitor(PacketPtr pkt)
Definition: base.cc:688
gem5::RequestPort::sendAtomic
Tick sendAtomic(PacketPtr pkt)
Send an atomic request packet, where the data is moved and the state is updated in zero time,...
Definition: port.hh:464
gem5::BaseCPU::updateCycleCounters
void updateCycleCounters(CPUState state)
base method keeping track of cycle progression
Definition: base.hh:523
gem5::System::isAtomicMode
bool isAtomicMode() const
Is the system in atomic mode?
Definition: system.hh:264
gem5::AtomicSimpleCPU::~AtomicSimpleCPU
virtual ~AtomicSimpleCPU()
Definition: atomic.cc:95
gem5::AtomicSimpleCPU::data_read_req
RequestPtr data_read_req
Definition: atomic.hh:166
gem5::BaseSimpleCPU::curStaticInst
StaticInstPtr curStaticInst
Current instruction.
Definition: base.hh:104
exetrace.hh
gem5::ArmISA::a
Bitfield< 8 > a
Definition: misc_types.hh:65
gem5::Packet::isWrite
bool isWrite() const
Definition: packet.hh:583
gem5::BaseCPU::system
System * system
Definition: base.hh:376
gem5::AtomicSimpleCPU::dcachePort
AtomicCPUDPort dcachePort
Definition: atomic.hh:162
gem5::addrBlockOffset
Addr addrBlockOffset(Addr addr, Addr block_size)
Calculates the offset of a given address wrt aligned fixed-size blocks.
Definition: utils.hh:53
gem5::EventManager::schedule
void schedule(Event &event, Tick when)
Definition: eventq.hh:1019
std::vector< bool >
gem5::StaticInst::isDelayedCommit
bool isDelayedCommit() const
Definition: static_inst.hh:209
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
gem5::StaticInst::isFirstMicroop
bool isFirstMicroop() const
Definition: static_inst.hh:211
faults.hh
gem5::BaseCPU::schedulePowerGatingEvent
void schedulePowerGatingEvent()
Definition: base.cc:460
gem5::SimpleThread
The SimpleThread object provides a combination of the ThreadState object and the ThreadContext interf...
Definition: simple_thread.hh:94
output.hh
gem5::AtomicSimpleCPU::printAddr
void printAddr(Addr a)
Print state of address in memory system via PrintReq (for debugging).
Definition: atomic.cc:770
gem5::BaseMMU::Execute
@ Execute
Definition: mmu.hh:53
gem5::AtomicSimpleCPU::AtomicCPUDPort::cacheBlockMask
Addr cacheBlockMask
Definition: atomic.hh:152
gem5::BaseSimpleCPU::checkForInterrupts
void checkForInterrupts()
Definition: base.cc:258
gem5::StaticInst::execute
virtual Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const =0
gem5::AtomicSimpleCPU::init
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: atomic.cc:64
gem5::AtomicSimpleCPU::simulate_inst_stalls
const bool simulate_inst_stalls
Definition: atomic.hh:68
packet.hh
gem5::RequestPort
A RequestPort is a specialisation of a Port, which implements the default protocol for the three diff...
Definition: port.hh:77
gem5::Cycles
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:78
gem5::ArmISA::handleLockedWrite
bool handleLockedWrite(XC *xc, const RequestPtr &req, Addr cacheBlockMask)
Definition: locked_mem.hh:113
gem5::BaseCPU::numThreads
ThreadID numThreads
Number of threads we're actually simulating (<= SMT_MAX_THREADS).
Definition: base.hh:368
gem5::SimpleThread::mmu
BaseMMU * mmu
Definition: simple_thread.hh:134
gem5::Packet::dataStatic
void dataStatic(T *p)
Set the data pointer to the following value that should not be freed.
Definition: packet.hh:1134
gem5::BaseCPU::deschedulePowerGatingEvent
void deschedulePowerGatingEvent()
Definition: base.cc:452
gem5::AtomicSimpleCPU
Definition: atomic.hh:53
gem5::Flags< FlagsType >
gem5::DrainState
DrainState
Object drain/handover states.
Definition: drain.hh:74
gem5::BaseCPU::suspendContext
virtual void suspendContext(ThreadID thread_num)
Notify the CPU that the indicated context is now suspended.
Definition: base.cc:502
gem5::BaseCPU::baseStats
gem5::BaseCPU::BaseCPUStats baseStats
gem5::BaseCPU::taskId
uint32_t taskId() const
Get cpu task id.
Definition: base.hh:212
gem5::BaseSimpleCPU::checkPcEventQueue
void checkPcEventQueue()
Definition: base.cc:133
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::AtomicSimpleCPU::suspendContext
void suspendContext(ThreadID thread_num) override
Notify the CPU that the indicated context is now suspended.
Definition: atomic.cc:247
gem5::ArmISA::width
Bitfield< 4 > width
Definition: misc_types.hh:71
gem5::AtomicSimpleCPU::takeOverFrom
void takeOverFrom(BaseCPU *old_cpu) override
Load the state of a CPU from the previous CPU object, invoked on all new CPUs that are about to be sw...
Definition: atomic.cc:204
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::AtomicSimpleCPU::data_amo_req
RequestPtr data_amo_req
Definition: atomic.hh:168
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::BaseSimpleCPU::preExecute
void preExecute()
Definition: base.cc:313
gem5::BaseCPU::BaseCPUStats::numCycles
statistics::Scalar numCycles
Definition: base.hh:597
gem5::MipsISA::PCState
GenericISA::DelaySlotPCState< 4 > PCState
Definition: pcstate.hh:40
gem5::probing::Packet
ProbePointArg< PacketInfo > Packet
Packet probe point.
Definition: mem.hh:109
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::AtomicSimpleCPU::AtomicCPUDPort::cpu
BaseSimpleCPU * cpu
Definition: atomic.hh:154
gem5::AtomicSimpleCPU::fetchInstMem
virtual Tick fetchInstMem()
Definition: atomic.cc:744
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::SimpleExecContext::stayAtPC
bool stayAtPC
Definition: exec_context.hh:70
gem5::AtomicSimpleCPU::tickEvent
EventFunctionWrapper tickEvent
Definition: atomic.hh:63
gem5::BaseSimpleCPU::setupFetchRequest
void setupFetchRequest(const RequestPtr &req)
Definition: base.cc:289
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::Packet::getConstPtr
const T * getConstPtr() const
Definition: packet.hh:1193
gem5::MemCmd::ReadReq
@ ReadReq
Definition: packet.hh:86
gem5::AtomicSimpleCPU::AtomicSimpleCPU
AtomicSimpleCPU(const AtomicSimpleCPUParams &params)
Definition: atomic.cc:75
gem5::BaseCPU::regProbePoints
void regProbePoints() override
Register probe points for this object.
Definition: base.cc:340
gem5::isAnyActiveElement
bool isAnyActiveElement(const std::vector< bool >::const_iterator &it_start, const std::vector< bool >::const_iterator &it_end)
Test if there is any active element in an enablement range.
Definition: utils.hh:89
gem5::BaseCPU::CPU_STATE_ON
@ CPU_STATE_ON
Definition: base.hh:514
gem5::AtomicSimpleCPU::verifyMemoryMode
void verifyMemoryMode() const override
Verify that the system is in a memory mode supported by the CPU.
Definition: atomic.cc:213
gem5::BaseSimpleCPU::activeThreads
std::list< ThreadID > activeThreads
Definition: base.hh:101
gem5::AtomicSimpleCPU::drainResume
void drainResume() override
Resume execution after a successful drain.
Definition: atomic.cc:143
gem5::BaseCPU
Definition: base.hh:107
gem5::EventManager::reschedule
void reschedule(Event &event, Tick when, bool always=false)
Definition: eventq.hh:1037
gem5::BaseSimpleCPU
Definition: base.hh:80
gem5::AtomicSimpleCPU::genMemFragmentRequest
bool genMemFragmentRequest(const RequestPtr &req, Addr frag_addr, int size, Request::Flags flags, const std::vector< bool > &byte_enable, int &frag_size, int &size_left) const
Helper function used to set up the request for a single fragment of a memory access.
Definition: atomic.cc:333
gem5::Packet::makeReadCmd
static MemCmd makeReadCmd(const RequestPtr &req)
Generate the appropriate read MemCmd based on the Request flags.
Definition: packet.hh:966
gem5::roundDown
static constexpr T roundDown(const T &val, const U &align)
This function is used to align addresses in memory.
Definition: intmath.hh:279
gem5::BaseSimpleCPU::traceFault
void traceFault()
Handler used when encountering a fault; its purpose is to tear down the InstRecord.
Definition: base.cc:247
gem5::SimpleThread::pcState
TheISA::PCState pcState() const override
Definition: simple_thread.hh:430
gem5::DrainState::Drained
@ Drained
Buffers drained, ready for serialization/handover.
gem5::AtomicSimpleCPU::locked
bool locked
Definition: atomic.hh:66
gem5::AtomicSimpleCPU::activateContext
void activateContext(ThreadID thread_num) override
Notify the CPU that the indicated context is now active.
Definition: atomic.cc:221
gem5::AtomicSimpleCPU::isCpuDrained
bool isCpuDrained() const
Check if a system is in a drained state.
Definition: atomic.hh:92
gem5::AtomicSimpleCPU::amoMem
Fault amoMem(Addr addr, uint8_t *data, unsigned size, Request::Flags flags, AtomicOpFunctorPtr amo_op) override
Definition: atomic.cc:548
gem5::AtomicSimpleCPU::drain
DrainState drain() override
Draining is the process of clearing out the states of SimObjects.These are the SimObjects that are pa...
Definition: atomic.cc:103
gem5::BaseCPU::getCpuAddrMonitor
AddressMonitor * getCpuAddrMonitor(ThreadID tid)
Definition: base.hh:609
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::Packet::isError
bool isError() const
Definition: packet.hh:610
gem5::AtomicSimpleCPU::dcache_latency
Tick dcache_latency
Definition: atomic.hh:171
name
const std::string & name()
Definition: trace.cc:49
gem5::BaseCPU::instCnt
Tick instCnt
Instruction count used for SPARC misc register.
Definition: base.hh:113
packet_access.hh
gem5::AtomicSimpleCPU::data_write_req
RequestPtr data_write_req
Definition: atomic.hh:167
gem5::Clocked::clockEdge
Tick clockEdge(Cycles cycles=Cycles(0)) const
Determine the tick when a cycle begins, by default the current one, but the argument also enables the...
Definition: clocked_object.hh:177
gem5::EventManager::deschedule
void deschedule(Event &event)
Definition: eventq.hh:1028
full_system.hh
gem5::divCeil
static constexpr T divCeil(const T &a, const U &b)
Definition: intmath.hh:110
gem5::BaseSimpleCPU::postExecute
void postExecute()
Definition: base.cc:394
gem5::ProbePointArg
ProbePointArg generates a point for the class of Arg.
Definition: thermal_domain.hh:54
gem5::Drainable::signalDrainDone
void signalDrainDone() const
Signal that an object is drained.
Definition: drain.hh:305
gem5::SimpleExecContext::thread
SimpleThread * thread
Definition: exec_context.hh:64
gem5::Clocked::nextCycle
Tick nextCycle() const
Based on the clock of the object, determine the start tick of the first cycle that is at least one cy...
Definition: clocked_object.hh:213
gem5::SimpleThread::getTC
ThreadContext * getTC()
Returns the pointer to this SimpleThread's ThreadContext.
Definition: simple_thread.hh:169
gem5::Request::STORE_NO_DATA
static const FlagsType STORE_NO_DATA
Definition: request.hh:244
gem5::SimObject::getProbeManager
ProbeManager * getProbeManager()
Get the probe manager for this object.
Definition: sim_object.cc:120
gem5::AtomicSimpleCPU::switchOut
void switchOut() override
Prepare for another CPU to take over execution.
Definition: atomic.cc:193
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:203
gem5::BaseCPU::threadContexts
std::vector< ThreadContext * > threadContexts
Definition: base.hh:262
gem5::BaseSimpleCPU::countInst
void countInst()
Definition: base.cc:161
gem5::BaseCPU::takeOverFrom
virtual void takeOverFrom(BaseCPU *cpu)
Load the state of a CPU from the previous CPU object, invoked on all new CPUs that are about to be sw...
Definition: base.cc:554
gem5::BaseCPU::activateContext
virtual void activateContext(ThreadID thread_num)
Notify the CPU that the indicated context is now active.
Definition: base.cc:488
gem5::SimpleExecContext
Definition: exec_context.hh:60
gem5::BaseSimpleCPU::Running
@ Running
Definition: base.hh:111
gem5::AtomicSimpleCPU::ifetch_req
RequestPtr ifetch_req
Definition: atomic.hh:165
gem5::AtomicSimpleCPU::threadSnoop
void threadSnoop(PacketPtr pkt, ThreadID sender)
Perform snoop for other cpu-local thread contexts.
Definition: atomic.cc:125
gem5::BaseSimpleCPU::swapActiveThread
void swapActiveThread()
Definition: base.cc:145
physical.hh
gem5::ContextID
int ContextID
Globally unique thread context ID.
Definition: types.hh:246
gem5::AtomicSimpleCPU::icachePort
AtomicCPUPort icachePort
Definition: atomic.hh:161
gem5::BaseSimpleCPU::serviceInstCountEvents
void serviceInstCountEvents()
Definition: base.cc:306
gem5::BaseCPU::switchOut
virtual void switchOut()
Prepare for another CPU to take over execution.
Definition: base.cc:540
gem5::ArmISA::handleLockedRead
void handleLockedRead(XC *xc, const RequestPtr &req)
Definition: locked_mem.hh:93
gem5::BaseCPU::syscallRetryLatency
Cycles syscallRetryLatency
Definition: base.hh:615
gem5::BaseSimpleCPU::wakeup
void wakeup(ThreadID tid) override
Definition: base.cc:236
gem5::Request::NO_ACCESS
@ NO_ACCESS
The request should not cause a memory access.
Definition: request.hh:146
gem5::BaseSimpleCPU::advancePC
void advancePC(const Fault &fault)
Definition: base.cc:470
gem5::AtomicSimpleCPU::ppCommit
ProbePointArg< std::pair< SimpleThread *, const StaticInstPtr > > * ppCommit
Probe Points.
Definition: atomic.hh:174
gem5::BaseCPU::dataRequestorId
RequestorID dataRequestorId() const
Reads this CPU's unique data requestor ID.
Definition: base.hh:194
decoder
output decoder
Definition: nop.cc:61
gem5::ArmISA::handleLockedSnoop
void handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask)
Definition: locked_mem.hh:64
gem5::Clocked::ticksToCycles
Cycles ticksToCycles(Tick t) const
Definition: clocked_object.hh:222
gem5::AtomicSimpleCPU::dcache_access
bool dcache_access
Definition: atomic.hh:170
gem5::Packet::getAddr
Addr getAddr() const
Definition: packet.hh:781
gem5::EventBase::CPU_Tick_Pri
static const Priority CPU_Tick_Pri
CPU ticks must come after other associated CPU events (such as writebacks).
Definition: eventq.hh:204
gem5::AtomicSimpleCPU::AtomicCPUDPort::recvFunctionalSnoop
virtual void recvFunctionalSnoop(PacketPtr pkt)
Receive a functional snoop request packet from the peer.
Definition: atomic.cc:309
gem5::AtomicOpFunctorPtr
std::unique_ptr< AtomicOpFunctor > AtomicOpFunctorPtr
Definition: amo.hh:242
gem5::BaseMMU::translateAtomic
Fault translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode)
Definition: mmu.cc:65
gem5::RequestPort::owner
SimObject & owner
Definition: port.hh:86
fatal_if
#define fatal_if(cond,...)
Conditional fatal macro that checks the supplied condition and only causes a fatal error if the condi...
Definition: logging.hh:225
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::BaseSimpleCPU::Idle
@ Idle
Definition: base.hh:110
gem5::AtomicSimpleCPU::AtomicCPUDPort::recvAtomicSnoop
virtual Tick recvAtomicSnoop(PacketPtr pkt)
Receive an atomic snoop request packet from our peer.
Definition: atomic.cc:279
gem5::RequestPort::printAddr
void printAddr(Addr a)
Inject a PrintReq for the given address to print the state of that address throughout the memory syst...
Definition: port.cc:157
gem5::BaseSimpleCPU::curMacroStaticInst
StaticInstPtr curMacroStaticInst
Definition: base.hh:105
gem5::AtomicSimpleCPU::tick
void tick()
Definition: atomic.cc:612
gem5::BaseSimpleCPU::curThread
ThreadID curThread
Definition: base.hh:83
gem5::DrainState::Draining
@ Draining
Draining buffers pending serialization/handover.
gem5::Event::scheduled
bool scheduled() const
Determine if the current event is scheduled.
Definition: eventq.hh:465
gem5::ThreadID
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:242
gem5::Packet::isInvalidate
bool isInvalidate() const
Definition: packet.hh:598
gem5::BaseSimpleCPU::init
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: base.cc:122
gem5::Clocked::clockPeriod
Tick clockPeriod() const
Definition: clocked_object.hh:217
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84

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