gem5  v21.2.1.1
simple_thread.cc
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2018, 2020 ARM Limited
3  * All rights reserved
4  *
5  * The license below extends only to copyright in the software and shall
6  * not be construed as granting a license to any other intellectual
7  * property including but not limited to intellectual property relating
8  * to a hardware implementation of the functionality of the software
9  * licensed hereunder. You may use the software subject to the license
10  * terms below provided that you ensure that this notice is replicated
11  * unmodified and in its entirety in all distributions of the software,
12  * modified or unmodified, in source code or in binary form.
13  *
14  * Copyright (c) 2001-2006 The Regents of The University of Michigan
15  * All rights reserved.
16  *
17  * Redistribution and use in source and binary forms, with or without
18  * modification, are permitted provided that the following conditions are
19  * met: redistributions of source code must retain the above copyright
20  * notice, this list of conditions and the following disclaimer;
21  * redistributions in binary form must reproduce the above copyright
22  * notice, this list of conditions and the following disclaimer in the
23  * documentation and/or other materials provided with the distribution;
24  * neither the name of the copyright holders nor the names of its
25  * contributors may be used to endorse or promote products derived from
26  * this software without specific prior written permission.
27  *
28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39  */
40 
41 #include "cpu/simple_thread.hh"
42 
43 #include <string>
44 
45 #include "arch/generic/decoder.hh"
46 #include "base/callback.hh"
47 #include "base/compiler.hh"
48 #include "base/cprintf.hh"
49 #include "base/output.hh"
50 #include "base/trace.hh"
51 #include "config/the_isa.hh"
52 #include "cpu/base.hh"
53 #include "cpu/simple/base.hh"
54 #include "cpu/thread_context.hh"
57 #include "params/BaseCPU.hh"
58 #include "sim/faults.hh"
59 #include "sim/full_system.hh"
60 #include "sim/process.hh"
61 #include "sim/serialize.hh"
62 #include "sim/sim_exit.hh"
63 #include "sim/system.hh"
64 
65 namespace gem5
66 {
67 
68 // constructor
69 SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
70  Process *_process, BaseMMU *_mmu,
71  BaseISA *_isa, InstDecoder *_decoder)
72  : ThreadState(_cpu, _thread_num, _process),
73  isa(dynamic_cast<TheISA::ISA *>(_isa)),
74  predicate(true), memAccPredicate(true),
75  comInstEventQueue("instruction-based event queue"),
76  system(_sys), mmu(_mmu), decoder(_decoder),
77  htmTransactionStarts(0), htmTransactionStops(0)
78 {
79  assert(isa);
80  const auto &regClasses = isa->regClasses();
81  intRegs.resize(regClasses.at(IntRegClass).size());
82  floatRegs.resize(regClasses.at(FloatRegClass).size());
83  vecRegs.resize(regClasses.at(VecRegClass).size());
84  vecElemRegs.resize(regClasses.at(VecElemClass).size());
85  vecPredRegs.resize(regClasses.at(VecPredRegClass).size());
86  ccRegs.resize(regClasses.at(CCRegClass).size());
87  clearArchRegs();
88 }
89 
90 SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
91  BaseMMU *_mmu, BaseISA *_isa, InstDecoder *_decoder)
92  : SimpleThread(_cpu, _thread_num, _sys, nullptr, _mmu, _isa, _decoder)
93 {}
94 
95 void
97 {
98  gem5::takeOverFrom(*this, *oldContext);
99  decoder->takeOverFrom(oldContext->getDecoderPtr());
100 
101  isa->takeOverFrom(this, oldContext);
102 
103  storeCondFailures = 0;
104 }
105 
106 void
108 {
109  // copy over functional state
110  _status = oldContext->status();
111  copyArchRegs(oldContext);
112 
113  _threadId = oldContext->threadId();
114  _contextId = oldContext->contextId();
115 }
116 
117 void
119 {
121  gem5::serialize(*this, cp);
122 }
123 
124 
125 void
127 {
129  gem5::unserialize(*this, cp);
130 }
131 
132 void
134 {
135  if (status() == ThreadContext::Active)
136  return;
137 
138  lastActivate = curTick();
140  baseCpu->activateContext(_threadId);
141 }
142 
143 void
145 {
147  return;
148 
149  lastActivate = curTick();
150  lastSuspend = curTick();
152  baseCpu->suspendContext(_threadId);
153 }
154 
155 
156 void
158 {
159  if (status() == ThreadContext::Halted)
160  return;
161 
163  baseCpu->haltContext(_threadId);
164 }
165 
166 void
168 {
169  getIsaPtr()->copyRegsFrom(src_tc);
170 }
171 
172 // hardware transactional memory
173 void
175 {
176  baseCpu->htmSendAbortSignal(threadId(), htm_uid, cause);
177 
178  // these must be reset after the abort signal has been sent
181 }
182 
185 {
186  return _htmCheckpoint;
187 }
188 
189 void
191 {
192  _htmCheckpoint = std::move(new_cpt);
193 }
194 
195 } // namespace gem5
gem5::curTick
Tick curTick()
The universal simulation clock.
Definition: cur_tick.hh:46
gem5::unserialize
void unserialize(ThreadContext &tc, CheckpointIn &cp)
Definition: thread_context.cc:206
gem5::ThreadContext::Active
@ Active
Running.
Definition: thread_context.hh:109
gem5::BaseHTMCheckpointPtr
std::unique_ptr< BaseHTMCheckpoint > BaseHTMCheckpointPtr
Definition: htm.hh:125
gem5::SimpleThread::htmTransactionStops
int64_t htmTransactionStops
Definition: simple_thread.hh:140
system.hh
gem5::BaseISA::copyRegsFrom
virtual void copyRegsFrom(ThreadContext *src)=0
gem5::ThreadContext::Halted
@ Halted
Permanently shut down.
Definition: thread_context.hh:122
serialize.hh
gem5::HtmFailureFaultCause
HtmFailureFaultCause
Definition: htm.hh:47
gem5::InstDecoder::takeOverFrom
virtual void takeOverFrom(InstDecoder *old)
Take over the state from an old decoder when switching CPUs.
Definition: decoder.hh:89
gem5::VecElemClass
@ VecElemClass
Vector Register Native Elem lane.
Definition: reg_class.hh:63
gem5::ThreadState
Struct for holding general thread state that is needed across CPU models.
Definition: thread_state.hh:47
gem5::ArmISA::ISA
Definition: isa.hh:68
gem5::CCRegClass
@ CCRegClass
Condition-code register.
Definition: reg_class.hh:65
gem5::SimpleThread::copyArchRegs
void copyArchRegs(ThreadContext *tc) override
Definition: simple_thread.cc:167
gem5::CheckpointIn
Definition: serialize.hh:68
translating_port_proxy.hh
gem5::ThreadState::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: thread_state.cc:60
gem5::SimpleThread::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: simple_thread.cc:126
gem5::ThreadState::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: thread_state.cc:54
gem5::ThreadContext::contextId
virtual ContextID contextId() const =0
gem5::ThreadState::_contextId
ContextID _contextId
Definition: thread_state.hh:118
gem5::X86ISA::system
Bitfield< 15 > system
Definition: misc.hh:1003
gem5::SimpleThread::vecElemRegs
std::vector< RegVal > vecElemRegs
Definition: simple_thread.hh:102
gem5::SimpleThread::clearArchRegs
void clearArchRegs() override
Definition: simple_thread.hh:249
gem5::SimpleThread::_htmCheckpoint
std::unique_ptr< BaseHTMCheckpoint > _htmCheckpoint
Definition: simple_thread.hh:110
gem5::SimpleThread::activate
void activate() override
Set the status to Active.
Definition: simple_thread.cc:133
faults.hh
sim_exit.hh
gem5::SimpleThread::htmTransactionStarts
int64_t htmTransactionStarts
Definition: simple_thread.hh:139
gem5::SimpleThread
The SimpleThread object provides a combination of the ThreadState object and the ThreadContext interf...
Definition: simple_thread.hh:93
output.hh
gem5::VecPredRegClass
@ VecPredRegClass
Definition: reg_class.hh:64
gem5::takeOverFrom
void takeOverFrom(ThreadContext &ntc, ThreadContext &otc)
Copy state between thread contexts in preparation for CPU handover.
Definition: thread_context.cc:254
gem5::BaseMMU
Definition: mmu.hh:53
gem5::ThreadContext::status
virtual Status status() const =0
gem5::SimpleThread::htmAbortTransaction
void htmAbortTransaction(uint64_t htm_uid, HtmFailureFaultCause cause) override
Definition: simple_thread.cc:174
gem5::FloatRegClass
@ FloatRegClass
Floating-point register.
Definition: reg_class.hh:59
gem5::ThreadState::lastSuspend
Tick lastSuspend
Last time suspend was called on this thread.
Definition: thread_state.hh:128
decoder.hh
gem5::System
Definition: system.hh:75
gem5::SimpleThread::copyState
void copyState(ThreadContext *oldContext)
Definition: simple_thread.cc:107
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::SimpleThread::isa
TheISA::ISA *const isa
Definition: simple_thread.hh:105
gem5::SimpleThread::setHtmCheckpointPtr
void setHtmCheckpointPtr(BaseHTMCheckpointPtr new_cpt) override
Definition: simple_thread.cc:190
gem5::InstDecoder
Definition: decoder.hh:42
gem5::ThreadContext::Suspended
@ Suspended
Temporarily inactive.
Definition: thread_context.hh:113
gem5::ThreadContext::getDecoderPtr
virtual InstDecoder * getDecoderPtr()=0
gem5::ThreadState::storeCondFailures
unsigned storeCondFailures
Definition: thread_state.hh:138
process.hh
gem5::SimpleThread::threadId
int threadId() const override
Definition: simple_thread.hh:204
gem5::SimpleThread::getIsaPtr
BaseISA * getIsaPtr() override
Definition: simple_thread.hh:213
gem5::SimpleThread::takeOverFrom
void takeOverFrom(ThreadContext *oldContext) override
Definition: simple_thread.cc:96
cprintf.hh
compiler.hh
gem5::SimpleThread::floatRegs
std::vector< RegVal > floatRegs
Definition: simple_thread.hh:99
gem5::serialize
void serialize(const ThreadContext &tc, CheckpointOut &cp)
Thread context serialization helpers.
Definition: thread_context.cc:157
gem5::SimpleThread::decoder
InstDecoder * decoder
Definition: simple_thread.hh:136
gem5::SimpleThread::halt
void halt() override
Set the status to Halted.
Definition: simple_thread.cc:157
gem5::SimpleThread::getHtmCheckpointPtr
BaseHTMCheckpointPtr & getHtmCheckpointPtr() override
Definition: simple_thread.cc:184
full_system.hh
gem5::Process
Definition: process.hh:68
base.hh
gem5::IntRegClass
@ IntRegClass
Integer register.
Definition: reg_class.hh:58
gem5::SimpleThread::ccRegs
std::vector< RegVal > ccRegs
Definition: simple_thread.hh:104
gem5::ThreadState::lastActivate
Tick lastActivate
Last time activate was called on this thread.
Definition: thread_state.hh:125
simple_thread.hh
gem5::SimpleThread::suspend
void suspend() override
Set the status to Suspended.
Definition: simple_thread.cc:144
base.hh
gem5::ThreadState::_status
ThreadContext::Status _status
Definition: thread_state.hh:112
gem5::SimpleThread::vecPredRegs
std::vector< TheISA::VecPredRegContainer > vecPredRegs
Definition: simple_thread.hh:103
gem5::SimpleThread::vecRegs
std::vector< TheISA::VecRegContainer > vecRegs
Definition: simple_thread.hh:101
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
se_translating_port_proxy.hh
gem5::ThreadContext::threadId
virtual int threadId() const =0
trace.hh
decoder
output decoder
Definition: nop.cc:61
gem5::VecRegClass
@ VecRegClass
Vector Register.
Definition: reg_class.hh:61
gem5::BaseISA
Definition: isa.hh:57
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::SimpleThread::intRegs
std::vector< RegVal > intRegs
Definition: simple_thread.hh:100
gem5::ThreadState::baseCpu
BaseCPU * baseCpu
Definition: thread_state.hh:115
gem5::SimpleThread::status
Status status() const override
Definition: simple_thread.hh:222
gem5::SimpleThread::SimpleThread
SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, BaseMMU *_mmu, BaseISA *_isa, InstDecoder *_decoder)
Definition: simple_thread.cc:90
thread_context.hh
callback.hh
gem5::SimpleThread::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: simple_thread.cc:118
gem5::ThreadState::_threadId
ThreadID _threadId
Definition: thread_state.hh:121

Generated on Wed May 4 2022 12:13:54 for gem5 by doxygen 1.8.17