gem5  v21.1.0.2
base.cc
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43 
44 #include "cpu/base.hh"
45 
46 #include <iostream>
47 #include <sstream>
48 #include <string>
49 
50 #include "arch/generic/tlb.hh"
51 #include "base/cprintf.hh"
52 #include "base/loader/symtab.hh"
53 #include "base/logging.hh"
54 #include "base/output.hh"
55 #include "base/trace.hh"
56 #include "cpu/checker/cpu.hh"
57 #include "cpu/thread_context.hh"
58 #include "debug/Mwait.hh"
59 #include "debug/SyscallVerbose.hh"
60 #include "debug/Thread.hh"
61 #include "mem/page_table.hh"
62 #include "params/BaseCPU.hh"
63 #include "sim/clocked_object.hh"
64 #include "sim/full_system.hh"
65 #include "sim/process.hh"
66 #include "sim/root.hh"
67 #include "sim/sim_events.hh"
68 #include "sim/sim_exit.hh"
69 #include "sim/system.hh"
70 
71 // Hack
72 #include "sim/stat_control.hh"
73 
74 namespace gem5
75 {
76 
77 std::unique_ptr<BaseCPU::GlobalStats> BaseCPU::globalStats;
78 
80 
81 // This variable reflects the max number of threads in any CPU. Be
82 // careful to only use it once all the CPUs that you care about have
83 // been initialized
85 
87  : Event(Event::Progress_Event_Pri), _interval(ival), lastNumInst(0),
88  cpu(_cpu), _repeatEvent(true)
89 {
90  if (_interval)
91  cpu->schedule(this, curTick() + _interval);
92 }
93 
94 void
96 {
97  Counter temp = cpu->totalOps();
98 
99  if (_repeatEvent)
100  cpu->schedule(this, curTick() + _interval);
101 
102  if (cpu->switchedOut()) {
103  return;
104  }
105 
106 #ifndef NDEBUG
107  double ipc = double(temp - lastNumInst) / (_interval / cpu->clockPeriod());
108 
109  DPRINTFN("%s progress event, total committed:%i, progress insts committed: "
110  "%lli, IPC: %0.8d\n", cpu->name(), temp, temp - lastNumInst,
111  ipc);
112  ipc = 0.0;
113 #else
114  cprintf("%lli: %s progress event, total committed:%i, progress insts "
115  "committed: %lli\n", curTick(), cpu->name(), temp,
116  temp - lastNumInst);
117 #endif
118  lastNumInst = temp;
119 }
120 
121 const char *
123 {
124  return "CPU Progress";
125 }
126 
127 BaseCPU::BaseCPU(const Params &p, bool is_checker)
128  : ClockedObject(p), instCnt(0), _cpuId(p.cpu_id), _socketId(p.socket_id),
129  _instRequestorId(p.system->getRequestorId(this, "inst")),
130  _dataRequestorId(p.system->getRequestorId(this, "data")),
131  _taskId(context_switch_task_id::Unknown), _pid(invldPid),
132  _switchedOut(p.switched_out), _cacheLineSize(p.system->cacheLineSize()),
133  interrupts(p.interrupts), numThreads(p.numThreads), system(p.system),
134  previousCycle(0), previousState(CPU_STATE_SLEEP),
135  functionTraceStream(nullptr), currentFunctionStart(0),
136  currentFunctionEnd(0), functionEntryTick(0),
137  baseStats(this),
138  addressMonitor(p.numThreads),
139  syscallRetryLatency(p.syscallRetryLatency),
140  pwrGatingLatency(p.pwr_gating_latency),
141  powerGatingOnIdle(p.power_gating_on_idle),
142  enterPwrGatingEvent([this]{ enterPwrGating(); }, name())
143 {
144  // if Python did not provide a valid ID, do it here
145  if (_cpuId == -1 ) {
146  _cpuId = cpuList.size();
147  }
148 
149  // add self to global list of CPUs
150  cpuList.push_back(this);
151 
152  DPRINTF(SyscallVerbose, "Constructing CPU with id %d, socket id %d\n",
153  _cpuId, _socketId);
154 
155  if (numThreads > maxThreadsPerCPU)
156  maxThreadsPerCPU = numThreads;
157 
158  functionTracingEnabled = false;
159  if (p.function_trace) {
160  const std::string fname = csprintf("ftrace.%s", name());
161  functionTraceStream = simout.findOrCreate(fname)->stream();
162 
163  currentFunctionStart = currentFunctionEnd = 0;
164  functionEntryTick = p.function_trace_start;
165 
166  if (p.function_trace_start == 0) {
167  functionTracingEnabled = true;
168  } else {
169  Event *event = new EventFunctionWrapper(
170  [this]{ enableFunctionTrace(); }, name(), true);
171  schedule(event, p.function_trace_start);
172  }
173  }
174 
175  tracer = params().tracer;
176 
177  if (params().isa.size() != numThreads) {
178  fatal("Number of ISAs (%i) assigned to the CPU does not equal number "
179  "of threads (%i).\n", params().isa.size(), numThreads);
180  }
181 }
182 
183 void
185 {
186  functionTracingEnabled = true;
187 }
188 
190 {
191 }
192 
193 void
194 BaseCPU::postInterrupt(ThreadID tid, int int_num, int index)
195 {
196  interrupts[tid]->post(int_num, index);
197  // Only wake up syscall emulation if it is not waiting on a futex.
198  // This is to model the fact that instructions such as ARM SEV
199  // should wake up a WFE sleep, but not a futex syscall WAIT. */
201  wakeup(tid);
202 }
203 
204 void
206 {
207  assert(tid < numThreads);
208  AddressMonitor &monitor = addressMonitor[tid];
209 
210  monitor.armed = true;
211  monitor.vAddr = address;
212  monitor.pAddr = 0x0;
213  DPRINTF(Mwait,"[tid:%d] Armed monitor (vAddr=0x%lx)\n", tid, address);
214 }
215 
216 bool
218 {
219  assert(tid < numThreads);
220  AddressMonitor &monitor = addressMonitor[tid];
221 
222  if (!monitor.gotWakeup) {
223  int block_size = cacheLineSize();
224  uint64_t mask = ~((uint64_t)(block_size - 1));
225 
226  assert(pkt->req->hasPaddr());
227  monitor.pAddr = pkt->getAddr() & mask;
228  monitor.waiting = true;
229 
230  DPRINTF(Mwait,"[tid:%d] mwait called (vAddr=0x%lx, "
231  "line's paddr=0x%lx)\n", tid, monitor.vAddr, monitor.pAddr);
232  return true;
233  } else {
234  monitor.gotWakeup = false;
235  return false;
236  }
237 }
238 
239 void
241 {
242  assert(tid < numThreads);
243  AddressMonitor &monitor = addressMonitor[tid];
244 
245  RequestPtr req = std::make_shared<Request>();
246 
247  Addr addr = monitor.vAddr;
248  int block_size = cacheLineSize();
249  uint64_t mask = ~((uint64_t)(block_size - 1));
250  int size = block_size;
251 
252  //The address of the next line if it crosses a cache line boundary.
253  Addr secondAddr = roundDown(addr + size - 1, block_size);
254 
255  if (secondAddr > addr)
256  size = secondAddr - addr;
257 
258  req->setVirt(addr, size, 0x0, dataRequestorId(), tc->instAddr());
259 
260  // translate to physical address
261  Fault fault = mmu->translateAtomic(req, tc, BaseMMU::Read);
262  assert(fault == NoFault);
263 
264  monitor.pAddr = req->getPaddr() & mask;
265  monitor.waiting = true;
266 
267  DPRINTF(Mwait,"[tid:%d] mwait called (vAddr=0x%lx, line's paddr=0x%lx)\n",
268  tid, monitor.vAddr, monitor.pAddr);
269 }
270 
271 void
273 {
274  // Set up instruction-count-based termination events, if any. This needs
275  // to happen after threadContexts has been constructed.
276  if (params().max_insts_any_thread != 0) {
277  const char *cause = "a thread reached the max instruction count";
278  for (ThreadID tid = 0; tid < numThreads; ++tid)
279  scheduleInstStop(tid, params().max_insts_any_thread, cause);
280  }
281 
282  // Set up instruction-count-based termination events for SimPoints
283  // Typically, there are more than one action points.
284  // Simulation.py is responsible to take the necessary actions upon
285  // exitting the simulation loop.
286  if (!params().simpoint_start_insts.empty()) {
287  const char *cause = "simpoint starting point found";
288  for (size_t i = 0; i < params().simpoint_start_insts.size(); ++i)
289  scheduleInstStop(0, params().simpoint_start_insts[i], cause);
290  }
291 
292  if (params().max_insts_all_threads != 0) {
293  const char *cause = "all threads reached the max instruction count";
294 
295  // allocate & initialize shared downcounter: each event will
296  // decrement this when triggered; simulation will terminate
297  // when counter reaches 0
298  int *counter = new int;
299  *counter = numThreads;
300  for (ThreadID tid = 0; tid < numThreads; ++tid) {
301  Event *event = new CountedExitEvent(cause, *counter);
302  threadContexts[tid]->scheduleInstCountEvent(
303  event, params().max_insts_all_threads);
304  }
305  }
306 
307  if (!params().switched_out) {
309 
311  }
312 }
313 
314 void
316 {
317  if (params().progress_interval) {
318  new CPUProgressEvent(this, params().progress_interval);
319  }
320 
321  if (_switchedOut)
323 
324  // Assumption CPU start to operate instantaneously without any latency
325  if (powerState->get() == enums::PwrState::UNDEFINED)
326  powerState->set(enums::PwrState::ON);
327 
328 }
329 
332 {
333  probing::PMUUPtr ptr;
334  ptr.reset(new probing::PMU(getProbeManager(), name));
335 
336  return ptr;
337 }
338 
339 void
341 {
342  ppAllCycles = pmuProbePoint("Cycles");
343  ppActiveCycles = pmuProbePoint("ActiveCycles");
344 
345  ppRetiredInsts = pmuProbePoint("RetiredInsts");
346  ppRetiredInstsPC = pmuProbePoint("RetiredInstsPC");
347  ppRetiredLoads = pmuProbePoint("RetiredLoads");
348  ppRetiredStores = pmuProbePoint("RetiredStores");
349  ppRetiredBranches = pmuProbePoint("RetiredBranches");
350 
352  "Sleeping");
353 }
354 
355 void
357 {
358  if (!inst->isMicroop() || inst->isLastMicroop()) {
359  ppRetiredInsts->notify(1);
360  ppRetiredInstsPC->notify(pc);
361  }
362 
363  if (inst->isLoad())
364  ppRetiredLoads->notify(1);
365 
366  if (inst->isStore() || inst->isAtomic())
367  ppRetiredStores->notify(1);
368 
369  if (inst->isControl())
370  ppRetiredBranches->notify(1);
371 }
372 
373 BaseCPU::
375  : statistics::Group(parent),
376  ADD_STAT(numCycles, statistics::units::Cycle::get(),
377  "Number of cpu cycles simulated"),
378  ADD_STAT(numWorkItemsStarted, statistics::units::Count::get(),
379  "Number of work items this cpu started"),
380  ADD_STAT(numWorkItemsCompleted, statistics::units::Count::get(),
381  "Number of work items this cpu completed")
382 {
383 }
384 
385 void
387 {
389 
390  if (!globalStats) {
391  /* We need to construct the global CPU stat structure here
392  * since it needs a pointer to the Root object. */
393  globalStats.reset(new GlobalStats(Root::root()));
394  }
395 
396  using namespace statistics;
397 
398  int size = threadContexts.size();
399  if (size > 1) {
400  for (int i = 0; i < size; ++i) {
401  std::stringstream namestr;
402  ccprintf(namestr, "%s.ctx%d", name(), i);
403  threadContexts[i]->regStats(namestr.str());
404  }
405  } else if (size == 1)
406  threadContexts[0]->regStats(name());
407 }
408 
409 Port &
410 BaseCPU::getPort(const std::string &if_name, PortID idx)
411 {
412  // Get the right port based on name. This applies to all the
413  // subclasses of the base CPU and relies on their implementation
414  // of getDataPort and getInstPort.
415  if (if_name == "dcache_port")
416  return getDataPort();
417  else if (if_name == "icache_port")
418  return getInstPort();
419  else
420  return ClockedObject::getPort(if_name, idx);
421 }
422 
423 void
425 {
426  assert(system->multiThread || numThreads == 1);
427 
428  fatal_if(interrupts.size() != numThreads,
429  "CPU %s has %i interrupt controllers, but is expecting one "
430  "per thread (%i)\n",
431  name(), interrupts.size(), numThreads);
432 
433  ThreadID size = threadContexts.size();
434  for (ThreadID tid = 0; tid < size; ++tid) {
435  ThreadContext *tc = threadContexts[tid];
436 
437  if (system->multiThread) {
439  } else {
441  }
442 
443  if (!FullSystem)
445 
446  interrupts[tid]->setThreadContext(tc);
447  tc->getIsaPtr()->setThreadContext(tc);
448  }
449 }
450 
451 void
453 {
456  }
457 }
458 
459 void
461 {
462  for (auto tc : threadContexts) {
463  if (tc->status() == ThreadContext::Active)
464  return;
465  }
466 
467  if (powerState->get() == enums::PwrState::CLK_GATED &&
469  assert(!enterPwrGatingEvent.scheduled());
470  // Schedule a power gating event when clock gated for the specified
471  // amount of time
473  }
474 }
475 
476 int
478 {
479  ThreadID size = threadContexts.size();
480  for (ThreadID tid = 0; tid < size; ++tid) {
481  if (tc == threadContexts[tid])
482  return tid;
483  }
484  return 0;
485 }
486 
487 void
489 {
490  DPRINTF(Thread, "activate contextId %d\n",
491  threadContexts[thread_num]->contextId());
492  // Squash enter power gating event while cpu gets activated
495  // For any active thread running, update CPU power state to active (ON)
496  powerState->set(enums::PwrState::ON);
497 
499 }
500 
501 void
503 {
504  DPRINTF(Thread, "suspend contextId %d\n",
505  threadContexts[thread_num]->contextId());
506  // Check if all threads are suspended
507  for (auto t : threadContexts) {
508  if (t->status() != ThreadContext::Suspended) {
509  return;
510  }
511  }
512 
513  // All CPU thread are suspended, update cycle count
515 
516  // All CPU threads suspended, enter lower power state for the CPU
517  powerState->set(enums::PwrState::CLK_GATED);
518 
519  // If pwrGatingLatency is set to 0 then this mechanism is disabled
520  if (powerGatingOnIdle) {
521  // Schedule power gating event when clock gated for pwrGatingLatency
522  // cycles
524  }
525 }
526 
527 void
529 {
531 }
532 
533 void
535 {
537 }
538 
539 void
541 {
542  assert(!_switchedOut);
543  _switchedOut = true;
544 
545  // Flush all TLBs in the CPU to avoid having stale translations if
546  // it gets switched in later.
547  flushTLBs();
548 
549  // Go to the power gating state
551 }
552 
553 void
555 {
556  assert(threadContexts.size() == oldCPU->threadContexts.size());
557  assert(_cpuId == oldCPU->cpuId());
558  assert(_switchedOut);
559  assert(oldCPU != this);
560  _pid = oldCPU->getPid();
561  _taskId = oldCPU->taskId();
562  // Take over the power state of the switchedOut CPU
563  powerState->set(oldCPU->powerState->get());
564 
565  previousState = oldCPU->previousState;
566  previousCycle = oldCPU->previousCycle;
567 
568  _switchedOut = false;
569 
570  ThreadID size = threadContexts.size();
571  for (ThreadID i = 0; i < size; ++i) {
572  ThreadContext *newTC = threadContexts[i];
573  ThreadContext *oldTC = oldCPU->threadContexts[i];
574 
575  newTC->getIsaPtr()->setThreadContext(newTC);
576 
577  newTC->takeOverFrom(oldTC);
578 
579  assert(newTC->contextId() == oldTC->contextId());
580  assert(newTC->threadId() == oldTC->threadId());
581  system->replaceThreadContext(newTC, newTC->contextId());
582 
583  /* This code no longer works since the zero register (e.g.,
584  * r31 on Alpha) doesn't necessarily contain zero at this
585  * point.
586  if (debug::Context)
587  ThreadContext::compare(oldTC, newTC);
588  */
589 
590  newTC->getMMUPtr()->takeOverFrom(oldTC->getMMUPtr());
591 
592  // Checker whether or not we have to transfer CheckerCPU
593  // objects over in the switch
594  CheckerCPU *old_checker = oldTC->getCheckerCpuPtr();
595  CheckerCPU *new_checker = newTC->getCheckerCpuPtr();
596  if (old_checker && new_checker) {
597  new_checker->getMMUPtr()->takeOverFrom(old_checker->getMMUPtr());
598  }
599  }
600 
601  interrupts = oldCPU->interrupts;
602  for (ThreadID tid = 0; tid < numThreads; tid++) {
603  interrupts[tid]->setThreadContext(threadContexts[tid]);
604  }
605  oldCPU->interrupts.clear();
606 
607  // All CPUs have an instruction and a data port, and the new CPU's
608  // ports are dangling while the old CPU has its ports connected
609  // already. Unbind the old CPU and then bind the ports of the one
610  // we are switching to.
611  getInstPort().takeOverFrom(&oldCPU->getInstPort());
612  getDataPort().takeOverFrom(&oldCPU->getDataPort());
613 }
614 
615 void
617 {
618  for (ThreadID i = 0; i < threadContexts.size(); ++i) {
620  CheckerCPU *checker(tc.getCheckerCpuPtr());
621 
622  tc.getMMUPtr()->flushAll();
623  if (checker) {
624  checker->getMMUPtr()->flushAll();
625  }
626  }
627 }
628 
629 void
631 {
633 
634  if (!_switchedOut) {
635  /* Unlike _pid, _taskId is not serialized, as they are dynamically
636  * assigned unique ids that are only meaningful for the duration of
637  * a specific run. We will need to serialize the entire taskMap in
638  * system. */
640 
641  // Serialize the threads, this is done by the CPU implementation.
642  for (ThreadID i = 0; i < numThreads; ++i) {
643  ScopedCheckpointSection sec(cp, csprintf("xc.%i", i));
644  interrupts[i]->serialize(cp);
645  serializeThread(cp, i);
646  }
647  }
648 }
649 
650 void
652 {
654 
655  if (!_switchedOut) {
657 
658  // Unserialize the threads, this is done by the CPU implementation.
659  for (ThreadID i = 0; i < numThreads; ++i) {
660  ScopedCheckpointSection sec(cp, csprintf("xc.%i", i));
661  interrupts[i]->unserialize(cp);
662  unserializeThread(cp, i);
663  }
664  }
665 }
666 
667 void
668 BaseCPU::scheduleInstStop(ThreadID tid, Counter insts, const char *cause)
669 {
670  const Tick now(getCurrentInstCount(tid));
671  Event *event(new LocalSimLoopExitEvent(cause, 0));
672 
673  threadContexts[tid]->scheduleInstCountEvent(event, now + insts);
674 }
675 
676 Tick
678 {
679  return threadContexts[tid]->getCurrentInstCount();
680 }
681 
683  armed = false;
684  waiting = false;
685  gotWakeup = false;
686 }
687 
689  assert(pkt->req->hasPaddr());
690  if (armed && waiting) {
691  if (pAddr == pkt->getAddr()) {
692  DPRINTF(Mwait,"pAddr=0x%lx invalidated: waking up core\n",
693  pkt->getAddr());
694  waiting = false;
695  return true;
696  }
697  }
698  return false;
699 }
700 
701 
702 void
704 {
705  if (loader::debugSymbolTable.empty())
706  return;
707 
708  // if pc enters different function, print new function symbol and
709  // update saved range. Otherwise do nothing.
710  if (pc < currentFunctionStart || pc >= currentFunctionEnd) {
713 
714  std::string sym_str;
715  if (it == loader::debugSymbolTable.end()) {
716  // no symbol found: use addr as label
717  sym_str = csprintf("%#x", pc);
719  currentFunctionEnd = pc + 1;
720  } else {
721  sym_str = it->name;
722  currentFunctionStart = it->address;
723  }
724 
725  ccprintf(*functionTraceStream, " (%d)\n%d: %s",
726  curTick() - functionEntryTick, curTick(), sym_str);
728  }
729 }
730 
731 
733  : statistics::Group(parent),
734  ADD_STAT(simInsts, statistics::units::Count::get(),
735  "Number of instructions simulated"),
736  ADD_STAT(simOps, statistics::units::Count::get(),
737  "Number of ops (including micro ops) simulated"),
738  ADD_STAT(hostInstRate, statistics::units::Rate<
739  statistics::units::Count, statistics::units::Second>::get(),
740  "Simulator instruction rate (inst/s)"),
741  ADD_STAT(hostOpRate, statistics::units::Rate<
742  statistics::units::Count, statistics::units::Second>::get(),
743  "Simulator op (including micro ops) rate (op/s)")
744 {
745  simInsts
747  .precision(0)
748  .prereq(simInsts)
749  ;
750 
751  simOps
753  .precision(0)
754  .prereq(simOps)
755  ;
756 
758  .precision(0)
759  .prereq(simInsts)
760  ;
761 
762  hostOpRate
763  .precision(0)
764  .prereq(simOps)
765  ;
766 
769 }
770 
771 } // namespace gem5
gem5::CPUProgressEvent::CPUProgressEvent
CPUProgressEvent(BaseCPU *_cpu, Tick ival=0)
Definition: base.cc:86
gem5::curTick
Tick curTick()
The universal simulation clock.
Definition: cur_tick.hh:46
fatal
#define fatal(...)
This implements a cprintf based fatal() function.
Definition: logging.hh:189
gem5::PortID
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:252
gem5::Process::assignThreadContext
void assignThreadContext(ContextID context_id)
Definition: process.hh:119
gem5::SimObject::getPort
virtual Port & getPort(const std::string &if_name, PortID idx=InvalidPortID)
Get a port with a given name and index.
Definition: sim_object.cc:126
gem5::CPUProgressEvent::lastNumInst
Counter lastNumInst
Definition: base.hh:90
gem5::BaseCPU::currentFunctionStart
Addr currentFunctionStart
Definition: base.hh:553
gem5::BaseMMU::Read
@ Read
Definition: mmu.hh:53
gem5::maxThreadsPerCPU
int maxThreadsPerCPU
The maximum number of active threads across all cpus.
Definition: base.cc:84
gem5::BaseCPU::armMonitor
void armMonitor(ThreadID tid, Addr address)
Definition: base.cc:205
gem5::BaseCPU::functionTraceStream
std::ostream * functionTraceStream
Definition: base.hh:552
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:260
gem5::ThreadContext::Active
@ Active
Running.
Definition: thread_context.hh:108
gem5::BaseCPU::switchedOut
bool switchedOut() const
Determine if the CPU is switched out.
Definition: base.hh:357
gem5::StaticInst::isMicroop
bool isMicroop() const
Definition: static_inst.hh:208
gem5::BaseCPU::interrupts
std::vector< BaseInterrupts * > interrupts
Definition: base.hh:225
gem5::BaseCPU::getInstPort
virtual Port & getInstPort()=0
Purely virtual method that returns a reference to the instruction port.
gem5::cprintf
void cprintf(const char *format, const Args &...args)
Definition: cprintf.hh:155
gem5::BaseCPU::mwaitAtomic
void mwaitAtomic(ThreadID tid, ThreadContext *tc, BaseMMU *mmu)
Definition: base.cc:240
system.hh
gem5::BaseCPU::ppSleeping
ProbePointArg< bool > * ppSleeping
ProbePoint that signals transitions of threadContexts sets.
Definition: base.hh:509
gem5::BaseCPU::startup
void startup() override
startup() is the final initialization call before simulation.
Definition: base.cc:315
gem5::CheckerCPU::getMMUPtr
BaseMMU * getMMUPtr()
Definition: cpu.hh:154
UNSERIALIZE_SCALAR
#define UNSERIALIZE_SCALAR(scalar)
Definition: serialize.hh:575
gem5::BaseCPU::BaseCPUStats::BaseCPUStats
BaseCPUStats(statistics::Group *parent)
Definition: base.cc:374
gem5::RiscvISA::Unknown
Static instruction class for unknown (illegal) instructions.
Definition: unknown.hh:53
gem5::BaseCPU::enableFunctionTrace
void enableFunctionTrace()
Definition: base.cc:184
gem5::BaseCPU::unserializeThread
virtual void unserializeThread(CheckpointIn &cp, ThreadID tid)
Unserialize one thread.
Definition: base.hh:421
gem5::CPUProgressEvent::process
void process()
Definition: base.cc:95
gem5::MipsISA::index
Bitfield< 30, 0 > index
Definition: pra_constants.hh:47
sim_events.hh
gem5::BaseCPU::GlobalStats::hostOpRate
statistics::Formula hostOpRate
Definition: base.hh:160
gem5::BaseCPU::unserialize
void unserialize(CheckpointIn &cp) override
Reconstruct the state of this object from a checkpoint.
Definition: base.cc:651
gem5::Packet::req
RequestPtr req
A pointer to the original request.
Definition: packet.hh:366
gem5::BaseCPU::ppRetiredInsts
probing::PMUUPtr ppRetiredInsts
Instruction commit probe point.
Definition: base.hh:484
gem5::System::futexMap
FutexMap futexMap
Definition: system.hh:626
gem5::BaseCPU::pmuProbePoint
probing::PMUUPtr pmuProbePoint(const char *name)
Helper method to instantiate probe points belonging to this object.
Definition: base.cc:331
gem5::BaseCPU::cacheLineSize
unsigned int cacheLineSize() const
Get the cache line size of the system.
Definition: base.hh:381
gem5::ThreadContext::getMMUPtr
virtual BaseMMU * getMMUPtr()=0
gem5::StaticInst::isControl
bool isControl() const
Definition: static_inst.hh:182
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::AddressMonitor::AddressMonitor
AddressMonitor()
Definition: base.cc:682
gem5::AddressMonitor::doMonitor
bool doMonitor(PacketPtr pkt)
Definition: base.cc:688
gem5::MipsISA::event
Bitfield< 10, 5 > event
Definition: pra_constants.hh:300
gem5::BaseCPU::updateCycleCounters
void updateCycleCounters(CPUState state)
base method keeping track of cycle progression
Definition: base.hh:523
gem5::BaseCPU::GlobalStats
Global CPU statistics that are merged into the Root object.
Definition: base.hh:152
gem5::BaseCPU::BaseCPU
BaseCPU(const Params &params, bool is_checker=false)
Definition: base.cc:127
tlb.hh
gem5::BaseCPU::init
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: base.cc:272
gem5::PowerState::get
enums::PwrState get() const
Definition: power_state.hh:84
gem5::simout
OutputDirectory simout
Definition: output.cc:62
gem5::ThreadContext::contextId
virtual ContextID contextId() const =0
gem5::BaseCPU::system
System * system
Definition: base.hh:376
gem5::BaseCPU::enterPwrGating
void enterPwrGating()
Definition: base.cc:534
gem5::X86ISA::system
Bitfield< 15 > system
Definition: misc.hh:1003
gem5::AddressMonitor::vAddr
Addr vAddr
Definition: base.hh:79
gem5::BaseCPU::cpuList
static std::vector< BaseCPU * > cpuList
Static global cpu list.
Definition: base.hh:560
gem5::BaseCPU::numSimulatedOps
static Counter numSimulatedOps()
Definition: base.hh:581
gem5::EventManager::schedule
void schedule(Event &event, Tick when)
Definition: eventq.hh:1019
std::vector
STL vector class.
Definition: stl.hh:37
gem5::ThreadContext::instAddr
virtual Addr instAddr() const =0
gem5::csprintf
std::string csprintf(const char *format, const Args &...args)
Definition: cprintf.hh:161
gem5::BaseCPU::previousCycle
Cycles previousCycle
Definition: base.hh:519
gem5::BaseCPU::getPid
uint32_t getPid() const
Definition: base.hh:216
gem5::Port::takeOverFrom
void takeOverFrom(Port *old)
A utility function to make it easier to swap out ports.
Definition: port.hh:137
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
gem5::BaseCPU::schedulePowerGatingEvent
void schedulePowerGatingEvent()
Definition: base.cc:460
sim_exit.hh
gem5::OutputDirectory::findOrCreate
OutputStream * findOrCreate(const std::string &name, bool binary=false)
Definition: output.cc:262
output.hh
gem5::ccprintf
void ccprintf(cp::Print &print)
Definition: cprintf.hh:130
gem5::BaseCPU::_taskId
uint32_t _taskId
An intrenal representation of a task identifier within gem5.
Definition: base.hh:139
root.hh
gem5::RefCountingPtr< StaticInst >
gem5::BaseMMU
Definition: mmu.hh:50
gem5::mask
constexpr uint64_t mask(unsigned nbits)
Generate a 64-bit mask of 'nbits' 1s, right justified.
Definition: bitfield.hh:63
gem5::BaseCPU::ppAllCycles
probing::PMUUPtr ppAllCycles
CPU cycle counter even if any thread Context is suspended.
Definition: base.hh:496
gem5::AddressMonitor
Definition: base.hh:73
gem5::BaseCPU::numThreads
ThreadID numThreads
Number of threads we're actually simulating (<= SMT_MAX_THREADS).
Definition: base.hh:368
gem5::BaseCPU::serializeThread
virtual void serializeThread(CheckpointOut &cp, ThreadID tid) const
Serialize a single thread.
Definition: base.hh:413
gem5::BaseCPU::_cpuId
int _cpuId
Definition: base.hh:119
gem5::BaseCPU::regStats
void regStats() override
Callback to set stat parameters.
Definition: base.cc:386
gem5::BaseCPU::ppRetiredInstsPC
probing::PMUUPtr ppRetiredInstsPC
Definition: base.hh:485
gem5::BaseCPU::wakeup
virtual void wakeup(ThreadID tid)=0
gem5::BaseCPU::getDataPort
virtual Port & getDataPort()=0
Purely virtual method that returns a reference to the data port.
gem5::BaseCPU::deschedulePowerGatingEvent
void deschedulePowerGatingEvent()
Definition: base.cc:452
gem5::OutputStream::stream
std::ostream * stream() const
Get the output underlying output stream.
Definition: output.hh:62
gem5::CPUProgressEvent::description
virtual const char * description() const
Return a C string describing the event.
Definition: base.cc:122
gem5::BaseCPU::suspendContext
virtual void suspendContext(ThreadID thread_num)
Notify the CPU that the indicated context is now suspended.
Definition: base.cc:502
gem5::BaseCPU::registerThreadContexts
void registerThreadContexts()
Definition: base.cc:424
gem5::BaseCPU::taskId
uint32_t taskId() const
Get cpu task id.
Definition: base.hh:212
gem5::BaseCPU::GlobalStats::simInsts
statistics::Value simInsts
Definition: base.hh:156
gem5::BaseCPU::ppRetiredStores
probing::PMUUPtr ppRetiredStores
Retired store instructions.
Definition: base.hh:490
gem5::BaseCPU::scheduleInstStop
void scheduleInstStop(ThreadID tid, Counter insts, const char *cause)
Schedule an event that exits the simulation loops after a predefined number of instructions.
Definition: base.cc:668
gem5::ThreadContext::getIsaPtr
virtual BaseISA * getIsaPtr()=0
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::Named::name
virtual std::string name() const
Definition: named.hh:47
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::BaseCPU::flushTLBs
void flushTLBs()
Flush all TLBs in the CPU.
Definition: base.cc:616
gem5::SimObject::params
const Params & params() const
Definition: sim_object.hh:176
gem5::probing::PMUUPtr
std::unique_ptr< PMU > PMUUPtr
Definition: pmu.hh:61
gem5::StaticInst::isAtomic
bool isAtomic() const
Definition: static_inst.hh:171
gem5::BaseCPU::pwrGatingLatency
const Cycles pwrGatingLatency
Definition: base.hh:621
gem5::ThreadContext::Suspended
@ Suspended
Temporarily inactive.
Definition: thread_context.hh:112
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::Event
Definition: eventq.hh:251
ADD_STAT
#define ADD_STAT(n,...)
Convenience macro to add a stat to a statistics group.
Definition: group.hh:75
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::BaseCPU::CPU_STATE_WAKEUP
@ CPU_STATE_WAKEUP
Definition: base.hh:516
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::CheckerCPU
CheckerCPU class.
Definition: cpu.hh:84
gem5::BaseCPU::haltContext
virtual void haltContext(ThreadID thread_num)
Notify the CPU that the indicated context is now halted.
Definition: base.cc:528
gem5::BaseCPU::GlobalStats::hostInstRate
statistics::Formula hostInstRate
Definition: base.hh:159
cpu.hh
gem5::BaseCPU::functionEntryTick
Tick functionEntryTick
Definition: base.hh:555
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
process.hh
gem5::BaseCPU::regProbePoints
void regProbePoints() override
Register probe points for this object.
Definition: base.cc:340
gem5::BaseISA::setThreadContext
virtual void setThreadContext(ThreadContext *_tc)
Definition: isa.hh:68
gem5::BaseCPU::serialize
void serialize(CheckpointOut &cp) const override
Serialize this object to the given output stream.
Definition: base.cc:630
gem5::loader::SymbolTable::findNearest
const_iterator findNearest(Addr addr, Addr &next_addr) const
Find the nearest symbol equal to or less than the supplied address (e.g., the label for the enclosing...
Definition: symtab.hh:361
gem5::StaticInst::isLoad
bool isLoad() const
Definition: static_inst.hh:169
gem5::BaseCPU::previousState
CPUState previousState
Definition: base.hh:520
gem5::StaticInst::isStore
bool isStore() const
Definition: static_inst.hh:170
gem5::BaseCPU
Definition: base.hh:107
gem5::BaseCPU::totalOps
virtual Counter totalOps() const =0
gem5::BaseCPU::findContext
int findContext(ThreadContext *tc)
Given a Thread Context pointer return the thread num.
Definition: base.cc:477
cprintf.hh
gem5::statistics::ValueBase::functor
Derived & functor(const T &func)
Definition: statistics.hh:738
gem5::ThreadContext::takeOverFrom
virtual void takeOverFrom(ThreadContext *old_context)=0
gem5::roundDown
static constexpr T roundDown(const T &val, const U &align)
This function is used to align addresses in memory.
Definition: intmath.hh:279
gem5::BaseCPU::numSimulatedInsts
static Counter numSimulatedInsts()
Definition: base.hh:570
gem5::BaseCPU::functionTracingEnabled
bool functionTracingEnabled
Definition: base.hh:551
gem5::BaseCPU::~BaseCPU
virtual ~BaseCPU()
Definition: base.cc:189
gem5::ArmISA::t
Bitfield< 5 > t
Definition: misc_types.hh:70
gem5::statistics::DataWrap::precision
Derived & precision(int _precision)
Set the precision and marks this stat to print at the end of simulation.
Definition: statistics.hh:343
gem5::BaseCPU::postInterrupt
void postInterrupt(ThreadID tid, int int_num, int index)
Definition: base.cc:194
gem5::CountedExitEvent
Definition: sim_events.hh:104
gem5::BaseCPU::enterPwrGatingEvent
EventFunctionWrapper enterPwrGatingEvent
Definition: base.hh:623
gem5::BaseCPU::probeInstCommit
virtual void probeInstCommit(const StaticInstPtr &inst, Addr pc)
Helper method to trigger PMU probes for a committed instruction.
Definition: base.cc:356
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::AddressMonitor::gotWakeup
bool gotWakeup
Definition: base.hh:83
name
const std::string & name()
Definition: trace.cc:49
gem5::StaticInst::isLastMicroop
bool isLastMicroop() const
Definition: static_inst.hh:210
SERIALIZE_SCALAR
#define SERIALIZE_SCALAR(scalar)
Definition: serialize.hh:568
gem5::statistics::Group::regStats
virtual void regStats()
Callback to set stat parameters.
Definition: group.cc:69
gem5::BaseCPU::instCnt
Tick instCnt
Instruction count used for SPARC misc register.
Definition: base.hh:113
gem5::BaseCPU::GlobalStats::GlobalStats
GlobalStats(statistics::Group *parent)
Definition: base.cc:732
gem5::FutexMap::is_waiting
bool is_waiting(ThreadContext *tc)
Determine if the given thread context is currently waiting on a futex wait operation on any of the fu...
Definition: futex_map.cc:185
gem5::CPUProgressEvent::_repeatEvent
bool _repeatEvent
Definition: base.hh:92
gem5::ClockedObject
The ClockedObject class extends the SimObject with a clock and accessor functions to relate ticks to ...
Definition: clocked_object.hh:234
gem5::BaseCPU::_switchedOut
bool _switchedOut
Is the CPU switched out or active?
Definition: base.hh:146
gem5::Clocked::clockEdge
Tick clockEdge(Cycles cycles=Cycles(0)) const
Determine the tick when a cycle begins, by default the current one, but the argument also enables the...
Definition: clocked_object.hh:177
gem5::ClockedObject::powerState
PowerState * powerState
Definition: clocked_object.hh:245
gem5::LocalSimLoopExitEvent
Definition: sim_events.hh:76
gem5::EventManager::deschedule
void deschedule(Event &event)
Definition: eventq.hh:1028
full_system.hh
gem5::BaseCPU::CPU_STATE_SLEEP
@ CPU_STATE_SLEEP
Definition: base.hh:515
gem5::ProbePointArg
ProbePointArg generates a point for the class of Arg.
Definition: thermal_domain.hh:54
gem5::BaseCPU::currentFunctionEnd
Addr currentFunctionEnd
Definition: base.hh:554
gem5::ThreadContext::getProcessPtr
virtual Process * getProcessPtr()=0
gem5::System::multiThread
const bool multiThread
Definition: system.hh:318
gem5::FullSystem
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:223
gem5::SimObject::getProbeManager
ProbeManager * getProbeManager()
Get the probe manager for this object.
Definition: sim_object.cc:120
stat_control.hh
gem5::BaseCPU::threadContexts
std::vector< ThreadContext * > threadContexts
Definition: base.hh:262
gem5::BaseCPU::takeOverFrom
virtual void takeOverFrom(BaseCPU *cpu)
Load the state of a CPU from the previous CPU object, invoked on all new CPUs that are about to be sw...
Definition: base.cc:554
gem5::BaseCPU::activateContext
virtual void activateContext(ThreadID thread_num)
Notify the CPU that the indicated context is now active.
Definition: base.cc:488
base.hh
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
gem5::statistics::DataWrap::prereq
Derived & prereq(const Stat &prereq)
Set the prerequisite stat and marks this stat to print at the end of simulation.
Definition: statistics.hh:369
gem5::BaseCPU::getPort
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port on this CPU.
Definition: base.cc:410
gem5::BaseCPU::cpuId
int cpuId() const
Reads this CPU's ID.
Definition: base.hh:188
clocked_object.hh
gem5::BaseCPU::verifyMemoryMode
virtual void verifyMemoryMode() const
Verify that the system is in a memory mode supported by the CPU.
Definition: base.hh:368
gem5::BaseCPU::ppRetiredLoads
probing::PMUUPtr ppRetiredLoads
Retired load instructions.
Definition: base.hh:488
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::statistics::Counter
double Counter
All counters are of 64-bit values.
Definition: types.hh:47
gem5::BaseCPU::traceFunctionsInternal
void traceFunctionsInternal(Addr pc)
Definition: base.cc:703
gem5::BaseCPU::switchOut
virtual void switchOut()
Prepare for another CPU to take over execution.
Definition: base.cc:540
gem5::BaseMMU::flushAll
virtual void flushAll()
Definition: mmu.cc:51
logging.hh
gem5::statistics::Group
Statistics container.
Definition: group.hh:93
gem5::BaseCPU::GlobalStats::simOps
statistics::Value simOps
Definition: base.hh:157
gem5::BaseCPU::getCurrentInstCount
uint64_t getCurrentInstCount(ThreadID tid)
Get the number of instructions executed by the specified thread on this CPU.
Definition: base.cc:677
gem5::System::registerThreadContext
void registerThreadContext(ThreadContext *tc, ContextID assigned=InvalidContextID)
Definition: system.cc:290
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::System::replaceThreadContext
void replaceThreadContext(ThreadContext *tc, ContextID context_id)
Definition: system.cc:322
gem5::AddressMonitor::pAddr
Addr pAddr
Definition: base.hh:80
gem5::ThreadContext::threadId
virtual int threadId() const =0
gem5::BaseCPU::dataRequestorId
RequestorID dataRequestorId() const
Reads this CPU's unique data requestor ID.
Definition: base.hh:194
trace.hh
symtab.hh
gem5::ClockedObject::Params
ClockedObjectParams Params
Parameters of ClockedObject.
Definition: clocked_object.hh:240
DPRINTFN
#define DPRINTFN(...)
Definition: trace.hh:214
gem5::AddressMonitor::waiting
bool waiting
Definition: base.hh:82
gem5::BaseCPU::mwait
bool mwait(ThreadID tid, PacketPtr pkt)
Definition: base.cc:217
gem5::loader::debugSymbolTable
SymbolTable debugSymbolTable
Global unified debugging symbol table (for target).
Definition: symtab.cc:44
gem5::BaseCPU::ppActiveCycles
probing::PMUUPtr ppActiveCycles
CPU cycle counter, only counts if any thread contexts is active.
Definition: base.hh:499
gem5::CPUProgressEvent::cpu
BaseCPU * cpu
Definition: base.hh:91
gem5::Packet::getAddr
Addr getAddr() const
Definition: packet.hh:781
gem5::RiscvISA::OFF
@ OFF
Definition: isa.hh:61
gem5::BaseMMU::translateAtomic
Fault translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode)
Definition: mmu.cc:65
fatal_if
#define fatal_if(cond,...)
Conditional fatal macro that checks the supplied condition and only causes a fatal error if the condi...
Definition: logging.hh:225
page_table.hh
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::PowerState::set
void set(enums::PwrState p)
Change the power state of this object to the power state p.
Definition: power_state.cc:96
gem5::hostSeconds
statistics::Value & hostSeconds
Definition: stats.cc:48
gem5::BaseMMU::takeOverFrom
virtual void takeOverFrom(BaseMMU *old_mmu)
Definition: mmu.cc:93
gem5::Serializable::ScopedCheckpointSection
Definition: serialize.hh:172
gem5::BaseCPU::ppRetiredBranches
probing::PMUUPtr ppRetiredBranches
Retired branches (any type)
Definition: base.hh:493
gem5::CPUProgressEvent
Definition: base.hh:86
gem5::ThreadContext::getCheckerCpuPtr
virtual CheckerCPU * getCheckerCpuPtr()=0
gem5::BaseCPU::_pid
uint32_t _pid
The current OS process ID that is executing on this processor.
Definition: base.hh:143
thread_context.hh
gem5::Root::root
static Root * root()
Use this function to get a pointer to the single Root object in the simulation.
Definition: root.hh:93
gem5::AddressMonitor::armed
bool armed
Definition: base.hh:78
gem5::BaseCPU::powerGatingOnIdle
const bool powerGatingOnIdle
Definition: base.hh:622
gem5::BaseCPU::globalStats
static std::unique_ptr< GlobalStats > globalStats
Pointer to the global stat structure.
Definition: base.hh:167
gem5::Event::scheduled
bool scheduled() const
Determine if the current event is scheduled.
Definition: eventq.hh:465
gem5::ThreadID
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:242
gem5::BaseCPU::addressMonitor
std::vector< AddressMonitor > addressMonitor
Definition: base.hh:603
gem5::Clocked::clockPeriod
Tick clockPeriod() const
Definition: clocked_object.hh:217
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::CPUProgressEvent::_interval
Tick _interval
Definition: base.hh:89

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