gem5  v21.1.0.2
pagetable_walker.cc
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49 
51 
52 #include <memory>
53 
54 #include "arch/x86/faults.hh"
55 #include "arch/x86/pagetable.hh"
56 #include "arch/x86/tlb.hh"
57 #include "base/bitfield.hh"
58 #include "base/trie.hh"
59 #include "cpu/base.hh"
60 #include "cpu/thread_context.hh"
61 #include "debug/PageTableWalker.hh"
62 #include "mem/packet_access.hh"
63 #include "mem/request.hh"
64 
65 namespace gem5
66 {
67 
68 namespace X86ISA {
69 
70 Fault
72  const RequestPtr &_req, BaseMMU::Mode _mode)
73 {
74  // TODO: in timing mode, instead of blocking when there are other
75  // outstanding requests, see if this request can be coalesced with
76  // another one (i.e. either coalesce or start walk)
77  WalkerState * newState = new WalkerState(this, _translation, _req);
78  newState->initState(_tc, _mode, sys->isTimingMode());
79  if (currStates.size()) {
80  assert(newState->isTiming());
81  DPRINTF(PageTableWalker, "Walks in progress: %d\n", currStates.size());
82  currStates.push_back(newState);
83  return NoFault;
84  } else {
85  currStates.push_back(newState);
86  Fault fault = newState->startWalk();
87  if (!newState->isTiming()) {
88  currStates.pop_front();
89  delete newState;
90  }
91  return fault;
92  }
93 }
94 
95 Fault
96 Walker::startFunctional(ThreadContext * _tc, Addr &addr, unsigned &logBytes,
97  BaseMMU::Mode _mode)
98 {
99  funcState.initState(_tc, _mode);
100  return funcState.startFunctional(addr, logBytes);
101 }
102 
103 bool
105 {
106  return walker->recvTimingResp(pkt);
107 }
108 
109 bool
111 {
112  WalkerSenderState * senderState =
113  dynamic_cast<WalkerSenderState *>(pkt->popSenderState());
114  WalkerState * senderWalk = senderState->senderWalk;
115  bool walkComplete = senderWalk->recvPacket(pkt);
116  delete senderState;
117  if (walkComplete) {
119  for (iter = currStates.begin(); iter != currStates.end(); iter++) {
120  WalkerState * walkerState = *(iter);
121  if (walkerState == senderWalk) {
122  iter = currStates.erase(iter);
123  break;
124  }
125  }
126  delete senderWalk;
127  // Since we block requests when another is outstanding, we
128  // need to check if there is a waiting request to be serviced
129  if (currStates.size() && !startWalkWrapperEvent.scheduled())
130  // delay sending any new requests until we are finished
131  // with the responses
133  }
134  return true;
135 }
136 
137 void
139 {
140  walker->recvReqRetry();
141 }
142 
143 void
145 {
147  for (iter = currStates.begin(); iter != currStates.end(); iter++) {
148  WalkerState * walkerState = *(iter);
149  if (walkerState->isRetrying()) {
150  walkerState->retry();
151  }
152  }
153 }
154 
155 bool Walker::sendTiming(WalkerState* sendingState, PacketPtr pkt)
156 {
157  WalkerSenderState* walker_state = new WalkerSenderState(sendingState);
158  pkt->pushSenderState(walker_state);
159  if (port.sendTimingReq(pkt)) {
160  return true;
161  } else {
162  // undo the adding of the sender state and delete it, as we
163  // will do it again the next time we attempt to send it
164  pkt->popSenderState();
165  delete walker_state;
166  return false;
167  }
168 
169 }
170 
171 Port &
172 Walker::getPort(const std::string &if_name, PortID idx)
173 {
174  if (if_name == "port")
175  return port;
176  else
177  return ClockedObject::getPort(if_name, idx);
178 }
179 
180 void
182  BaseMMU::Mode _mode, bool _isTiming)
183 {
184  assert(state == Ready);
185  started = false;
186  tc = _tc;
187  mode = _mode;
188  timing = _isTiming;
189 }
190 
191 void
193 {
194  unsigned num_squashed = 0;
195  WalkerState *currState = currStates.front();
196  while ((num_squashed < numSquashable) && currState &&
197  currState->translation->squashed()) {
198  currStates.pop_front();
199  num_squashed++;
200 
201  DPRINTF(PageTableWalker, "Squashing table walk for address %#x\n",
202  currState->req->getVaddr());
203 
204  // finish the translation which will delete the translation object
205  currState->translation->finish(
206  std::make_shared<UnimpFault>("Squashed Inst"),
207  currState->req, currState->tc, currState->mode);
208 
209  // delete the current request if there are no inflight packets.
210  // if there is something in flight, delete when the packets are
211  // received and inflight is zero.
212  if (currState->numInflight() == 0) {
213  delete currState;
214  } else {
215  currState->squash();
216  }
217 
218  // check the next translation request, if it exists
219  if (currStates.size())
220  currState = currStates.front();
221  else
222  currState = NULL;
223  }
224  if (currState && !currState->wasStarted())
225  currState->startWalk();
226 }
227 
228 Fault
230 {
231  Fault fault = NoFault;
232  assert(!started);
233  started = true;
234  setupWalk(req->getVaddr());
235  if (timing) {
236  nextState = state;
237  state = Waiting;
238  timingFault = NoFault;
239  sendPackets();
240  } else {
241  do {
242  walker->port.sendAtomic(read);
243  PacketPtr write = NULL;
244  fault = stepWalk(write);
245  assert(fault == NoFault || read == NULL);
246  state = nextState;
247  nextState = Ready;
248  if (write)
249  walker->port.sendAtomic(write);
250  } while (read);
251  state = Ready;
252  nextState = Waiting;
253  }
254  return fault;
255 }
256 
257 Fault
259 {
260  Fault fault = NoFault;
261  assert(!started);
262  started = true;
263  setupWalk(addr);
264 
265  do {
266  walker->port.sendFunctional(read);
267  // On a functional access (page table lookup), writes should
268  // not happen so this pointer is ignored after stepWalk
269  PacketPtr write = NULL;
270  fault = stepWalk(write);
271  assert(fault == NoFault || read == NULL);
272  state = nextState;
273  nextState = Ready;
274  } while (read);
275  logBytes = entry.logBytes;
276  addr = entry.paddr;
277 
278  return fault;
279 }
280 
281 Fault
283 {
284  assert(state != Ready && state != Waiting);
285  Fault fault = NoFault;
286  write = NULL;
287  PageTableEntry pte;
288  if (dataSize == 8)
289  pte = read->getLE<uint64_t>();
290  else
291  pte = read->getLE<uint32_t>();
292  VAddr vaddr = entry.vaddr;
293  bool uncacheable = pte.pcd;
294  Addr nextRead = 0;
295  bool doWrite = false;
296  bool doTLBInsert = false;
297  bool doEndWalk = false;
298  bool badNX = pte.nx && mode == BaseMMU::Execute && enableNX;
299  switch(state) {
300  case LongPML4:
301  DPRINTF(PageTableWalker,
302  "Got long mode PML4 entry %#016x.\n", (uint64_t)pte);
303  nextRead = ((uint64_t)pte & (mask(40) << 12)) + vaddr.longl3 * dataSize;
304  doWrite = !pte.a;
305  pte.a = 1;
306  entry.writable = pte.w;
307  entry.user = pte.u;
308  if (badNX || !pte.p) {
309  doEndWalk = true;
310  fault = pageFault(pte.p);
311  break;
312  }
313  entry.noExec = pte.nx;
314  nextState = LongPDP;
315  break;
316  case LongPDP:
317  DPRINTF(PageTableWalker,
318  "Got long mode PDP entry %#016x.\n", (uint64_t)pte);
319  nextRead = ((uint64_t)pte & (mask(40) << 12)) + vaddr.longl2 * dataSize;
320  doWrite = !pte.a;
321  pte.a = 1;
322  entry.writable = entry.writable && pte.w;
323  entry.user = entry.user && pte.u;
324  if (badNX || !pte.p) {
325  doEndWalk = true;
326  fault = pageFault(pte.p);
327  break;
328  }
329  nextState = LongPD;
330  break;
331  case LongPD:
332  DPRINTF(PageTableWalker,
333  "Got long mode PD entry %#016x.\n", (uint64_t)pte);
334  doWrite = !pte.a;
335  pte.a = 1;
336  entry.writable = entry.writable && pte.w;
337  entry.user = entry.user && pte.u;
338  if (badNX || !pte.p) {
339  doEndWalk = true;
340  fault = pageFault(pte.p);
341  break;
342  }
343  if (!pte.ps) {
344  // 4 KB page
345  entry.logBytes = 12;
346  nextRead =
347  ((uint64_t)pte & (mask(40) << 12)) + vaddr.longl1 * dataSize;
348  nextState = LongPTE;
349  break;
350  } else {
351  // 2 MB page
352  entry.logBytes = 21;
353  entry.paddr = (uint64_t)pte & (mask(31) << 21);
354  entry.uncacheable = uncacheable;
355  entry.global = pte.g;
356  entry.patBit = bits(pte, 12);
357  entry.vaddr = entry.vaddr & ~((2 * (1 << 20)) - 1);
358  doTLBInsert = true;
359  doEndWalk = true;
360  break;
361  }
362  case LongPTE:
363  DPRINTF(PageTableWalker,
364  "Got long mode PTE entry %#016x.\n", (uint64_t)pte);
365  doWrite = !pte.a;
366  pte.a = 1;
367  entry.writable = entry.writable && pte.w;
368  entry.user = entry.user && pte.u;
369  if (badNX || !pte.p) {
370  doEndWalk = true;
371  fault = pageFault(pte.p);
372  break;
373  }
374  entry.paddr = (uint64_t)pte & (mask(40) << 12);
375  entry.uncacheable = uncacheable;
376  entry.global = pte.g;
377  entry.patBit = bits(pte, 12);
378  entry.vaddr = entry.vaddr & ~((4 * (1 << 10)) - 1);
379  doTLBInsert = true;
380  doEndWalk = true;
381  break;
382  case PAEPDP:
383  DPRINTF(PageTableWalker,
384  "Got legacy mode PAE PDP entry %#08x.\n", (uint32_t)pte);
385  nextRead = ((uint64_t)pte & (mask(40) << 12)) + vaddr.pael2 * dataSize;
386  if (!pte.p) {
387  doEndWalk = true;
388  fault = pageFault(pte.p);
389  break;
390  }
391  nextState = PAEPD;
392  break;
393  case PAEPD:
394  DPRINTF(PageTableWalker,
395  "Got legacy mode PAE PD entry %#08x.\n", (uint32_t)pte);
396  doWrite = !pte.a;
397  pte.a = 1;
398  entry.writable = pte.w;
399  entry.user = pte.u;
400  if (badNX || !pte.p) {
401  doEndWalk = true;
402  fault = pageFault(pte.p);
403  break;
404  }
405  if (!pte.ps) {
406  // 4 KB page
407  entry.logBytes = 12;
408  nextRead = ((uint64_t)pte & (mask(40) << 12)) + vaddr.pael1 * dataSize;
409  nextState = PAEPTE;
410  break;
411  } else {
412  // 2 MB page
413  entry.logBytes = 21;
414  entry.paddr = (uint64_t)pte & (mask(31) << 21);
415  entry.uncacheable = uncacheable;
416  entry.global = pte.g;
417  entry.patBit = bits(pte, 12);
418  entry.vaddr = entry.vaddr & ~((2 * (1 << 20)) - 1);
419  doTLBInsert = true;
420  doEndWalk = true;
421  break;
422  }
423  case PAEPTE:
424  DPRINTF(PageTableWalker,
425  "Got legacy mode PAE PTE entry %#08x.\n", (uint32_t)pte);
426  doWrite = !pte.a;
427  pte.a = 1;
428  entry.writable = entry.writable && pte.w;
429  entry.user = entry.user && pte.u;
430  if (badNX || !pte.p) {
431  doEndWalk = true;
432  fault = pageFault(pte.p);
433  break;
434  }
435  entry.paddr = (uint64_t)pte & (mask(40) << 12);
436  entry.uncacheable = uncacheable;
437  entry.global = pte.g;
438  entry.patBit = bits(pte, 7);
439  entry.vaddr = entry.vaddr & ~((4 * (1 << 10)) - 1);
440  doTLBInsert = true;
441  doEndWalk = true;
442  break;
443  case PSEPD:
444  DPRINTF(PageTableWalker,
445  "Got legacy mode PSE PD entry %#08x.\n", (uint32_t)pte);
446  doWrite = !pte.a;
447  pte.a = 1;
448  entry.writable = pte.w;
449  entry.user = pte.u;
450  if (!pte.p) {
451  doEndWalk = true;
452  fault = pageFault(pte.p);
453  break;
454  }
455  if (!pte.ps) {
456  // 4 KB page
457  entry.logBytes = 12;
458  nextRead =
459  ((uint64_t)pte & (mask(20) << 12)) + vaddr.norml2 * dataSize;
460  nextState = PTE;
461  break;
462  } else {
463  // 4 MB page
464  entry.logBytes = 21;
465  entry.paddr = bits(pte, 20, 13) << 32 | bits(pte, 31, 22) << 22;
466  entry.uncacheable = uncacheable;
467  entry.global = pte.g;
468  entry.patBit = bits(pte, 12);
469  entry.vaddr = entry.vaddr & ~((4 * (1 << 20)) - 1);
470  doTLBInsert = true;
471  doEndWalk = true;
472  break;
473  }
474  case PD:
475  DPRINTF(PageTableWalker,
476  "Got legacy mode PD entry %#08x.\n", (uint32_t)pte);
477  doWrite = !pte.a;
478  pte.a = 1;
479  entry.writable = pte.w;
480  entry.user = pte.u;
481  if (!pte.p) {
482  doEndWalk = true;
483  fault = pageFault(pte.p);
484  break;
485  }
486  // 4 KB page
487  entry.logBytes = 12;
488  nextRead = ((uint64_t)pte & (mask(20) << 12)) + vaddr.norml2 * dataSize;
489  nextState = PTE;
490  break;
491  case PTE:
492  DPRINTF(PageTableWalker,
493  "Got legacy mode PTE entry %#08x.\n", (uint32_t)pte);
494  doWrite = !pte.a;
495  pte.a = 1;
496  entry.writable = pte.w;
497  entry.user = pte.u;
498  if (!pte.p) {
499  doEndWalk = true;
500  fault = pageFault(pte.p);
501  break;
502  }
503  entry.paddr = (uint64_t)pte & (mask(20) << 12);
504  entry.uncacheable = uncacheable;
505  entry.global = pte.g;
506  entry.patBit = bits(pte, 7);
507  entry.vaddr = entry.vaddr & ~((4 * (1 << 10)) - 1);
508  doTLBInsert = true;
509  doEndWalk = true;
510  break;
511  default:
512  panic("Unknown page table walker state %d!\n");
513  }
514  if (doEndWalk) {
515  if (doTLBInsert)
516  if (!functional)
517  walker->tlb->insert(entry.vaddr, entry);
518  endWalk();
519  } else {
520  PacketPtr oldRead = read;
521  //If we didn't return, we're setting up another read.
522  Request::Flags flags = oldRead->req->getFlags();
523  flags.set(Request::UNCACHEABLE, uncacheable);
524  RequestPtr request = std::make_shared<Request>(
525  nextRead, oldRead->getSize(), flags, walker->requestorId);
526  read = new Packet(request, MemCmd::ReadReq);
527  read->allocate();
528  // If we need to write, adjust the read packet to write the modified
529  // value back to memory.
530  if (doWrite) {
531  write = oldRead;
532  write->setLE<uint64_t>(pte);
533  write->cmd = MemCmd::WriteReq;
534  } else {
535  write = NULL;
536  delete oldRead;
537  }
538  }
539  return fault;
540 }
541 
542 void
544 {
545  nextState = Ready;
546  delete read;
547  read = NULL;
548 }
549 
550 void
552 {
553  VAddr addr = vaddr;
554  CR3 cr3 = tc->readMiscRegNoEffect(MISCREG_CR3);
555  // Check if we're in long mode or not
556  Efer efer = tc->readMiscRegNoEffect(MISCREG_EFER);
557  dataSize = 8;
558  Addr topAddr;
559  if (efer.lma) {
560  // Do long mode.
561  state = LongPML4;
562  topAddr = (cr3.longPdtb << 12) + addr.longl4 * dataSize;
563  enableNX = efer.nxe;
564  } else {
565  // We're in some flavor of legacy mode.
566  CR4 cr4 = tc->readMiscRegNoEffect(MISCREG_CR4);
567  if (cr4.pae) {
568  // Do legacy PAE.
569  state = PAEPDP;
570  topAddr = (cr3.paePdtb << 5) + addr.pael3 * dataSize;
571  enableNX = efer.nxe;
572  } else {
573  dataSize = 4;
574  topAddr = (cr3.pdtb << 12) + addr.norml2 * dataSize;
575  if (cr4.pse) {
576  // Do legacy PSE.
577  state = PSEPD;
578  } else {
579  // Do legacy non PSE.
580  state = PD;
581  }
582  enableNX = false;
583  }
584  }
585 
586  nextState = Ready;
587  entry.vaddr = vaddr;
588 
590  if (cr3.pcd)
591  flags.set(Request::UNCACHEABLE);
592 
593  RequestPtr request = std::make_shared<Request>(
594  topAddr, dataSize, flags, walker->requestorId);
595 
596  read = new Packet(request, MemCmd::ReadReq);
597  read->allocate();
598 }
599 
600 bool
602 {
603  assert(pkt->isResponse());
604  assert(inflight);
605  assert(state == Waiting);
606  inflight--;
607  if (squashed) {
608  // if were were squashed, return true once inflight is zero and
609  // this WalkerState will be freed there.
610  return (inflight == 0);
611  }
612  if (pkt->isRead()) {
613  // should not have a pending read it we also had one outstanding
614  assert(!read);
615 
616  // @todo someone should pay for this
617  pkt->headerDelay = pkt->payloadDelay = 0;
618 
619  state = nextState;
620  nextState = Ready;
621  PacketPtr write = NULL;
622  read = pkt;
623  timingFault = stepWalk(write);
624  state = Waiting;
625  assert(timingFault == NoFault || read == NULL);
626  if (write) {
627  writes.push_back(write);
628  }
629  sendPackets();
630  } else {
631  sendPackets();
632  }
633  if (inflight == 0 && read == NULL && writes.size() == 0) {
634  state = Ready;
635  nextState = Waiting;
636  if (timingFault == NoFault) {
637  /*
638  * Finish the translation. Now that we know the right entry is
639  * in the TLB, this should work with no memory accesses.
640  * There could be new faults unrelated to the table walk like
641  * permissions violations, so we'll need the return value as
642  * well.
643  */
644  bool delayedResponse;
645  Fault fault = walker->tlb->translate(req, tc, NULL, mode,
646  delayedResponse, true);
647  assert(!delayedResponse);
648  // Let the CPU continue.
649  translation->finish(fault, req, tc, mode);
650  } else {
651  // There was a fault during the walk. Let the CPU know.
652  translation->finish(timingFault, req, tc, mode);
653  }
654  return true;
655  }
656 
657  return false;
658 }
659 
660 void
662 {
663  //If we're already waiting for the port to become available, just return.
664  if (retrying)
665  return;
666 
667  //Reads always have priority
668  if (read) {
669  PacketPtr pkt = read;
670  read = NULL;
671  inflight++;
672  if (!walker->sendTiming(this, pkt)) {
673  retrying = true;
674  read = pkt;
675  inflight--;
676  return;
677  }
678  }
679  //Send off as many of the writes as we can.
680  while (writes.size()) {
681  PacketPtr write = writes.back();
682  writes.pop_back();
683  inflight++;
684  if (!walker->sendTiming(this, write)) {
685  retrying = true;
686  writes.push_back(write);
687  inflight--;
688  return;
689  }
690  }
691 }
692 
693 unsigned
695 {
696  return inflight;
697 }
698 
699 bool
701 {
702  return retrying;
703 }
704 
705 bool
707 {
708  return timing;
709 }
710 
711 bool
713 {
714  return started;
715 }
716 
717 void
719 {
720  squashed = true;
721 }
722 
723 void
725 {
726  retrying = false;
727  sendPackets();
728 }
729 
730 Fault
732 {
733  DPRINTF(PageTableWalker, "Raising page fault.\n");
734  HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
735  if (mode == BaseMMU::Execute && !enableNX)
737  return std::make_shared<PageFault>(entry.vaddr, present, mode,
738  m5reg.cpl == 3, false);
739 }
740 
741 } // namespace X86ISA
742 } // namespace gem5
gem5::X86ISA::Walker::WalkerSenderState
Definition: pagetable_walker.hh:156
gem5::X86ISA::mask
mask
Definition: misc.hh:802
gem5::PortID
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:252
pagetable.hh
gem5::BaseMMU::Translation::squashed
virtual bool squashed() const
This function is used by the page table walker to determine if it should translate the a pending requ...
Definition: mmu.hh:81
gem5::SimObject::getPort
virtual Port & getPort(const std::string &if_name, PortID idx=InvalidPortID)
Get a port with a given name and index.
Definition: sim_object.cc:126
gem5::BaseMMU::Read
@ Read
Definition: mmu.hh:53
gem5::X86ISA::MISCREG_M5_REG
@ MISCREG_M5_REG
Definition: misc.hh:143
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:260
gem5::X86ISA::Walker::WalkerState::startWalk
Fault startWalk()
Definition: pagetable_walker.cc:229
gem5::RequestPort::sendTimingReq
bool sendTimingReq(PacketPtr pkt)
Attempt to send a timing request to the responder port by calling its corresponding receive function.
Definition: port.hh:495
gem5::X86ISA::Walker::WalkerState::translation
BaseMMU::Translation * translation
Definition: pagetable_walker.hh:111
gem5::X86ISA::Walker::WalkerState::isTiming
bool isTiming()
Definition: pagetable_walker.cc:706
gem5::X86ISA::Walker::recvReqRetry
void recvReqRetry()
Definition: pagetable_walker.cc:144
gem5::Packet::pushSenderState
void pushSenderState(SenderState *sender_state)
Push a new sender state to the packet and make the current sender state the predecessor of the new on...
Definition: packet.cc:316
gem5::BaseMMU::Mode
Mode
Definition: mmu.hh:53
gem5::Flags::set
void set(Type mask)
Set all flag's bits matching the given mask.
Definition: flags.hh:116
gem5::Request::UNCACHEABLE
@ UNCACHEABLE
The request is to an uncacheable address.
Definition: request.hh:125
gem5::Packet::req
RequestPtr req
A pointer to the original request.
Definition: packet.hh:366
gem5::X86ISA::Walker::recvTimingResp
bool recvTimingResp(PacketPtr pkt)
Definition: pagetable_walker.cc:110
gem5::X86ISA::Walker::WalkerState::tc
ThreadContext * tc
Definition: pagetable_walker.hh:100
gem5::X86ISA::Walker::getPort
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
Definition: pagetable_walker.cc:172
gem5::X86ISA::Walker::WalkerState::startFunctional
Fault startFunctional(Addr &addr, unsigned &logBytes)
Definition: pagetable_walker.cc:258
gem5::X86ISA::Walker::WalkerState
Definition: pagetable_walker.hh:82
gem5::X86ISA::Walker::WalkerSenderState::senderWalk
WalkerState * senderWalk
Definition: pagetable_walker.hh:158
gem5::X86ISA::Walker::WalkerState::sendPackets
void sendPackets()
Definition: pagetable_walker.cc:661
gem5::X86ISA::Walker::start
Fault start(ThreadContext *_tc, BaseMMU::Translation *translation, const RequestPtr &req, BaseMMU::Mode mode)
Definition: pagetable_walker.cc:71
pagetable_walker.hh
gem5::Request::PHYSICAL
@ PHYSICAL
The virtual address is also the physical address.
Definition: request.hh:117
gem5::EventManager::schedule
void schedule(Event &event, Tick when)
Definition: eventq.hh:1019
gem5::X86ISA::Walker::currStates
std::list< WalkerState * > currStates
Definition: pagetable_walker.hh:152
gem5::Packet::headerDelay
uint32_t headerDelay
The extra delay from seeing the packet until the header is transmitted.
Definition: packet.hh:420
faults.hh
gem5::X86ISA::Walker::port
WalkerPort port
Definition: pagetable_walker.hh:79
gem5::X86ISA::Walker::WalkerState::setupWalk
void setupWalk(Addr vaddr)
Definition: pagetable_walker.cc:551
request.hh
gem5::X86ISA::MISCREG_CR3
@ MISCREG_CR3
Definition: misc.hh:114
gem5::BaseMMU::Execute
@ Execute
Definition: mmu.hh:53
gem5::X86ISA::Walker::WalkerState::recvPacket
bool recvPacket(PacketPtr pkt)
Definition: pagetable_walker.cc:601
gem5::X86ISA::Walker::WalkerState::endWalk
void endWalk()
Definition: pagetable_walker.cc:543
gem5::Packet::payloadDelay
uint32_t payloadDelay
The extra pipelining delay from seeing the packet until the end of payload is transmitted by the comp...
Definition: packet.hh:438
gem5::X86ISA::present
Bitfield< 7 > present
Definition: misc.hh:998
gem5::Flags< FlagsType >
gem5::X86ISA::Walker::WalkerState::retry
void retry()
Definition: pagetable_walker.cc:724
gem5::Packet::isRead
bool isRead() const
Definition: packet.hh:582
bitfield.hh
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::X86ISA::Walker::sendTiming
bool sendTiming(WalkerState *sendingState, PacketPtr pkt)
Definition: pagetable_walker.cc:155
gem5::probing::Packet
ProbePointArg< PacketInfo > Packet
Packet probe point.
Definition: mem.hh:109
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::MemCmd::ReadReq
@ ReadReq
Definition: packet.hh:86
gem5::X86ISA::Walker::WalkerState
friend class WalkerState
Definition: pagetable_walker.hh:149
gem5::X86ISA::MISCREG_CR4
@ MISCREG_CR4
Definition: misc.hh:115
gem5::SparcISA::PageTableEntry
Definition: pagetable.hh:68
gem5::X86ISA::MISCREG_EFER
@ MISCREG_EFER
Definition: misc.hh:251
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
gem5::System::isTimingMode
bool isTimingMode() const
Is the system in timing mode?
Definition: system.hh:276
gem5::X86ISA::Walker::funcState
WalkerState funcState
Definition: pagetable_walker.hh:154
gem5::Packet::cmd
MemCmd cmd
The command field of the packet.
Definition: packet.hh:361
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::X86ISA::Walker::numSquashable
unsigned numSquashable
Definition: pagetable_walker.hh:179
packet_access.hh
gem5::Clocked::clockEdge
Tick clockEdge(Cycles cycles=Cycles(0)) const
Determine the tick when a cycle begins, by default the current one, but the argument also enables the...
Definition: clocked_object.hh:177
gem5::Packet::popSenderState
SenderState * popSenderState()
Pop the top of the state stack and return a pointer to it.
Definition: packet.cc:324
gem5::BaseMMU::Translation
Definition: mmu.hh:55
gem5::X86ISA::Walker::WalkerPort::recvReqRetry
void recvReqRetry()
Called by the peer if sendTimingReq was called on this peer (causing recvTimingReq to be called on th...
Definition: pagetable_walker.cc:138
gem5::X86ISA::Walker::startFunctional
Fault startFunctional(ThreadContext *_tc, Addr &addr, unsigned &logBytes, BaseMMU::Mode mode)
Definition: pagetable_walker.cc:96
base.hh
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
gem5::X86ISA::Walker::WalkerState::isRetrying
bool isRetrying()
Definition: pagetable_walker.cc:700
gem5::X86ISA::Walker::WalkerState::req
RequestPtr req
Definition: pagetable_walker.hh:101
gem5::X86ISA::Walker::WalkerState::wasStarted
bool wasStarted()
Definition: pagetable_walker.cc:712
gem5::MemCmd::WriteReq
@ WriteReq
Definition: packet.hh:89
gem5::X86ISA::Walker::WalkerState::numInflight
unsigned numInflight() const
Definition: pagetable_walker.cc:694
gem5::X86ISA::Walker::WalkerState::mode
BaseMMU::Mode mode
Definition: pagetable_walker.hh:112
gem5::Packet::setLE
void setLE(T v)
Set the value in the data pointer to v as little endian.
Definition: packet_access.hh:108
gem5::MipsISA::vaddr
vaddr
Definition: pra_constants.hh:278
tlb.hh
std::list
STL list class.
Definition: stl.hh:51
gem5::X86ISA::Walker::startWalkWrapperEvent
EventFunctionWrapper startWalkWrapperEvent
Event used to call startWalkWrapper.
Definition: pagetable_walker.hh:187
gem5::X86ISA::Walker::WalkerState::stepWalk
Fault stepWalk(PacketPtr &write)
Definition: pagetable_walker.cc:282
gem5::X86ISA::Walker::WalkerPort::walker
Walker * walker
Definition: pagetable_walker.hh:72
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::X86ISA::Walker::WalkerState::pageFault
Fault pageFault(bool present)
Definition: pagetable_walker.cc:731
gem5::X86ISA::Walker::WalkerState::initState
void initState(ThreadContext *_tc, BaseMMU::Mode _mode, bool _isTiming=false)
Definition: pagetable_walker.cc:181
gem5::BaseMMU::Translation::finish
virtual void finish(const Fault &fault, const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode)=0
gem5::X86ISA::Walker::startWalkWrapper
void startWalkWrapper()
Definition: pagetable_walker.cc:192
gem5::X86ISA::Walker::WalkerState::squash
void squash()
Definition: pagetable_walker.cc:718
gem5::ArmISA::PTE
Definition: pagetable.hh:61
gem5::Packet::isResponse
bool isResponse() const
Definition: packet.hh:587
thread_context.hh
gem5::Packet::getSize
unsigned getSize() const
Definition: packet.hh:791
trie.hh
gem5::Event::scheduled
bool scheduled() const
Determine if the current event is scheduled.
Definition: eventq.hh:465
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::X86ISA::Walker::sys
System * sys
Definition: pagetable_walker.hh:175
gem5::ArmISA::mode
Bitfield< 4, 0 > mode
Definition: misc_types.hh:73
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::X86ISA::Walker::WalkerPort::recvTimingResp
bool recvTimingResp(PacketPtr pkt)
Receive a timing response from the peer.
Definition: pagetable_walker.cc:104

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