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| void | gem5::ArmISA::sendEvent (ThreadContext *tc) |
| | Send an event (SEV) to a specific PE if there isn't already a pending event.
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| bool | gem5::ArmISA::isSecure (ThreadContext *tc) |
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| bool | gem5::ArmISA::isSecureBelowEL3 (ThreadContext *tc) |
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| bool | gem5::ArmISA::isSecureAtEL (ThreadContext *tc, ExceptionLevel el) |
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| ExceptionLevel | gem5::ArmISA::debugTargetFrom (ThreadContext *tc, bool secure) |
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| bool | gem5::ArmISA::inAArch64 (ThreadContext *tc) |
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| ExceptionLevel | gem5::ArmISA::currEL (const ThreadContext *tc) |
| | Returns the current Exception Level (EL) of the provided ThreadContext.
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| bool | gem5::ArmISA::longDescFormatInUse (ThreadContext *tc) |
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| RegVal | gem5::ArmISA::readMPIDR (ArmSystem *arm_sys, ThreadContext *tc) |
| | This helper function is either returing the value of MPIDR_EL1 (by calling getMPIDR), or it is issuing a read to VMPIDR_EL2 (as it happens in virtualized systems)
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| RegVal | gem5::ArmISA::getMPIDR (ArmSystem *arm_sys, ThreadContext *tc) |
| | This helper function is returning the value of MPIDR_EL1.
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| static RegVal | gem5::ArmISA::getAff2 (ArmSystem *arm_sys, ThreadContext *tc) |
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| static RegVal | gem5::ArmISA::getAff1 (ArmSystem *arm_sys, ThreadContext *tc) |
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| static RegVal | gem5::ArmISA::getAff0 (ArmSystem *arm_sys, ThreadContext *tc) |
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| Affinity | gem5::ArmISA::getAffinity (ArmSystem *arm_sys, ThreadContext *tc) |
| | Retrieves MPIDR_EL1.
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| bool | gem5::ArmISA::HaveExt (ThreadContext *tc, ArmExtension ext) |
| | Returns true if the provided ThreadContext supports the ArmExtension passed as a second argument.
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| ExceptionLevel | gem5::ArmISA::s1TranslationRegime (ThreadContext *tc, ExceptionLevel el) |
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| bool | gem5::ArmISA::IsSecureEL2Enabled (ThreadContext *tc) |
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| bool | gem5::ArmISA::EL2Enabled (ThreadContext *tc) |
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| bool | gem5::ArmISA::ELIs64 (ThreadContext *tc, ExceptionLevel el) |
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| bool | gem5::ArmISA::ELIs32 (ThreadContext *tc, ExceptionLevel el) |
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| bool | gem5::ArmISA::ELIsInHost (ThreadContext *tc, ExceptionLevel el) |
| | Returns true if the current exception level el is executing a Host OS or an application of a Host OS (Armv8.1 Virtualization Host Extensions).
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| std::pair< bool, bool > | gem5::ArmISA::ELUsingAArch32K (ThreadContext *tc, ExceptionLevel el) |
| | This function checks whether selected EL provided as an argument is using the AArch32 ISA.
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| bool | gem5::ArmISA::haveAArch32EL (ThreadContext *tc, ExceptionLevel el) |
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| std::pair< bool, bool > | gem5::ArmISA::ELStateUsingAArch32K (ThreadContext *tc, ExceptionLevel el, bool secure) |
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| bool | gem5::ArmISA::ELStateUsingAArch32 (ThreadContext *tc, ExceptionLevel el, bool secure) |
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| bool | gem5::ArmISA::isBigEndian64 (const ThreadContext *tc) |
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| bool | gem5::ArmISA::badMode32 (ThreadContext *tc, OperatingMode mode) |
| | badMode is checking if the execution mode provided as an argument is valid and implemented for AArch32
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| bool | gem5::ArmISA::badMode (ThreadContext *tc, OperatingMode mode) |
| | badMode is checking if the execution mode provided as an argument is valid and implemented.
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| int | gem5::ArmISA::computeAddrTop (ThreadContext *tc, bool selbit, bool is_instr, TCR tcr, ExceptionLevel el) |
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| Addr | gem5::ArmISA::maskTaggedAddr (Addr addr, ThreadContext *tc, ExceptionLevel el, int topbit) |
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| Addr | gem5::ArmISA::purifyTaggedAddr (Addr addr, ThreadContext *tc, ExceptionLevel el, TCR tcr, bool isInstr) |
| | Removes the tag from tagged addresses if that mode is enabled.
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| Addr | gem5::ArmISA::purifyTaggedAddr (Addr addr, ThreadContext *tc, ExceptionLevel el, bool is_instr) |
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| Addr | gem5::ArmISA::truncPage (Addr addr) |
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| Addr | gem5::ArmISA::roundPage (Addr addr) |
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| Fault | gem5::ArmISA::mcrMrc15Trap (const MiscRegIndex misc_reg, ExtMachInst mach_inst, ThreadContext *tc, uint32_t imm) |
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| bool | gem5::ArmISA::mcrMrc15TrapToHyp (const MiscRegIndex misc_reg, ThreadContext *tc, uint32_t iss, ExceptionClass *ec) |
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| bool | gem5::ArmISA::mcrMrc14TrapToHyp (const MiscRegIndex misc_reg, ThreadContext *tc, uint32_t iss) |
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| Fault | gem5::ArmISA::mcrrMrrc15Trap (const MiscRegIndex misc_reg, ExtMachInst mach_inst, ThreadContext *tc, uint32_t imm) |
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| bool | gem5::ArmISA::mcrrMrrc15TrapToHyp (const MiscRegIndex misc_reg, ThreadContext *tc, uint32_t iss, ExceptionClass *ec) |
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| Fault | gem5::ArmISA::AArch64AArch32SystemAccessTrap (const MiscRegIndex misc_reg, ExtMachInst mach_inst, ThreadContext *tc, uint32_t imm, ExceptionClass ec) |
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| bool | gem5::ArmISA::isAArch64AArch32SystemAccessTrapEL1 (const MiscRegIndex misc_reg, ThreadContext *tc) |
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| bool | gem5::ArmISA::isGenericTimerHypTrap (const MiscRegIndex misc_reg, ThreadContext *tc, ExceptionClass *ec) |
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| bool | gem5::ArmISA::isGenericTimerCommonEL0HypTrap (const MiscRegIndex misc_reg, ThreadContext *tc, ExceptionClass *ec) |
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| bool | gem5::ArmISA::isGenericTimerPhysHypTrap (const MiscRegIndex misc_reg, ThreadContext *tc, ExceptionClass *ec) |
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| bool | gem5::ArmISA::condGenericTimerPhysHypTrap (const MiscRegIndex misc_reg, ThreadContext *tc) |
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| bool | gem5::ArmISA::isGenericTimerSystemAccessTrapEL1 (const MiscRegIndex misc_reg, ThreadContext *tc) |
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| bool | gem5::ArmISA::condGenericTimerSystemAccessTrapEL1 (const MiscRegIndex misc_reg, ThreadContext *tc) |
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| bool | gem5::ArmISA::isAArch64AArch32SystemAccessTrapEL2 (const MiscRegIndex misc_reg, ThreadContext *tc) |
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| bool | gem5::ArmISA::isGenericTimerSystemAccessTrapEL2 (const MiscRegIndex misc_reg, ThreadContext *tc) |
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| bool | gem5::ArmISA::isGenericTimerCommonEL0SystemAccessTrapEL2 (const MiscRegIndex misc_reg, ThreadContext *tc) |
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| bool | gem5::ArmISA::isGenericTimerPhysEL0SystemAccessTrapEL2 (const MiscRegIndex misc_reg, ThreadContext *tc) |
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| bool | gem5::ArmISA::isGenericTimerPhysEL1SystemAccessTrapEL2 (const MiscRegIndex misc_reg, ThreadContext *tc) |
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| bool | gem5::ArmISA::isGenericTimerVirtSystemAccessTrapEL2 (const MiscRegIndex misc_reg, ThreadContext *tc) |
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| bool | gem5::ArmISA::condGenericTimerCommonEL0SystemAccessTrapEL2 (const MiscRegIndex misc_reg, ThreadContext *tc) |
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| bool | gem5::ArmISA::condGenericTimerCommonEL1SystemAccessTrapEL2 (const MiscRegIndex misc_reg, ThreadContext *tc) |
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| bool | gem5::ArmISA::condGenericTimerPhysEL1SystemAccessTrapEL2 (const MiscRegIndex misc_reg, ThreadContext *tc) |
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| bool | gem5::ArmISA::isGenericTimerSystemAccessTrapEL3 (const MiscRegIndex misc_reg, ThreadContext *tc) |
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| bool | gem5::ArmISA::decodeMrsMsrBankedReg (uint8_t sysM, bool r, bool &isIntReg, int ®Idx, CPSR cpsr, SCR scr, NSACR nsacr, bool checkSecurity) |
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| bool | gem5::ArmISA::isUnpriviledgeAccess (ThreadContext *tc) |
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| bool | gem5::ArmISA::SPAlignmentCheckEnabled (ThreadContext *tc) |
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| int | gem5::ArmISA::decodePhysAddrRange64 (uint8_t pa_enc) |
| | Returns the n.
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| uint8_t | gem5::ArmISA::encodePhysAddrRange64 (int pa_size) |
| | Returns the encoding corresponding to the specified n.
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| void | gem5::ArmISA::syncVecRegsToElems (ThreadContext *tc) |
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| void | gem5::ArmISA::syncVecElemsToRegs (ThreadContext *tc) |
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| bool | gem5::ArmISA::fgtEnabled (ThreadContext *tc) |
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| bool | gem5::ArmISA::isHcrxEL2Enabled (ThreadContext *tc) |
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| TranslationRegime | gem5::ArmISA::translationRegime (ThreadContext *tc, ExceptionLevel el) |
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| ExceptionLevel | gem5::ArmISA::translationEl (TranslationRegime regime) |
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