gem5  v21.1.0.2
Public Member Functions | Public Attributes | List of all members
gem5::minor::ExecContext Class Reference

ExecContext bears the exec_context interface for Minor. More...

#include <exec_context.hh>

Inheritance diagram for gem5::minor::ExecContext:
gem5::ExecContext

Public Member Functions

 ExecContext (MinorCPU &cpu_, SimpleThread &thread_, Execute &execute_, MinorDynInstPtr inst_, RegIndex zeroReg)
 
 ~ExecContext ()
 
Fault initiateMemRead (Addr addr, unsigned int size, Request::Flags flags, const std::vector< bool > &byte_enable) override
 Initiate a timing memory read operation. More...
 
Fault initiateHtmCmd (Request::Flags flags) override
 Initiate an HTM command, e.g. More...
 
Fault writeMem (uint8_t *data, unsigned int size, Addr addr, Request::Flags flags, uint64_t *res, const std::vector< bool > &byte_enable) override
 For atomic-mode contexts, perform an atomic memory write operation. More...
 
Fault initiateMemAMO (Addr addr, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op) override
 For timing-mode contexts, initiate an atomic AMO (atomic read-modify-write memory operation) More...
 
RegVal readIntRegOperand (const StaticInst *si, int idx) override
 Reads an integer register. More...
 
RegVal readFloatRegOperandBits (const StaticInst *si, int idx) override
 Reads a floating point register in its binary format, instead of by value. More...
 
const TheISA::VecRegContainer & readVecRegOperand (const StaticInst *si, int idx) const override
 Vector Register Interfaces. More...
 
TheISA::VecRegContainer & getWritableVecRegOperand (const StaticInst *si, int idx) override
 Gets destination vector register operand for modification. More...
 
TheISA::VecElem readVecElemOperand (const StaticInst *si, int idx) const override
 Vector Elem Interfaces. More...
 
const TheISA::VecPredRegContainer & readVecPredRegOperand (const StaticInst *si, int idx) const override
 Predicate registers interface. More...
 
TheISA::VecPredRegContainer & getWritableVecPredRegOperand (const StaticInst *si, int idx) override
 Gets destination predicate register operand for modification. More...
 
void setIntRegOperand (const StaticInst *si, int idx, RegVal val) override
 Sets an integer register to a value. More...
 
void setFloatRegOperandBits (const StaticInst *si, int idx, RegVal val) override
 Sets the bits of a floating point register of single width to a binary value. More...
 
void setVecRegOperand (const StaticInst *si, int idx, const TheISA::VecRegContainer &val) override
 Sets a destination vector register operand to a value. More...
 
void setVecPredRegOperand (const StaticInst *si, int idx, const TheISA::VecPredRegContainer &val) override
 Sets a destination predicate register operand to a value. More...
 
void setVecElemOperand (const StaticInst *si, int idx, const TheISA::VecElem val) override
 Sets a vector register to a value. More...
 
bool readPredicate () const override
 
void setPredicate (bool val) override
 
bool readMemAccPredicate () const override
 
void setMemAccPredicate (bool val) override
 
uint64_t getHtmTransactionUid () const override
 
uint64_t newHtmTransactionUid () const override
 
bool inHtmTransactionalState () const override
 
uint64_t getHtmTransactionalDepth () const override
 
TheISA::PCState pcState () const override
 
void pcState (const TheISA::PCState &val) override
 
RegVal readMiscRegNoEffect (int misc_reg) const
 
RegVal readMiscReg (int misc_reg) override
 Reads a miscellaneous register, handling any architectural side effects due to reading that register. More...
 
void setMiscReg (int misc_reg, RegVal val) override
 Sets a miscellaneous register, handling any architectural side effects due to writing that register. More...
 
RegVal readMiscRegOperand (const StaticInst *si, int idx) override
 
void setMiscRegOperand (const StaticInst *si, int idx, RegVal val) override
 
ThreadContexttcBase () const override
 Returns a pointer to the ThreadContext. More...
 
unsigned int readStCondFailures () const override
 Returns the number of consecutive store conditional failures. More...
 
void setStCondFailures (unsigned int st_cond_failures) override
 Sets the number of consecutive store conditional failures. More...
 
ContextID contextId ()
 
void demapPage (Addr vaddr, uint64_t asn) override
 Invalidate a page in the DTLB and ITLB. More...
 
RegVal readCCRegOperand (const StaticInst *si, int idx) override
 
void setCCRegOperand (const StaticInst *si, int idx, RegVal val) override
 
BaseCPUgetCpuPtr ()
 
void armMonitor (Addr address) override
 
bool mwait (PacketPtr pkt) override
 
void mwaitAtomic (ThreadContext *tc) override
 
AddressMonitorgetAddrMonitor () override
 
- Public Member Functions inherited from gem5::ExecContext
virtual Fault readMem (Addr addr, uint8_t *data, unsigned int size, Request::Flags flags, const std::vector< bool > &byte_enable)
 Perform an atomic memory read operation. More...
 
virtual Fault amoMem (Addr addr, uint8_t *data, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op)
 For atomic-mode contexts, perform an atomic AMO (a.k.a., Atomic Read-Modify-Write Memory Operation) More...
 

Public Attributes

MinorCPUcpu
 
SimpleThreadthread
 ThreadState object, provides all the architectural state. More...
 
Executeexecute
 The execute stage so we can peek at its contents. More...
 
MinorDynInstPtr inst
 Instruction for the benefit of memory operations and for PC. More...
 

Detailed Description

ExecContext bears the exec_context interface for Minor.

This nicely separates that interface from other classes such as Pipeline, MinorCPU and DynMinorInst and makes it easier to see what state is accessed by it.

Definition at line 73 of file exec_context.hh.

Constructor & Destructor Documentation

◆ ExecContext()

gem5::minor::ExecContext::ExecContext ( MinorCPU cpu_,
SimpleThread thread_,
Execute execute_,
MinorDynInstPtr  inst_,
RegIndex  zeroReg 
)
inline

◆ ~ExecContext()

gem5::minor::ExecContext::~ExecContext ( )
inline

Definition at line 103 of file exec_context.hh.

References inst, readMemAccPredicate(), and readPredicate().

Member Function Documentation

◆ armMonitor()

void gem5::minor::ExecContext::armMonitor ( Addr  address)
inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 386 of file exec_context.hh.

References gem5::BaseCPU::armMonitor(), getCpuPtr(), and inst.

◆ contextId()

ContextID gem5::minor::ExecContext::contextId ( )
inline

Definition at line 355 of file exec_context.hh.

References gem5::SimpleThread::contextId(), and thread.

◆ demapPage()

void gem5::minor::ExecContext::demapPage ( Addr  vaddr,
uint64_t  asn 
)
inlineoverridevirtual

Invalidate a page in the DTLB and ITLB.

Implements gem5::ExecContext.

Definition at line 360 of file exec_context.hh.

References gem5::BaseMMU::demapPage(), gem5::SimpleThread::getMMUPtr(), thread, and gem5::MipsISA::vaddr.

◆ getAddrMonitor()

AddressMonitor* gem5::minor::ExecContext::getAddrMonitor ( )
inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 404 of file exec_context.hh.

References gem5::BaseCPU::getCpuAddrMonitor(), getCpuPtr(), and inst.

◆ getCpuPtr()

BaseCPU* gem5::minor::ExecContext::getCpuPtr ( )
inline

Definition at line 381 of file exec_context.hh.

References cpu.

Referenced by armMonitor(), getAddrMonitor(), mwait(), and mwaitAtomic().

◆ getHtmTransactionalDepth()

uint64_t gem5::minor::ExecContext::getHtmTransactionalDepth ( ) const
inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 296 of file exec_context.hh.

References panic.

◆ getHtmTransactionUid()

uint64_t gem5::minor::ExecContext::getHtmTransactionUid ( ) const
inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 272 of file exec_context.hh.

References panic.

◆ getWritableVecPredRegOperand()

TheISA::VecPredRegContainer& gem5::minor::ExecContext::getWritableVecPredRegOperand ( const StaticInst si,
int  idx 
)
inlineoverridevirtual

Gets destination predicate register operand for modification.

Implements gem5::ExecContext.

Definition at line 196 of file exec_context.hh.

References gem5::SimpleThread::getWritableVecPredReg(), gem5::X86ISA::reg, gem5::ArmISA::si, thread, and gem5::VecPredRegClass.

◆ getWritableVecRegOperand()

TheISA::VecRegContainer& gem5::minor::ExecContext::getWritableVecRegOperand ( const StaticInst si,
int  idx 
)
inlineoverridevirtual

Gets destination vector register operand for modification.

Implements gem5::ExecContext.

Definition at line 172 of file exec_context.hh.

References gem5::SimpleThread::getWritableVecReg(), gem5::X86ISA::reg, gem5::ArmISA::si, thread, and gem5::VecRegClass.

◆ inHtmTransactionalState()

bool gem5::minor::ExecContext::inHtmTransactionalState ( ) const
inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 288 of file exec_context.hh.

◆ initiateHtmCmd()

Fault gem5::minor::ExecContext::initiateHtmCmd ( Request::Flags  flags)
inlineoverridevirtual

Initiate an HTM command, e.g.

tell Ruby we're starting/stopping a transaction

Implements gem5::ExecContext.

Definition at line 120 of file exec_context.hh.

References gem5::NoFault, and panic.

◆ initiateMemAMO()

Fault gem5::minor::ExecContext::initiateMemAMO ( Addr  addr,
unsigned int  size,
Request::Flags  flags,
AtomicOpFunctorPtr  amo_op 
)
inlineoverridevirtual

For timing-mode contexts, initiate an atomic AMO (atomic read-modify-write memory operation)

Reimplemented from gem5::ExecContext.

Definition at line 138 of file exec_context.hh.

References gem5::X86ISA::addr, execute, gem5::minor::Execute::getLSQ(), inst, and gem5::minor::LSQ::pushRequest().

◆ initiateMemRead()

Fault gem5::minor::ExecContext::initiateMemRead ( Addr  addr,
unsigned int  size,
Request::Flags  flags,
const std::vector< bool > &  byte_enable 
)
inlineoverridevirtual

Initiate a timing memory read operation.

Must be overridden for exec contexts that support timing memory mode. Not pure virtual since exec contexts that only support atomic memory mode need not override (though in that case this function should never be called).

Reimplemented from gem5::ExecContext.

Definition at line 110 of file exec_context.hh.

References gem5::X86ISA::addr, execute, gem5::minor::Execute::getLSQ(), inst, and gem5::minor::LSQ::pushRequest().

◆ mwait()

bool gem5::minor::ExecContext::mwait ( PacketPtr  pkt)
inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 392 of file exec_context.hh.

References getCpuPtr(), inst, and gem5::BaseCPU::mwait().

◆ mwaitAtomic()

void gem5::minor::ExecContext::mwaitAtomic ( ThreadContext tc)
inlineoverridevirtual

◆ newHtmTransactionUid()

uint64_t gem5::minor::ExecContext::newHtmTransactionUid ( ) const
inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 280 of file exec_context.hh.

References panic.

◆ pcState() [1/2]

TheISA::PCState gem5::minor::ExecContext::pcState ( ) const
inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 304 of file exec_context.hh.

References gem5::SimpleThread::pcState(), and thread.

Referenced by ExecContext().

◆ pcState() [2/2]

void gem5::minor::ExecContext::pcState ( const TheISA::PCState &  val)
inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 310 of file exec_context.hh.

References gem5::SimpleThread::pcState(), thread, and gem5::X86ISA::val.

◆ readCCRegOperand()

RegVal gem5::minor::ExecContext::readCCRegOperand ( const StaticInst si,
int  idx 
)
inlineoverridevirtual

◆ readFloatRegOperandBits()

RegVal gem5::minor::ExecContext::readFloatRegOperandBits ( const StaticInst si,
int  idx 
)
inlineoverridevirtual

Reads a floating point register in its binary format, instead of by value.

Implements gem5::ExecContext.

Definition at line 156 of file exec_context.hh.

References gem5::FloatRegClass, gem5::SimpleThread::readFloatReg(), gem5::X86ISA::reg, gem5::ArmISA::si, and thread.

◆ readIntRegOperand()

RegVal gem5::minor::ExecContext::readIntRegOperand ( const StaticInst si,
int  idx 
)
inlineoverridevirtual

Reads an integer register.

Implements gem5::ExecContext.

Definition at line 148 of file exec_context.hh.

References gem5::IntRegClass, gem5::SimpleThread::readIntReg(), gem5::X86ISA::reg, gem5::ArmISA::si, and thread.

◆ readMemAccPredicate()

bool gem5::minor::ExecContext::readMemAccPredicate ( ) const
inlineoverridevirtual

◆ readMiscReg()

RegVal gem5::minor::ExecContext::readMiscReg ( int  misc_reg)
inlineoverridevirtual

Reads a miscellaneous register, handling any architectural side effects due to reading that register.

Implements gem5::ExecContext.

Definition at line 322 of file exec_context.hh.

References gem5::SimpleThread::readMiscReg(), and thread.

◆ readMiscRegNoEffect()

RegVal gem5::minor::ExecContext::readMiscRegNoEffect ( int  misc_reg) const
inline

Definition at line 316 of file exec_context.hh.

References gem5::SimpleThread::readMiscRegNoEffect(), and thread.

◆ readMiscRegOperand()

RegVal gem5::minor::ExecContext::readMiscRegOperand ( const StaticInst si,
int  idx 
)
inlineoverridevirtual

◆ readPredicate()

bool gem5::minor::ExecContext::readPredicate ( ) const
inlineoverridevirtual

◆ readStCondFailures()

unsigned int gem5::minor::ExecContext::readStCondFailures ( ) const
inlineoverridevirtual

Returns the number of consecutive store conditional failures.

Implements gem5::ExecContext.

Definition at line 352 of file exec_context.hh.

◆ readVecElemOperand()

TheISA::VecElem gem5::minor::ExecContext::readVecElemOperand ( const StaticInst si,
int  idx 
) const
inlineoverridevirtual

Vector Elem Interfaces.

Reads an element of a vector register.

Implements gem5::ExecContext.

Definition at line 180 of file exec_context.hh.

References gem5::SimpleThread::readVecElem(), gem5::X86ISA::reg, gem5::ArmISA::si, thread, and gem5::VecElemClass.

◆ readVecPredRegOperand()

const TheISA::VecPredRegContainer& gem5::minor::ExecContext::readVecPredRegOperand ( const StaticInst si,
int  idx 
) const
inlineoverridevirtual

Predicate registers interface.

Reads source predicate register operand.

Implements gem5::ExecContext.

Definition at line 188 of file exec_context.hh.

References gem5::SimpleThread::readVecPredReg(), gem5::X86ISA::reg, gem5::ArmISA::si, thread, and gem5::VecPredRegClass.

◆ readVecRegOperand()

const TheISA::VecRegContainer& gem5::minor::ExecContext::readVecRegOperand ( const StaticInst si,
int  idx 
) const
inlineoverridevirtual

Vector Register Interfaces.

Reads source vector register operand.

Implements gem5::ExecContext.

Definition at line 164 of file exec_context.hh.

References gem5::SimpleThread::readVecReg(), gem5::X86ISA::reg, gem5::ArmISA::si, thread, and gem5::VecRegClass.

◆ setCCRegOperand()

void gem5::minor::ExecContext::setCCRegOperand ( const StaticInst si,
int  idx,
RegVal  val 
)
inlineoverridevirtual

◆ setFloatRegOperandBits()

void gem5::minor::ExecContext::setFloatRegOperandBits ( const StaticInst si,
int  idx,
RegVal  val 
)
inlineoverridevirtual

Sets the bits of a floating point register of single width to a binary value.

Implements gem5::ExecContext.

Definition at line 212 of file exec_context.hh.

References gem5::FloatRegClass, gem5::X86ISA::reg, gem5::SimpleThread::setFloatReg(), gem5::ArmISA::si, thread, and gem5::X86ISA::val.

◆ setIntRegOperand()

void gem5::minor::ExecContext::setIntRegOperand ( const StaticInst si,
int  idx,
RegVal  val 
)
inlineoverridevirtual

Sets an integer register to a value.

Implements gem5::ExecContext.

Definition at line 204 of file exec_context.hh.

References gem5::IntRegClass, gem5::X86ISA::reg, gem5::SimpleThread::setIntReg(), gem5::ArmISA::si, thread, and gem5::X86ISA::val.

◆ setMemAccPredicate()

void gem5::minor::ExecContext::setMemAccPredicate ( bool  val)
inlineoverridevirtual

◆ setMiscReg()

void gem5::minor::ExecContext::setMiscReg ( int  misc_reg,
RegVal  val 
)
inlineoverridevirtual

Sets a miscellaneous register, handling any architectural side effects due to writing that register.

Implements gem5::ExecContext.

Definition at line 328 of file exec_context.hh.

References gem5::SimpleThread::setMiscReg(), thread, and gem5::X86ISA::val.

◆ setMiscRegOperand()

void gem5::minor::ExecContext::setMiscRegOperand ( const StaticInst si,
int  idx,
RegVal  val 
)
inlineoverridevirtual

◆ setPredicate()

void gem5::minor::ExecContext::setPredicate ( bool  val)
inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 253 of file exec_context.hh.

References gem5::SimpleThread::setPredicate(), thread, and gem5::X86ISA::val.

Referenced by ExecContext().

◆ setStCondFailures()

void gem5::minor::ExecContext::setStCondFailures ( unsigned int  sc_failures)
inlineoverridevirtual

Sets the number of consecutive store conditional failures.

Implements gem5::ExecContext.

Definition at line 353 of file exec_context.hh.

◆ setVecElemOperand()

void gem5::minor::ExecContext::setVecElemOperand ( const StaticInst si,
int  idx,
const TheISA::VecElem  val 
)
inlineoverridevirtual

Sets a vector register to a value.

Implements gem5::ExecContext.

Definition at line 238 of file exec_context.hh.

References gem5::X86ISA::reg, gem5::SimpleThread::setVecElem(), gem5::ArmISA::si, thread, gem5::X86ISA::val, and gem5::VecElemClass.

◆ setVecPredRegOperand()

void gem5::minor::ExecContext::setVecPredRegOperand ( const StaticInst si,
int  idx,
const TheISA::VecPredRegContainer &  val 
)
inlineoverridevirtual

Sets a destination predicate register operand to a value.

Implements gem5::ExecContext.

Definition at line 229 of file exec_context.hh.

References gem5::X86ISA::reg, gem5::SimpleThread::setVecPredReg(), gem5::ArmISA::si, thread, gem5::X86ISA::val, and gem5::VecPredRegClass.

◆ setVecRegOperand()

void gem5::minor::ExecContext::setVecRegOperand ( const StaticInst si,
int  idx,
const TheISA::VecRegContainer &  val 
)
inlineoverridevirtual

Sets a destination vector register operand to a value.

Implements gem5::ExecContext.

Definition at line 220 of file exec_context.hh.

References gem5::X86ISA::reg, gem5::SimpleThread::setVecReg(), gem5::ArmISA::si, thread, gem5::X86ISA::val, and gem5::VecRegClass.

◆ tcBase()

ThreadContext* gem5::minor::ExecContext::tcBase ( ) const
inlineoverridevirtual

Returns a pointer to the ThreadContext.

Implements gem5::ExecContext.

Definition at line 349 of file exec_context.hh.

References gem5::SimpleThread::getTC(), and thread.

◆ writeMem()

Fault gem5::minor::ExecContext::writeMem ( uint8_t *  data,
unsigned int  size,
Addr  addr,
Request::Flags  flags,
uint64_t *  res,
const std::vector< bool > &  byte_enable 
)
inlineoverridevirtual

For atomic-mode contexts, perform an atomic memory write operation.

For timing-mode contexts, initiate a timing memory write operation.

Implements gem5::ExecContext.

Definition at line 127 of file exec_context.hh.

References gem5::X86ISA::addr, data, execute, gem5::minor::Execute::getLSQ(), inst, and gem5::minor::LSQ::pushRequest().

Member Data Documentation

◆ cpu

MinorCPU& gem5::minor::ExecContext::cpu

Definition at line 76 of file exec_context.hh.

Referenced by getCpuPtr().

◆ execute

Execute& gem5::minor::ExecContext::execute

The execute stage so we can peek at its contents.

Definition at line 82 of file exec_context.hh.

Referenced by initiateMemAMO(), initiateMemRead(), and writeMem().

◆ inst

MinorDynInstPtr gem5::minor::ExecContext::inst

Instruction for the benefit of memory operations and for PC.

Definition at line 85 of file exec_context.hh.

Referenced by armMonitor(), ExecContext(), getAddrMonitor(), initiateMemAMO(), initiateMemRead(), mwait(), mwaitAtomic(), writeMem(), and ~ExecContext().

◆ thread

SimpleThread& gem5::minor::ExecContext::thread

The documentation for this class was generated from the following file:

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