gem5
v22.1.0.0
|
ExecContext bears the exec_context interface for Minor. More...
#include <exec_context.hh>
Public Member Functions | |
ExecContext (MinorCPU &cpu_, SimpleThread &thread_, Execute &execute_, MinorDynInstPtr inst_) | |
~ExecContext () | |
Fault | initiateMemRead (Addr addr, unsigned int size, Request::Flags flags, const std::vector< bool > &byte_enable) override |
Initiate a timing memory read operation. More... | |
Fault | initiateMemMgmtCmd (Request::Flags flags) override |
Initiate a memory management command with no valid address. More... | |
Fault | writeMem (uint8_t *data, unsigned int size, Addr addr, Request::Flags flags, uint64_t *res, const std::vector< bool > &byte_enable) override |
For atomic-mode contexts, perform an atomic memory write operation. More... | |
Fault | initiateMemAMO (Addr addr, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op) override |
For timing-mode contexts, initiate an atomic AMO (atomic read-modify-write memory operation) More... | |
RegVal | getRegOperand (const StaticInst *si, int idx) override |
void | getRegOperand (const StaticInst *si, int idx, void *val) override |
void * | getWritableRegOperand (const StaticInst *si, int idx) override |
void | setRegOperand (const StaticInst *si, int idx, RegVal val) override |
void | setRegOperand (const StaticInst *si, int idx, const void *val) override |
bool | readPredicate () const override |
void | setPredicate (bool val) override |
bool | readMemAccPredicate () const override |
void | setMemAccPredicate (bool val) override |
uint64_t | getHtmTransactionUid () const override |
uint64_t | newHtmTransactionUid () const override |
bool | inHtmTransactionalState () const override |
uint64_t | getHtmTransactionalDepth () const override |
const PCStateBase & | pcState () const override |
void | pcState (const PCStateBase &val) override |
RegVal | readMiscRegNoEffect (int misc_reg) const |
RegVal | readMiscReg (int misc_reg) override |
Reads a miscellaneous register, handling any architectural side effects due to reading that register. More... | |
void | setMiscReg (int misc_reg, RegVal val) override |
Sets a miscellaneous register, handling any architectural side effects due to writing that register. More... | |
RegVal | readMiscRegOperand (const StaticInst *si, int idx) override |
void | setMiscRegOperand (const StaticInst *si, int idx, RegVal val) override |
ThreadContext * | tcBase () const override |
Returns a pointer to the ThreadContext. More... | |
unsigned int | readStCondFailures () const override |
Returns the number of consecutive store conditional failures. More... | |
void | setStCondFailures (unsigned int st_cond_failures) override |
Sets the number of consecutive store conditional failures. More... | |
ContextID | contextId () |
void | demapPage (Addr vaddr, uint64_t asn) override |
Invalidate a page in the DTLB and ITLB. More... | |
BaseCPU * | getCpuPtr () |
void | armMonitor (Addr address) override |
bool | mwait (PacketPtr pkt) override |
void | mwaitAtomic (ThreadContext *tc) override |
AddressMonitor * | getAddrMonitor () override |
![]() | |
virtual Fault | readMem (Addr addr, uint8_t *data, unsigned int size, Request::Flags flags, const std::vector< bool > &byte_enable) |
Perform an atomic memory read operation. More... | |
virtual Fault | amoMem (Addr addr, uint8_t *data, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op) |
For atomic-mode contexts, perform an atomic AMO (a.k.a., Atomic Read-Modify-Write Memory Operation) More... | |
Public Attributes | |
MinorCPU & | cpu |
SimpleThread & | thread |
ThreadState object, provides all the architectural state. More... | |
Execute & | execute |
The execute stage so we can peek at its contents. More... | |
MinorDynInstPtr | inst |
Instruction for the benefit of memory operations and for PC. More... | |
ExecContext bears the exec_context interface for Minor.
This nicely separates that interface from other classes such as Pipeline, MinorCPU and DynMinorInst and makes it easier to see what state is accessed by it.
Definition at line 73 of file exec_context.hh.
|
inline |
Definition at line 87 of file exec_context.hh.
References DPRINTF, inst, pcState(), setMemAccPredicate(), and setPredicate().
|
inline |
Definition at line 102 of file exec_context.hh.
References inst, readMemAccPredicate(), and readPredicate().
|
inlineoverridevirtual |
Implements gem5::ExecContext.
Definition at line 307 of file exec_context.hh.
References gem5::BaseCPU::armMonitor(), getCpuPtr(), and inst.
|
inline |
Definition at line 292 of file exec_context.hh.
References gem5::SimpleThread::contextId(), and thread.
|
inlineoverridevirtual |
Invalidate a page in the DTLB and ITLB.
Implements gem5::ExecContext.
Definition at line 297 of file exec_context.hh.
References gem5::BaseMMU::demapPage(), gem5::SimpleThread::getMMUPtr(), thread, and gem5::MipsISA::vaddr.
|
inlineoverridevirtual |
Implements gem5::ExecContext.
Definition at line 325 of file exec_context.hh.
References gem5::BaseCPU::getCpuAddrMonitor(), getCpuPtr(), and inst.
|
inline |
Definition at line 302 of file exec_context.hh.
References cpu.
Referenced by armMonitor(), getAddrMonitor(), mwait(), and mwaitAtomic().
|
inlineoverridevirtual |
|
inlineoverridevirtual |
|
inlineoverridevirtual |
Implements gem5::ExecContext.
Definition at line 148 of file exec_context.hh.
References gem5::SimpleThread::getReg(), gem5::InvalidRegClass, gem5::X86ISA::reg, gem5::ArmISA::si, and thread.
|
inlineoverridevirtual |
Implements gem5::ExecContext.
Definition at line 157 of file exec_context.hh.
References gem5::SimpleThread::getReg(), gem5::ArmISA::si, thread, and gem5::X86ISA::val.
|
inlineoverridevirtual |
Implements gem5::ExecContext.
Definition at line 163 of file exec_context.hh.
References gem5::SimpleThread::getWritableReg(), gem5::ArmISA::si, and thread.
|
inlineoverridevirtual |
Implements gem5::ExecContext.
Definition at line 225 of file exec_context.hh.
|
inlineoverridevirtual |
For timing-mode contexts, initiate an atomic AMO (atomic read-modify-write memory operation)
Reimplemented from gem5::ExecContext.
Definition at line 138 of file exec_context.hh.
References gem5::X86ISA::addr, execute, flags, gem5::minor::Execute::getLSQ(), inst, and gem5::minor::LSQ::pushRequest().
|
inlineoverridevirtual |
Initiate a memory management command with no valid address.
Currently, these instructions need to bypass squashing in the O3 model Examples include HTM commands and TLBI commands. e.g. tell Ruby we're starting/stopping a HTM transaction, or tell Ruby to issue a TLBI operation
Implements gem5::ExecContext.
Definition at line 119 of file exec_context.hh.
References gem5::NoFault, and panic.
|
inlineoverridevirtual |
Initiate a timing memory read operation.
Must be overridden for exec contexts that support timing memory mode. Not pure virtual since exec contexts that only support atomic memory mode need not override (though in that case this function should never be called).
Reimplemented from gem5::ExecContext.
Definition at line 109 of file exec_context.hh.
References gem5::X86ISA::addr, execute, flags, gem5::minor::Execute::getLSQ(), inst, and gem5::minor::LSQ::pushRequest().
|
inlineoverridevirtual |
Implements gem5::ExecContext.
Definition at line 313 of file exec_context.hh.
References getCpuPtr(), inst, and gem5::BaseCPU::mwait().
|
inlineoverridevirtual |
Implements gem5::ExecContext.
Definition at line 319 of file exec_context.hh.
References getCpuPtr(), inst, gem5::SimpleThread::mmu, gem5::BaseCPU::mwaitAtomic(), and thread.
|
inlineoverridevirtual |
|
inlineoverridevirtual |
Implements gem5::ExecContext.
Definition at line 241 of file exec_context.hh.
References gem5::SimpleThread::pcState(), and thread.
Referenced by ExecContext().
|
inlineoverridevirtual |
Implements gem5::ExecContext.
Definition at line 247 of file exec_context.hh.
References gem5::SimpleThread::pcState(), thread, and gem5::X86ISA::val.
|
inlineoverridevirtual |
Implements gem5::ExecContext.
Definition at line 196 of file exec_context.hh.
References gem5::SimpleThread::readMemAccPredicate(), and thread.
Referenced by gem5::minor::Execute::executeMemRefInst(), gem5::minor::Execute::handleMemResponse(), and ~ExecContext().
|
inlineoverridevirtual |
Reads a miscellaneous register, handling any architectural side effects due to reading that register.
Implements gem5::ExecContext.
Definition at line 259 of file exec_context.hh.
References gem5::SimpleThread::readMiscReg(), and thread.
|
inline |
Definition at line 253 of file exec_context.hh.
References gem5::SimpleThread::readMiscRegNoEffect(), and thread.
|
inlineoverridevirtual |
Implements gem5::ExecContext.
Definition at line 271 of file exec_context.hh.
References gem5::MiscRegClass, gem5::SimpleThread::readMiscReg(), gem5::X86ISA::reg, gem5::ArmISA::si, and thread.
|
inlineoverridevirtual |
Implements gem5::ExecContext.
Definition at line 184 of file exec_context.hh.
References gem5::SimpleThread::readPredicate(), and thread.
Referenced by gem5::minor::Execute::commitInst(), gem5::minor::Execute::executeMemRefInst(), gem5::minor::Execute::handleMemResponse(), and ~ExecContext().
|
inlineoverridevirtual |
Returns the number of consecutive store conditional failures.
Implements gem5::ExecContext.
Definition at line 289 of file exec_context.hh.
|
inlineoverridevirtual |
Implements gem5::ExecContext.
Definition at line 202 of file exec_context.hh.
References gem5::SimpleThread::setMemAccPredicate(), thread, and gem5::X86ISA::val.
Referenced by gem5::minor::LSQ::LSQRequest::completeDisabledMemAccess(), and ExecContext().
|
inlineoverridevirtual |
Sets a miscellaneous register, handling any architectural side effects due to writing that register.
Implements gem5::ExecContext.
Definition at line 265 of file exec_context.hh.
References gem5::SimpleThread::setMiscReg(), thread, and gem5::X86ISA::val.
|
inlineoverridevirtual |
Implements gem5::ExecContext.
Definition at line 279 of file exec_context.hh.
References gem5::MiscRegClass, gem5::X86ISA::reg, gem5::SimpleThread::setMiscReg(), gem5::ArmISA::si, thread, and gem5::X86ISA::val.
|
inlineoverridevirtual |
Implements gem5::ExecContext.
Definition at line 190 of file exec_context.hh.
References gem5::SimpleThread::setPredicate(), thread, and gem5::X86ISA::val.
Referenced by ExecContext().
|
inlineoverridevirtual |
Implements gem5::ExecContext.
Definition at line 178 of file exec_context.hh.
References gem5::SimpleThread::setReg(), gem5::ArmISA::si, thread, and gem5::X86ISA::val.
|
inlineoverridevirtual |
Implements gem5::ExecContext.
Definition at line 169 of file exec_context.hh.
References gem5::InvalidRegClass, gem5::X86ISA::reg, gem5::SimpleThread::setReg(), gem5::ArmISA::si, thread, and gem5::X86ISA::val.
|
inlineoverridevirtual |
Sets the number of consecutive store conditional failures.
Implements gem5::ExecContext.
Definition at line 290 of file exec_context.hh.
|
inlineoverridevirtual |
Returns a pointer to the ThreadContext.
Implements gem5::ExecContext.
Definition at line 286 of file exec_context.hh.
References gem5::SimpleThread::getTC(), and thread.
|
inlineoverridevirtual |
For atomic-mode contexts, perform an atomic memory write operation.
For timing-mode contexts, initiate a timing memory write operation.
Implements gem5::ExecContext.
Definition at line 127 of file exec_context.hh.
References gem5::X86ISA::addr, data, execute, flags, gem5::minor::Execute::getLSQ(), inst, and gem5::minor::LSQ::pushRequest().
MinorCPU& gem5::minor::ExecContext::cpu |
Definition at line 76 of file exec_context.hh.
Referenced by getCpuPtr().
Execute& gem5::minor::ExecContext::execute |
The execute stage so we can peek at its contents.
Definition at line 82 of file exec_context.hh.
Referenced by initiateMemAMO(), initiateMemRead(), and writeMem().
MinorDynInstPtr gem5::minor::ExecContext::inst |
Instruction for the benefit of memory operations and for PC.
Definition at line 85 of file exec_context.hh.
Referenced by armMonitor(), ExecContext(), getAddrMonitor(), initiateMemAMO(), initiateMemRead(), mwait(), mwaitAtomic(), writeMem(), and ~ExecContext().
SimpleThread& gem5::minor::ExecContext::thread |
ThreadState object, provides all the architectural state.
Definition at line 79 of file exec_context.hh.
Referenced by contextId(), demapPage(), getRegOperand(), getWritableRegOperand(), mwaitAtomic(), pcState(), readMemAccPredicate(), readMiscReg(), readMiscRegNoEffect(), readMiscRegOperand(), readPredicate(), setMemAccPredicate(), setMiscReg(), setMiscRegOperand(), setPredicate(), setRegOperand(), and tcBase().