gem5  v22.1.0.0
thread_context.cc
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41 
42 #include "cpu/o3/thread_context.hh"
43 
44 #include "debug/O3CPU.hh"
45 
46 namespace gem5
47 {
48 
49 namespace o3
50 {
51 
52 void
54 {
55  gem5::takeOverFrom(*this, *old_context);
56 
57  getIsaPtr()->takeOverFrom(this, old_context);
58 
59  InstDecoder *newDecoder = getDecoderPtr();
60  InstDecoder *oldDecoder = old_context->getDecoderPtr();
61  newDecoder->takeOverFrom(oldDecoder);
62 
63  thread->noSquashFromTC = false;
64  thread->trapPending = false;
65 }
66 
67 void
69 {
70  DPRINTF(O3CPU, "Calling activate on Thread Context %d\n",
71  threadId());
72 
74  return;
75 
78 
79  // status() == Suspended
81 }
82 
83 void
85 {
86  DPRINTF(O3CPU, "Calling suspend on Thread Context %d\n",
87  threadId());
88 
90  return;
91 
92  if (cpu->isDraining()) {
93  DPRINTF(O3CPU, "Ignoring suspend on TC due to pending drain\n");
94  return;
95  }
96 
99 
102 }
103 
104 void
106 {
107  DPRINTF(O3CPU, "Calling halt on Thread Context %d\n", threadId());
108 
111  return;
112 
113  // the thread is not going to halt/terminate immediately in this cycle.
114  // The thread will be removed after an exit trap is processed
115  // (e.g., after trapLatency cycles). Until then, the thread's status
116  // will be Halting.
118 
119  // add this thread to the exiting list to mark that it is trying to exit.
121 }
122 
123 Tick
125 {
126  return thread->lastActivate;
127 }
128 
129 Tick
131 {
132  return thread->lastSuspend;
133 }
134 
135 void
137 {
138  // Prevent squashing
139  thread->noSquashFromTC = true;
140  getIsaPtr()->copyRegsFrom(tc);
141  thread->noSquashFromTC = false;
142 }
143 
144 void
146 {
147  cpu->isa[thread->threadId()]->clear();
148 }
149 
150 RegVal
152 {
153  return cpu->getArchReg(reg, thread->threadId());
154 }
155 
156 void *
158 {
160 }
161 
162 void
163 ThreadContext::getReg(const RegId &reg, void *val) const
164 {
166 }
167 
168 void
170 {
173 }
174 
175 void
176 ThreadContext::setReg(const RegId &reg, const void *val)
177 {
180 }
181 
182 void
184 {
185  cpu->pcState(val, thread->threadId());
186 
188 }
189 
190 void
192 {
193  cpu->pcState(val, thread->threadId());
194 
196 }
197 
198 void
200 {
201  cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId());
202 
204 }
205 
206 void
208 {
209  cpu->setMiscReg(misc_reg, val, thread->threadId());
210 
212 }
213 
214 // hardware transactional memory
215 void
217  HtmFailureFaultCause cause)
218 {
219  cpu->htmSendAbortSignal(thread->threadId(), htmUid, cause);
220 
222 }
223 
226 {
227  return thread->htmCheckpoint;
228 }
229 
230 void
232 {
233  thread->htmCheckpoint = std::move(new_cpt);
234 }
235 
236 } // namespace o3
237 } // namespace gem5
#define DPRINTF(x,...)
Definition: trace.hh:186
virtual void copyRegsFrom(ThreadContext *src)=0
virtual void takeOverFrom(ThreadContext *new_tc, ThreadContext *old_tc)
Definition: isa.hh:79
virtual void takeOverFrom(InstDecoder *old)
Take over the state from an old decoder when switching CPUs.
Definition: decoder.hh:89
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:91
ThreadContext is the external interface to all thread state for anything outside of the CPU.
@ Halted
Permanently shut down.
@ Halting
Trying to exit and waiting for an event to completely exit.
@ Suspended
Temporarily inactive.
virtual InstDecoder * getDecoderPtr()=0
std::vector< BaseISA * > isa
Definition: cpu.hh:444
void htmSendAbortSignal(ThreadID tid, uint64_t htm_uid, HtmFailureFaultCause cause) override
This function is used to instruct the memory subsystem that a transaction should be aborted and the s...
Definition: cpu.cc:1529
void setArchReg(const RegId &reg, RegVal val, ThreadID tid)
Definition: cpu.cc:1181
void activateContext(ThreadID tid) override
Add Thread to Active Threads List.
Definition: cpu.cc:598
void setMiscReg(int misc_reg, RegVal val, ThreadID tid)
Sets a misc.
Definition: cpu.cc:1030
void setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid)
Sets a miscellaneous register.
Definition: cpu.cc:1024
bool isDraining() const
Is the CPU draining?
Definition: cpu.hh:235
void suspendContext(ThreadID tid) override
Remove Thread from Active Threads List.
Definition: cpu.cc:636
RegVal getArchReg(const RegId &reg, ThreadID tid)
Architectural register accessors.
Definition: cpu.cc:1157
void addThreadToExitingList(ThreadID tid)
Insert tid to the list of threads trying to exit.
Definition: cpu.cc:1461
void pcState(const PCStateBase &new_pc_state, ThreadID tid)
Sets the commit PC state of a specific thread.
Definition: cpu.cc:1203
void * getWritableArchReg(const RegId &reg, ThreadID tid)
Definition: cpu.cc:1173
InstDecoder * getDecoderPtr() override
void setHtmCheckpointPtr(BaseHTMCheckpointPtr new_cpt) override
void conditionalSquash()
check if the cpu is currently in state update mode and squash if not.
ThreadState * thread
Pointer to the thread state that this TC corrseponds to.
void pcStateNoRecord(const PCStateBase &val) override
void clearArchRegs() override
Resets all architectural registers to 0.
BaseISA * getIsaPtr() const override
void htmAbortTransaction(uint64_t htm_uid, HtmFailureFaultCause cause) override
Tick readLastActivate() override
Reads the last tick that this thread was activated on.
void * getWritableReg(const RegId &reg) override
void setMiscReg(RegIndex misc_reg, RegVal val) override
Sets a misc.
void activate() override
Set the status to Active.
void suspend() override
Set the status to Suspended.
int threadId() const override
Returns this thread's ID number.
void halt() override
Set the status to Halted.
void takeOverFrom(gem5::ThreadContext *old_context) override
Takes over execution of a thread from another CPU.
Tick readLastSuspend() override
Reads the last tick that this thread was suspended on.
CPU * cpu
Pointer to the CPU.
void setReg(const RegId &reg, RegVal val) override
RegVal getReg(const RegId &reg) const override
BaseHTMCheckpointPtr & getHtmCheckpointPtr() override
void setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override
Sets a misc.
const PCStateBase & pcState() const override
Reads this thread's PC state.
void copyArchRegs(gem5::ThreadContext *tc) override
Copies the architectural registers from another TC into this TC.
bool trapPending
Whether or not the thread is currently waiting on a trap, and thus able to be externally updated with...
Definition: thread_state.hh:89
std::unique_ptr< BaseHTMCheckpoint > htmCheckpoint
Pointer to the hardware transactional memory checkpoint.
Definition: thread_state.hh:92
Bitfield< 5, 3 > reg
Definition: types.hh:92
Bitfield< 63 > val
Definition: misc.hh:776
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
uint16_t RegIndex
Definition: types.hh:176
Tick curTick()
The universal simulation clock.
Definition: cur_tick.hh:46
uint64_t Tick
Tick count type.
Definition: types.hh:58
void takeOverFrom(ThreadContext &ntc, ThreadContext &otc)
Copy state between thread contexts in preparation for CPU handover.
uint64_t RegVal
Definition: types.hh:173
std::unique_ptr< BaseHTMCheckpoint > BaseHTMCheckpointPtr
Definition: htm.hh:125
HtmFailureFaultCause
Definition: htm.hh:48
ThreadID threadId() const
Definition: thread_state.hh:69
void setStatus(Status new_status)
Sets the status of this thread.
Definition: thread_state.hh:83
Tick lastSuspend
Last time suspend was called on this thread.
Tick lastActivate
Last time activate was called on this thread.
Status status() const
Returns the status of this thread.
Definition: thread_state.hh:80

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