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44 #include "arch/vecregs.hh"
45 #include "config/the_isa.hh"
46 #include "debug/O3CPU.hh"
72 DPRINTF(O3CPU,
"Calling activate on Thread Context %d\n",
88 DPRINTF(O3CPU,
"Calling suspend on Thread Context %d\n",
95 DPRINTF(O3CPU,
"Ignoring suspend on TC due to pending drain\n");
Tick curTick()
The universal simulation clock.
void addThreadToExitingList(ThreadID tid)
Insert tid to the list of threads trying to exit.
void * getWritableArchReg(const RegId ®, ThreadID tid)
ThreadState * thread
Pointer to the thread state that this TC corrseponds to.
std::unique_ptr< BaseHTMCheckpoint > BaseHTMCheckpointPtr
void htmAbortTransaction(uint64_t htm_uid, HtmFailureFaultCause cause) override
void activate() override
Set the status to Active.
void takeOverFrom(gem5::ThreadContext *old_context) override
Takes over execution of a thread from another CPU.
BaseHTMCheckpointPtr & getHtmCheckpointPtr() override
virtual void copyRegsFrom(ThreadContext *src)=0
@ Halted
Permanently shut down.
virtual void takeOverFrom(InstDecoder *old)
Take over the state from an old decoder when switching CPUs.
BaseISA * getIsaPtr() const override
int threadId() const override
Returns this thread's ID number.
void htmSendAbortSignal(ThreadID tid, uint64_t htm_uid, HtmFailureFaultCause cause) override
void setMiscReg(int misc_reg, RegVal val, ThreadID tid)
Sets a misc.
virtual void takeOverFrom(ThreadContext *new_tc, ThreadContext *old_tc)
void conditionalSquash()
check if the cpu is currently in state update mode and squash if not.
void takeOverFrom(ThreadContext &ntc, ThreadContext &otc)
Copy state between thread contexts in preparation for CPU handover.
InstDecoder * getDecoderPtr() override
std::unique_ptr< BaseHTMCheckpoint > htmCheckpoint
Pointer to the hardware transactional memory checkpoint.
Tick lastSuspend
Last time suspend was called on this thread.
void setRegFlat(const RegId ®, RegVal val) override
void suspend() override
Set the status to Suspended.
ThreadContext is the external interface to all thread state for anything outside of the CPU.
RegId flattenRegId(const RegId ®Id) const override
void suspendContext(ThreadID tid) override
Remove Thread from Active Threads List.
@ Suspended
Temporarily inactive.
virtual InstDecoder * getDecoderPtr()=0
uint64_t Tick
Tick count type.
void pcState(const PCStateBase &new_pc_state, ThreadID tid)
Sets the commit PC state of a specific thread.
void setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override
Sets a misc.
void * getWritableRegFlat(const RegId ®) override
void setHtmCheckpointPtr(BaseHTMCheckpointPtr new_cpt) override
void setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid)
Sets a miscellaneous register.
ThreadID threadId() const
void setStatus(Status new_status)
Sets the status of this thread.
RegVal getRegFlat(const RegId ®) const override
Flat register interfaces.
Tick lastActivate
Last time activate was called on this thread.
void halt() override
Set the status to Halted.
void clearArchRegs() override
Resets all architectural registers to 0.
void copyArchRegs(gem5::ThreadContext *tc) override
Copies the architectural registers from another TC into this TC.
Tick readLastSuspend() override
Reads the last tick that this thread was suspended on.
Status status() const
Returns the status of this thread.
@ Halting
Trying to exit and waiting for an event to completely exit.
void setArchReg(const RegId ®, RegVal val, ThreadID tid)
bool isDraining() const
Is the CPU draining?
const PCStateBase & pcState() const override
Reads this thread's PC state.
CPU * cpu
Pointer to the CPU.
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
void pcStateNoRecord(const PCStateBase &val) override
void activateContext(ThreadID tid) override
Add Thread to Active Threads List.
RegVal getArchReg(const RegId ®, ThreadID tid)
Architectural register accessors.
Tick readLastActivate() override
Reads the last tick that this thread was activated on.
bool trapPending
Whether or not the thread is currently waiting on a trap, and thus able to be externally updated with...
void setMiscReg(RegIndex misc_reg, RegVal val) override
Sets a misc.
std::vector< TheISA::ISA * > isa
Register ID: describe an architectural register with its class and index.
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