gem5  v22.0.0.1
thread_context.cc
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41 
42 #include "cpu/o3/thread_context.hh"
43 
44 #include "arch/vecregs.hh"
45 #include "config/the_isa.hh"
46 #include "debug/O3CPU.hh"
47 
48 namespace gem5
49 {
50 
51 namespace o3
52 {
53 
54 void
56 {
57  gem5::takeOverFrom(*this, *old_context);
58 
59  getIsaPtr()->takeOverFrom(this, old_context);
60 
61  InstDecoder *newDecoder = getDecoderPtr();
62  InstDecoder *oldDecoder = old_context->getDecoderPtr();
63  newDecoder->takeOverFrom(oldDecoder);
64 
65  thread->noSquashFromTC = false;
66  thread->trapPending = false;
67 }
68 
69 void
71 {
72  DPRINTF(O3CPU, "Calling activate on Thread Context %d\n",
73  threadId());
74 
76  return;
77 
80 
81  // status() == Suspended
83 }
84 
85 void
87 {
88  DPRINTF(O3CPU, "Calling suspend on Thread Context %d\n",
89  threadId());
90 
92  return;
93 
94  if (cpu->isDraining()) {
95  DPRINTF(O3CPU, "Ignoring suspend on TC due to pending drain\n");
96  return;
97  }
98 
101 
104 }
105 
106 void
108 {
109  DPRINTF(O3CPU, "Calling halt on Thread Context %d\n", threadId());
110 
113  return;
114 
115  // the thread is not going to halt/terminate immediately in this cycle.
116  // The thread will be removed after an exit trap is processed
117  // (e.g., after trapLatency cycles). Until then, the thread's status
118  // will be Halting.
120 
121  // add this thread to the exiting list to mark that it is trying to exit.
123 }
124 
125 Tick
127 {
128  return thread->lastActivate;
129 }
130 
131 Tick
133 {
134  return thread->lastSuspend;
135 }
136 
137 void
139 {
140  // Prevent squashing
141  thread->noSquashFromTC = true;
142  getIsaPtr()->copyRegsFrom(tc);
143  thread->noSquashFromTC = false;
144 }
145 
146 void
148 {
149  cpu->isa[thread->threadId()]->clear();
150 }
151 
152 RegVal
154 {
155  return cpu->getArchReg(reg, thread->threadId());
156 }
157 
158 void *
160 {
162 }
163 
164 void
166 {
168 }
169 
170 void
172 {
175 }
176 
177 void
179 {
182 }
183 
184 void
186 {
187  cpu->pcState(val, thread->threadId());
188 
190 }
191 
192 void
194 {
195  cpu->pcState(val, thread->threadId());
196 
198 }
199 
200 RegId
202 {
203  return cpu->isa[thread->threadId()]->flattenRegId(regId);
204 }
205 
206 void
208 {
209  cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId());
210 
212 }
213 
214 void
216 {
217  cpu->setMiscReg(misc_reg, val, thread->threadId());
218 
220 }
221 
222 // hardware transactional memory
223 void
225  HtmFailureFaultCause cause)
226 {
227  cpu->htmSendAbortSignal(thread->threadId(), htmUid, cause);
228 
230 }
231 
234 {
235  return thread->htmCheckpoint;
236 }
237 
238 void
240 {
241  thread->htmCheckpoint = std::move(new_cpt);
242 }
243 
244 } // namespace o3
245 } // namespace gem5
gem5::curTick
Tick curTick()
The universal simulation clock.
Definition: cur_tick.hh:46
gem5::o3::CPU::addThreadToExitingList
void addThreadToExitingList(ThreadID tid)
Insert tid to the list of threads trying to exit.
Definition: cpu.cc:1459
gem5::o3::CPU::getWritableArchReg
void * getWritableArchReg(const RegId &reg, ThreadID tid)
Definition: cpu.cc:1174
gem5::o3::ThreadContext::thread
ThreadState * thread
Pointer to the thread state that this TC corrseponds to.
Definition: thread_context.hh:102
gem5::ThreadContext::Active
@ Active
Running.
Definition: thread_context.hh:109
gem5::BaseHTMCheckpointPtr
std::unique_ptr< BaseHTMCheckpoint > BaseHTMCheckpointPtr
Definition: htm.hh:125
gem5::o3::ThreadContext::htmAbortTransaction
void htmAbortTransaction(uint64_t htm_uid, HtmFailureFaultCause cause) override
Definition: thread_context.cc:224
gem5::o3::ThreadContext::activate
void activate() override
Set the status to Active.
Definition: thread_context.cc:70
gem5::o3::ThreadContext::takeOverFrom
void takeOverFrom(gem5::ThreadContext *old_context) override
Takes over execution of a thread from another CPU.
Definition: thread_context.cc:55
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::o3::ThreadContext::getHtmCheckpointPtr
BaseHTMCheckpointPtr & getHtmCheckpointPtr() override
Definition: thread_context.cc:233
gem5::BaseISA::copyRegsFrom
virtual void copyRegsFrom(ThreadContext *src)=0
gem5::ThreadContext::Halted
@ Halted
Permanently shut down.
Definition: thread_context.hh:122
gem5::HtmFailureFaultCause
HtmFailureFaultCause
Definition: htm.hh:47
gem5::InstDecoder::takeOverFrom
virtual void takeOverFrom(InstDecoder *old)
Take over the state from an old decoder when switching CPUs.
Definition: decoder.hh:89
gem5::o3::ThreadContext::getIsaPtr
BaseISA * getIsaPtr() const override
Definition: thread_context.hh:110
gem5::o3::ThreadContext::threadId
int threadId() const override
Returns this thread's ID number.
Definition: thread_context.hh:135
gem5::o3::CPU::htmSendAbortSignal
void htmSendAbortSignal(ThreadID tid, uint64_t htm_uid, HtmFailureFaultCause cause) override
Definition: cpu.cc:1527
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:769
gem5::o3::CPU::setMiscReg
void setMiscReg(int misc_reg, RegVal val, ThreadID tid)
Sets a misc.
Definition: cpu.cc:1033
gem5::BaseISA::takeOverFrom
virtual void takeOverFrom(ThreadContext *new_tc, ThreadContext *old_tc)
Definition: isa.hh:71
gem5::o3::ThreadContext::conditionalSquash
void conditionalSquash()
check if the cpu is currently in state update mode and squash if not.
Definition: thread_context.hh:236
gem5::takeOverFrom
void takeOverFrom(ThreadContext &ntc, ThreadContext &otc)
Copy state between thread contexts in preparation for CPU handover.
Definition: thread_context.cc:312
gem5::o3::ThreadContext::getDecoderPtr
InstDecoder * getDecoderPtr() override
Definition: thread_context.hh:116
gem5::o3::ThreadState::htmCheckpoint
std::unique_ptr< BaseHTMCheckpoint > htmCheckpoint
Pointer to the hardware transactional memory checkpoint.
Definition: thread_state.hh:92
gem5::ThreadState::lastSuspend
Tick lastSuspend
Last time suspend was called on this thread.
Definition: thread_state.hh:128
gem5::o3::ThreadContext::setRegFlat
void setRegFlat(const RegId &reg, RegVal val) override
Definition: thread_context.cc:171
gem5::o3::ThreadContext::suspend
void suspend() override
Set the status to Suspended.
Definition: thread_context.cc:86
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::o3::ThreadContext::flattenRegId
RegId flattenRegId(const RegId &regId) const override
Definition: thread_context.cc:201
gem5::o3::CPU::suspendContext
void suspendContext(ThreadID tid) override
Remove Thread from Active Threads List.
Definition: cpu.cc:639
gem5::InstDecoder
Definition: decoder.hh:42
gem5::ThreadContext::Suspended
@ Suspended
Temporarily inactive.
Definition: thread_context.hh:113
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::ThreadContext::getDecoderPtr
virtual InstDecoder * getDecoderPtr()=0
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::o3::CPU::pcState
void pcState(const PCStateBase &new_pc_state, ThreadID tid)
Sets the commit PC state of a specific thread.
Definition: cpu.cc:1201
gem5::o3::ThreadContext::setMiscRegNoEffect
void setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override
Sets a misc.
Definition: thread_context.cc:207
gem5::o3::ThreadContext::getWritableRegFlat
void * getWritableRegFlat(const RegId &reg) override
Definition: thread_context.cc:159
gem5::o3::ThreadContext::setHtmCheckpointPtr
void setHtmCheckpointPtr(BaseHTMCheckpointPtr new_cpt) override
Definition: thread_context.cc:239
gem5::o3::CPU::setMiscRegNoEffect
void setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid)
Sets a miscellaneous register.
Definition: cpu.cc:1027
gem5::ThreadState::threadId
ThreadID threadId() const
Definition: thread_state.hh:69
gem5::ThreadState::setStatus
void setStatus(Status new_status)
Sets the status of this thread.
Definition: thread_state.hh:83
gem5::o3::ThreadContext::getRegFlat
RegVal getRegFlat(const RegId &reg) const override
Flat register interfaces.
Definition: thread_context.cc:153
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::o3::ThreadState::noSquashFromTC
bool noSquashFromTC
Definition: thread_state.hh:84
gem5::ThreadState::lastActivate
Tick lastActivate
Last time activate was called on this thread.
Definition: thread_state.hh:125
gem5::o3::ThreadContext::halt
void halt() override
Set the status to Halted.
Definition: thread_context.cc:107
gem5::o3::ThreadContext::clearArchRegs
void clearArchRegs() override
Resets all architectural registers to 0.
Definition: thread_context.cc:147
gem5::o3::ThreadContext::copyArchRegs
void copyArchRegs(gem5::ThreadContext *tc) override
Copies the architectural registers from another TC into this TC.
Definition: thread_context.cc:138
gem5::o3::ThreadContext::readLastSuspend
Tick readLastSuspend() override
Reads the last tick that this thread was suspended on.
Definition: thread_context.cc:132
gem5::ThreadState::status
Status status() const
Returns the status of this thread.
Definition: thread_state.hh:80
gem5::ThreadContext::Halting
@ Halting
Trying to exit and waiting for an event to completely exit.
Definition: thread_context.hh:117
gem5::o3::CPU::setArchReg
void setArchReg(const RegId &reg, RegVal val, ThreadID tid)
Definition: cpu.cc:1181
gem5::o3::CPU::isDraining
bool isDraining() const
Is the CPU draining?
Definition: cpu.hh:236
gem5::o3::ThreadContext::pcState
const PCStateBase & pcState() const override
Reads this thread's PC state.
Definition: thread_context.hh:181
thread_context.hh
gem5::PCStateBase
Definition: pcstate.hh:57
gem5::o3::ThreadContext::cpu
CPU * cpu
Pointer to the CPU.
Definition: thread_context.hh:72
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::o3::ThreadContext::pcStateNoRecord
void pcStateNoRecord(const PCStateBase &val) override
Definition: thread_context.cc:193
gem5::o3::CPU::activateContext
void activateContext(ThreadID tid) override
Add Thread to Active Threads List.
Definition: cpu.cc:601
gem5::o3::CPU::getArchReg
RegVal getArchReg(const RegId &reg, ThreadID tid)
Architectural register accessors.
Definition: cpu.cc:1160
gem5::o3::ThreadContext::readLastActivate
Tick readLastActivate() override
Reads the last tick that this thread was activated on.
Definition: thread_context.cc:126
gem5::o3::ThreadState::trapPending
bool trapPending
Whether or not the thread is currently waiting on a trap, and thus able to be externally updated with...
Definition: thread_state.hh:89
gem5::o3::ThreadContext::setMiscReg
void setMiscReg(RegIndex misc_reg, RegVal val) override
Sets a misc.
Definition: thread_context.cc:215
gem5::o3::CPU::isa
std::vector< TheISA::ISA * > isa
Definition: cpu.hh:445
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:126

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