gem5  v21.1.0.2
thread_context.cc
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41 
42 #include "cpu/o3/thread_context.hh"
43 
44 #include "arch/vecregs.hh"
45 #include "config/the_isa.hh"
46 #include "debug/O3CPU.hh"
47 
48 namespace gem5
49 {
50 
51 namespace o3
52 {
53 
54 PortProxy&
56 {
57  return thread->getVirtProxy();
58 }
59 
60 void
62 {
63  gem5::takeOverFrom(*this, *old_context);
64 
65  getIsaPtr()->takeOverFrom(this, old_context);
66 
67  TheISA::Decoder *newDecoder = getDecoderPtr();
68  TheISA::Decoder *oldDecoder = old_context->getDecoderPtr();
69  newDecoder->takeOverFrom(oldDecoder);
70 
71  thread->noSquashFromTC = false;
72  thread->trapPending = false;
73 }
74 
75 void
77 {
78  DPRINTF(O3CPU, "Calling activate on Thread Context %d\n",
79  threadId());
80 
82  return;
83 
86 
87  // status() == Suspended
89 }
90 
91 void
93 {
94  DPRINTF(O3CPU, "Calling suspend on Thread Context %d\n",
95  threadId());
96 
98  return;
99 
100  if (cpu->isDraining()) {
101  DPRINTF(O3CPU, "Ignoring suspend on TC due to pending drain\n");
102  return;
103  }
104 
107 
110 }
111 
112 void
114 {
115  DPRINTF(O3CPU, "Calling halt on Thread Context %d\n", threadId());
116 
119  return;
120 
121  // the thread is not going to halt/terminate immediately in this cycle.
122  // The thread will be removed after an exit trap is processed
123  // (e.g., after trapLatency cycles). Until then, the thread's status
124  // will be Halting.
126 
127  // add this thread to the exiting list to mark that it is trying to exit.
129 }
130 
131 Tick
133 {
134  return thread->lastActivate;
135 }
136 
137 Tick
139 {
140  return thread->lastSuspend;
141 }
142 
143 void
145 {
146  // Set vector renaming mode before copying registers
148 
149  // Prevent squashing
150  thread->noSquashFromTC = true;
151  getIsaPtr()->copyRegsFrom(tc);
152  thread->noSquashFromTC = false;
153 }
154 
155 void
157 {
158  cpu->isa[thread->threadId()]->clear();
159 }
160 
161 RegVal
163 {
164  return cpu->readArchIntReg(reg_idx, thread->threadId());
165 }
166 
167 RegVal
169 {
170  return cpu->readArchFloatReg(reg_idx, thread->threadId());
171 }
172 
175 {
176  return cpu->readArchVecReg(reg_id, thread->threadId());
177 }
178 
181 {
182  return cpu->getWritableArchVecReg(reg_id, thread->threadId());
183 }
184 
185 const TheISA::VecElem&
187 {
188  return cpu->readArchVecElem(idx, elemIndex, thread->threadId());
189 }
190 
193 {
194  return cpu->readArchVecPredReg(reg_id, thread->threadId());
195 }
196 
199 {
200  return cpu->getWritableArchVecPredReg(reg_id, thread->threadId());
201 }
202 
203 RegVal
205 {
206  return cpu->readArchCCReg(reg_idx, thread->threadId());
207 }
208 
209 void
211 {
212  cpu->setArchIntReg(reg_idx, val, thread->threadId());
213 
215 }
216 
217 void
219 {
220  cpu->setArchFloatReg(reg_idx, val, thread->threadId());
221 
223 }
224 
225 void
227  RegIndex reg_idx, const TheISA::VecRegContainer& val)
228 {
229  cpu->setArchVecReg(reg_idx, val, thread->threadId());
230 
232 }
233 
234 void
236  const ElemIndex& elemIndex, const TheISA::VecElem& val)
237 {
238  cpu->setArchVecElem(idx, elemIndex, val, thread->threadId());
240 }
241 
242 void
245 {
246  cpu->setArchVecPredReg(reg_idx, val, thread->threadId());
247 
249 }
250 
251 void
253 {
254  cpu->setArchCCReg(reg_idx, val, thread->threadId());
255 
257 }
258 
259 void
261 {
262  cpu->pcState(val, thread->threadId());
263 
265 }
266 
267 void
269 {
270  cpu->pcState(val, thread->threadId());
271 
273 }
274 
275 RegId
277 {
278  return cpu->isa[thread->threadId()]->flattenRegId(regId);
279 }
280 
281 void
283 {
284  cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId());
285 
287 }
288 
289 void
291 {
292  cpu->setMiscReg(misc_reg, val, thread->threadId());
293 
295 }
296 
297 // hardware transactional memory
298 void
300  HtmFailureFaultCause cause)
301 {
302  cpu->htmSendAbortSignal(thread->threadId(), htmUid, cause);
303 
305 }
306 
309 {
310  return thread->htmCheckpoint;
311 }
312 
313 void
315 {
316  thread->htmCheckpoint = std::move(new_cpt);
317 }
318 
319 } // namespace o3
320 } // namespace gem5
gem5::o3::ThreadContext::getDecoderPtr
TheISA::Decoder * getDecoderPtr() override
Definition: thread_context.hh:116
gem5::curTick
Tick curTick()
The universal simulation clock.
Definition: cur_tick.hh:46
gem5::o3::CPU::setArchIntReg
void setArchIntReg(int reg_idx, RegVal val, ThreadID tid)
Architectural register accessors.
Definition: cpu.cc:1318
gem5::o3::ThreadContext::readVecElemFlat
const TheISA::VecElem & readVecElemFlat(RegIndex idx, const ElemIndex &elemIndex) const override
Definition: thread_context.cc:186
gem5::o3::CPU::addThreadToExitingList
void addThreadToExitingList(ThreadID tid)
Insert tid to the list of threads trying to exit.
Definition: cpu.cc:1656
gem5::o3::ThreadContext::thread
ThreadState * thread
Pointer to the thread state that this TC corrseponds to.
Definition: thread_context.hh:102
gem5::o3::ThreadContext::getVirtProxy
PortProxy & getVirtProxy() override
Definition: thread_context.cc:55
gem5::o3::CPU::setArchVecElem
void setArchVecElem(const RegIndex &reg_idx, const ElemIndex &ldx, const TheISA::VecElem &val, ThreadID tid)
Definition: cpu.cc:1347
gem5::ThreadContext::Active
@ Active
Running.
Definition: thread_context.hh:108
gem5::BaseHTMCheckpointPtr
std::unique_ptr< BaseHTMCheckpoint > BaseHTMCheckpointPtr
Definition: htm.hh:125
gem5::o3::ThreadContext::htmAbortTransaction
void htmAbortTransaction(uint64_t htm_uid, HtmFailureFaultCause cause) override
Definition: thread_context.cc:299
gem5::o3::ThreadContext::activate
void activate() override
Set the status to Active.
Definition: thread_context.cc:76
gem5::o3::ThreadContext::takeOverFrom
void takeOverFrom(gem5::ThreadContext *old_context) override
Takes over execution of a thread from another CPU.
Definition: thread_context.cc:61
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::o3::ThreadContext::getHtmCheckpointPtr
BaseHTMCheckpointPtr & getHtmCheckpointPtr() override
Definition: thread_context.cc:308
gem5::ArmISA::VecPredRegContainer
VecPredReg::Container VecPredRegContainer
Definition: vec.hh:68
gem5::BaseISA::copyRegsFrom
virtual void copyRegsFrom(ThreadContext *src)=0
gem5::ThreadContext::Halted
@ Halted
Permanently shut down.
Definition: thread_context.hh:121
gem5::HtmFailureFaultCause
HtmFailureFaultCause
Definition: htm.hh:47
gem5::o3::ThreadContext::getWritableVecRegFlat
TheISA::VecRegContainer & getWritableVecRegFlat(RegIndex idx) override
Read vector register operand for modification, flat indexing.
Definition: thread_context.cc:180
gem5::o3::ThreadContext::threadId
int threadId() const override
Returns this thread's ID number.
Definition: thread_context.hh:135
gem5::o3::CPU::readArchFloatReg
RegVal readArchFloatReg(int reg_idx, ThreadID tid)
Definition: cpu.cc:1257
gem5::o3::CPU::readArchCCReg
RegVal readArchCCReg(int reg_idx, ThreadID tid)
Definition: cpu.cc:1308
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
gem5::o3::CPU::htmSendAbortSignal
void htmSendAbortSignal(ThreadID tid, uint64_t htm_uid, HtmFailureFaultCause cause)
Definition: cpu.cc:1724
gem5::o3::ThreadContext::setCCRegFlat
void setCCRegFlat(RegIndex idx, RegVal val) override
Definition: thread_context.cc:252
gem5::o3::CPU::setMiscReg
void setMiscReg(int misc_reg, RegVal val, ThreadID tid)
Sets a misc.
Definition: cpu.cc:1141
gem5::BaseISA::takeOverFrom
virtual void takeOverFrom(ThreadContext *new_tc, ThreadContext *old_tc)
Definition: isa.hh:67
gem5::o3::ThreadContext::readVecPredRegFlat
const TheISA::VecPredRegContainer & readVecPredRegFlat(RegIndex idx) const override
Definition: thread_context.cc:192
gem5::ThreadContext::getDecoderPtr
virtual TheISA::Decoder * getDecoderPtr()=0
gem5::o3::ThreadContext::conditionalSquash
void conditionalSquash()
check if the cpu is currently in state update mode and squash if not.
Definition: thread_context.hh:365
gem5::ThreadState::getVirtProxy
PortProxy & getVirtProxy()
Definition: thread_state.cc:88
gem5::takeOverFrom
void takeOverFrom(ThreadContext &ntc, ThreadContext &otc)
Copy state between thread contexts in preparation for CPU handover.
Definition: thread_context.cc:254
gem5::o3::ThreadContext::setFloatRegFlat
void setFloatRegFlat(RegIndex idx, RegVal val) override
Definition: thread_context.cc:218
gem5::o3::ThreadState::htmCheckpoint
std::unique_ptr< BaseHTMCheckpoint > htmCheckpoint
Pointer to the hardware transactional memory checkpoint.
Definition: thread_state.hh:92
gem5::o3::ThreadContext::readFloatRegFlat
RegVal readFloatRegFlat(RegIndex idx) const override
Definition: thread_context.cc:168
gem5::o3::CPU::setArchFloatReg
void setArchFloatReg(int reg_idx, RegVal val, ThreadID tid)
Definition: cpu.cc:1328
gem5::o3::CPU::setArchCCReg
void setArchCCReg(int reg_idx, RegVal val, ThreadID tid)
Definition: cpu.cc:1365
gem5::ThreadState::lastSuspend
Tick lastSuspend
Last time suspend was called on this thread.
Definition: thread_state.hh:138
gem5::o3::CPU::setArchVecReg
void setArchVecReg(int reg_idx, const TheISA::VecRegContainer &val, ThreadID tid)
Definition: cpu.cc:1338
gem5::o3::CPU::readArchVecPredReg
const TheISA::VecPredRegContainer & readArchVecPredReg(int reg_idx, ThreadID tid) const
Definition: cpu.cc:1292
gem5::ThreadContext::getIsaPtr
virtual BaseISA * getIsaPtr()=0
gem5::o3::ThreadContext::pcStateNoRecord
void pcStateNoRecord(const TheISA::PCState &val) override
Definition: thread_context.cc:268
gem5::o3::ThreadContext::suspend
void suspend() override
Set the status to Suspended.
Definition: thread_context.cc:92
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::o3::ThreadContext::flattenRegId
RegId flattenRegId(const RegId &regId) const override
Definition: thread_context.cc:276
gem5::o3::CPU::suspendContext
void suspendContext(ThreadID tid) override
Remove Thread from Active Threads List.
Definition: cpu.cc:694
gem5::o3::CPU::readArchVecElem
const TheISA::VecElem & readArchVecElem(const RegIndex &reg_idx, const ElemIndex &ldx, ThreadID tid) const
Definition: cpu.cc:1283
gem5::ThreadContext::Suspended
@ Suspended
Temporarily inactive.
Definition: thread_context.hh:112
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::MipsISA::PCState
GenericISA::DelaySlotPCState< 4 > PCState
Definition: pcstate.hh:40
gem5::o3::ThreadContext::setVecRegFlat
void setVecRegFlat(RegIndex idx, const TheISA::VecRegContainer &val) override
Definition: thread_context.cc:226
gem5::o3::CPU::vecRenameMode
enums::VecRegRenameMode vecRenameMode() const
Returns current vector renaming mode.
Definition: cpu.hh:337
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::o3::ThreadContext::getWritableVecPredRegFlat
TheISA::VecPredRegContainer & getWritableVecPredRegFlat(RegIndex idx) override
Definition: thread_context.cc:198
gem5::o3::ThreadContext::setMiscRegNoEffect
void setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override
Sets a misc.
Definition: thread_context.cc:282
gem5::o3::ThreadContext::setVecElemFlat
void setVecElemFlat(RegIndex idx, const ElemIndex &elemIdx, const TheISA::VecElem &val) override
Definition: thread_context.cc:235
gem5::o3::ThreadContext::pcState
TheISA::PCState pcState() const override
Reads this thread's PC state.
Definition: thread_context.hh:289
gem5::o3::CPU::setArchVecPredReg
void setArchVecPredReg(int reg_idx, const TheISA::VecPredRegContainer &val, ThreadID tid)
Definition: cpu.cc:1356
gem5::o3::ThreadContext::setHtmCheckpointPtr
void setHtmCheckpointPtr(BaseHTMCheckpointPtr new_cpt) override
Definition: thread_context.cc:314
gem5::ArmISA::VecRegContainer
gem5::VecRegContainer< NumVecElemPerVecReg *sizeof(VecElem)> VecRegContainer
Definition: vec.hh:62
gem5::o3::CPU::setMiscRegNoEffect
void setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid)
Sets a miscellaneous register.
Definition: cpu.cc:1135
gem5::ThreadState::threadId
ThreadID threadId() const
Definition: thread_state.hh:69
gem5::BaseISA::vecRegRenameMode
virtual enums::VecRegRenameMode vecRegRenameMode(ThreadContext *_tc) const
Definition: isa.hh:81
gem5::ElemIndex
uint16_t ElemIndex
Logical vector register elem index type.
Definition: types.hh:179
gem5::o3::ThreadContext::readVecRegFlat
const TheISA::VecRegContainer & readVecRegFlat(RegIndex idx) const override
Definition: thread_context.cc:174
gem5::ThreadState::setStatus
void setStatus(Status new_status)
Sets the status of this thread.
Definition: thread_state.hh:93
gem5::o3::CPU::getWritableArchVecReg
TheISA::VecRegContainer & getWritableArchVecReg(int reg_idx, ThreadID tid)
Read architectural vector register for modification.
Definition: cpu.cc:1275
gem5::o3::ThreadState::noSquashFromTC
bool noSquashFromTC
Definition: thread_state.hh:84
gem5::ThreadState::lastActivate
Tick lastActivate
Last time activate was called on this thread.
Definition: thread_state.hh:135
gem5::o3::CPU::getWritableArchVecPredReg
TheISA::VecPredRegContainer & getWritableArchVecPredReg(int reg_idx, ThreadID tid)
Definition: cpu.cc:1300
gem5::o3::ThreadContext::halt
void halt() override
Set the status to Halted.
Definition: thread_context.cc:113
gem5::o3::ThreadContext::clearArchRegs
void clearArchRegs() override
Resets all architectural registers to 0.
Definition: thread_context.cc:156
gem5::o3::ThreadContext::readCCRegFlat
RegVal readCCRegFlat(RegIndex idx) const override
Definition: thread_context.cc:204
gem5::o3::ThreadContext::copyArchRegs
void copyArchRegs(gem5::ThreadContext *tc) override
Copies the architectural registers from another TC into this TC.
Definition: thread_context.cc:144
gem5::o3::ThreadContext::getIsaPtr
BaseISA * getIsaPtr() override
Definition: thread_context.hh:110
gem5::o3::ThreadContext::readLastSuspend
Tick readLastSuspend() override
Reads the last tick that this thread was suspended on.
Definition: thread_context.cc:138
gem5::ArmISA::VecElem
uint32_t VecElem
Definition: vec.hh:60
gem5::ThreadState::status
Status status() const
Returns the status of this thread.
Definition: thread_state.hh:90
gem5::ThreadContext::Halting
@ Halting
Trying to exit and waiting for an event to completely exit.
Definition: thread_context.hh:116
gem5::o3::CPU::isDraining
bool isDraining() const
Is the CPU draining?
Definition: cpu.hh:232
thread_context.hh
gem5::o3::CPU::readArchIntReg
RegVal readArchIntReg(int reg_idx, ThreadID tid)
Definition: cpu.cc:1247
gem5::o3::ThreadContext::cpu
CPU * cpu
Pointer to the CPU.
Definition: thread_context.hh:72
gem5::o3::ThreadContext::setIntRegFlat
void setIntRegFlat(RegIndex idx, RegVal val) override
Definition: thread_context.cc:210
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
gem5::o3::CPU::pcState
void pcState(const TheISA::PCState &newPCState, ThreadID tid)
Sets the commit PC state of a specific thread.
Definition: cpu.cc:1381
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::o3::ThreadContext::setVecPredRegFlat
void setVecPredRegFlat(RegIndex idx, const TheISA::VecPredRegContainer &val) override
Definition: thread_context.cc:243
gem5::o3::CPU::activateContext
void activateContext(ThreadID tid) override
Add Thread to Active Threads List.
Definition: cpu.cc:656
gem5::o3::ThreadContext::readLastActivate
Tick readLastActivate() override
Reads the last tick that this thread was activated on.
Definition: thread_context.cc:132
gem5::o3::ThreadState::trapPending
bool trapPending
Whether or not the thread is currently waiting on a trap, and thus able to be externally updated with...
Definition: thread_state.hh:89
gem5::o3::ThreadContext::setMiscReg
void setMiscReg(RegIndex misc_reg, RegVal val) override
Sets a misc.
Definition: thread_context.cc:290
gem5::o3::CPU::isa
std::vector< TheISA::ISA * > isa
Definition: cpu.hh:528
gem5::o3::ThreadContext::readIntRegFlat
RegVal readIntRegFlat(RegIndex idx) const override
Flat register interfaces.
Definition: thread_context.cc:162
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:88
gem5::o3::CPU::readArchVecReg
const TheISA::VecRegContainer & readArchVecReg(int reg_idx, ThreadID tid) const
Definition: cpu.cc:1267

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